JP5920170B2 - Oscillator circuit - Google Patents

Description

  The present invention relates to an oscillation circuit.

  2. Description of the Related Art Conventionally, an oscillation circuit that generates and outputs an oscillation signal using a capacitor for charging and discharging, a comparison circuit such as a comparator, and a logic circuit such as a flip-flop circuit has been provided. For example, an oscillation circuit disclosed in Patent Document 1 includes a first capacitor and a second capacitor that are charged and discharged with a constant current, and a first comparison circuit that compares a charging voltage of the first capacitor with a reference voltage ( A comparator), a second comparison circuit (comparator) for comparing the charging voltage of the second capacitor with the reference voltage, and an RS flip-flop circuit. In this RS flip-flop circuit, when the voltage of the first capacitor becomes higher than the reference voltage, the S terminal to which a high level signal is input, and when the voltage of the second capacitor becomes higher than the reference voltage, a low level signal is input. R terminal. In this configuration, one of the first capacitors operates so as to be in a discharging state when the output signal Q of the RS flip-flop circuit is at a high level, and to be in a charging state when the output signal Q is at a low level, and the other second capacitor. The capacitor of the RS flip-flop circuit operates so that it is discharged when the inverted output signal QB of the RS flip-flop circuit is high level, and is charged when the inverted output signal QB is low level. These operations generate and output an oscillation signal. Is done.

JP 2007-243922 A

  By the way, the oscillation circuit using the comparison circuit as described above has a characteristic that the delay time in the comparison circuit depends on the temperature, and there is a problem that the delay time varies due to a change in the ambient temperature. Such a variation in delay time causes a variation in output frequency (oscillation frequency), and therefore it is desirable to suppress it as much as possible. However, the oscillation circuit of Patent Document 1 cannot solve such a problem. .

  On the other hand, as a method of solving such a problem, there is a method of mounting a temperature sensor in the oscillation circuit and correcting the circuit parameters based on the measured temperature. However, in order to monitor the temperature in the oscillation circuit When the new configuration is provided, the number of parts increases and a space for mounting the temperature sensor is required in the circuit, so that the circuit scale is increased, and thus the overall configuration of the apparatus cannot be increased.

  The present invention has been made to solve the above-described problem, and an object of the present invention is to more easily realize a configuration that can suppress variation in oscillation frequency caused by variation in delay time in a comparison circuit. .

In order to achieve the above object, the first invention provides:
A constant current source (15) for generating a constant current;
A first capacitor (C1) and a second capacitor (C2) configured to be conductive with the constant current source and capable of being charged with a constant current supplied from the constant current source;
When the charging voltage charged in the first capacitor (C1) is less than a predetermined first threshold, a predetermined first signal is output, and when the charging voltage is equal to or higher than the first threshold, the first signal differs from the first signal A first comparison circuit (11) that outputs two signals;
When the charge voltage charged in the second capacitor (C2) is less than a second threshold value that is the same as the first threshold value or different from the first threshold value, a predetermined third signal is output, and the second A second comparison circuit (13) that outputs a fourth signal different from the third signal when the threshold is equal to or greater than a threshold;
A threshold setting circuit (20) for setting the first threshold and the second threshold;
Based on the signals output from the first comparison circuit (11) and the second comparison circuit (13), the charging target from the constant current source (15) is set to the first capacitor (C1) and the second capacitor ( A switching control circuit (8) for switching to either one of C2) and the other to be discharged;
The charging voltage at the time when either one of the first capacitor (C1) and the second capacitor (C2) is switched to the discharge target by the switching control circuit (8), or both capacitors are respectively A correction unit (4) that generates correction data used to correct the first threshold value and the second threshold value set by the threshold value setting circuit (20) based on each charging voltage at each time when it is switched to a discharge target. )When,
A control unit (3) for controlling the threshold value setting circuit to set the first threshold value and the second threshold value based on the correction data generated by the correction unit;
It is characterized by having.

  In the first aspect of the invention, the charging voltage of the capacitor at the time when one of the first capacitor (C1) and the second capacitor (C2) is switched to the discharge target is the first comparison circuit (11) and the second capacitor (C1). After the condition for switching one of the first capacitor (C1) and the second capacitor (C2) to the discharge target is established in any one of the two comparison circuits (13), until the discharge of the capacitor is actually started The delay voltage is a value reflecting the delay time. If the delay time is large, the charging voltage becomes relatively large. If the delay time is small, the charging voltage becomes relatively small. Therefore, when either one of the first capacitor (C1) and the second capacitor (C2) is switched to the discharge target, either one of the charging voltage or both capacitors are switched to the discharge target. If correction data is generated based on each charging voltage at each time, it is possible to generate correction data that appropriately considers the delay time.

According to a second aspect of the present invention, the threshold value setting circuit (20) is configured to set the first threshold value and the second threshold value as the same value. In addition, the correction unit (4) is configured so that one of the first capacitor (C1) and the second capacitor (C2) is switched to a discharge target by the switching control circuit (8). When the detected charging voltage exceeds a predetermined representative voltage, correction data for generating the same value lower than a predetermined reference value is generated, and the detected charging voltage is When the voltage is less than the representative voltage, correction data for generating the same value higher than a predetermined reference value is generated.
In this configuration, since the threshold value used for each comparison circuit can be shared, the arithmetic processing can be simplified. Further, the correction data can be generated with a simple circuit structure in which one of the charging voltages is detected and the charging voltage is compared with the representative voltage.

According to a third aspect of the present invention, the threshold setting circuit (20) is configured to set the first threshold and the second threshold as the same value. The correction unit (4) detects a charging voltage of the first capacitor (C1) at a time when the first capacitor (C1) is switched to a discharge target by the switching control circuit (8), and The charging voltage of the second capacitor (C2) is detected when the two capacitors (C2) are switched to discharge targets. Further, when a statistical value reflecting the detected charging voltage of the first capacitor (C1) and the charging voltage of the second capacitor (C2) exceeds a predetermined representative voltage, the statistical value is more than a predetermined reference value. Correction data for lowering the same value is generated, and when the statistical value is less than the representative voltage, correction data for generating the same value higher than a predetermined reference value is generated.
In this configuration, since the threshold value used for each comparison circuit can be shared, the arithmetic processing can be simplified. In addition, since the charging voltage of both capacitors can be detected separately and the correction data can be generated in a form reflecting these charging voltages (that is, reflecting both delay times of both comparison circuits), both comparison circuits Even when there is a difference in the delay state, it can be corrected more appropriately.

According to a fourth aspect of the present invention, the threshold setting circuit (20) can set the first threshold and the second threshold separately, and the first comparison circuit (11) includes the first capacitor ( The second signal is output at the timing when the charging voltage of C1) reaches the first threshold value, and the second comparison circuit (13) causes the charging voltage of the second capacitor (C2) to reach the second threshold value. The fourth signal is output at the same timing. The switching control circuit (4) performs control to switch the first capacitor (C1) from a charging target to a discharging target when the second signal is output from the first comparison circuit (11), and When the fourth signal is output from the second comparison circuit (13), control is performed to switch the second capacitor (C2) from the charging target to the discharging target.
Further, the correction unit (4) detects a charging voltage of the first capacitor (C1) at a time when the first capacitor (C1) is switched to a discharge target by the switching control circuit (8). When the charging voltage of the first capacitor (C1) exceeds a predetermined representative voltage, first correction data for generating the first threshold value lower than a predetermined reference value of the first capacitor (C1) is generated. If the detected charging voltage of the first capacitor (C1) is less than the representative voltage, first correction data for making the first threshold value higher than a predetermined reference value of the first capacitor (C1) is obtained. The charging voltage of the second capacitor (C2) is detected when the second capacitor (C2) is switched to the discharge target by the switching control circuit (8), and the detected second capacitor (C2 ) Exceeds the second representative voltage that is the same as or different from the representative voltage, and generates second correction data that makes the second threshold value lower than a predetermined reference value of the second capacitor (C2). When the detected charging voltage of the second capacitor (C2) is lower than the second representative voltage, the second correction for increasing the second threshold value above a predetermined reference value of the second capacitor (C2). Data is being generated.
In this configuration, it is possible to obtain the charging voltage at the start of discharge of each of the first capacitor and the second capacitor, and it can be said that each of these charging voltages reflects the delay time of each comparison circuit separately. It is possible to individually grasp the delay time of the comparison circuit. And since each correction data (1st correction data, 2nd correction data) for correcting each comparison circuit based on each such charging voltage can be generated individually, the delay state of both comparison circuits Even if there is a difference, it is possible to perform more appropriate correction.

  In the invention of claim 5, the charging voltage of the capacitor at the time when one of the first capacitor (C1) and the second capacitor (C2) is switched to the discharge target is the first capacitor (C1) and The value reflects the delay time from when the condition for switching any one of the second capacitors (C2) to discharge is established until the capacitor is actually started to be discharged. Becomes relatively large, and the charging voltage becomes relatively small when the delay time is small. Therefore, either one of the first capacitor (C1) and the second capacitor (C2) at the time when one of the capacitors is switched to the discharge target, or each of the capacitors whose capacitors are switched to the discharge target, respectively. If the correction data is generated based on each charging voltage at the time, it is possible to generate the correction data appropriately considering the delay time. Furthermore, the present invention is configured to be switched by the switching control circuit (8) so that the charging voltage of the capacitor to be charged among the first capacitor (C1) and the second capacitor (C2) becomes the input voltage of the comparison circuit. Therefore, the number of comparison circuits can be reduced, and the circuit configuration can be simplified.

  According to a sixth aspect of the present invention, the switching control circuit (8) switches the charging target to be the other capacitor when the charging voltage of one of the charging target capacitors becomes equal to or higher than the predetermined threshold value. And after predetermined time passes from the switching timing, it is comprised so that switching of the next charging object may be permitted. That is, in this configuration, since the switching of the next charging target is not permitted for the predetermined time immediately after switching so that the charging target is the other capacitor, the comparison is made for a short time immediately after the switching (during the predetermined time). Even if the second signal continues from the circuit, it is possible to prevent the charging target from being further switched. Thereby, it is possible to prevent malfunctions until the signal from the comparison circuit returns to the first signal immediately after the charging target is switched.

  According to the seventh aspect of the present invention, correction data can be generated with a simple circuit structure in which any one charging voltage is detected and the charging voltage is compared with a representative voltage.

  According to the eighth aspect of the present invention, it is possible to separately detect the charging voltages of both capacitors and generate correction data in a form reflecting these charging voltages. That is, it is possible to generate more appropriate correction data that reflects the actual delay state of both capacitors.

According to a ninth aspect of the present invention, the correction unit includes an AD converter that converts a charging voltage of at least one of the first capacitor (C1) and the second capacitor (C2) into a digital signal. Further, the path of the signal input to the AD converter is connected to the first path connected to one of the first capacitor (C1) and the second capacitor (C2) and to another analog signal generation source. A route switching unit for switching to the second route.
According to this configuration, the AD converter can be used for AD conversion of a signal from another analog signal generation source and AD conversion of a capacitor charging voltage, and a configuration in which an AD converter is prepared separately. In comparison, the apparatus configuration can be simplified and the number of parts can be reduced.

FIG. 1 is a circuit diagram schematically illustrating an oscillation circuit according to the first embodiment of the invention. FIG. 2 is a circuit diagram schematically illustrating the configuration of the reference voltage generation unit in the oscillation circuit of FIG. FIG. 3 is a timing chart illustrating each signal used in the oscillation circuit of FIG. FIG. 4 is a circuit diagram schematically illustrating an oscillation circuit according to the second embodiment of the invention. FIG. 5 is a circuit diagram schematically illustrating the configuration of the reference voltage generation unit in the oscillation circuit of FIG. FIG. 6 is a timing chart illustrating each signal used in the oscillation circuit of FIG. FIG. 7 is a circuit diagram schematically illustrating an oscillation circuit according to the third embodiment of the invention. FIG. 8 is a circuit diagram schematically illustrating the configuration of the reference voltage generation unit in the oscillation circuit of FIG. FIG. 9 is a timing chart illustrating each signal used in the oscillation circuit of FIG. FIG. 10 is a circuit diagram schematically illustrating an oscillation circuit according to another embodiment in which a part of FIG. 1 is changed. FIG. 11 is a circuit diagram schematically illustrating an oscillation circuit according to the fourth embodiment of the invention. FIG. 12 is a timing chart illustrating each signal used in the oscillation circuit of FIG. FIG. 13 is a circuit diagram schematically illustrating an oscillation circuit according to the fifth embodiment of the invention. FIG. 14 is a timing chart illustrating each signal used in the oscillation circuit of FIG.

[First embodiment]
Hereinafter, a first embodiment embodying the present invention will be described with reference to the drawings.
The oscillation circuit 1 shown in FIG. 1 is provided, for example, so as to generate and output an oscillation signal in a semiconductor integrated circuit, and mainly includes a control unit 3, a correction unit 4, a storage device 5, a switching control circuit 8, The circuit includes a first comparison circuit 11, a second comparison circuit 13, a constant current source 15, a threshold setting circuit 20, a first capacitor C1, a second capacitor C2, and other switches.

  The control unit 3 is configured such that an output signal Q, which will be described later, is input as a trigger signal, and can output the control signals φ1, φ2 for a predetermined period at a predetermined timing (a rising timing of the output signal Q, which will be described later). Has been. In the normal mode (a mode in which a basic operation described later) is performed, the control unit 3 maintains the output signal φ1 at the L level and the output signal φ2 at the H level. On the other hand, in the mode in which the self-correction operation is performed, the output signal φ1 is maintained at the H level for a certain time and the output signal φ2 is maintained at the L level for a certain time using the rising edge of the output signal Q as a trigger. The control unit 3 may be configured by a known control circuit such as a microcomputer, and can output an H level output signal φ1 and an L level output signal φ2 for a certain period of time using a rise of the output signal Q as a trigger. Other circuits may be used as long as they are configured. Note that the switching from the normal mode to the mode for performing the self-correction operation in the control unit 3 may be performed periodically or when a predetermined condition is satisfied.

  The constant current source 15 is configured by a known constant current circuit that outputs a predetermined constant current, and functions to supply a charging current to the first capacitor C1 or the second capacitor C2.

  The first capacitor C1 and the second capacitor C2 are both configured to be able to conduct with the constant current source 15, and are charged with a constant current supplied from the constant current source 15. The first capacitor C1 is connected to the constant current source 15 via a switch SW10, which will be described later, and is charged when the switch SW10 is on and when the switch SW11 or SW12 is off, and the switch SW10 is off. And when the switches SW11 and SW12 are in the ON state, the discharge is performed. The second capacitor C2 is connected to the constant current source 15 via a switch SW10 'described later, and is connected in parallel with the first capacitor C1. The second capacitor C2 is charged when the switch SW10 ′ is on and the switch SW12 ′ is off, and is discharged when the switch SW10 ′ is off and the switch SW12 ′ is on. The

  The switching control circuit 8 includes a flip-flop circuit 9 and charge / discharge switching units 10a and 10b, and is charged from the constant current source 15 based on signals output from the first comparison circuit 11 and the second comparison circuit 13. Is switched to one of the first capacitor C1 and the second capacitor C2, and the other is to be discharged.

  The flip-flop circuit 9 is configured as a known RS flip-flop circuit, and the output signal Vset from the first comparison circuit 11 is input to the S terminal, and the output signal Vrst from the second comparison circuit 13 is input to the R terminal. It has come to be. The flip-flop circuit 9 outputs an H level signal from the Q terminal and an L level signal from the QB terminal when an H level signal is input to the S terminal and an L level signal is input to the R terminal. Further, when an H level signal is input to the R terminal and an L level signal is input to the S terminal, the L level signal is output from the Q terminal, and the H level signal is output from the QB terminal. When both the S terminal and R terminal inputs are at the L level, the output state up to that point is maintained, and the H level signal is not simultaneously input to the S terminal and the R terminal. .

  The charge / discharge switching unit 10a includes semiconductor switch elements (hereinafter also referred to as switches) SW10, SW11, SW12 and connection lines connected to these. The switch SW10 is configured as a P-channel type MOSFET, the source is connected to the output side of the constant current source 15, and the drain is connected to one end side of the first capacitor C1. The gate of the switch SW10 is connected to the Q terminal (output terminal) of the flip-flop circuit 9. The switch SW11 is configured as an N-channel MOSFET, and has a drain connected to the drain of the switch SW10 and one end of the first capacitor C1, and a source connected to the drain of the switch SW12. The gate of the switch SW11 is connected to the output terminal of the φ2 signal in the control unit 3. The switch SW12 is configured as an N-channel MOSFET, and has a drain connected to the source of the switch SW11 and a source connected to the ground. The gate of the switch SW12 is connected to the Q terminal (output terminal) of the flip-flop circuit 9.

  The charge / discharge switching unit 10b is connected in parallel to the charge / discharge switching unit 10a, and includes semiconductor switch elements (hereinafter also referred to as switches) SW10 'and SW12' and connection lines connected to these. The switch SW10 'is configured as a P-channel type MOSFET, the source is connected to the output side of the constant current source 15, and the drain is connected to one end side of the second capacitor C2. The gate of the switch SW10 'is connected to the QB terminal of the flip-flop circuit 9. The switch SW12 'is configured as an N-channel MOSFET, and has a drain connected to the drain of the switch SW10' and one end of the second capacitor C2, and a source connected to the ground. The gate of the switch SW12 'is connected to the QB terminal of the flip-flop circuit 9.

Both the first comparison circuit 11 and the second comparison circuit 13 are configured as known comparators.
The first comparison circuit 11 has a positive input terminal connected to one end of the first capacitor C1 via switches (switches SW31 and SW32), and when the switches (switches SW31 and SW32) are in an ON state. The charging voltage V1 of the first capacitor C1 is configured to be input as a positive input signal. The threshold value Vstd_comp set by the threshold setting circuit (reference voltage generation unit) 20 is input to the negative input terminal of the first comparison circuit 11. The threshold value Vstd_comp corresponds to an example of a first threshold value that serves as a comparison reference in the first comparison circuit 11. The first comparison circuit 11 outputs an L level signal when the charging voltage V1 charged in the first capacitor C1 is less than the threshold value Vstd_comp (first threshold value) in the normal mode in which the switches SW31 and SW32 are in the on state. (First signal) is output, and when the charging voltage V1 charged in the first capacitor C1 is equal to or higher than a threshold value Vstd_comp (first threshold value), an H level signal (second signal different from the first signal) is output. To function.

The second comparison circuit 13 has a positive input terminal connected to one end of the second capacitor C2, and is configured to input the charging voltage V2 of the second capacitor C2 as a positive input signal. The threshold value Vstd_comp set by the threshold setting circuit (reference voltage generation unit) 20 is input to the negative input terminal of the second comparison circuit 13. The threshold value Vstd_comp corresponds to an example of a second threshold value that serves as a comparison reference in the second comparison circuit 13. The second comparison circuit 13 outputs an L level signal (third signal) when the charging voltage V2 charged in the second capacitor C2 is less than a threshold value Vstd_comp (second threshold value), and charges the second capacitor C2. It functions to output an H level signal (a fourth signal different from the third signal) when the charged voltage V2 is equal to or higher than the threshold value Vstd_comp (second threshold value).
The first comparison circuit 11 and the second comparison circuit 13 are generally good to use a comparator circuit having hysteresis in order to be strong against noise.

  The correction unit 4 includes a storage device 5 and an AD converter 7. The correction unit 4 discharges the first capacitor C1 by the switching control circuit 8 in response to the output from the first comparison circuit 11 being switched from the first signal (L level signal) to the second signal (H level signal). A common value set by the threshold setting circuit 20 based on the charging voltage V1 of the first capacitor C1 at the time when the switch is switched to the target (that is, the time when the switch SW10 is turned off and the switch SW12 is turned on). Correction data used to correct the threshold values (first threshold value, second threshold value) is generated. The generation of correction data will be described in detail later.

  The storage device 5 is configured by a known semiconductor memory or the like, and stores information (reference code) that can specify a voltage that is a reference for threshold setting in the threshold setting circuit 20. The reference code is a value for setting the reference voltage Vstd so that the oscillation circuit 1 has a desired oscillation frequency when the device temperature of the oscillation circuit 1 is a typical specific temperature (for example, 20 ° C.). When the reference voltage Vstd is set, the charging voltage V1 at the start of discharging the first capacitor C1 becomes a unique representative voltage V1typ in a self-correction mode to be described later. The digital data of the difference voltage between the representative voltage V1typ and the reference voltage Vstd is defined to be a reference code.

  The AD converter 7 is configured by a known AD converter. The AD converter 7 is connected to the first capacitor C1 via switches (switches SW21 and SW22), and the charging voltage V1 of the first capacitor C1 can be input. The switch SW21 is configured as an N-channel MOSFET, and has a drain connected to one end of the capacitor C1 and the drain of the switch SW10, and a source connected to one input side of the AD converter 7. The gate of the switch SW21 is connected to the output terminal of the output signal φ1 in the control unit 3. Further, the switch SW22 is configured as a P-channel type MOSFET, the source is connected to one end side of the capacitor C1 and the drain of the switch SW10, and the drain is connected to one input side of the AD converter 7. The gate of the switch SW22 is connected to the output terminal of the output signal φ2 in the control unit 3. Further, the reference voltage Vstd generated by the threshold setting circuit 20 is input to the AD converter 7, and the charging voltage of the first capacitor C1 at the timing when the switches SW21 and SW22 are turned on. It functions to convert the difference voltage between V1 and the reference voltage Vstd into a digital signal.

  The threshold value setting circuit 20 functions to set a threshold value (a common value used as the first threshold value and the second threshold value) as a comparison reference in the first comparison circuit 11 and the second comparison circuit 13. The threshold setting circuit 20 is configured as shown in FIG. 2, for example, and the reference code output from the storage device 5 and the correction code output from the AD converter 7 (switches SW21 and SW22 are turned on). The reference voltage Vstd and the threshold value Vstd_comp (a common value used as the first threshold value and the second threshold value) are output with the input of the charging voltage V1 of the first capacitor C1 and the reference voltage Vstd at the timing. Is configured to do.

  In the threshold setting circuit 20, resistors R1 to Rm are connected in series between a predetermined power source and the ground, and one ends of switches X1 to Xn made of MOSFETs, bipolar transistors, or the like are connected between the resistors, An output line of the reference voltage Vstd is connected to each other end of the switches X1 to Xn. The control terminals of the switches X1 to Xn are connected to n terminals provided in the decoder 21, and each switch X1 to Xn is turned on when the corresponding terminal in the decoder 21 becomes H level. When the corresponding terminal in the decoder 21 becomes L level, it is switched to the off state. Further, between the resistors, one ends of switches Y1 to Yn made of MOSFETs or bipolar transistors are connected, and an output line for outputting a threshold value Vstd_comp is connected to the other ends of the switches Y1 to Yn. . The control terminals of the switches Y1 to Yn are connected to n terminals provided in the decoder 25, and the switches Y1 to Yn are turned on when the corresponding terminals in the decoder 25 become H level. When the corresponding terminal in the decoder 25 becomes L level, it is switched to the off state. In this configuration, when the reference code read from the storage device 5 is input to the decoder 21, the state of each terminal of the decoder 21 corresponds to the reference code, and corresponds to the reference code for each of the switches X1 to Xn. Are output in parallel. As a result, the reference voltage Vstd corresponding to the reference code is output. In addition, when information (correction code) for specifying a correction value is held in the storage unit 23 and input to the decoder 25, the state of each terminal of the decoder 25 becomes a state corresponding to the correction code, and each switch Y1 to Yn has a state. On the other hand, signals corresponding to the correction codes are output in parallel. In this configuration, the state of the switches Y1 to Yn can be switched by changing the correction code, and the output threshold value Vstd_comp can be increased or decreased. In the initial setting after the oscillation circuit 1 is started, the reference code is held in the storage unit 23, and the threshold Vstd_comp is set to output the same voltage as the reference voltage Vstd.

Next, the operation of the oscillation circuit 1 will be described.
First, the basic operation of the oscillation circuit 1 will be described. The basic operation is an operation when the output signal φ1 from the control unit 3 is at L level and the output signal φ2 is at H level. That is, during the basic operation, the switches SW11, SW31, and SW32 are always on, and the switches SW21, SW22, and SW4 are always off.

  During this basic operation, since the switch SW10 is in the on state and the switch SW12 is in the off state while the output signal Q from the flip-flop circuit 9 is at the L level after the time T1 in FIG. The first capacitor C1 is charged by the charging current from the source 15. At this time, the output signal QB is at the H level, the switch SW10 'is turned off, and the switch SW12' is turned on, so that the second capacitor C2 is discharged. In this operation, while the charging voltage V1 of the first capacitor C1 is less than the threshold value Vstd_comp, the first comparison circuit 11 outputs an L level signal (output of “0”). On the other hand, when the charging voltage V1 of the first capacitor C1 exceeds the threshold value Vstd_comp, the first comparison circuit 11 outputs an H level signal (output “1”) (see the Vset signal from time T2: FIG. 3).

  When an H level signal is output from the first comparison circuit 11 (“1” output), the output signal Q of the flip-flop circuit 9 is switched to H level (“1” signal), and the output signal QB is L level. (Refer to output signals Q and QB from time T2). As from time T2, after the output signal Q from the flip-flop circuit 9 is at the H level, the switch SW10 is turned off and the switch SW12 is turned on. During the basic operation, the output signal φ2 is maintained at the H level. Since the switch SW11 is also in the on state, the current supply from the constant current source 15 to the first capacitor C1 is cut off, and the first capacitor C1 is discharged. On the other hand, while the output signal QB from the flip-flop circuit 9 is at the L level, the switch SW10 ′ is turned on and the switch SW12 ′ is turned off, so that the second capacitor C2 is driven by the charging current from the constant current source 15. Charged. In this operation, while the charging voltage V2 of the second capacitor C2 is less than the threshold value Vstd_comp, the second comparison circuit 13 outputs an L level signal (output of “0”). On the other hand, when the charging voltage V2 of the second capacitor C2 exceeds the threshold value Vstd_comp, the second comparison circuit 13 outputs an H level signal (output “1”) (see the Vrst signal from time T3: FIG. 3). As a result, the output signals Q and QB are inverted again (see time T3 in FIG. 3). By repeating such an operation, the output signal Q and the output signal QB become oscillation signals having a predetermined period.

Next, the self correction operation will be described.
In the oscillation circuit 1 according to the present embodiment, the control unit 3 switches from a mode in which the basic operation is performed periodically or when a predetermined condition is satisfied to a mode in which a self-correction operation is performed (self-correction mode). When the mode is switched to the self-correction operation mode, the control unit 3 inverts the output signals φ1 and φ2 at the rising timing of the output signal Q from the flip-flop circuit 9, sets the output signal φ1 to the H level, and outputs The state where the signal φ2 is set to the L level is maintained for a certain time.

  During this fixed time, since the switch SW10 is turned off from the rising edge of the output signal Q, charging is prevented and the switch SW11 is turned off, so that the discharge from the first capacitor C1 via the switch SW11 is also performed. Be blocked. In this configuration, the switch SW31 is configured as a P-channel MOSFET, the source is connected to one end of the capacitor C1 and the drain of the switch SW10, and the drain is an input terminal on the positive side of the first comparison circuit 11. It is connected to the. The gate of the switch SW31 is connected to the output terminal of the output signal φ1 in the control unit 3. Further, the switch SW32 is configured as an N-channel MOSFET, the drain is connected to one end of the capacitor C1 and the drain of the switch SW10, and the source is connected to the positive input terminal of the first comparison circuit 11. Yes. The gate of the switch SW32 is connected to the output terminal of the output signal φ2 in the control unit 3. Therefore, since the H level signal is input to the switch SW31 and the L level signal is input to the switch SW32 during the predetermined period, the switches SW31 and SW32 are turned off, and the first capacitor C1 and the first comparison circuit 11 are turned off. Is also cut off. The switch SW4 is configured as an N-channel type MOSFET, and the drain is connected between the switches (switches SW31 and SW32) and the positive input terminal of the first comparison circuit 11, and the source is connected to the ground. The gate of the switch SW4 is connected to the output terminal of the output signal φ1 in the control unit 3. Accordingly, since the H level signal is input to the gate of the switch SW4 during the predetermined period and is turned on, the input on the positive side of the first comparison circuit 11 is fixed to the ground level, thereby preventing malfunction.

  On the other hand, since the switches SW21 and SW22 are turned on, the charging voltage V1 when the charging of the first capacitor C1 is stopped is input to one side of the AD converter 7. The charging voltage at the time of stopping charging is the charging voltage at the time when the first capacitor C1 is switched from the charging target to the discharging target during the basic operation (that is, the charging voltage from the state where the first capacitor C1 was the charging target). When V1 exceeds the threshold value Vstd_comp, an H level signal is output from the first comparison circuit 11, and this corresponds to a charging voltage at the time of switching when the output signal Q is switched to the H level. The reference voltage Vstd is input to the other input of the AD converter 7. At this time, the AD converter 7 generates digital data of a difference voltage between the charging voltage V1 and the reference voltage Vstd at the time when the charging of the capacitor C1 is stopped (when the capacitor C1 is switched to the discharge target).

  Here, the concept of correction will be described. If a change in delay time due to a change in the device temperature of the oscillation circuit 1 from a typical specific temperature is Δt, it can be calculated by Δt = C / I × {(V1−Vstd) − (V1typ−Vstd)}. C is a capacitance (constant) of the capacitor C1, I is a charging current value (constant) from the constant current source 15, and V1 is a measured value of the charging voltage after temperature change (the self-correction mode). V1typ is a charging voltage at a typical specific temperature (the self-correction mode is performed when the device temperature of the oscillation circuit 1 is a typical specific temperature). The charging voltage (constant) of the capacitor C1 when charging is stopped. Vstd is a reference voltage (constant) generated by the threshold setting circuit 20.

  “V1 typ−Vstd” (reference difference voltage) in the above equation is obtained when the self-correction mode is performed in a typical state (that is, a state where the device temperature of the oscillation circuit 1 is a representative specific temperature). When the charging is stopped (that is, when the charging voltage V1 exceeds the threshold value Vstd_comp from the state in which the first capacitor C1 is charged), an H level signal is output from the first comparison circuit 11, and the output signal Q becomes H level. The charging voltage of the capacitor C1 at the time of switching), and the A / D conversion result is held in the storage device 5 as a reference code. Since C / I is a constant, a difference voltage of (V1−Vstd) − (V1typ−Vstd), that is, “V1−Vstd” (AD conversion value measured in the self-correction mode) and “V1typ−Vstd” ( The difference voltage (reference difference voltage) is proportional to Δt. That is, the AD conversion value “V1-Vstd” measured in the self-correction mode is data including information on the difference between the delay time in the typical state and the delay time changed due to the temperature change from the typical state. It can be said that there is.

  When the AD conversion value “V1−Vstd” measured in the self-correction mode is larger than the reference difference voltage “V1typ−Vstd”, that is, V1> V1typ (V1typ is an example of a predetermined representative voltage). The oscillation frequency is lower than in the typical state, and the AD conversion value “V1−Vstd” measured in the self-correction mode is smaller than the reference differential voltage “V1typ−Vstd”. In other words, when V1 <V1typ, it can be said that the oscillation frequency is higher than that in the typical state. Therefore, the threshold setting circuit 20 (reference voltage generation unit) inputs the AD conversion value “V1-Vstd” (correction code) measured in the self-correction mode, holds it in the storage unit 23, and decodes the correction code into the decoder. Decode at 25. Then, the switches Y1 to Yn are operated according to the decoding result, and the voltage corrected based on the correction code is output as the threshold value Vstd_comp.

  Specifically, when the AD conversion value “V1−Vstd” measured in the self-correction mode is larger than the reference difference voltage “V1typ−Vstd”, that is, V1> V1typ (V1typ is a predetermined representative voltage). In the case where the threshold Vstd_comp is lower than the value in the typical state (that is, the threshold Vstd_comp = Vstd (reference value) when the device temperature of the oscillation circuit 1 is a typical specific temperature)). And increase the oscillation frequency to match the oscillation frequency in the typical state. Conversely, when the AD conversion value “V1−Vstd” measured in the self-correction mode is smaller than the reference difference voltage “V1typ−Vstd”, that is, when V1 <V1typ, the threshold value Vstd_comp is set to the typical state. Correction is made to be higher than the current value (reference value), and the oscillation frequency is lowered to match the oscillation frequency in the typical state. For example, in the example of FIG. 3, the self-correction operation is performed between times T <b> 3 and T <b> 5, and the AD conversion value “V1−Vstd” is acquired by the AD converter 7. Since the AD conversion value “V1−Vstd” is larger than the reference difference voltage “V1typ−Vstd”, the threshold value Vstd_comp is a value (reference value) at a timing after a predetermined time from the time T5. The oscillation frequency is increased to match the oscillation frequency in the typical state. As shown in FIG. 3, it is desirable to reflect the corrected threshold value Vstd_comp immediately after the discharge operation of the second capacitor C2 starts so as not to affect the charging operation of the first capacitor C1.

  Thus, in this configuration, the correction unit 4 detects the charging voltage V1 of the first capacitor C1 at the time when the first capacitor C1 is switched to the discharge target by the switching control circuit 8, and the detected charging voltage is detected. When V1 exceeds a predetermined representative voltage V1typ (that is, V1> V1typ), correction data for generating a threshold value Vstd_comp lower than a predetermined reference value (threshold value set in the typical state) is generated. When the detected charging voltage V1 is less than the representative voltage V1typ, correction data for generating a threshold value Vstd_comp higher than a predetermined reference value (threshold value set in the typical state) is generated. In the oscillation circuit 1, the upper limit value and the lower limit value of the correction code are determined in advance, and when correction data exceeding the upper limit is input to the decoder 25, the decoder 25 sets the set upper limit value to the switch Y1. When the correction data that is lower than the lower limit is input to the decoder 25, the set lower limit value is output to the switches Y1 to Yn.

(Main effects of the first embodiment)
In the first embodiment, the charging voltage V1 of the first capacitor C1 at the time when the first capacitor C1 is switched to the discharge target is the time when the condition for switching the first capacitor C1 to the discharge target is satisfied in the first comparison circuit 11. This is a value reflecting a delay time from when the charging voltage V1 reaches the threshold value Vstd_comp until the discharge of the first capacitor C1 is actually started. If the delay time is large, the charging voltage V1 is relative. If the delay time is small, the charging voltage V1 becomes relatively small. Therefore, if the correction data is generated based on the charging voltage V1 of the first capacitor C1 at the time when the first capacitor C1 is switched to the discharge target, the correction data can be generated in consideration of the delay time appropriately. .

  Further, in this configuration, since the threshold value used for each comparison circuit can be shared, the arithmetic processing can be simplified. Furthermore, correction data can be generated with a simple circuit structure in which only the charging voltage V1 of the first capacitor C1 is detected and the charging voltage V1 is compared with the reference voltage Vstd. In particular, a change in delay time due to temperature characteristics can be corrected without using a special temperature sensor or the like, which is more advantageous in reducing the number of parts and simplifying the device configuration.

[Second Embodiment]
Next, a second embodiment will be described with reference to FIGS.
In the second embodiment, as shown in FIGS. 4 and 6, the control unit 3 can output the output signals φ1 ′ and φ2 ′ in addition to the same output signals φ1 and φ2 as in the first embodiment. The point that the switches SW11 ′, SW21 ′, SW22 ′, SW31 ′, SW32 ′, and SW4 ′ are added, and the generation method of the correction code in the AD converter 7 and the average value generation unit (hereinafter also referred to as the average unit) 26 are first. Unlike the first embodiment, the other configuration is the same as that of the first embodiment. Therefore, configurations other than these (same points as in the first embodiment) are denoted by the same reference numerals as those in the first embodiment, and detailed description thereof is omitted.

  In the oscillation circuit 1 of the second embodiment, an output signal Q is input as a trigger signal in the control unit 3. In the normal mode (the mode in which the basic operation similar to that of the first embodiment is performed), the control unit 3 maintains the output signal φ1 at the L level, maintains the output signal φ2 at the H level, and outputs the output signal φ1 ′. Is maintained at the L level, and the output signal φ2 ′ is maintained at the H level. On the other hand, in the mode in which the self-correction operation is performed, the output signal φ1 ′ is maintained at the H level for a certain time and the output signal φ2 ′ is maintained at the L level for a certain time by using the falling edge of the output signal Q as a trigger. Further, with the rising edge of the output signal Q as a trigger, the output signal φ1 is maintained at the H level for a certain time and the output signal φ2 is maintained at the L level for the certain time. The control unit 3 may be configured by a known control circuit such as a microcomputer, or may be another circuit as long as the signal can be output using the rising and falling edges of the output signal Q as a trigger. Note that the switching from the normal mode to the mode for performing the self-correction operation in the control unit 3 may be performed periodically or when a predetermined condition is satisfied.

In the oscillation circuit 1 according to the present embodiment, the oscillation operation during the basic operation is the same as that of the first embodiment.
During this basic operation, the control unit 3 outputs the L level signal φ1, the H level signal φ2, the L level signal φ1 ′, and the H level signal φ2 ′, as described above. SW22, SW21 ′, SW22 ′, SW4, and SW4 ′ are all turned off, and switches SW11, SW11 ′, SW31, SW32, SW31 ′, and SW32 ′ are all turned on.

  Also in the present embodiment, the control unit 3 switches from the mode in which the basic operation is performed periodically or when a predetermined condition is satisfied to the mode in which the self-correction operation is performed (self-correction mode). When the mode is switched to the self-correction operation mode, the control unit 3 outputs the output signals φ1 ′ and φ2 ′ at the falling timing of the output signal Q from the flip-flop circuit 9, as at time T3 in FIG. Inverted, the output signal φ1 ′ is set to the H level, and the output signal φ2 ′ is set to the L level and maintained for a certain time.

  During this fixed time, the switch SW10 ′ is turned off from the fall of the output signal Q (that is, the rise of the output signal QB), so that charging of the capacitor C2 is prevented and the switch SW11 ′ is turned off. Therefore, the discharge from the second capacitor C2 via the switch SW11 ′ is also prevented. In this configuration, the switch SW31 ′ is configured as a P-channel MOSFET, the source is connected to one end of the capacitor C2 and the drain of the switch SW10 ′, and the drain is on the positive side of the second comparison circuit 13. Connected to the input terminal. Further, the gate of the switch SW 31 ′ is connected to the output terminal of the output signal φ 1 ′ in the control unit 3. Further, the switch SW32 ′ is configured as an N-channel MOSFET, the drain is connected to one end of the capacitor C2 and the drain of the switch SW10 ′, and the source is connected to the positive input terminal of the second comparison circuit 13. Has been. The gate of the switch SW 32 ′ is connected to the output terminal of the output signal φ 2 ′ in the control unit 3. Accordingly, since the H level signal is input to the switch SW31 ′ and the L level signal is input to the switch SW32 ′ during the predetermined period, the switches SW31 ′ and SW32 ′ are turned off, and the second capacitor C2 and the second capacitor C2 The energization state with the 2 comparison circuit 13 is also cut off. The switch SW4 ′ is configured as an N-channel MOSFET, and the drain is connected between the switches (switches SW31 ′ and SW32 ′) and the positive input terminal of the second comparison circuit 13, and the source Is connected to the ground, and the gate of the switch SW4 ′ is connected to the output terminal of the output signal φ1 ′ in the control unit 3. Therefore, since the H level signal is input to the gate of the switch SW4 'during the predetermined period and is turned on, the input on the positive side of the second comparison circuit 13 is fixed at the ground level, thereby preventing malfunction.

  On the other hand, since the switches SW21 ′ and SW22 ′ are in the on state and the switches SW21 and SW22 are maintained in the off state during the predetermined period, the charging of the second capacitor C2 is stopped at one side of the AD converter 7. The charging voltage V2 at is input. The charging voltage at the time of stopping the charging is the charging voltage at the time when the second capacitor C2 is switched from the charging target to the discharging target during the basic operation (that is, the charging voltage from the state where the second capacitor C2 was the charging target). When V2 exceeds the threshold value Vstd_comp, an H level signal is output from the second comparison circuit 13, and this corresponds to the charging voltage at the time of switching when the output signal QB is switched to the H level. The reference voltage Vstd is input to the other input of the AD converter 7. At this time, the AD converter 7 generates digital data of a difference voltage between the charging voltage V2 and the reference voltage Vstd at the time when the charging of the second capacitor C2 is stopped (when it is switched to the discharge target). This digital data is input as the correction code 2 to the averaging unit 26 described later.

  Thus, after the digital data of the difference voltage between the charging voltage V2 and the reference voltage Vstd at the time when the charging of the second capacitor C2 is stopped (the time when the second capacitor C2 is switched to the discharge target) is generated, the output signal φ1 ′ is The output signal φ2 ′ is returned to the H level by returning to the L level. Then, the output signals φ1 and φ2 are inverted at the rising timing of the output signal Q from the flip-flop circuit 9 (time T4 in FIG. 6), the output signal φ1 is set to H level, and the output signal φ2 is set to L level. Maintain the state for a certain period of time. Thereby, the correction code 1 is generated by the same method as the method of generating the correction code in the first embodiment. That is, since the switch SW10 is in an off state from the rising edge of the output signal Q during this fixed time, charging is blocked and the switch SW11 is in an off state, so that the switch SW11 from the first capacitor C1 passes through the switch SW11. Discharge is also prevented. Further, since the H level signal is input to the gate of the switch SW31 and the L level signal is input to the gate of the switch SW32 during the predetermined period, the switches SW31 and SW32 are turned off, and the first capacitor C1 and the first capacitor C1 are connected. The energization state with the 1 comparison circuit 11 is also cut off. Further, since the H level signal is input to the gate of the switch SW4 during the predetermined period, the positive side input of the first comparison circuit 11 is fixed to the ground level, thereby preventing malfunction.

  On the other hand, since the switches SW21 and SW22 are turned on, the charging voltage V1 when the charging of the first capacitor C1 is stopped is input to one side of the AD converter 7. The charging voltage at the time of stopping charging is the charging voltage V1 when the first capacitor C1 is switched from the charging target to the discharging target during the basic operation (that is, charging from the state where the first capacitor C1 was the charging target). When the voltage V1 exceeds the threshold value Vstd_comp, an H level signal is output from the first comparison circuit 11, and this corresponds to the charging voltage at the time when the output signal Q is switched to the H level. The reference voltage Vstd is input to the other input of the AD converter 7. At this time, the AD converter 7 generates digital data of the difference voltage between the charging voltage V1 and the reference voltage Vstd at the time when the charging of the capacitor C1 is stopped (when the capacitor C1 is switched to the discharge target), and the digital data is corrected. The code 1 is input to the averaging unit 26 described later.

  In this configuration, the correction code 1 input to the averaging unit 26 as described above (the difference voltage between the charging voltage V1 and the reference voltage Vstd at the time when the first capacitor C1 is switched from the charging target to the discharging target). And the average value of the correction code 2 (the difference voltage between the charging voltage V2 and the reference voltage Vstd at the time when the second capacitor C2 is switched from the charging target to the discharging target) is obtained, and this is stored as a “correction code” in the storage unit 27. Hold on.

  The correction method after the correction code is stored in the storage unit 27 (the method for generating the threshold value Vstd_comp in the threshold setting circuit 20) is the same as that in the first embodiment. That is, the threshold setting circuit 20 (reference voltage generation unit) finally calculates the average value “(V1 + V2) / 2−Vstd” of the AD conversion values (correction code 1, correction code 2) measured in the self-correction mode. The correction code is input and held in the storage unit 23, and the correction code is decoded by the decoder 25. Then, the switches Y1 to Yn are operated according to the decoding result, and the voltage corrected based on the correction code is output as the threshold value Vstd_comp.

  Specifically, when the average value “(V1 + V2) / 2−Vstd” of the AD conversion values (correction codes 1 and 2) measured in the self-correction mode is larger than the reference difference voltage “Vtyp−Vstd”. That is, when (V1 + V2) / 2> Vtyp, the threshold Vstd_comp is corrected to a value lower than the value (reference value) in the typical state, and the oscillation frequency is adjusted to match the oscillation frequency in the typical state. Make it high. Conversely, when the AD conversion value “(V1 + V2) / 2−Vstd” measured in the self-correction mode is smaller than the reference difference voltage “Vtyp−Vstd”, that is, (V1 + V2) / 2 <Vtyp. Corrects the threshold value Vstd_comp to be higher than the value (reference value) in the typical state, and lowers the oscillation frequency to match the oscillation frequency in the typical state. For example, in the example of FIG. 6, the self-correction operation is performed between times T3 and T5, and the average value “(V1 + V2) / 2−Vstd” of the AD conversion values is acquired. Since the average value “(V1 + V2) / 2−Vstd” of the AD conversion values is larger than the reference difference voltage “Vtyp−Vstd”, the threshold value Vstd_comp is typically set at a timing after a predetermined time from time T5. Correction is made to be lower than the value at the state (reference value), and the oscillation frequency is increased to match the oscillation frequency in the typical state. Note that Vtyp corresponds to an example of a predetermined representative voltage, and may be set in the same manner as in the first embodiment. When the device temperature of the oscillation circuit 1 is a representative specific temperature, An average value of the charging voltage V1 of the first capacitor C1 at the time of stopping charging and the charging voltage V2 of the second capacitor C2 at the time of stopping charging when the self-correction mode is performed may be used.

  As described above, also in this configuration, the threshold setting circuit 20 is configured such that the threshold serving as the comparison reference in the first comparison circuit 11 (first threshold) and the threshold serving as the comparison reference in the second comparison circuit 13 (second threshold). Are set as the same value. And the correction | amendment part 4 detects the charge voltage V1 of the said 1st capacitor | condenser C1 in the time (time T4 of FIG. 6) when the 1st capacitor | condenser C1 was switched to discharge object by the switching control circuit 8 in self correction | amendment mode, The charging voltage V2 of the second capacitor C2 is detected at the time when the second capacitor C2 is switched to the discharge target (time T3 in FIG. 6). Further, when the statistical values (specifically, average values) reflecting the detected charging voltage V1 of the first capacitor C1 and the charging voltage V2 of the second capacitor C2 exceed the predetermined representative voltage Vtyp, the predetermined state Correction data for lowering the threshold value Vstd_comp so as to match the oscillation frequency in the above (typical state) is generated, and when the statistical value (average value) is less than the representative voltage Vtyp, in the predetermined state (the above typical state) Correction data for increasing the threshold value Vstd_comp so as to match the oscillation frequency is generated.

  The configuration of the second embodiment can achieve the same effects as the first embodiment, and the configuration of the second embodiment can also share the threshold value used for each comparison circuit, thus simplifying the arithmetic processing. Can be planned. Furthermore, since the charging voltages V1 and V2 of both capacitors can be detected separately, the correction data can be generated in a form reflecting these charging voltages V1 and V2, that is, reflecting both delay times of both comparison circuits. Even when there is a difference between the delay states of the two comparison circuits, it can be corrected more appropriately.

[Third Embodiment]
Next, a third embodiment will be described with reference to FIGS.
The third embodiment differs from the second embodiment only in the configuration of the threshold setting circuit 20, and is otherwise the same as the second embodiment. Therefore, portions other than the threshold setting circuit 20 are denoted by the same reference numerals as those in the second embodiment, and detailed description thereof is omitted.

  In the present embodiment, as shown in FIGS. 7 and 8, the threshold setting circuit 20 can set the first threshold Vstd_comp1 and the second threshold Vstd_comp2 separately, and the first comparison circuit 11 includes the first capacitor C1. An H level signal (second signal) is output when the charging voltage V1 of the current voltage reaches the first threshold value Vstd_comp1, and an L level signal (first signal) is output when the charging voltage V1 is less than the first threshold value Vstd_comp1. It has become. The second comparison circuit 13 outputs an H level signal (fourth signal) when the charging voltage V2 of the second capacitor C2 reaches the second threshold value Vstd_comp2, and the charging voltage V2 is less than the second threshold value Vstd_comp2. Sometimes an L level signal (third signal) is output.

  Also in the oscillation circuit 1 according to the present embodiment, the oscillation operation during the basic operation is the same as in the first and second embodiments, and the switching control circuit 8 receives an H level signal (second signal) from the first comparison circuit 11. When it is output, control is performed to switch the first capacitor C1 from the charging target to the discharging target, and when the H level signal (fourth signal) is output from the second comparison circuit 13, the second capacitor C2 is discharged from the charging target. Control to switch to the target. In the basic operation, since the control unit 3 outputs the L level signal φ1, the H level signal φ2, the L level signal φ1 ′, and the H level signal φ2 ′, the switches SW21, SW22, SW21 ′, SW22 ′, SW4, and SW4 ′ are all turned off, and SW11, SW11 ′, and the switches SW31, SW32, SW31 ′, and SW32 ′ are all turned on.

  Also in the present embodiment, the control unit 3 switches from the mode in which the basic operation is performed periodically or when a predetermined condition is satisfied to the mode in which the self-correction operation is performed (self-correction mode). The generation method of the correction codes 1 and 2 in this self-correction mode is the same as that in the second embodiment. That is, when the mode is switched to the mode for performing the self-correction operation, the control unit 3 outputs the output signals φ1 ′ and φ2 at the falling timing of the output signal Q from the flip-flop circuit 9, as at time T3 in FIG. 'Is inverted, the output signal φ1' is set to the H level, and the state where the output signal φ2 'is set to the L level is maintained for a certain time. As a result, the AD converter 7 obtains the digital data (correction code 2) of the difference voltage between the charging voltage V2 and the reference voltage Vstd at the time when the charging of the second capacitor C2 is stopped (when it is switched to the discharge target). Generate and output in the same way as in the second embodiment.

  After generating the correction code 2 in this way, the output signal φ1 'is returned to the L level, and the output signal φ2' is returned to the H level. Then, the output signals φ1 and φ2 are inverted at the rising timing of the output signal Q from the flip-flop circuit 9 (time T4 in FIG. 9), the output signal φ1 is set to H level, and the output signal φ2 is set to L level. Maintain the state for a certain period of time. As a result, the AD converter 7 uses the same method as in the second embodiment to calculate the correction code 1 (the charging voltage V1 and the reference voltage Vstd at the time when the charging of the first capacitor C1 is stopped) Digital data of the difference voltage of

Next, a threshold setting method in the threshold setting circuit 20 will be described.
In the threshold value setting circuit 20, the first threshold value Vstd_comp1, the first threshold value Vstd_comp1, and the second threshold value are calculated based on the AD conversion values (“V1-Vstd” (correction code 1), “V2-Vstd” (correction code 2)) measured in the self-correction mode. 2 The threshold value Vstd_comp2 is set.

  The method of setting the first threshold value based on “V1−Vstd” (correction code 1) is the same as the threshold value setting method in the first embodiment, and “V1−Vstd” (correction code 1) is a reference difference. When the voltage is higher than “V1typ−Vstd”, that is, when V1> V1typ, the AD conversion value “V1−Vstd” (correction code 1) measured in the self-correction mode is input and held in the storage unit 23. At the same time, the correction code 1 is decoded by the decoder 25. Then, the switches Y1 to Yn are operated according to the decoding result, and the voltage corrected based on the correction code is output as the first threshold value Vstd_comp1.

  Specifically, when the AD conversion value “V1−Vstd” measured in the self-correction mode is larger than the reference difference voltage “V1typ−Vstd”, that is, when V1> V1typ, the first threshold value Vstd_comp1. Is corrected to a value lower than the value in the typical state (that is, the first threshold value Vstd_comp (first reference value) when the device temperature of the oscillation circuit 1 is a typical specific temperature). Raise the oscillation frequency to match the oscillation frequency. Conversely, when the AD conversion value “V1−Vstd” measured in the self-correction mode is smaller than the reference difference voltage “V1typ−Vstd”, that is, when V1 <V1typ, the first threshold value Vstd_comp1 is typically set. Correction is made to be higher than the value in the state (first reference value), and the oscillation frequency is lowered to match the oscillation frequency in the typical state. For example, in the example of FIG. 9, the self-correction operation is performed between times T <b> 3 and T <b> 5, and the AD conversion value “V1−Vstd” is acquired by the AD converter 7. Since the AD conversion value “V1−Vstd” is larger than the reference difference voltage “V1typ−Vstd”, the value when the first threshold value Vstd_comp1 is in the typical state at a timing after a predetermined time from the time T4. The oscillation frequency is corrected to be lower than (first reference value), and the oscillation frequency is increased so as to match the oscillation frequency in the typical state. Note that V1typ corresponds to an example of a predetermined representative voltage, and can be set similarly by the same method as V1typ in the first embodiment. For example, when the self-correction mode is performed when the device temperature of the oscillation circuit 1 is a typical specific temperature, the charging voltage V1 of the first capacitor C1 at the time of charging stop (time T4 in FIG. 9) is representative. The voltage may be V1typ.

  The method of setting the second threshold value Vstd_comp2 based on “V2-Vstd” (correction code 2) is basically the same as the setting of the first threshold value, and “V2-Vstd” (correction code 2) is the reference. When the difference voltage is larger than “V2typ−Vstd”, that is, when V2> V2typ, the AD conversion value “V2−Vstd” (correction code 2) measured in the self-correction mode is input and the storage unit 27 At the same time, the correction code 2 is decoded by the decoder 29. Then, the switches Z1 to Zn are operated according to the decoding result, and the voltage corrected based on the correction code 2 is output as the second threshold value Vstd_comp2.

  Specifically, when the AD conversion value “V2−Vstd” measured in the self-correction mode is larger than the reference difference voltage “V2typ−Vstd”, that is, when V2> V2typ, the second threshold value Vstd_comp2 Is corrected to a value lower than the value in the typical state (that is, the second threshold value Vstd_comp (second reference value) when the device temperature of the oscillation circuit 1 is a typical specific temperature). Raise the oscillation frequency to match the oscillation frequency. Conversely, when the AD conversion value “V2−Vstd” measured in the self-correction mode is smaller than the reference difference voltage “V2typ−Vstd”, that is, when V2 <V2typ, the second threshold value Vstd_comp2 is typically set. Correction is made to be higher than the value in the state (second reference value), and the oscillation frequency is lowered to match the oscillation frequency in the typical state. For example, in the example of FIG. 9, the self-correction operation is performed between times T <b> 3 and T <b> 5, and the AD converter 7 acquires the AD conversion value “V2−Vstd”. Since the AD conversion value “V2−Vstd” is larger than the reference difference voltage “V2typ−Vstd”, the second threshold value Vstd_comp2 is a value obtained when the second threshold value Vstd_comp2 is in the typical state at a timing after a predetermined time from the time T5. Correction is made to be lower than (second reference value), and the oscillation frequency is increased to match the oscillation frequency in the typical state. Note that V2typ corresponds to an example of the second representative voltage, and may be the same value as the representative voltage V1typ, or may be set in a similar manner. For example, when the self-correction mode is performed when the device temperature of the oscillation circuit 1 is a typical specific temperature, the charging voltage V2 of the second capacitor C2 at the charging stop time (time T3 in FIG. 9) is Two representative voltage V2 typ may be used.

  As described above, the correction unit 4 detects the charging voltage V1 of the first capacitor C1 at the time when the first capacitor C1 is switched to the discharge target by the switching control circuit 8, and the detected first capacitor C1 is detected. When the charging voltage V1 exceeds a predetermined representative voltage V1typ, the first correction data (correction code 1) for making the first threshold value lower than the first reference value (first threshold value set in the typical state) When the generated and detected charging voltage V1 of the first capacitor C1 is less than the representative voltage V1typ, the first threshold value is set higher than the first reference value (the first threshold value set in the typical state). First correction data (correction code 1) is generated. Further, the charging voltage V2 of the second capacitor C2 is detected at the time when the second capacitor C2 is switched to the discharge target by the switching control circuit 8, and the detected charging voltage V2 of the second capacitor C2 becomes the representative voltage V1typ. When the same or different second representative voltage V2typ is exceeded, second correction data (correction code 2) that makes the second threshold value lower than the second reference value (second threshold value set in the typical state) is generated. When the detected charging voltage V2 of the second capacitor C2 is less than the second representative voltage V2typ, the second threshold value is set higher than the second reference value (second threshold value set in the typical state). Second correction data (correction code 2) to be generated is generated.

  The configuration according to the present embodiment can achieve the same effects as those of the first embodiment. Further, in the configuration of the present embodiment, the charging voltages V1 and V2 at the start of discharging of the first capacitor C1 and the second capacitor C2 can be acquired, and these charging voltages V1 and V2 are obtained from the respective comparison circuits. Since it can be said that the delay time is reflected separately, the delay time of each comparison circuit can be grasped individually. And each correction data for correcting each comparison circuit based on each such charging voltage V1, V2 (correction code 1 corresponding to the first correction data and correction code 2 corresponding to the second correction data) Therefore, even if there is a difference between the delay states of both comparison circuits, more appropriate correction can be performed.

[Fourth embodiment]
Next, a fourth embodiment will be described.
The oscillation circuit 1 shown in FIG. 11 is also provided, for example, so as to generate and output an oscillation signal in a semiconductor integrated circuit, and mainly includes a control unit 3, a correction unit 4, a storage device 5, a switching control circuit 8, and a comparison circuit. The circuit 41, the constant current source 15, the threshold setting circuit 20, the first capacitor C1, the second capacitor C2, and other switches are included.

  The control unit 3 is configured such that an output signal Q, which will be described later, is input as a trigger signal, and can output the control signals φ1, φ2 for a predetermined period at a predetermined timing (a rising timing of the output signal Q, which will be described later). Has been. In the normal mode (mode in which the basic operation is performed), the control unit 3 maintains the output signal φ1 at the L level and the output signal φ2 at the H level. On the other hand, in the mode in which the self-correction operation is performed, the output signal φ1 is maintained at the H level for a certain time and the output signal φ2 is maintained at the L level for a certain time using the rising edge of the output signal Q as a trigger. The control unit 3 may be configured by a known control circuit such as a microcomputer, and can output an H level output signal φ1 and an L level output signal φ2 for a certain period of time using a rise of the output signal Q as a trigger. Other circuits may be used as long as they are configured. Note that the switching from the normal mode to the mode for performing the self-correction operation in the control unit 3 may be performed periodically or when a predetermined condition is satisfied.

  The constant current source 15 has the same configuration as that of the first embodiment, and is configured by a known constant current circuit that outputs a predetermined constant current, and supplies a charging current to the first capacitor C1 or the second capacitor C2. Functions to supply.

  The first capacitor C1 and the second capacitor C2 are both configured to be able to conduct with the constant current source 15, and are charged with a constant current supplied from the constant current source 15. The first capacitor C1 is connected to the constant current source 15 via a switch SW10, which will be described later, and is charged when the switch SW10 is on and when the switch SW11 or SW12 is off, and the switch SW10 is off. And when the switches SW11 and SW12 are in the ON state, the discharge is performed. The second capacitor C2 is connected to the constant current source 15 via a switch SW10 'described later, and is connected in parallel with the first capacitor C1. The second capacitor C2 is charged when the switch SW10 ′ is on and the switch SW12 ′ is off, and is discharged when the switch SW10 ′ is off and the switch SW12 ′ is on. The

  The switching control circuit 8 includes a flip-flop circuit 9, charge / discharge switching units 10 a and 10 b, an input switching unit 43, an output switching unit 45, and a delay unit 47, and a signal output from the comparison circuit 41. Based on the above, the charging target from the constant current source 15 is switched to one of the first capacitor C1 and the second capacitor C2, and the other is switched to the discharging target. In addition, the charging voltage of the capacitor to be charged is switched to the input voltage of the comparison circuit 41. That is, when the charging target from the constant current source 15 is switched to the first capacitor C1, the charging voltage V1 of the first capacitor C1 that is the charging target is used as the input voltage of the comparison circuit 41. When the switching is performed such that the charging target from the constant current source 15 is the second capacitor C2, the charging voltage V2 of the second capacitor C2 that is the charging target is used as the input voltage of the comparison circuit 41. Switching.

  The flip-flop circuit 9 has the same configuration as that of the first embodiment, and is configured as a known RS flip-flop circuit. The first output signal Vset from the output switching unit 45 is input to the S terminal, and the output switching unit The second output signal Vrst from 45 is input to the R terminal. The flip-flop circuit 9 outputs an H level signal from the Q terminal and an L level signal from the QB terminal when an H level signal is input to the S terminal and an L level signal is input to the R terminal. Further, when an H level signal is input to the R terminal and an L level signal is input to the S terminal, the L level signal is output from the Q terminal, and the H level signal is output from the QB terminal. When both the S terminal and R terminal inputs are at the L level, the output state up to that point is maintained, and the H level signal is not simultaneously input to the S terminal and the R terminal. .

  The charge / discharge switching unit 10a has the same configuration as that of the charge / discharge switching unit 10a of the first embodiment, and includes semiconductor switch elements SW10, SW11, SW12 and connection lines connected thereto. The switch SW10 is configured as a P-channel type MOSFET, the source is connected to the output side of the constant current source 15, and the drain is connected to one end side of the first capacitor C1. The gate of the switch SW10 is connected to the Q terminal (output terminal) of the flip-flop circuit 9. The switch SW11 is configured as an N-channel MOSFET, and has a drain connected to the drain of the switch SW10 and one end of the first capacitor C1, and a source connected to the drain of the switch SW12. The gate of the switch SW11 is connected to the output terminal of the φ2 signal in the control unit 3. The switch SW12 is configured as an N-channel MOSFET, and has a drain connected to the source of the switch SW11 and a source connected to the ground. The gate of the switch SW12 is connected to the Q terminal (output terminal) of the flip-flop circuit 9.

  The charge / discharge switching unit 10b has the same configuration as the charge / discharge switching unit 10b of the first embodiment, is connected in parallel to the charge / discharge switching unit 10a, and is connected to the semiconductor switch elements SW10 ′ and SW12 ′. Consists of lines. The switch SW10 'is configured as a P-channel type MOSFET, the source is connected to the output side of the constant current source 15, and the drain is connected to one end side of the second capacitor C2. The gate of the switch SW10 'is connected to the QB terminal of the flip-flop circuit 9. The switch SW12 'is configured as an N-channel MOSFET, and has a drain connected to the drain of the switch SW10' and one end of the second capacitor C2, and a source connected to the ground. The gate of the switch SW12 'is connected to the QB terminal of the flip-flop circuit 9.

  The comparison circuit 41 is configured as a known comparator. In the comparison circuit 41, the positive input terminal is connected to the output line 43a from the input switching unit 43, the switches SW51 and SW52 of the input switching unit 43 are on, and the switches SW51 ′ and SW52 ′ are switched on. In the OFF state, the charging voltage V1 of the first capacitor C1 is configured to be input as a positive input signal. Further, when the switches SW51 ′ and SW52 ′ of the input switching unit 43 are on and the switches SW51 and SW52 are off, the charging voltage V2 of the second capacitor C2 is input as a positive input signal. It is configured.

  Further, the threshold value Vstd_comp set by the threshold setting circuit (reference voltage generation unit) 20 is input to the negative input terminal of the comparison circuit 41. The threshold value Vstd_comp corresponds to an example of a “predetermined threshold value” that serves as a comparison reference in the comparison circuit 41. The comparison circuit 41 uses either the charging voltage V1 charged in the first capacitor C1 or the charging voltage V2 charged in the second capacitor C2 according to switching by the input switching unit 43 as the input voltage Vcomp_in, and the input voltage It functions to output an L level signal (first signal) when Vcomp_in is less than a predetermined threshold Vstd_comp, and to output an H level signal (second signal) when the input voltage Vcomp_in is equal to or higher than the predetermined threshold Vstd_comp. .

  The input switching unit 43 includes a pair of switches SW51 and SW52 and a pair of switches SW51 'and SW52'. The pair of switches SW51 and SW52 functions as a switch for turning on and off between the first capacitor C1 and the comparison circuit 41. The switch SW51 is configured as an N-channel type MOSFET, and the drain is the first capacitor. One end of C1 and the drain of the switch SW10 are connected, and the source is connected to the input terminal on the positive side of the comparison circuit 41. The gate of the switch SW51 is connected to the QB terminal of the flip-flop circuit 9. The switch SW52 is configured as a P-channel type MOSFET, and the source is connected to one end of the capacitor C1 and the drain of the switch SW10, and the drain is connected to the positive input terminal of the comparison circuit 41. The gate of the switch SW22 is connected to the Q terminal of the flip-flop circuit 9.

  The pair of switches SW51 ′ and SW52 ′ functions as a switch for turning on and off between the second capacitor C2 and the comparison circuit 41. The switch SW51 ′ is configured as an N-channel MOSFET, The drain is connected to one end of the second capacitor C2 and the drain of the switch SW10 ′, and the source is connected to the positive input terminal of the comparison circuit 41. The gate of the switch SW51 'is connected to the Q terminal of the flip-flop circuit 9. The switch SW52 ′ is configured as a P-channel type MOSFET, the source is connected to one end of the second capacitor C2 and the drain of the switch SW10 ′, and the drain is connected to the positive input terminal of the comparison circuit 41. Has been. The gate of the switch SW52 'is connected to the QB terminal of the flip-flop circuit 9.

  In the input switching unit 43 configured as described above, when the output from the Q terminal of the flip-flop circuit 9 is L level and the output from the QB terminal is H level, both the switches SW51 and SW52 are turned on. The switches SW51 ′ and SW52 ′ are both turned off, and at this time, the charging voltage V1 of the first capacitor C1 is input as the positive input voltage of the comparison circuit 41. When the output from the Q terminal of the flip-flop circuit 9 is at the H level and the output from the QB terminal is at the L level, both the switches SW51 and SW52 are turned off and both the switches SW51 ′ and SW52 ′ are turned on. At this time, the charging voltage V2 of the second capacitor C2 is input as the positive input voltage of the comparison circuit 41.

  The output switching unit 45 and the delay unit 47 switch the charging target to be the other capacitor when the charging voltage of one capacitor to be charged is equal to or higher than a predetermined threshold Vstd_comp, and based on the switching timing. Also, after a predetermined time elapses, it functions to permit switching of the next charging target.

  The delay unit 47 is configured, for example, as a known delay circuit, is configured to be able to input an output signal from the Q terminal of the flip-flop circuit 9, and delays and outputs the output signal from the Q terminal. It is configured. For example, as shown in FIG. 12, only a time shorter than the cycle of the pulse signal from the Q terminal (more specifically, a time shorter than a half cycle of the pulse signal from the Q terminal, for example, about 1/4 cycle). The delayed delay signal Q (Delay) is output.

  The output switching unit 45 includes AND circuits 45a and 45b and a NOT circuit (inverter) 45c. The NOT circuit (inverter) 45c has an input side connected to the output line from the delay unit 47, and an output side connected to the first input terminal of the AND circuit 45a. The output line from the delay unit 47 is also connected to the first input terminal of the AND circuit 45b. The output line from the comparison circuit 41 is connected to the second input terminals of the AND circuits 45a and 45b. In the output switching unit 45 configured as described above, when the H level signal is output from the delay unit 47, the output from the AND circuit 45a is maintained at the L level, and the signal from the comparison circuit 41 is the AND circuit. 45b to the R terminal of the flip-flop circuit 9. That is, when an H level signal is output from the delay unit 47, an L level signal is input to the S terminal of the flip-flop circuit 9, and when an H level signal is output from the comparison circuit 41, an H level signal is output to the R terminal. When the level signal is input and the L level signal is output from the comparison circuit 41, the L level signal is input to the R terminal. On the other hand, when the L level signal is output from the delay unit 47, the output from the AND circuit 45b is maintained at the L level, and the signal from the comparison circuit 41 is transferred from the AND circuit 45a to the S terminal of the flip-flop circuit 9. Is output. That is, when the L level signal is output from the delay unit 47, the L level signal is input to the R terminal of the flip-flop circuit 9, and when the H level signal is output from the comparison circuit 41, When the level signal is input and the comparison circuit 41 outputs the L level signal, the L level signal is input to the S terminal.

  The correction unit 4 has the same configuration as the correction unit 4 of the first embodiment and functions in the same manner, and includes a storage device 5 and an AD converter 7. In the correction unit 4, the first capacitor C <b> 1 is discharged by the switching control circuit 8 in response to the output from the comparison circuit 41 being switched from the first signal (L level signal) to the second signal (H level signal). Correction of the threshold value set by the threshold value setting circuit 20 based on the charging voltage V1 of the first capacitor C1 at the time of switching (that is, the time when the switch SW10 is turned off and the switch SW12 is turned on). The correction data used for is generated. Here, based on the charging voltage V1 of the first capacitor C1 at the time when the first capacitor C1 is switched to the discharge target by the switching control circuit 8, it is used for correcting the threshold set by the threshold setting circuit 20. Although the correction data is generated, the threshold set by the threshold setting circuit 20 based on the charging voltage V2 of the second capacitor C2 at the time when the second capacitor C2 is switched to the discharge target by the switching control circuit 8 Correction data used for the correction may be generated by a similar method.

  The storage device 5 has the same configuration as the storage device 5 of the first embodiment and functions in the same manner. It is remembered. The reference code is a value for setting the reference voltage Vstd so that the oscillation circuit 1 has a desired oscillation frequency when the device temperature of the oscillation circuit 1 is a typical specific temperature (for example, 20 ° C.). The charging voltage V1 at the start of discharging the first capacitor C1 in the self-correction mode when the reference voltage Vstd is set becomes a unique representative voltage V1typ. The digital data of the difference voltage between the representative voltage V1typ and the reference voltage Vstd is defined to be a reference code.

  The AD converter 7 has the same configuration as that of the AD converter 7 of the first embodiment and functions similarly. The AD converter 7 is connected to the first capacitor C1 via switches (switches SW21 and SW22), and the charging voltage V1 of the first capacitor C1 can be input. The switch SW21 is configured as an N-channel MOSFET, and has a drain connected to one end of the capacitor C1 and the drain of the switch SW10, and a source connected to one input side of the AD converter 7. The gate of the switch SW21 is connected to the output terminal of the output signal φ1 in the control unit 3. Further, the switch SW22 is configured as a P-channel type MOSFET, the source is connected to one end side of the capacitor C1 and the drain of the switch SW10, and the drain is connected to one input side of the AD converter 7. The gate of the switch SW22 is connected to the output terminal of the output signal φ2 in the control unit 3. Further, the reference voltage Vstd generated by the threshold setting circuit 20 is input to the AD converter 7, and the charging voltage of the first capacitor C1 at the timing when the switches SW21 and SW22 are turned on. It functions to convert the difference voltage between V1 and the reference voltage Vstd into a digital signal.

  The threshold value setting circuit 20 sets a threshold value (a common value used as the first threshold value and the second threshold value) as a comparison reference in the comparison circuit 41. Basically, the threshold value used in the first embodiment. It has the same configuration as the setting circuit 20 and has the same function (see FIG. 2). The threshold setting circuit 20 is also configured as shown in FIG. 2, and the reference code output from the storage device 5 and the correction code output from the AD converter 7 (timing when the switches SW21 and SW22 are turned on). And the reference voltage Vstd and the threshold value Vstd_comp are output. The digital data of the difference voltage between the charging voltage V1 of the first capacitor C1 and the reference voltage Vstd in FIG.

  In the threshold setting circuit 20, resistors R1 to Rm are connected in series between a predetermined power source and the ground, and one ends of switches X1 to Xn including MOSFETs, bipolar transistors and the like are connected between the resistors, An output line of the reference voltage Vstd is connected to each other end of the switches X1 to Xn. The control terminals of the switches X1 to Xn are connected to n terminals provided in the decoder 21, and each switch X1 to Xn is turned on when the corresponding terminal in the decoder 21 becomes H level. When the corresponding terminal in the decoder 21 becomes L level, it is switched to the off state. Further, between the resistors, one ends of switches Y1 to Yn made of MOSFETs or bipolar transistors are connected, and an output line for outputting a threshold value Vstd_comp is connected to the other ends of the switches Y1 to Yn. . The control terminals of the switches Y1 to Yn are connected to n terminals provided in the decoder 25, and the switches Y1 to Yn are turned on when the corresponding terminals in the decoder 25 become H level. When the corresponding terminal in the decoder 25 becomes L level, it is switched to the off state. In this configuration, when the reference code read from the storage device 5 is input to the decoder 21, the state of each terminal of the decoder 21 corresponds to the reference code, and corresponds to the reference code for each of the switches X1 to Xn. Are output in parallel. As a result, the reference voltage Vstd corresponding to the reference code is output. In addition, when information (correction code) for specifying a correction value is held in the storage unit 23 and input to the decoder 25, the state of each terminal of the decoder 25 becomes a state corresponding to the correction code, and each switch Y1 to Yn has a state. On the other hand, signals corresponding to the correction codes are output in parallel. In this configuration, the state of the switches Y1 to Yn can be switched by changing the correction code, and the output threshold value Vstd_comp can be increased or decreased. In the initial setting after the oscillation circuit 1 is started, the reference code is held in the storage unit 23, and the threshold Vstd_comp is set to output the same voltage as the reference voltage Vstd.

  Next, the operation of the oscillation circuit 1 of this embodiment will be described. The basic operation of the oscillation circuit 1 is the same as that of the first embodiment, and is the operation when the output signal φ1 from the control unit 3 is at L level and the output signal φ2 is at H level. That is, during the basic operation, the switch SW11 is always on and the switches SW21 and SW22 are always off.

  During this basic operation, since the switch SW10 is in the on state and the switch SW12 is in the off state while the output signal Q from the flip-flop circuit 9 is at the L level after the time T1 in FIG. The first capacitor C1 is charged by the charging current from the source 15. At this time, the output signal QB is at the H level, the switch SW10 'is turned off, and the switch SW12' is turned on, so that the second capacitor C2 is discharged. In this case, in the input switching unit 43, the switches SW51 and SW52 are turned on and the switches SW51 ′ and SW52 ′ are turned off, so that the charging voltage V1 of the first capacitor C1 is applied to the positive input terminal of the comparison circuit 41. Entered. In this operation, while the charging voltage V1 of the first capacitor C1 is less than the threshold value Vstd_comp, the comparison circuit 41 outputs an L level signal (output of “0”). On the other hand, when the charging voltage V1 of the first capacitor C1 exceeds the threshold value Vstd_comp, the comparison circuit 41 outputs an H level signal (output “1”) (see the Vset signal from time T2: FIG. 12). .

  When the comparison circuit 41 outputs an H level signal (“1” output), the H level signal is input to the AND circuits 45a and 45b, respectively. Immediately after this input (immediately after time T2), the L level signal is output from the delay unit 47 (that is, a signal obtained by delaying the L level signal from the Q terminal is output), and Vset input to the S terminal. The signal is an H level signal. That is, after the charging voltage V1 of the first capacitor C1 exceeds the threshold value Vstd_comp, the charging voltage V2 of the second capacitor C2 is switched to become the positive side input voltage of the comparison circuit 41, and the input voltage becomes less than the threshold value Vstd_comp. Until then, the H level Vset signal is input to the S terminal. When the H level Vset signal is input in this way, the output signal Q of the flip-flop circuit 9 is switched to the H level ("1" signal), and the output signal QB is switched to the L level ("0" signal). (Refer to output signals Q and QB from time T2). As from time T2, after the output signal Q from the flip-flop circuit 9 is at the H level, the switch SW10 is turned off and the switch SW12 is turned on. During the basic operation, the output signal φ2 is maintained at the H level. Since the switch SW11 is also in the on state, the current supply from the constant current source 15 to the first capacitor C1 is cut off, and the first capacitor C1 is discharged. On the other hand, while the output signal QB from the flip-flop circuit 9 is at the L level, the switch SW10 ′ is turned on and the switch SW12 ′ is turned off, so that the second capacitor C2 is driven by the charging current from the constant current source 15. Charged. In this case, in the input switching unit 43, the switches SW51 ′ and SW52 ′ are turned on and the switches SW51 and SW52 are turned off, so that the charging voltage V2 of the second capacitor C2 is applied to the positive input terminal of the comparison circuit 41. Will be entered. Further, in this configuration, after the output of the H level signal (output of “1”) from the comparison circuit 41 at time T2, a certain amount of time passes (at least after the time T2, the Vset signal becomes L level). Since the signal from the delay unit 47 is maintained at the L level (until it changes), the H level signal is not input to the R terminal during this period. That is, after the charging voltage V1 of the first capacitor C1 exceeds the threshold value Vstd_comp, the charging voltage V2 of the second capacitor C2 is switched to become the positive side input voltage of the comparison circuit 41, and the input voltage is less than the threshold value Vstd_comp. In the transition period until stabilization, switching of signals from the Q terminal and the QB terminal (next switching) is prevented.

  When the output signal from the QB terminal from the flip-flop circuit 9 is L level and the output signal from the Q terminal is H level and the second capacitor C2 is to be charged, the second capacitor input to the comparison circuit 41 While the charging voltage V2 of C2 is less than the threshold value Vstd_comp, the comparison circuit 41 outputs an L level signal (output of “0”). On the other hand, when the charging voltage V2 of the second capacitor C2 exceeds the threshold value Vstd_comp, the comparison circuit 41 outputs an H level signal (output of “1”) (see the Vrst signal from time T3: FIG. 3). . As a result, the output signals Q and QB are inverted again (see time T3 in FIG. 3). When the comparison circuit 41 outputs the H level signal (“1” output) as described above, the H level signal is input to the AND circuits 45a and 45b, respectively. Immediately after this input (immediately after time T3), an H level signal is output from the delay unit 47 (that is, a signal obtained by delaying the H level signal from the Q terminal is output), and Vrst input to the R terminal. The signal is an H level signal. That is, after the charging voltage V2 of the second capacitor C2 exceeds the threshold value Vstd_comp, the charging voltage V1 of the first capacitor C1 is switched to become the input voltage on the positive side of the comparison circuit 41, and the input voltage becomes less than the threshold value Vstd_comp. Until this time, the H level Vrst signal is input to the R terminal. When the H level Vrst signal is input in this manner, the output signal Q of the flip-flop circuit 9 is switched to the L level (“0” signal), and the output signal QB is switched to the H level (“1” signal). (Refer to output signals Q and QB from time T3). As from time T3, while the output signal QB from the flip-flop circuit 9 is at the H level, the switch SW10 ′ is turned off and the switch SW12 ′ is turned on, to the second capacitor C2 from the constant current source 15. The second capacitor C2 is discharged while the current supply is interrupted. On the other hand, while the output signal Q from the flip-flop circuit 9 is at the L level, the switch SW10 is turned on and the switch SW12 is turned off, so that the first capacitor C1 is charged by the charging current from the constant current source 15. The In this case, in the input switching unit 43, the switches SW51 and SW52 are turned on and the switches SW51 ′ and SW52 ′ are turned off, so that the charging voltage V1 of the first capacitor C1 is applied to the positive input terminal of the comparison circuit 41. Will be entered. Also in this case, after the output of the H level signal (output of “1”) from the comparison circuit 41 at time T3, a certain amount of time passes (after time T3, at least the Vrst signal becomes L level). Since the signal from the delay unit 47 is maintained at the H level until the change occurs, the H level signal is not input to the S terminal during this period. That is, after the charging voltage V2 of the second capacitor C2 exceeds the threshold value Vstd_comp, the charging voltage V1 of the first capacitor C1 is switched to become the input voltage on the positive side of the comparison circuit 41, and the input voltage is less than the threshold value Vstd_comp. In the transition period until stabilization, switching of signals from the Q terminal and the QB terminal (next switching) is prevented. By repeating such an operation, the output signal Q and the output signal QB become oscillation signals having a predetermined period.

  Next, the self correction operation will be described. In the oscillation circuit 1 of this embodiment, the self-correction operation is performed in the same manner as in the first embodiment, and the control unit 3 performs the self-correction operation from the mode in which the basic operation is performed periodically or when a predetermined condition is satisfied ( Switch to self-correction mode. When the mode is switched to the self-correction operation mode, the control unit 3 inverts the output signals φ1 and φ2 at the rising timing of the output signal Q from the flip-flop circuit 9, sets the output signal φ1 to the H level, and outputs The state where the signal φ2 is set to the L level is maintained for a certain time.

  During this fixed time, since the switch SW10 is turned off from the rising edge of the output signal Q, charging is prevented and the switch SW11 is turned off, so that the discharge from the first capacitor C1 via the switch SW11 is also performed. Be blocked. At this time, since the switches SW51 and SW52 are both turned off, the energization between the comparison circuit 41 and the first capacitor C1 is cut off.

  On the other hand, since the switches SW21 and SW22 are turned on, the charging voltage V1 when the charging of the first capacitor C1 is stopped is input to one side of the AD converter 7. The charging voltage at the time of stopping charging is the charging voltage at the time when the first capacitor C1 is switched from the charging target to the discharging target during the basic operation (that is, the charging voltage from the state where the first capacitor C1 was the charging target). When V1 exceeds the threshold value Vstd_comp, an H level signal is output from the comparison circuit 41, and this corresponds to the charging voltage at the time when the output signal Q is switched to the H level. The reference voltage Vstd is input to the other input of the AD converter 7. At this time, the AD converter 7 generates digital data of a difference voltage between the charging voltage V1 and the reference voltage Vstd at the time when the charging of the capacitor C1 is stopped (when the capacitor C1 is switched to the discharge target).

  The concept of correction of the present embodiment is the same as that of the first embodiment, and Δt = C / I × {, where Δt is a change in delay time due to a change in the device temperature of the oscillation circuit 1 from a typical specific temperature. (V1−Vstd) − (V1typ−Vstd)}. “V1typ−Vstd” (reference voltage difference) in this equation is the charge when the self-correction mode is performed in the typical state (that is, the device temperature of the oscillation circuit 1 is a representative specific temperature state). When the charge voltage V1 exceeds the threshold value Vstd_comp from the time point when the first capacitor C1 was charged, the comparison circuit 41 outputs an H level signal and the output signal Q is switched to the H level. This value reflects the charging voltage of the capacitor C1 at the time of switching), and the A / D conversion result is held in the storage device 5 as a reference code.

  When the AD conversion value “V1−Vstd” measured in the self-correction mode is larger than the reference difference voltage “V1typ−Vstd”, that is, V1> V1typ (V1typ is an example of a predetermined representative voltage). The oscillation frequency is lower than in the typical state, and the AD conversion value “V1−Vstd” measured in the self-correction mode is smaller than the reference differential voltage “V1typ−Vstd”. In other words, when V1 <V1typ, it can be said that the oscillation frequency is higher than that in the typical state. Therefore, the threshold setting circuit 20 (reference voltage generation unit) inputs the AD conversion value “V1-Vstd” (correction code) measured in the self-correction mode, holds it in the storage unit 23, and decodes the correction code into the decoder. Decode at 25. Then, the switches Y1 to Yn are operated according to the decoding result, and the voltage corrected based on the correction code is output as the threshold value Vstd_comp.

  Specifically, when the AD conversion value “V1−Vstd” measured in the self-correction mode is larger than the reference difference voltage “V1typ−Vstd”, that is, V1> V1typ (V1typ is a predetermined representative voltage). In the case where the threshold Vstd_comp is lower than the value in the typical state (that is, the threshold Vstd_comp = Vstd (reference value) when the device temperature of the oscillation circuit 1 is a typical specific temperature)). And increase the oscillation frequency to match the oscillation frequency in the typical state. Conversely, when the AD conversion value “V1−Vstd” measured in the self-correction mode is smaller than the reference difference voltage “V1typ−Vstd”, that is, when V1 <V1typ, the threshold value Vstd_comp is set to the typical state. Correction is made to be higher than the current value (reference value), and the oscillation frequency is lowered to match the oscillation frequency in the typical state. For example, in the example of FIG. 12, the self-correction operation is performed between times T <b> 3 and T <b> 5, and the AD conversion value “V1−Vstd” is acquired by the AD converter 7. Since the AD conversion value “V1−Vstd” is larger than the reference difference voltage “V1typ−Vstd”, the threshold value Vstd_comp is a value (reference value) at a timing after a predetermined time from the time T5. The oscillation frequency is increased to match the oscillation frequency in the typical state. As shown in FIG. 12, it is desirable to reflect the corrected threshold value Vstd_comp immediately after the discharge operation of the second capacitor C2 starts so as not to affect the charging operation of the first capacitor C1.

  Also in this configuration, the correction unit 4 detects the charging voltage V1 of the first capacitor C1 at the time when the first capacitor C1 is switched to the discharge target by the switching control circuit 8, and the detected charging voltage V1 is a predetermined value. When the representative voltage V1typ is exceeded (that is, V1> V1typ), correction data for generating the threshold value Vstd_comp lower than the predetermined reference value (threshold value set in the typical state) is generated and detected. When the charging voltage V1 is less than the representative voltage V1typ, correction data for generating a threshold value Vstd_comp higher than a predetermined reference value (threshold value set in the typical state) is generated. In the oscillation circuit 1, the upper limit value and the lower limit value of the correction code are determined in advance, and when correction data exceeding the upper limit is input to the decoder 25, the decoder 25 sets the set upper limit value to the switch Y1. When the correction data that is lower than the lower limit is input to the decoder 25, the set lower limit value is output to the switches Y1 to Yn.

[Fifth Embodiment]
Next, a fifth embodiment will be described with reference to FIGS.
In the fifth embodiment, as shown in FIGS. 13 and 14, the control unit 3 can output the output signals φ1 ′ and φ2 ′ in addition to the output signals φ1 and φ2 as in the fourth embodiment, The point where switches SW11 ′, SW21 ′, and SW22 ′ are added, the AD converter 7 and the average value generation unit 26 (the configuration is the same as that of the average value generation unit 26 of the second embodiment, hereinafter also referred to as an average unit). ) Is different from the fourth embodiment in the method of generating the correction code, and other configurations are the same as those in the fourth embodiment. Therefore, configurations other than these (same points as in the fourth embodiment) are denoted by the same reference numerals as those in the fourth embodiment, and detailed description thereof is omitted.

  In the oscillation circuit 1 of the fifth embodiment, an output signal Q is input as a trigger signal in the control unit 3. In the normal mode (the mode in which the basic operation similar to that of the fourth embodiment is performed), the control unit 3 maintains the output signal φ1 at the L level, maintains the output signal φ2 at the H level, and outputs the output signal φ1 ′. Is maintained at the L level, and the output signal φ2 ′ is maintained at the H level. On the other hand, in the mode in which the self-correction operation is performed, the output signal φ1 ′ is maintained at the H level for a certain time and the output signal φ2 ′ is maintained at the L level for a certain time by using the falling edge of the output signal Q as a trigger. Further, with the rising edge of the output signal Q as a trigger, the output signal φ1 is maintained at the H level for a certain time and the output signal φ2 is maintained at the L level for the certain time. The control unit 3 may be configured by a known control circuit such as a microcomputer, or may be another circuit as long as the signal can be output using the rising and falling edges of the output signal Q as a trigger. Further, switching from the normal mode to the mode for performing the self-correction operation in the control unit 3 may be performed periodically or when a predetermined condition is satisfied.

  In the oscillation circuit 1 according to the present embodiment, the oscillation operation during the basic operation is the same as in the first and fourth embodiments. In this basic operation, the control unit 3 outputs the L level signal φ1, the H level signal φ2, the L level signal φ1 ′, and the H level signal φ2 ′, as described above. SW22, SW21 ′, and SW22 ′ are all turned off, and switches SW11 and SW11 ′ are all turned on.

  Also in the present embodiment, the control unit 3 switches from the mode in which the basic operation is performed periodically or when a predetermined condition is satisfied to the mode in which the self-correction operation is performed (self-correction mode). When the mode is switched to the mode for performing the self-correction operation, the control unit 3 outputs the output signals φ1 ′ and φ2 ′ at the falling timing of the output signal Q from the flip-flop circuit 9, as at time T3 in FIG. Inverted, the output signal φ1 ′ is set to the H level, and the output signal φ2 ′ is set to the L level and maintained for a certain time.

  During this fixed time, the switch SW10 ′ is turned off from the fall of the output signal Q (that is, the rise of the output signal QB), so that charging of the capacitor C2 is prevented and the switch SW11 ′ is turned off. Therefore, the discharge from the second capacitor C2 via the switch SW11 ′ is also prevented. On the other hand, since the switches SW21 ′ and SW22 ′ are in the on state and the switches SW21 and SW22 are maintained in the off state during the predetermined period, the charging of the second capacitor C2 is stopped at one side of the AD converter 7. The charging voltage V2 at is input. The charging voltage at the time of stopping the charging is the charging voltage at the time when the second capacitor C2 is switched from the charging target to the discharging target during the basic operation (that is, the charging voltage from the state where the second capacitor C2 was the charging target). When V2 exceeds the threshold value Vstd_comp, the comparison circuit 41 outputs an H level signal, which corresponds to the charging voltage at the time of switching when the output signal QB is switched to the H level. The reference voltage Vstd is input to the other input of the AD converter 7. At this time, the AD converter 7 generates digital data of a difference voltage between the charging voltage V2 and the reference voltage Vstd at the time when the charging of the second capacitor C2 is stopped (when it is switched to the discharge target). This digital data is input as the correction code 2 to the averaging unit 26 described later.

  Thus, after the digital data of the difference voltage between the charging voltage V2 and the reference voltage Vstd at the time when the charging of the second capacitor C2 is stopped (the time when the second capacitor C2 is switched to the discharge target) is generated, the output signal φ1 ′ is The output signal φ2 ′ is returned to the H level by returning to the L level. Then, the output signals φ1 and φ2 are inverted at the rising timing of the output signal Q from the flip-flop circuit 9 (time T4 in FIG. 14), the output signal φ1 is set to the H level, and the output signal φ2 is set to the L level. Maintain the state for a certain time. Thereby, the correction code 1 is generated by the same method as the method of generating the correction code in the fourth embodiment. That is, since the switch SW10 is in an off state from the rising edge of the output signal Q during this fixed time, charging is blocked and the switch SW11 is in an off state, so that the switch SW11 from the first capacitor C1 passes through the switch SW11. Discharge is also prevented. On the other hand, since the switches SW21 and SW22 are turned on, the charging voltage V1 when the charging of the first capacitor C1 is stopped is input to one side of the AD converter 7. The charging voltage at the time of stopping charging is the charging voltage V1 when the first capacitor C1 is switched from the charging target to the discharging target during the basic operation (that is, charging from the state where the first capacitor C1 was the charging target). When the voltage V1 exceeds the threshold value Vstd_comp, an H level signal is output from the comparison circuit 41, and this corresponds to a charging voltage at the time of switching when the output signal Q is switched to the H level. The reference voltage Vstd is input to the other input of the AD converter 7. At this time, the AD converter 7 generates digital data of the difference voltage between the charging voltage V1 and the reference voltage Vstd at the time when the charging of the capacitor C1 is stopped (when the capacitor C1 is switched to the discharge target), and the digital data is corrected. The code 1 is input to the averaging unit 26 described later.

  In this configuration, the correction code 1 input to the averaging unit 26 as described above (the difference voltage between the charging voltage V1 and the reference voltage Vstd at the time when the first capacitor C1 is switched from the charging target to the discharging target). And the average value of the correction code 2 (the difference voltage between the charging voltage V2 and the reference voltage Vstd at the time when the second capacitor C2 is switched from the charging target to the discharging target) is obtained, and this is stored as a “correction code” in the storage unit 27. Hold on.

  The correction method after the correction code is stored in the storage unit 27 (the method for generating the threshold value Vstd_comp in the threshold setting circuit 20) is the same as that in the first embodiment. That is, the threshold setting circuit 20 (reference voltage generation unit) finally calculates the average value “(V1 + V2) / 2−Vstd” of the AD conversion values (correction code 1, correction code 2) measured in the self-correction mode. The correction code is input and held in the storage unit 23, and the correction code is decoded by the decoder 25. Then, the switches Y1 to Yn are operated according to the decoding result, and the voltage corrected based on the correction code is output as the threshold value Vstd_comp.

  Specifically, when the average value “(V1 + V2) / 2−Vstd” of the AD conversion values (correction codes 1 and 2) measured in the self-correction mode is larger than the reference difference voltage “Vtyp−Vstd”. That is, when (V1 + V2) / 2> Vtyp, the threshold Vstd_comp is corrected to a value lower than the value (reference value) in the typical state, and the oscillation frequency is adjusted to match the oscillation frequency in the typical state. Make it high. Conversely, when the AD conversion value “(V1 + V2) / 2−Vstd” measured in the self-correction mode is smaller than the reference difference voltage “Vtyp−Vstd”, that is, (V1 + V2) / 2 <Vtyp. Corrects the threshold value Vstd_comp to be higher than the value (reference value) in the typical state, and lowers the oscillation frequency to match the oscillation frequency in the typical state. For example, in the example of FIG. 14, the self-correction operation is performed between times T3 and T5, and the average value “(V1 + V2) / 2−Vstd” of the AD conversion values is acquired. Since the average value “(V1 + V2) / 2−Vstd” of the AD conversion values is larger than the reference difference voltage “Vtyp−Vstd”, the threshold value Vstd_comp is typically set at a timing after a predetermined time from time T5. Correction is made to be lower than the value at the state (reference value), and the oscillation frequency is increased to match the oscillation frequency in the typical state. Note that Vtyp corresponds to an example of a predetermined representative voltage, and may be set in the same manner as in the first and fourth embodiments, and the device temperature of the oscillation circuit 1 is typically specified. It may be an average value of the charging voltage V1 of the first capacitor C1 at the time of stopping charging and the charging voltage V2 of the second capacitor C2 at the time of stopping charging when the self-correction mode is performed at the temperature. .

  As described above, in this configuration, the correction unit 4 detects the charging voltage V1 of the first capacitor C1 at the time when the first capacitor C1 is switched to the discharge target by the switching control circuit 8, and the second capacitor C2 The charging voltage V2 of the second capacitor C2 is detected at the time of switching to the discharge target, and statistical values (for example, these) reflecting the detected charging voltage V1 of the first capacitor C1 and the charging voltage V2 of the second capacitor C2 are detected. If the statistical value is less than the representative voltage, the predetermined threshold value is set to be lower than the reference value. The correction data to be increased is generated. According to this configuration, the charging voltage of the capacitor can be detected separately, and correction data can be generated in a form reflecting these charging voltages. That is, it is possible to generate more appropriate correction data that reflects the actual delay state of both capacitors.

[Other Embodiments]
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  In the first embodiment, the correction data is generated based on the charging voltage V1 at the start of discharging the first capacitor C1 and the representative voltage V1typ. However, charging is performed without setting the input to the AD converter 7 as the charging voltage V1. The correction data may be generated by the same method based on the voltage V2 and the charging voltage V2 at the start of discharging the second capacitor C2 and the representative voltage V2typ similar to the third embodiment.

In the above embodiment, the input to the AD converter 7 is the path connected to either the first capacitor C1 or the second capacitor C2 and the reference voltage Vstd. However, as shown in FIG. It may be used for other purposes. For example, the path connected to the AD converter 7 is divided into a first path connected to one of the first capacitor C1 and the second capacitor C2, and another analog signal generation source (a pressure sensor, an acceleration sensor, a temperature in FIG. 10). You may make it provide the path | route switching part switched to the 2nd path | route connected to the sensor 30 consisting of physical quantity sensors, such as a sensor. For example, the control unit 3 may function as a path switching unit, and the switch SW5 that switches the path connected to the AD converter 7 between the first path and the second path may be switched by a control signal from the control unit 3. . According to this configuration, the AD converter 7 can be used for AD conversion of a signal from another analog signal generation source and AD conversion of a capacitor charging voltage, and each AD converter is prepared separately. Compared to the above, it is possible to simplify the apparatus configuration and reduce the number of parts.
In the case of this configuration, on the output side from the AD converter 7, a switch for switching the output destination from the AD converter 7 between the threshold setting circuit 20 and another signal processing unit (not shown). This switch may be controlled by the control unit 3. That is, during the period when the input path connected to the AD converter 7 in the switch SW5 is switched to the sensor 30 side, the output from the AD converter 7 is input to another signal processing unit, and the input path is connected to the AD converter 7. Can be switched so that the output from the AD converter 7 is input to the threshold setting circuit 20 during the period when the signal is switched to the path connected to either the first capacitor C1 or the second capacitor C2. Further, a signal processing result processed by another signal processing unit (signal processing circuit) may be output to an external device via a communication unit (not shown). In addition, such a configuration that also serves as the AD converter 7 can be applied to any of the above-described embodiments.

  In the above embodiment, the threshold value is set based on one AD conversion process and correction code generation process executed in the self-correction mode. A plurality of correction codes obtained by the conversion process and the correction code generation process may be averaged, and a threshold value may be set based on the average value of the correction codes.

DESCRIPTION OF SYMBOLS 1 ... Oscillation circuit 4 ... Correction | amendment part 8 ... Switching control circuit 11 ... 1st comparison circuit 13 ... 2nd comparison circuit 15 ... Constant current source 20 ... Threshold setting circuit 41 ... Comparison circuit C1 ... 1st capacitor C2 ... 2nd capacitor

Claims (9)

A constant current source (15) for generating a constant current;
A first capacitor (C1) and a second capacitor (C2) configured to be conductive with the constant current source and capable of being charged with a constant current supplied from the constant current source;
When the charging voltage charged in the first capacitor (C1) is less than a predetermined first threshold, a predetermined first signal is output, and when the charging voltage is equal to or higher than the first threshold, the first signal differs from the first signal A first comparison circuit (11) that outputs two signals;
When the charge voltage charged in the second capacitor (C2) is less than a second threshold value that is the same as the first threshold value or different from the first threshold value, a predetermined third signal is output, and the second A second comparison circuit (13) that outputs a fourth signal different from the third signal when the threshold is equal to or greater than a threshold;
A threshold setting circuit (20) for setting the first threshold and the second threshold;
Based on the signals output from the first comparison circuit (11) and the second comparison circuit (13), the charging target from the constant current source (15) is set to the first capacitor (C1) and the second capacitor ( A switching control circuit (8) for switching to either one of C2) and the other to be discharged;
The charging voltage at the time when either one of the first capacitor (C1) and the second capacitor (C2) is switched to the discharge target by the switching control circuit (8), or both capacitors are respectively A correction unit (4) that generates correction data used to correct the first threshold value and the second threshold value set by the threshold value setting circuit (20) based on each charging voltage at each time when it is switched to a discharge target. )When,
A control unit (3) for controlling the threshold value setting circuit to set the first threshold value and the second threshold value based on the correction data generated by the correction unit;
An oscillation circuit comprising: The threshold setting circuit (20) is configured to set the first threshold and the second threshold as the same value,
The correction unit (4) is configured to charge one of the first capacitor (C1) and the second capacitor (C2) when the switching control circuit (8) is switched to a discharge target. When the detected charging voltage exceeds a predetermined representative voltage, correction data for generating the same value lower than a predetermined reference value is generated, and the detected charging voltage is detected by the representative voltage. 2. The oscillation circuit according to claim 1, wherein if it is less, correction data for generating the same value higher than a predetermined reference value is generated. The threshold setting circuit (20) is configured to set the first threshold and the second threshold as the same value,
The correction unit (4) detects a charging voltage of the first capacitor (C1) at a time when the first capacitor (C1) is switched to a discharge target by the switching control circuit (8), and the second capacitor The charging voltage of the second capacitor (C2) is detected at the time when (C2) is switched to the discharge target, and the detected charging voltage of the first capacitor (C1) and the charging of the second capacitor (C2) are detected. When the statistical value reflecting the voltage exceeds a predetermined representative voltage, correction data for generating the same value lower than a predetermined reference value is generated. When the statistical value is less than the representative voltage, a predetermined data is generated. The oscillation circuit according to claim 1, wherein correction data for generating the same value higher than a reference value is generated. The threshold setting circuit (20) is capable of setting the first threshold and the second threshold separately,
The first comparison circuit (11) outputs the second signal at a timing when a charging voltage of the first capacitor (C1) reaches the first threshold,
The second comparison circuit (13) outputs the fourth signal at a timing when a charging voltage of the second capacitor (C2) reaches the second threshold value,
The switching control circuit (4) performs control to switch the first capacitor (C1) from a charging target to a discharging target when the second signal is output from the first comparison circuit (11), and When the fourth signal is output from the comparison circuit (13), the second capacitor (C2) is controlled to be switched from the charging target to the discharging target,
The correction unit (4)
The charging voltage of the first capacitor (C1) is detected at the time when the first capacitor (C1) is switched to the discharge target by the switching control circuit (8), and the detected charging of the first capacitor (C1) is detected. When the voltage exceeds a predetermined representative voltage, first correction data for lowering the first threshold value relative to a predetermined first reference value is generated, and the detected charging of the first capacitor (C1) is performed. If the voltage is less than the representative voltage, generating first correction data for making the first threshold value higher than a predetermined first reference value;
The charging voltage of the second capacitor (C2) is detected when the second capacitor (C2) is switched to the discharge target by the switching control circuit (8), and the detected charging of the second capacitor (C2) is detected. When the voltage exceeds a second representative voltage that is the same as or different from the representative voltage, second correction data that lowers the second threshold value than a predetermined second reference value that is the same as or different from the first reference value is generated. When the detected charging voltage of the second capacitor (C2) is less than the second representative voltage, second correction data for generating the second threshold value higher than the second reference value is generated. The oscillation circuit according to claim 1. A constant current source (15) for generating a constant current;
A first capacitor (C1) and a second capacitor (C2) configured to be electrically connected to the constant current source (15) and capable of being charged by a constant current supplied from the constant current source (15);
A charging voltage charged in the first capacitor (C1) or a charging voltage charged in the second capacitor (C2) is used as an input voltage, and a predetermined first signal is output when the input voltage is less than a predetermined threshold value. A comparator circuit that outputs a second signal different from the first signal when the threshold is equal to or greater than the predetermined threshold;
A threshold setting circuit (20) for setting the predetermined threshold;
Based on the signal output from the comparison circuit, the charging target from the constant current source (15) is one of the first capacitor (C1) and the second capacitor (C2), and the other is the discharging target. And a switching control circuit (8) that switches the charging voltage of the capacitor to be charged as the input voltage of the comparison circuit;
The charging voltage at the time when either one of the first capacitor (C1) and the second capacitor (C2) is switched to the discharge target by the switching control circuit (8), or both capacitors are respectively A correction unit (4) for generating correction data used for correcting the predetermined threshold value set by the threshold value setting circuit (20) based on each charging voltage at each time when it is switched to a discharge target;
A control unit (3) for controlling the threshold value setting circuit to set the predetermined threshold value based on the correction data generated by the correction unit;
An oscillation circuit comprising:   The switching control circuit (8) switches the charging target to be the other capacitor when the charging voltage of one capacitor to be charged is equal to or higher than the predetermined threshold, and the switching timing is higher than the switching timing. 6. The oscillation circuit according to claim 5, wherein switching of a next charging target is permitted after a predetermined time has elapsed.   The correction unit (4) is configured to charge one of the first capacitor (C1) and the second capacitor (C2) when the switching control circuit (8) is switched to a discharge target. When the detected charging voltage exceeds a predetermined representative voltage, correction data for generating the predetermined threshold value lower than a predetermined reference value is generated, and the detected charging voltage is the representative voltage. 7. The oscillation circuit according to claim 5, wherein if it is less than the correction value, correction data for generating the predetermined threshold value higher than the reference value is generated.   The correction unit (4) detects a charging voltage of the first capacitor (C1) at a time when the first capacitor (C1) is switched to a discharge target by the switching control circuit (8), and the second capacitor The charging voltage of the second capacitor (C2) is detected at the time when (C2) is switched to the discharge target, and the detected charging voltage of the first capacitor (C1) and the charging of the second capacitor (C2) are detected. When the statistical value reflecting the voltage exceeds a predetermined representative voltage, correction data for generating the predetermined threshold value lower than a predetermined reference value is generated. When the statistical value is lower than the representative voltage, the reference value is generated. 7. The oscillation circuit according to claim 5, wherein correction data for generating the predetermined threshold value higher than a value is generated. The correction unit includes an AD converter (7) that converts a charging voltage of at least one of the first capacitor (C1) and the second capacitor (C2) into a digital signal,
A path of a signal input to the AD converter is connected to a first path connected to one of the first capacitor (C1) and the second capacitor (C2) and another analog signal generation source (30). The oscillation circuit according to any one of claims 1 to 8, further comprising a path switching unit (3) for switching to a connected second path.

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