JP6498481B2 - Oscillation circuit and oscillation method - Google Patents

Description

  The present invention relates to an oscillation circuit and an oscillation method, and more particularly to an oscillation circuit built in a semiconductor device such as a microcontroller and an oscillation method thereof.

  Conventionally, as this type of oscillation circuit, one disclosed in Patent Document 1 is known. The oscillation circuit disclosed in Patent Document 1 compares the first and second capacitors charged or discharged by the current generated by the constant current source with the voltage V1 of the first capacitor and the reference voltage Vst. A first comparison circuit that outputs the first signal, a second comparison circuit that compares the voltage V2 of the second capacitor with the reference voltage Vst and outputs the second signal, and the first signal or the second RS flip-flop circuit that is set by one of the signals and reset by the other, and the first capacitor is charged when the RS flip-flop circuit is in the set state, and when the RS flip-flop is in the reset state The first charge / discharge control circuit to be discharged and the second capacitor to be charged when the RS flip-flop circuit is in the reset state. And a second charging and discharging control circuit to the discharge state when set. According to Patent Document 1, an oscillation signal having a stable frequency is output even if noise occurs due to the above configuration.

  Patent Document 2 discloses another type of oscillation circuit. The oscillation circuit disclosed in Patent Document 2 includes an RS flip-flop that generates output signals Q and QB based on a set signal and a reset signal, and capacitors C1 and C2, and capacitors C1 and C2 based on the output signals Q and QB. And a comparator 13 for comparing the first voltage corresponding to the charge accumulated in the capacitor C1 with the first reference voltage (Vcmp) and outputting a set signal. The comparator 14 outputs a reset signal by comparing the second voltage corresponding to the charge accumulated in the capacitor C2 with the first reference voltage (Vcmp), and the first reference voltage and the first voltage, respectively. The timing at which the levels match and the timing at which the respective voltage levels of the first reference voltage and the second voltage match are set to the frequencies of the output signals Q and QB. Flip and comprises a control unit for controlling.

JP 2007-243922 A JP 2013-038744 A

  However, in the configuration of the oscillation circuit disclosed in Patent Document 1, the output signal of the RS flip-flop circuit changes when the voltage V1 of the first capacitor reaches the reference voltage Vst or the voltage of the second capacitor. It is after the delay time Td caused by the operation delay of the first comparison circuit, the second comparison circuit, and the RS flip-flop circuit has elapsed since V2 reached the reference voltage Vst. For this reason, the oscillation circuit of Patent Document 1 has a problem that the oscillation frequency varies when the delay time Td varies due to variations in temperature and power supply voltage.

  Even in the configuration of the oscillation circuit disclosed in Patent Document 2, a high frequency such as 1 MHz or more is required as the oscillation frequency, and a high accuracy such as within ± 1% is required as the accuracy of the oscillation frequency. There is a concern that the temperature variation of the current source that generates the charge / discharge current and the reference voltage and the variation of the power supply voltage reach levels that cannot be ignored.

  The present invention has been made to solve the above-described problems, and an oscillation circuit and an oscillation method capable of suppressing fluctuations in oscillation frequency with respect to temperature fluctuations and power supply voltage fluctuations and improving the accuracy of the oscillation frequency. The purpose is to provide.

An oscillation circuit according to the present invention includes an RS flip-flop that generates an output signal by a set signal and a reset signal, a first capacitor that is charged by a first charging current, and a second capacitor that is charged by a second charging current A charge / discharge control unit for controlling the first charging current and the second charging current by the output signal to charge / discharge the first capacitor and the second capacitor; and A first comparator that compares the first charging signal and the first reference voltage, which is a change in voltage associated with charging and discharging, and outputs the set signal, and a change in voltage that accompanies charging and discharging of the second capacitor. a second comparator for outputting the reset signal by comparing the first reference voltage and the second charging signal, the peak value of the peak value and the second charging signal of the first charging signal A first control voltage generator for generating a Flip amplitude control voltage, with comprises a first voltage control unit which generates a difference voltage between the second reference voltage and the amplitude control voltage as said first reference voltage, a, The timing at which the voltage value of the first reference voltage and the voltage value of the first charging signal match, and the timing at which the voltage value of the first reference voltage and the voltage value of the second charging signal match, An amplitude control unit that controls the peak value of the first charge signal and the peak value of the second charge signal; and the slew rate of the first charge signal by changing the first charge current according to the frequency of the output signal And a charging current control unit that controls and controls the slew rate of the second charging signal by changing the second charging current according to the frequency of the output signal.

On the other hand, the oscillation method according to the present invention includes an RS flip-flop that generates an output signal by inputting a set signal and a reset signal, a first capacitor that is charged by a first charging current, and a first capacitor that is charged by a second charging current. An oscillation method for causing an oscillation circuit including two capacitors to oscillate, wherein a first charging signal, which is a change in voltage accompanying charging / discharging of the first capacitor due to the first charging current, is compared with a first reference voltage. The set signal is output, and a second charge signal, which is a change in voltage associated with charge / discharge of the second capacitor due to the second charge current, is compared with the first reference voltage, and the reset signal is is output, the timing at which the voltage value of the first reference voltage and the voltage value of the first charging signal matches the voltage value of the voltage value of the first reference voltage and the second charging signal And the first charging signal by changing the first charging current according to the frequency of the output signal, and controlling the timing according to the peak value of the first charging signal and the peak value of the second charging signal. And the slew rate of the second charging signal is controlled by changing the second charging current according to the frequency of the output signal .

  According to the present invention, it is possible to provide an oscillation circuit and an oscillation method capable of suppressing the fluctuation of the oscillation frequency with respect to the temperature fluctuation and the power supply voltage fluctuation and improving the accuracy of the oscillation frequency.

1 is a circuit diagram illustrating an example of an oscillation circuit according to a first embodiment. FIG. It is a circuit diagram which shows an example of the amplitude control part which concerns on 1st Embodiment. It is a circuit diagram which shows an example of the charging current control part which concerns on 1st Embodiment. 3 is a time chart illustrating an operation of the oscillation circuit according to the first embodiment. It is a circuit diagram which shows an example of the amplitude control part which concerns on 2nd Embodiment. It is a circuit diagram which shows an example of the charging current control part which concerns on 2nd Embodiment. It is a circuit diagram which shows an example of the oscillation circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows an example of the charging current control part which concerns on 3rd Embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
An oscillation circuit 10 according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 1, the oscillation circuit 10 includes a flip-flop 11, a charge / discharge control unit 12, comparators 13 and 14, an amplitude control unit 15, a charge current control unit 16, and capacitors C1 and C2. .

  The flip-flop 11 is an RS type flip-flop that generates output signals Q and QN based on the set signal S and the reset signal R. Output signals Q and QN of the flip-flop 11 are output as oscillation signals (clock signals) of the oscillation circuit 10.

Based on the output signals Q and QN, the charge / discharge control unit 12 controls the conduction state of the charging current B for charging the capacitor C1 and the charging current BN for charging the capacitor C2, and charges and discharges the capacitors C1 and C2 in a complementary manner. Circuit. More specifically, the charge / discharge control unit 12 includes a switch unit including switches SW1, SW2, SW3, and SW4.
The switches SW1, SW2, SW3, and SW4 are connected between the charging current control unit 16 that generates the charging currents B and BN and the capacitors C1 and C2, the GND (ground, ground), the capacitor C1, By controlling the conduction state with C2 based on the output signals Q and QN, the capacitors C1 and C2 are charged and discharged in a complementary manner. The terminal voltage of the capacitor C1 is changed by charging / discharging of the capacitor C1 to generate the charging signal A, and the terminal voltage of the capacitor C2 is changed by charging / discharging of the capacitor C2 to generate the charging signal AN.

  The comparator 13 compares the charge signal A of the capacitor C1 with the reference voltage WAVE_H and outputs a set signal S. The comparator 14 compares the charging signal AN of the capacitor C2 with the reference voltage WAVE_H and outputs a reset signal R.

  The amplitude control unit 15 is a circuit that detects the peak values of the charging signal A and the charging signal AN using the set signal S and the reset signal R, and generates the reference voltage WAVE_H based on the detected peak values.

  The charging current control unit 16 is a circuit that controls the charging current B for charging the capacitor C1 and the charging current BN for charging the capacitor C2 according to the frequencies of the output signals Q and QN of the flip-flop 11.

  The amplitude control unit 15 will be described in more detail with reference to FIG. As shown in FIG. 2, the amplitude control unit 15 includes a control voltage generation unit 151, a voltage control unit 152, and a buffer 157.

  The buffer 157 receives the set signal S and the reset signal R, generates an inverted signal SN (inverted set signal SN) of the set signal S, and an inverted signal RN (inverted reset signal RN) of the reset signal R, and a control voltage generation unit 151 is a circuit to be supplied to 151.

  The control voltage generator 151 includes a switch SW5 controlled by the inverted set signal SN, SW6 controlled by the set signal S, SW7 controlled by the inverted reset signal RN, SW8 controlled by the reset signal R, and a switch SW5. A switched capacitor circuit including a capacitor C4 connected to SW6, a capacitor C5 connected between switches SW7 and SW8, and a capacitor C6, and a wave of charging signal A and charging signal AN This circuit generates an amplitude control voltage PEAK corresponding to a high value.

  The voltage control unit 152 includes an amplifier 158, an integrator 154 including a capacitor C3, and a phase compensation circuit 153a including a resistor R8 and a capacitor C8, and according to a difference between the reference voltage VREF_H and the amplitude control voltage PEAK. The reference voltage WAVE_H is generated.

  With reference to FIG. 3, the charging current control unit 16 according to the present embodiment will be described in more detail. The charging current control unit 16 includes a control voltage generation unit 161, a voltage control unit 162, and a variable current source circuit 163.

  The control voltage generation unit 161 includes a switched capacitor resistor 165, a current mirror 164, a filter 166, and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, hereinafter referred to as “MOS transistor”) Q1, and converts a frequency into a voltage. Frequency-voltage conversion circuit (fV) conversion circuit). That is, the control voltage VFCR having a voltage value corresponding to the frequency of the output signals Q and QN is generated.

  Switched capacitor resistor 165 includes switch SW9 controlled by output signal Q, SW10 controlled by output signal QN, capacitor C9 connected between switches SW9 and SW10, and capacitor C10. . Then, the switches SW9 and SW10 are complementarily turned on and off by the output signals Q and QN, whereby C9 and C10 are complementarily charged and discharged. As a result, the resistance value between the source and GND of the MOS transistor Q1 changes according to the frequency of the output signals Q and QN, and the current I flowing through the MOS transistor Q1 changes with the frequency of the output signals Q and QN.

  The MOS transistor Q1 is connected between the current mirror 164 and the switched capacitor resistor 165, and the gate voltage is controlled by the reference voltage VCONT. That is, the MOS transistor Q1 forms a source follower circuit having the switched capacitor resistor 165 as a load, and functions as a voltage control element.

  The current mirror 164 includes current sources CS1 and CS2, mirrors the reference current I flowing through the current source CS1, and allows a current having a predetermined magnification to flow through the current source CS2. The current flowing through the current source CS2 is converted into a voltage by the resistor R1 connected to the current source CS2.

  The filter 166 removes switching noise from the signal converted into a voltage by the resistor R1, and generates a control voltage VFCR.

  The voltage control unit 162 includes an amplifier 169, an integration circuit 167 including a capacitor C11, and a phase compensation circuit 153b including a resistor R12 and a capacitor C12. Reference is made according to the difference between the reference voltage VREF and the control voltage VFCR. It is a circuit that generates a voltage as a reference voltage VCONT.

  The variable current source circuit 163 includes a MOS transistor Q2, a trimming circuit 168, and a resistor R2.

  In the MOS transistor Q2, the gate voltage is controlled by the reference voltage VCONT, the source potential is changed according to the reference voltage VCONT, and the current I ′ corresponding to the reference voltage VCONT is caused to flow through the resistor R2. That is, the MOS transistor Q2 forms a source follower circuit having the resistor R2 as a load, and functions as a voltage control element.

  The trimming circuit 168 is a mirror circuit configured to include current sources CS3, CS4, and CS5, and generates charging currents B and BN that are a predetermined multiple of the reference current I '. In the trimming circuit 168, the mirror ratio of the current sources CS4 and CS5 can be adjusted by the current adjustment signal, and the current values of the charging currents B and BN are adjusted.

  Next, the operation of the oscillation circuit 10 will be described with reference to FIG. FIG. 4 is a time chart showing changes in the charging signals A, AN, the set signal S, the reset signal R, and the output signals Q, QN over time.

  Consider a state in which the reset signal R input to the input terminal R of the flip-flop 11 is at the L (low) level and the set signal S input to the input terminal S rises to the H (high) level. At this time, the output signal Q output from the output terminal Q at time t1 becomes H level, and the output signal QN output from one output terminal QN becomes L level.

  Then, due to the output signals Q and QN, the switch SW1 of the charge / discharge control unit 12 shown in FIG. 1 is turned off and the switch SW2 is turned on, so that the charge stored in the capacitor C1 is discharged via the switch SW2 and charged. The signal A becomes L level, and as a result, the set signal S after passing through the comparator 13 becomes L level.

  On the other hand, since the switch SW3 is turned on and the switch SW4 is turned off, the capacitor C2 is charged by the charging current BN that is a constant current from the variable current source circuit 163 of the charging current control unit 16 shown in FIG. The potential increases gradually. When the potential of the charging signal AN reaches the reference voltage WAVE_H of the comparator 14, the reset signal R becomes H level, the output signal Q of the flip-flop 11 becomes L level, and QN becomes H level. The above is the operation from time t1 to time t2.

  Due to the output signals Q and QN, the switch SW3 of the charge / discharge control unit 12 is turned off and the switch SW4 is turned on. Therefore, the charge stored in the capacitor C2 is discharged through the switch SW4, and the charge signal AN becomes L level. The reset signal after passing through the comparator 14 becomes L level.

  On the other hand, since the switch SW1 is turned on and the switch SW2 is turned off by the output signals Q and QN, the capacitor C1 is charged by the charging current B, which is a constant current from the variable current source circuit 163 of the charging current control unit 16, and charged. The potential of the signal A gradually increases. When the potential of the charging signal A reaches the reference voltage WAVE_H of the comparator 13, the set signal S becomes H level, the output signal Q of the flip-flop 11 becomes H level, and the output signal QN becomes L level. The above is the operation from time t2 to time t3.

  By repeating the operation from time t1 to time t3, the oscillation circuit 10 outputs the output signals Q and QN of the flip-flop 11 as oscillation signals (clock signals).

  Here, the delay times Td of the charging signals A and AN will be described. As shown in FIG. 4, the delay time Td is the difference between the time when the peaks of the charging signals A and AN reach the reference voltage VREF_H and the time when the peak reaches the reference voltage WAVE_H. This delay time Td is generated by the total delay time of the delay time of the comparator 13 or 14 and the delay time of the flip-flop 11.

  Originally, it is desirable that the set signal S and the reset signal R are instantaneously output from the comparators 13 and 14 when the charging signals A and AN reach the comparison level of the comparators 13 and 14. However, due to the delay time Td, which is the sum of the delay times of the comparators 13 and 14 and the flip-flop 11, the peak values of the charging signals A and AN become higher than the comparison level of the comparators 13 and 14. When the delay time Td changes due to a change in temperature or a change in power supply voltage (VDD), the waveforms (crest values) of the charging signals A and AN change, so the oscillation frequency of the oscillation circuit 10 changes. Therefore, in the present embodiment, the amplitude control unit 15 keeps the peak values of the charging signals A and AN constant, thereby suppressing fluctuations in the oscillation frequency due to the delay time Td.

  Hereinafter, circuit operations of the amplitude control unit 15 and the charging current control unit 16 in the oscillation circuit 10 according to the present embodiment will be described in more detail.

  As described above, the control voltage generation unit 151 of the amplitude control unit 15 illustrated in FIG. 2 is configured as a switched capacitor including the switches SW5, SW6, SW7, and SW8, and the capacitors C4, C5, and C6. That is, when the set signal S is at the L level, the capacitor C4 is charged by the charge signal A, and when the set signal S is at the H level, the charge of the capacitor C4 is transferred to the capacitor C6, and the output from the control voltage generator 151 An amplitude control voltage PEAK is generated. Similarly, when the reset signal R is at the L level, the capacitor C5 is charged by the charge signal AN, and when the reset signal R is at the H level, the charge of the capacitor C5 is transferred to the capacitor C6 and output from the control voltage generation unit 151. A certain amplitude control voltage PEAK is generated.

  Since the set signal S samples the charging signal A at a timing at which the voltage of the charging signal A becomes substantially maximum, the voltage of the amplitude control voltage PEAK that is the output of the control voltage generator 151 is the maximum value of the charging signal A, that is, Crest value. Further, since the reset signal R samples the charging signal AN at the timing when the charging signal AN becomes substantially maximum, the voltage of the amplitude control voltage PEAK becomes the maximum value of the charging signal AN, that is, the peak value.

  The voltage control unit 152 of the amplitude control unit 15 shown in FIG. 2 is configured as an integration circuit including an integrator 154, and the integrator 154 includes an amplifier 158 and a capacitor C3. That is, the integrator 154 integrates the difference between the reference voltage VREF_H of the amplifier 158 and the amplitude control voltage PEAK and accumulates it in the capacitor C3. When the amplitude control voltage PEAK is higher than the reference voltage VREF_H, the voltage of the reference voltage WAVE_H that is the output of the integrator 154 decreases and the comparison level of the comparators 13 and 14 shown in FIG. The peak value of the signal AN decreases. When the peak values of the charging signal A and the charging signal AN decrease, negative feedback is applied so as to decrease the voltage of the amplitude control voltage PEAK that is the output of the control voltage generator 151.

  On the other hand, when the amplitude control voltage PEAK is lower than the reference voltage VREF_H, the voltage of the reference voltage WAVE_H increases and the comparison level of the comparators 13 and 14 increases, so that the peak values of the charging signal A and the charging signal AN increase. When the peak values of the charge signal A and the charge signal AN rise, negative feedback is applied so as to raise the voltage of the amplitude control voltage PEAK.

  With the above operation, the amplitude control unit 15 performs control so that the peak values of the charging signals A and AN are maintained constant. The phase compensation circuit 153a is a circuit that compensates for the phase margin of the negative feedback loop so that the negative feedback loop does not oscillate when the phase margin of the negative feedback loop is small. Therefore, it is not necessary to provide the negative feedback loop if the phase margin is sufficient.

As described above, the charging current control unit 16 shown in FIG. 3 is a circuit that supplies the charging current B to the capacitor C1 and the charging current BN to the capacitor C2 shown in FIG. The control voltage generation unit 161 is a frequency-voltage conversion circuit (fV conversion circuit). When the resistance value of the switched capacitor resistor 165 connected to the source of the MOS transistor Q1 changes according to the output signals Q and QN, The source load of the MOS transistor changes. As a result, the average current I flowing through the MOS transistor Q1 is as follows. The oscillation frequency of the oscillation circuit 10 is f (Hz), the capacitance of the capacitor C9 is C (F), and the voltage applied to the capacitor C10 is V (V). It is represented by (Formula 1) shown below.
I = fCV (Formula 1)

In other words, since the equivalent resistance R is derived from the relationship between I and V, the equivalent resistance R of the switched capacitor resistor 165 can be expressed as (Expression 2) shown below. Can do.
R = V / I = 1 / (fC) (Formula 2)

  More specifically, the capacitor C10 is connected to the source of the MOS transistor (voltage control element) Q1, and the MOS transistor Q1 operates as a source follower circuit. Therefore, the voltage applied to the capacitor C10 is the gate voltage of the MOS transistor Q1. Is controlled by a reference voltage VCONT. As a result, the current I flowing through the capacitor C10 is controlled by the reference voltage VCONT. The current I is passed through the resistor R <b> 1 by the current mirror 164, converted into a voltage, and output as a control voltage VFCR that is an output of the control voltage generation unit 161 via the filter 166.

  The second voltage control unit 162 includes an integration circuit 167 including an amplifier 169 and a capacitor C11. The second voltage control unit 162 integrates the difference between the reference voltage VREF and the control voltage VFCR that is the output of the control voltage generation unit 161 and accumulates it in the capacitor C11. To do.

  Since the MOS transistor (voltage control element) Q2 of the variable current source circuit 163 operates as a source follower circuit having a resistor R2 connected to the source, the voltage across the resistor R2 is a reference voltage VCONT that is the gate voltage of the MOS transistor Q2. Controlled by In the present embodiment, the MOS transistors Q1 and Q2 are configured with the same dimension (size). Then, the resistance value of the resistor R2 is set to the value shown in (Expression 2) and R2 = 1 / (fC), whereby the current I ′ flowing through the resistor R2 is changed to the reference current I flowing through the switched capacitor resistor 165. The current is the same size.

  The trimming circuit 168 configured by a current mirror mirrors the current source CS3 serving as the current source of the current I ′, the current I flowing through the current source CS3 at a predetermined magnification, and generates a charging current B. A current source CS4 for generating BN is provided. The current sources CS4 and CS5 are each configured to be adjustable by a charging current adjustment signal, and the current values of the charging currents B and BN are variable using the current I 'flowing through the resistor R2 as a reference current. In the present embodiment, the charging currents B and BN have the same current value.

  Next, the negative feedback operation of the charging current control unit 16 will be described with reference to FIG. When the frequency (oscillation frequency) of the output signals Q and QN increases, the resistance value of the switched capacitor resistor 165 decreases, the reference current I increases, and the control voltage VFCR, which is the output of the control voltage generator 161, increases. Then, at the input of the integrating circuit 167, the control voltage VFCR becomes higher than the reference voltage VREF, and the reference voltage VCONT is lowered. As a result, the gate potential of the MOS transistor Q1 decreases, and the current I flowing through the switched capacitor resistor 165 decreases.

  On the other hand, since the potential of the MOS transistor Q2 is lowered by the lowered reference voltage VCONT, the current I ′ flowing through the resistor R2 is also lowered, and the charging currents B and BN output from the variable current source circuit 163 are lowered. The slew rate of the charging signals A and AN shown decreases. Then, the time until the charging signals A and AN reach a predetermined peak value becomes long, and as a result, the oscillation frequency of the oscillation circuit 10 decreases. When the frequencies of the output signals Q and QN are lowered, the operation is reversed.

  As described above, the charging current control unit 16 applies negative feedback to the slew rates of the charging signals A and AN so that the oscillation frequency of the oscillation circuit 10 becomes constant. The phase compensation circuit 153b is a circuit that compensates for the phase margin of the negative feedback loop so that the negative feedback loop does not oscillate when the phase margin of the negative feedback loop is small. Therefore, it is not necessary to provide the negative feedback loop if the phase margin is sufficient.

  As described above in detail, in the oscillation circuit 10 according to the present embodiment, the amplitude control unit 15 determines the peak values of the charging signal A for charging / discharging the capacitor C1 and the charging signal AN for charging / discharging the capacitor C2. Feedback control is performed so as to be equal to the reference voltage VREF_H. As a result, the peak values of the charging signals A and AN for charging the capacitors C1 and C2 are kept constant even when the temperature and the power supply voltage VDD change. In the oscillation circuit 10 according to the present embodiment, the charging current control unit 16 further detects the oscillation frequency of the oscillation circuit 10 so that the charging currents B and BN for charging the capacitors C1 and C2 are kept constant. Feedback control. As a result, the slew rates of the charging signals A and AN are kept constant even when the temperature and the power supply voltage VDD change. In other words, in the oscillation circuit 10 according to the present embodiment, feedback control is performed by the amplitude control unit 15 and the charging current control unit 16 so that the waveforms of the charging signals A and AN are constant. According to the oscillation circuit 10 according to the present embodiment configured as described above, fluctuations in the oscillation frequency with respect to temperature fluctuations and power supply voltage fluctuations can be suppressed, and an oscillation signal with a high frequency can be output.

[Second Embodiment]
The oscillator circuit according to the present embodiment will be described with reference to FIGS. The oscillation circuit according to the present embodiment is obtained by changing the amplitude control unit 15 and the charging current control unit 16 in the oscillation circuit 10 described above. Therefore, since the configuration of the entire oscillation circuit is the same as that of the oscillation circuit 10, the reference to the entire oscillation circuit will be described with reference to FIG.

  FIG. 5 shows an amplitude control unit 15a according to the present embodiment. In contrast to the amplitude control unit 15 illustrated in FIG. 2, the amplitude control unit 15 a further includes a reference voltage generation unit 155 that controls the voltage level of the reference voltage VREF_H according to the power supply voltage VDD.

  The reference voltage generation unit 155 includes voltage dividing resistors R3 and R4 that divide the power supply voltage VDD, a unity gain amplifier (buffer) 156 that buffers the reference voltage VBG, and a variable resistor R5. A variable resistor R5 is connected between the voltage dividing point of the voltage dividing resistors R3 and R4 and the output of the unity gain amplifier 156, and a plurality of voltage dependency adjustment signals (not shown, trimming circuit according to the voltage value). ) To adjust the resistance value of the variable resistor R5. The reference voltage VBG is generated from a band gap circuit (not shown). A bandgap circuit is a circuit that creates a stable voltage value against temperature fluctuations and power supply voltage fluctuations using a bandgap voltage that is a physical property of a semiconductor material, and is also called a bandgap reference.

  Under standard design conditions, the voltage divided by the voltage dividing resistors R3 and R4 is equal to the reference voltage VBG. Then, the resistance value of the variable resistor R5 is adjusted by the plurality of voltage dependency adjustment signals in accordance with the delay time of the comparators 13 and 14 and the flip-flop 11, that is, the change of the delay time Td due to the fluctuation of the power supply voltage VDD. As a result, the power supply voltage dependency of the reference voltage VREF_H is adjusted.

  That is, when the power supply voltage VDD changes, the reference voltage VREF_H also changes. However, if the resistance value of the variable resistor R5 is reduced, the reference voltage VREF_H becomes a voltage close to the reference voltage VBG. On the contrary, if the resistance value of the variable resistor R5 is increased, the voltage is close to the voltage divided by the ratio of the voltage dividing resistors R3 and R4 without being affected by the reference voltage VBG. That is, the power supply voltage dependency of the reference voltage VREF_H can be adjusted by the variable resistor R5.

  When the power supply voltage VDD rises and VREF_H rises, the crest values of the charging signals A and AN increase when the charging current to the capacitors C1 and C2 is constant (the charging time for the capacitors C1 and C2 is long). Become). On the other hand, the delay time Td generally decreases as the power supply voltage VDD increases (the charging time for the capacitors C1 and C2 decreases). Therefore, both are canceled, and as a result, fluctuations in the oscillation frequency of the oscillation circuit 10 due to fluctuations in the power supply voltage are suppressed. When the power supply voltage VDD decreases, the operation is the reverse of the above, and the fluctuation of the oscillation frequency of the oscillation circuit 10 due to the fluctuation of the power supply voltage is also suppressed.

  Next, the charging current control unit 16a according to the present embodiment will be described with reference to FIG. The charging current control unit 16a further includes a reference voltage generation unit 17 that controls the voltage level of the reference voltage VREF according to the temperature with respect to the charging current control unit 16 shown in FIG.

    The reference voltage generation unit 17 includes a PTAT (Proportional To Absolute Temperature) current source 171, an R 17 connected to the PTAT current source 171, a CTAT (Complementary To Absolute Temperature) element 172, and a PTAT current source 171 value. A trimming circuit 173 that adjusts using a plurality of voltage dependence adjustment signals is provided, and a current adjusted by the trimming circuit 173 is supplied to the CTAT element 172 to generate the reference voltage VREF.

  The delay time Td from the input of the comparators 13 and 14 to the output of the flip-flop 11 described above has a large proportion of the delay time Td in one cycle of the oscillation waveform when the oscillation frequency of the oscillation circuit 10 is relatively high. And cannot be ignored.

The delay time Td generally has temperature dependency, but the reference voltage generation unit 17 according to the present embodiment adjusts the temperature dependency of the reference voltage VREF by combining the PTAT current source 171 and the CTAT element 172. Thus, the temperature dependence of the delay time Td is suppressed.
That is, the PTAT current source 171 is a current source having a positive temperature dependency, while the CTAT element 172 is configured to include a diode-connected MOS transistor Q3 and the resistor R18, and has a negative temperature dependency of the resistance value. It is a resistance element. The current dependency of the PTAT current source 171 adjusted by the trimming circuit 173 is passed through the CTAT element 172 to adjust the temperature dependence of the reference voltage VREF.

  More specifically, when the temperature dependence of the delay time Td is positive, the delay time Td increases as the temperature rises. At this time, if the temperature dependence of the reference voltage VREF is positive, that is, the voltage is set to increase when the temperature rises, the reference voltage VCONT increases, and the capacitors C1, C2 generated by the variable current source circuit 163 The charging currents B and BN are increased. When the charging currents B and BN are increased, the slew rates of the charging signals A and AN are increased and the charging time is shortened. Therefore, the increase in the delay time Td can be canceled and the fluctuation of the oscillation frequency can be reduced. .

  On the other hand, when the temperature dependence of the delay time Td is negative, the delay time Td decreases as the temperature rises. At this time, if the temperature dependence of the reference voltage VREF is negative, that is, the voltage is set to be low when the temperature rises, the reference voltage VCONT is lowered, and the charging currents B and BN to the capacitors C1 and C2 are small. Become. When the charging currents B and BN are reduced, the slew rates of the charging signals A and AN are reduced and the charging time is increased, so that the decrease in the delay time Td can be canceled and the fluctuation of the oscillation frequency can be reduced. .

  The delay time Td generally has temperature dependency and power supply voltage dependency. In the oscillation circuit 10 according to the present embodiment, the amplitude control unit 15a that adjusts the peak values of the charging signals A and AN suppresses fluctuations in the power supply voltage. A reference voltage generation unit 155 is provided. Further, a reference voltage generation unit 17 for suppressing temperature fluctuation is provided in the charging current control unit 16a that adjusts the charging currents B and BN to the capacitors C1 and C2. As a result, according to the oscillation circuit according to the present embodiment, there is an effect that it is possible to obtain an oscillation frequency with higher accuracy even when the oscillation frequency is relatively high.

  The reference voltage generation unit 155 that suppresses power supply voltage dependency is not limited to the amplitude control unit 15, and may be used for the charging current control unit 16, and the reference voltage generation unit 17 that suppresses temperature fluctuations Not only the current control unit 16 but also the amplitude control unit 15 may be used. That is, the reference voltage generation unit 155 and the reference voltage generation unit 17 are general-purpose circuits that generate a reference voltage in which power supply voltage fluctuations and temperature fluctuations are suppressed.

[Third Embodiment]
The oscillation circuit 10a according to the present embodiment will be described with reference to FIGS. In the oscillation circuit 10a, the capacitors C1 and C2 are replaced with variable capacitors C13 and C14, and the charging current control unit 16 is replaced with a charging current control unit 16b as compared with the oscillation circuit 10 shown in FIG. FIG. 7 shows the entire circuit of the oscillation circuit 10a, and FIG. 8 shows the circuit of the charging current control unit 16b.

  As shown in FIG. 7, in the oscillation circuit 10a, the capacitor C13 charged and discharged by the charge / discharge control unit 12 and the capacitor C14 each have a variable capacitance. Each of the variable capacitors C13 and C14 includes a plurality of capacitors and a plurality of switches connected to each capacitor, and the capacitance values of the variable capacitors C13 and C14 are adjusted by a control signal for controlling the plurality of switches.

  When the capacitance value of the variable capacitor C13 (C14) is set to be large, the slew rate of the charging signal A (AN) is reduced, so that the time to reach the reference voltage WAVE_H that is the comparison voltage of the comparator 13 (14) is increased, and the oscillation frequency Decreases. On the other hand, if the capacitance value of the variable capacitor C13 (C14) is set to be small, the slew rate of the charging signal A (AN) is increased, so that the time to reach the reference voltage WAVE_H is shortened and the oscillation frequency is increased. As described above, the oscillation frequency can be controlled by adjusting the capacitance values of the variable capacitors C13 and C14.

  As the capacitors C1 and C2 are replaced with the variable capacitors C13 and C14, as shown in FIG. 8, in the charging current control unit 16b according to the present embodiment, the trimming circuit 168 shown in FIG. Replaced. That is, the trimming circuit 168 includes a current mirror including current sources CS3, CS4, and CS5. The current flowing through the current source CS3 is used as a reference current, and the currents flowing through the current sources CS4 and CS5 are adjusted by a plurality of current adjustment signals. Currents B and BN were set. On the other hand, in the oscillation circuit 10a, the charging currents B and BN output from the charging current control unit 16b are constant in the current mirror circuit 174 including the current sources CS8, CS9, and CS10, and the variable capacitor C13 The charging currents B and BN are set by changing the capacitance value of C14.

  As described above, the oscillation circuit and the oscillation method that can suppress the fluctuation of the oscillation frequency with respect to the temperature fluctuation and the power supply voltage fluctuation and can improve the accuracy of the oscillation frequency also by the oscillation circuit according to the present embodiment are provided. can do. In the present embodiment, in particular, the oscillation circuit according to the present embodiment is configured by a semiconductor integrated circuit, and characteristic changes due to stress generated when packaged with a mold resin are reduced, thereby suppressing fluctuations in oscillation frequency. The effect of being able to be obtained is obtained.

  In the above embodiment, the variable current source circuit 163 includes the resistor R2 that allows the reference current I ′ to flow according to the reference voltage VCONT, and further generates a variable current from the reference current I ′ by a plurality of current adjustment signals. Although the trimming circuit 168 is provided, the present invention is not limited to this. For example, instead of the resistor R2, a circuit including a plurality of resistor elements connected in series and a plurality of switch elements connecting the connection points of the plurality of resistor elements to GND is used. The resistance value may be changed by selectively connecting connection points of a plurality of resistors to GND by a plurality of adjustment signals for controlling the above.

  In the above embodiment, the reference voltage generation unit 17 uses a configuration in which the current value is changed by the trimming circuit 173 that mirrors the current flowing through the PTAT current source 171. However, the present invention is not limited to this. For example, instead of the CTAT element 172, a circuit including a plurality of CTAT elements connected in series and a plurality of switch elements that connect each of connection points of the plurality of CTAT elements to GND is used. A current value may be changed by selectively connecting connection points of a plurality of CTAT elements to GND by an adjustment signal for controlling each of them.

10, 10a Oscillator 11 Flip-flop 12, 12a Charge / discharge controller 13 Comparator 14 Comparator 15, 15a Amplitude controller 16, 16a, 16b Charge current controller 17 Reference voltage generator 151 Control voltage generator 152 Voltage controller 153a, 153b Phase compensation circuit 154 Integrator 155 Reference voltage generation unit 156 Unity gain amplifier 157 Buffer 158 Amplifier 161 Control voltage generation unit 162 Voltage control unit 163, 163a Variable current source circuit 164 Current mirror 165 Switched capacitor resistance 166 Filter 167 Integration circuit 168 Trimming circuit 169 Amplifier 171 PTAT current source 172 CTAT element 173 Trimming circuit 174 Current mirror circuit A, AN Charge signal B, BN Charge current C1, C2, C3, C4, C5, C6, C8, C9, C10, C11, C12 Capacitors C13, C14 Variable capacitors CS1, CS2, CS3, CS4, CS5, CS8, CS9, CS10 Current source Q1, Q2, Q3 MOS transistor Q, QN Output signals R1, R2, R3, R4, R8, R12, R17, R18 Resistor R5 Variable resistors SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10 Switch PEAK Amplitude control voltage VBG Reference voltage VCONT Reference voltage VDD Power supply voltage VFCR Control voltage VREF Reference voltage VREF_H Reference voltage WAVE_H Reference voltage

Claims (9)

An RS flip-flop that generates an output signal by a set signal and a reset signal;
A first capacitor charged by a first charging current;
A second capacitor charged by a second charging current;
A charge / discharge controller that controls the first charge current and the second charge current by the output signal to charge / discharge the first capacitor and the second capacitor;
A first comparator that compares the first charging signal, which is a change in voltage associated with charging and discharging of the first capacitor, with a first reference voltage and outputs the set signal;
A second comparator that compares the first reference voltage with a second charging signal, which is a change in voltage associated with charging and discharging of the second capacitor, and outputs the reset signal;
A first control voltage generation unit configured to generate an amplitude control voltage according to a peak value of the first charging signal and a peak value of the second charging signal; and a difference voltage between the second reference voltage and the amplitude control voltage A first voltage control unit that generates a first reference voltage, a timing at which a voltage value of the first reference voltage and a voltage value of the first charging signal match, and a voltage value of the first reference voltage And an amplitude control unit that controls the timing at which the voltage value of the second charging signal coincides with the peak value of the first charging signal and the peak value of the second charging signal;
The first charging current is changed according to the frequency of the output signal to control the slew rate of the first charging signal, and the second charging current is changed according to the frequency of the output signal to slew the second charging signal. A charge current control unit for controlling the rate;
An oscillation circuit comprising: The first control voltage generation unit includes a plurality of capacitors and a plurality of switches, and generates the amplitude control voltage by sampling the first charging signal by switching the plurality of switches according to the set signal, A switched capacitor circuit that generates the amplitude control voltage by switching the plurality of switches according to the reset signal and sampling the second charging signal;
The oscillation circuit according to claim 1, wherein the first voltage control unit is an integration circuit that integrates a voltage difference between the second reference voltage and the amplitude control voltage. The first voltage control unit includes a resistor pair that divides a power supply voltage, a buffer that receives a third reference voltage, and a variable resistor connected between a connection point of the resistor pair and an output of the buffer, The second reference voltage generation unit that generates the second reference voltage in which the fluctuation of the voltage value due to the fluctuation of the power supply voltage is suppressed by adjusting the resistance value of the variable resistor by an adjustment signal. 2. The oscillation circuit according to 2.   The oscillation circuit according to claim 3, wherein the second reference voltage generation unit includes a band gap circuit that generates the third reference voltage. The charge / discharge control unit includes a first switch unit that switches between charging the first capacitor with the first charging current or discharging the charge accumulated in the first capacitor, and the second capacitor. A second switch unit that switches between charging with the second charging current or discharging the electric charge stored in the second capacitor, and the first switch unit and the second switch unit, The oscillation circuit according to claim 1, wherein the oscillation circuit is switched by the output signal to charge / discharge the first capacitor and the second capacitor. The charging current control unit is a second control voltage generating unit that generates a control voltage based on a fourth reference voltage and the frequency of the output signal, and a difference voltage between a fifth reference voltage and the control voltage is a fourth reference voltage. The variable voltage source circuit which produces | generates the said 1st charging current and the said 2nd charging current based on the said 2nd voltage control part produced | generated as said, and the said 4th reference voltage, The any one of Claims 1-5 The oscillation circuit described in 1. The second control voltage generation unit is inserted between a switched capacitor resistor and a current mirror that indicate a resistance value according to the frequency of the output signal, and between the switched capacitor resistor and the input of the current mirror, and A first voltage control element that controls a voltage at a connection point with the switched capacitor resistor by a fourth reference voltage, and converts an output current of the current mirror into a voltage according to a frequency of the output signal; Generating the control voltage;
The second voltage control unit is an integration circuit that integrates a difference voltage between the fifth reference voltage and the control voltage,
The variable current source circuit is connected to the fourth reference voltage, and a second voltage control element that flows a reference current according to the fourth reference voltage, and replicates a plurality of currents having a plurality of current values from the reference current. The oscillation circuit according to claim 6, further comprising a trimming circuit that adjusts each of the current values of the plurality of currents with an adjustment signal to generate the first charging current and the second charging current. The second voltage control unit includes a PTAT current source, a CTAT element, and a trimming circuit that adjusts a current value of the PTAT current source by an adjustment signal, and causes the current adjusted by the trimming circuit to flow around the CTAT element. Including a fifth reference voltage generation unit that generates the fifth reference voltage in which a variation in voltage value due to a variation in temperature is suppressed;
The oscillation circuit according to claim 6 or 7. An oscillation circuit including an RS flip-flop that generates an output signal by inputting a set signal and a reset signal, a first capacitor that is charged by a first charging current, and a second capacitor that is charged by a second charging current is oscillated. An oscillation method,
A first charging signal, which is a change in voltage associated with charging / discharging of the first capacitor due to the first charging current, is compared with a first reference voltage to output the set signal, and the second charging current is used to output the set signal. A second charge signal, which is a change in voltage associated with charging / discharging of the second capacitor, and the first reference voltage are compared to output the reset signal;
The timing at which the voltage value of the first reference voltage and the voltage value of the first charging signal match, and the timing at which the voltage value of the first reference voltage and the voltage value of the second charging signal match, Control according to the peak value of the first charging signal and the peak value of the second charging signal,
The first charging current is changed according to the frequency of the output signal to control the slew rate of the first charging signal, and the second charging current is changed according to the frequency of the output signal. An oscillation method that controls the slew rate .

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