JP5955608B2 - Communication system between processing units - Google Patents

Description

  The present invention relates to a communication system between processing devices, and particularly relates to a communication abnormality.

  There is a communication system that performs communication between a first device and a second device via a transmission line. In a certain communication system, each of the first device and the second device determines whether they can communicate with each other and transmits communication availability information. Thereby, the first device and the second device can recognize whether or not the communication partner can communicate.

  In order to reduce the number of signal lines in the transmission path, for example, a serial / parallel converter may be provided in each of the first device and the second device. Each converter receives a clock and data (serial data) from a communication partner via a transmission path, and converts the serial data into appropriate parallel data using the clock.

  Patent Document 1 discloses a technique related to communication between the apparatus main body and an external apparatus. In Patent Document 1, the apparatus main body transmits a clock signal (CLK signal) and a data signal (CMD signal) to an external apparatus, and the external apparatus analyzes the data signal and outputs a status signal (STS signal) corresponding thereto. Send to the main unit. This exchange is performed every communication cycle.

  When the external device takes a predetermined time or longer to transmit the status signal, it is determined that a communication error has occurred, and the external device maintains the status signal at the high level. On the other hand, the apparatus main body receives the status signal maintained at the high level at the start of the next communication cycle, and recognizes that a communication error has occurred.

JP 2011-187079 A

  However, in the communication system described above, for example, when communication abnormality occurs in the first device and the clock cannot be transmitted to the second device, the conversion unit of the second device stops without receiving the clock (cannot execute the conversion operation). . Therefore, the second device cannot recognize that the first device cannot communicate.

  Further, in the technique of Patent Document 1, when it is recognized that a communication error has occurred in the external device, a high-level status signal is transmitted. However, if a communication error occurs in the external device itself and the status signal cannot be transmitted, The main unit cannot recognize a communication error.

  Accordingly, an object of the present invention is to provide an inter-processor communication system in which the second device can recognize the abnormality when the clock from the first device to the second device stops.

A first aspect of an inter-processing device communication system according to the present invention is an inter-processing device communication system including a first device, a second device, and a transmission line connecting the first device and the second device. The first device transmits transmission data synchronized with a predetermined transmission clock to the second device via the transmission path in M (M is a natural number of 2 or more) bit parallel or 1 bit serial. The transmission clock is transmitted to the second device via the transmission line, and the second device transmits data synchronized with a predetermined bus clock in n (n is a natural number of 2 or more) bit parallel. A signal line group, a processing unit that transmits / receives data between the signal line group, the transmission clock and the transmission data from the transmission path, and determines whether the transmission clock has stopped; Judgment The transmission clock and the transmission data are transmitted as a reception clock and reception data, and when a positive determination is made, a predetermined alternative clock is synchronized as the reception clock and the alternative clock as the reception data. And receiving the reception data from the reception data relay unit and the reception data relay unit in M-bit parallel or 1-bit serial, and receiving the reception clock from the reception data relay unit, Converting the received data into n-bit parallel received data using a bus clock and the received clock, and transmitting the converted received data to the processing unit via the signal line group ; and a clock generator for generating the generated clock to the bus clock, the received data The relay section samples a determination clock that is equal to the transmission clock or is generated based on the transmission clock and repeatedly takes active / inactive at a sampling frequency higher than twice the frequency of the determination clock, and the sampling value Determines that the transmission clock has stopped when the number of times of continuously taking the same value is greater than a reference number of times that is an integer equal to or greater than a value obtained by dividing the sampling frequency by twice the frequency of the determination clock, The converter generates a second transmission clock using the generation clock, receives second transmission data synchronized with the bus clock in n-bit parallel from the signal line group, and converts the bus clock and the second transmission clock. To convert the second transmission data into M-bit parallel or 1-bit serial third transmission data. And transmitting the third transmission data and the second transmission clock to the first device via the transmission line, the sampling frequency being defined based on the generation clock or the bus clock, and the sampling The frequency is equal to the frequency of the generation clock, the frequency of the transmission clock takes a value between the maximum value ftmax and the minimum value ftmin, and the frequency of the generation clock is between the maximum value fpmax and the minimum value fpmin. The determination clock is generated by dividing the transmission clock by a predetermined division ratio DIV, the division ratio DIV satisfies DIV> 2 ftmax / fpmin, and the number of times reference value DETCT is DETCT> fpmax -DIV / (2xftmin) is satisfied .

A second aspect of the inter-processor communication system according to the present invention is the inter-processor communication system according to the first aspect, wherein the alternative clock is the bus clock or generated based on the bus clock. .

A third aspect of the inter-processor communication system according to the present invention is the inter-processor communication system according to the first or second aspect, wherein the alternative clock is the generation clock or the generation clock. Based on.

A fourth aspect of the inter-processing apparatus communication system according to the present invention is the inter-processing apparatus communication system according to any one of the first to third aspects, wherein the first apparatus is capable of communicating with itself. Is transmitted to the second device as the transmission information, and the abnormality information is equal to information indicating that communication is impossible in the communication availability information.

According to the first and third aspects of the inter-processor communication system according to the present invention, even when the transmission clock from the first device is stopped, the conversion unit receives the alternative clock as the reception clock, Abnormal information is received as reception data defined by the alternative clock. At this time, the conversion unit converts the abnormality information defined by the alternative clock into reception data defined by the bus clock and transmits the received data to the processing unit.

  Therefore, when the transmission clock from the first device stops, the conversion unit can transmit the abnormality information to the processing unit.

  In addition, since the abnormality information is transmitted to the processing unit using the function of the conversion unit, it is necessary to increase the number of signal lines in the signal line group as compared with the case where the signal line group and the reception data relay unit are separately connected. There is no.

In addition , the stop of the transmission clock can be determined based on the number of times that the sampling value continuously takes the same value.

In addition , the sampling frequency is defined by a generation clock or a bus clock. Therefore, the circuit scale or manufacturing cost can be reduced as compared with the case where the clock defining the sampling frequency is generated from scratch.

Moreover , even if each of the frequency of the transmission clock and the frequency of the generation clock fluctuates between the maximum value and the minimum value, it is possible to appropriately determine whether the transmission clock is stopped.

According to the second aspect of the inter-processor communication system according to the present invention, the circuit scale and manufacturing cost can be suppressed as compared with the case where an alternative clock is generated from scratch.

According to the fourth aspect of the inter-processing-device communication system of the present invention, it can be recognized that the first device cannot communicate without increasing the types of information that the processing unit should recognize.

It is a figure which shows an example of a notional structure of the communication system between processing apparatuses. It is a figure which shows an example of a notional structure of the communication system between processing apparatuses. It is a figure which shows an example of a notional internal structure of a selection part. It is a figure which shows an example of the relationship between a determination clock and a sampling period. It is a figure which shows an example of the relationship between a determination clock and a sampling period. It is a figure which shows an example of a notional structure of the communication system between processing apparatuses.

  As shown in FIG. 1, the first device 10 and the second device 20 are connected to each other via a transmission line 30 and communicate with each other. For example, the first device 10 transmits whether or not it can communicate to the second device 20 via the transmission line 30, and the second device 20 indicates whether or not it can communicate with the transmission line 30. To the first device 10 via

  In the example of FIG. 1, the first device 10 is connected to, for example, an imaging device (for example, an image sensor) 40, and is connected to the second device 20 via an image transmission path 31 that is different from the transmission path 30. For example, the first device 10 receives imaging data (original image data) captured by the imaging device 40, appropriately processes the imaging data, and then passes the image data to the second device 20 via the image transmission path 31. Send.

  The second device 20 appropriately performs known image processing on the received data, and transmits this to a device (not shown).

  In such an image processing device, the first device 10 can be grasped as an intermediary device that mediates communication between the imaging device 40 and the second device 20, for example. For example, the first device 10 is an intermediary device for matching a mismatch in connection conditions between the imaging device 40 and the second device 20 (for example, a mismatch in the number of signal lines and / or a mismatch in operation speed). In this case, the first device 10 converts the imaging data from the imaging device 40 into data that can be input to the second device 20, and transmits this to the second device 20.

  In the illustration of FIG. 1, the first device 10 includes a circuit 11, a signal line group (hereinafter referred to as a CPU bus) 13, a processing unit 14, a storage unit 15, a conversion unit 16, and a clock generation unit 18. The processing unit 14 is, for example, a central processing unit (CPU). The processing unit 14 receives a predetermined bus clock BC1 from the clock generation unit 18. The processing unit 14 is connected to the CPU bus 13 and transmits and receives signals to and from the CPU bus 13 using the bus clock BC1. For example, the processing unit 14 controls the entire first device 10.

  The storage unit 15 is, for example, a memory (for example, SRAM (Static-Random-Access-Memory)) and is connected to the CPU bus 13. The storage unit 15 stores a program executed by the processing unit 14, for example, and provides a work area for executing the program, for example.

  The circuit 11 receives imaging data from the imaging device 40. The circuit 11 is connected to the CPU bus 13 and is controlled by, for example, the processing unit 14. The circuit 11 performs processing on the imaging data and converts it into data suitable for the second device 20, for example. Since the contents of this process are different from the essence of the present invention, a detailed description is omitted.

  The conversion unit 16 is connected to the CPU bus 13 and the transmission path 30. The conversion unit 16 transmits data from the CPU bus 13 to the transmission path 30 and transmits data from the transmission path 30 to the CPU bus 13. At that time, the conversion unit 16 transmits and receives data in parallel via N (N is a plurality of two or more) signal lines of the CPU bus 13. The conversion unit 16 transmits and receives data in parallel via M signal lines (M is a natural number, for example, smaller than N) on the transmission line 30. However, when M is 1, the conversion unit 16 transmits / receives data to / from the transmission line 30 serially.

  In other words, the conversion unit 16 performs conversion between the N-bit parallel data on the CPU bus 13 side and the M-bit parallel data on the transmission line 30 side (1 bit serial when M is 1; the same applies hereinafter). Run. Details will be described below.

  The converter 16 receives the bus clock BC1 from the clock generator 18 (see also FIG. 2). 2, illustration of the circuit 11, the processing unit 14, the storage unit 15, the clock generation unit 18, and a part of the second device 20 (described later) is omitted for simplification of the drawing. doing.

  The conversion unit 16 receives transmission data to be transmitted from the processing unit 14 to the second device 20 via N signal lines of the CPU bus 13 in N-bit parallel. At this stage, the transmission data is synchronized with the bus clock BC1.

  For example, the conversion unit 16 receives the generation clock PC1 from the clock generation unit 18. The conversion unit 16 generates the transmission clock TC1 based on the generation clock PC1. The transmission clock TC <b> 1 is a clock used when the conversion unit 16 transmits transmission data to the transmission path 30.

  The conversion unit 16 converts the N-bit parallel transmission data into the M-bit parallel transmission data TD1 using the bus clock BC1 and the transmission clock TC1. The transmission data TD1 is synchronized with the transmission clock TC1. Since such conversion itself is a known technique, detailed description thereof is omitted. The conversion unit 16 transmits the transmission data TD1 to the M signal lines of the transmission line 30 and transmits the transmission clock TC1 to the other signal line of the transmission line 30. FIG. 2 shows a transmission path 30 when the transmission data TD1 is transmitted in 1-bit serial.

  The conversion unit 16 receives the reception clock RC1 and the reception data RD1 transmitted from the second device 20 via the transmission line 30. More specifically, the conversion unit 16 receives the reception clock RC1 through one signal line of the transmission path 30, and receives the reception data RD1 in M bit parallel through the M signal lines of the transmission path 30. To do. At this stage, the reception data RD1 is synchronized with the reception clock RC1. The conversion unit 16 converts the M-bit parallel reception data RD1 into N-bit parallel reception data using the bus clock BC1 and the reception clock RC1. The converted received data is synchronized with the bus clock BC1. Then, the conversion unit 16 transmits the N-bit parallel received data to the processing unit 14 via the N signal lines of the CPU bus 13.

  For example, the second device 20 includes a circuit 21, a signal line group (CPU bus) 23, a processing unit 24, a storage unit 25, a conversion unit 26, a reception data relay unit 27, and a clock generation unit 28. The processing unit 24 is, for example, a central processing unit (CPU). The processing unit 24 receives the bus clock BC2 from the clock generation unit 28. The processing unit 24 is connected to the CPU bus 23, and transmits and receives signals to and from the CPU bus 23 using the bus clock BC2. For example, the processing unit 24 controls the entire second device 20.

  The storage unit 25 is, for example, a memory (for example, SRAM (Static-Random-Access-Memory)) and is connected to the CPU bus 23. The storage unit 25 stores, for example, a program executed by the processing unit 24, and provides a work area for executing the program.

  The circuit 21 receives image data from the first device 10 via the image transmission path 31. The circuit 21 is connected to the CPU bus 23, for example, and is controlled by the processing unit 24, for example. The circuit 21 appropriately performs image processing on the image data and transmits it to a device (not shown). Since the contents of this image processing are different from the essence of the present invention, detailed description thereof is omitted.

  The conversion unit 26 is connected to the CPU bus 23 and the transmission path 30. The conversion unit 26 has a function similar to that of the conversion unit 16, transmits data from the CPU bus 23 to the transmission path 30, and transmits data from the transmission path 30 to the CPU bus 23. At that time, the conversion unit 26 transmits / receives data in parallel with n (n is a plurality of 2 or more) signal lines of the CPU bus 23, and in parallel with M (natural number smaller than n) signal lines of the transmission path 30. Send and receive data with. When M is 1, the conversion unit 26 transmits / receives data to / from the transmission line 30 serially.

  In other words, the conversion unit 26 performs conversion between the n-bit parallel data on the CPU bus 23 side and the M-bit parallel data on the transmission line 30 side (1 bit serial when M is 1; the same applies hereinafter). Run. Details will be described below.

  The converter 26 receives the bus clock BC2 from the clock generator 28 (see also FIG. 2). In FIG. 2, the circuit 21, the processing unit 24, the storage unit 25, and the clock generation unit 28 of the second device 20 are omitted for simplification of the drawing.

  The conversion unit 26 receives transmission data to be transmitted from the processing unit 24 to the first device 10 through n signal lines of the CPU bus 23 in n-bit parallel. At this stage, the transmission data is synchronized with the bus clock BC2.

  Further, the conversion unit 26 receives the generation clock PC2 from the clock generation unit 28, for example. The conversion unit 26 generates a transmission clock TC2 based on the generation clock PC2. The transmission clock TC <b> 2 is a clock used when the conversion unit 26 transmits transmission data to the transmission path 30.

  The converter 26 uses the bus clock BC2 and the transmission clock TC2 to convert the n-bit parallel transmission data into the M-bit parallel transmission data TD2. The transmission data TD2 is synchronized with the transmission clock TC2. The conversion unit 26 transmits the transmission data TD2 to the M signal lines of the transmission path 30, and transmits the transmission clock TC2 to the other signal line of the transmission path 30.

  The transmission clock TC2 and the transmission data TD2 are received by the conversion unit 26 as the reception clock RC1 and the reception data RD1.

  The conversion unit 26 receives the transmission clock TC1 and the transmission data TD1 transmitted from the first device 10 via the transmission path 30 and the reception data relay unit 27.

  The reception data relay unit 27 receives the transmission clock TC1 and the transmission data TD1 via the transmission path 30. Then, the reception data relay unit 27 determines whether or not the transmission clock TC1 is stopped. If a negative determination is made, the reception data relay unit 27 transmits the transmission clock TC1 as the reception clock RC2 to the conversion unit 26 and transmits the transmission data TD1 as reception data RD2 to the conversion unit 26. Therefore, when the transmission clock TC1 is operating normally, the conversion unit 26 can receive the transmission clock TC1 and the transmission data TD1 transmitted from the first device 10 as the reception clock RC2 and the reception data RD2, respectively. .

  On the other hand, if a positive determination is made, the reception data relay unit 27 transmits a predetermined alternative clock (for example, the bus clock BC2) as the reception clock RC2 to the conversion unit 26, and synchronizes with the alternative clock as the reception data RD2. The abnormal information to be transmitted is transmitted to the conversion unit 26. Therefore, when transmission clock TC1 is stopped, conversion unit 26 receives the alternative clock and the abnormality information as reception clock RC2 and reception data RD2, respectively.

  The converter 26 receives the reception clock RC2 through one signal line and receives the reception data RD2 in M-bit parallel through the M signal lines. The reception data RD2 is synchronized with the reception clock RC2. The conversion unit 26 converts the M-bit parallel reception data RD2 into n-bit parallel reception data using the bus clock BC2 and the reception clock RC2. The converted received data is synchronized with the bus clock BC2. Then, the conversion unit 26 transmits the n-bit parallel received data to the processing unit 24 via the n signal lines of the CPU bus 23.

  According to such a system, when the transmission clock TC1 is not stopped, the processing unit 24 can appropriately receive the transmission data TD1 as the reception data RD2 via the conversion unit 26 and the CPU bus 23. An example of such data is 8-bit communication availability information indicating whether the first device 10 is communicable.

  On the other hand, when the transmission clock TC1 is stopped, the alternative clock is input to the conversion unit 26 as the reception clock RC2, and abnormality information is input as the reception data RD2. Therefore, although the transmission clock TC <b> 1 is stopped, the conversion unit 26 can continue the operation and can appropriately transmit the abnormality information to the processing unit 24. Therefore, the processing unit 24 can recognize that the first device 10 is in a state where communication is not possible.

  Moreover, according to this system, when the reception data relay unit 27 detects the stop of the transmission clock TC1, the abnormality information is notified to the processing unit 24 by using the function of the conversion unit 26. Therefore, it is not necessary to increase the number of signal lines of the CPU bus 23 as compared with the case where the CPU bus 23 and the reception data relay unit 27 are separately connected, and the circuit scale can be suppressed.

  The first device 10 and the second device 20 may continuously transmit the transmission clocks TC1 and TC2, or may be transmitted at predetermined intervals. The reception data relay unit 27 may determine that the transmission clock has stopped when the transmission clock remains active or inactive beyond the period considering the predetermined interval.

  As described above, for example, the bus clock BC2 can be adopted as the alternative clock. Therefore, in the example of FIG. 2, the reception data relay unit 27 inputs the bus clock BC2 from the clock generation unit 28, and outputs the bus clock BC2 as an alternative clock. However, it is not necessarily limited to this. For example, a clock generated separately from the bus clock BC2 (for example, the generation clock PC2) may be used as an alternative clock. If the bus clock BC2 or the generation clock PC2 is employed, it is not necessary to generate an alternative clock, so that the circuit scale and manufacturing cost can be suppressed. Alternatively, the alternative clock may be generated based on the bus clock BC2 or the generation clock PC2.

  Further, as the abnormality information, information that is communication enable / disable information of the transmission data TD1 and that indicates that communication is impossible may be employed. This makes it possible to recognize that the first device 10 cannot communicate without increasing the types of information that the processing unit 24 should recognize.

  Moreover, the 1st apparatus 10 and the 2nd apparatus 20 are not restricted to the aspect shown in FIG. In short, the first device 10 only has to transmit the transmission clock TC1 and transmission data TD1 synchronized with the transmission clock TC1 to the transmission line 30, and the second device 20 receives the CPU bus 23, the processing unit 24, the conversion unit 26, and the reception. What is necessary is just to provide the data relay part 27 and the clock generation part 28. FIG. This is because the conversion unit 26 can transmit the abnormality of the first device 10 to the processing unit 24 when the reception data relay unit 27 determines that the transmission clock TC1 is stopped.

<Received data relay unit 27>
An example of the internal configuration of the reception data relay unit 27 is not limited to the aspect of FIG. In the example of FIG. 2, for example, the reception data relay unit 27 includes a clock reception data relay unit 271, a selection unit 272, and logic circuits 273 to 275. In the following, the activation / inactivation of the signal is represented by “1” and “0”, respectively. For example, the activation / inactivation of each clock is represented by “1” and “0”.

  The clock reception data relay unit 271 determines whether or not the transmission clock TC1 is stopped. For example, when the period in which the transmission clock TC1 takes “0” is longer than a predetermined reference period, the clock reception data relay unit 271 makes a positive determination. The period can be measured using, for example, a known timer circuit, and the comparison between the period and the reference period can be performed using, for example, a known comparator. The clock reception data relay unit 271 outputs “1” when a positive determination is made, and outputs “0” when a negative determination is made.

  The logic circuit 273 receives the output from the clock reception data relay unit 271 and the transmission clock TC1. The logic circuit 273 is an AND circuit, and outputs “1” when the clock reception data relay unit 271 outputs “0” and the transmission clock TC1 takes “1”. In other cases, the logic circuit 273 outputs “0”. Therefore, the logic circuit 273 outputs the transmission clock TC1 when it is determined that the transmission clock TC1 is not stopped, and outputs “0” when it is determined that the transmission clock TC1 is stopped.

  The selection unit 272 receives an alternative clock (for example, the bus clock BC2) and the output of the clock reception data relay unit 271. The selection unit 272 outputs “0” when the output of the clock reception data relay unit 271 is “0”. On the other hand, when the output of the clock reception data relay unit 271 is “1”, an alternative clock is output.

  The selection unit 272 includes flip-flops 2721 and 2722, a latch circuit 2723, and a logic circuit 2724 as shown in FIG. The flip-flops 2721 and 2722 are, for example, D-type flip-flops. The output of the clock reception data relay unit 271 and the alternative clock are input to the flip-flop 2721. The output of the flip-flop 2721 and the alternative clock are input to the flip-flop 2722. The output of the flip-flop 2722 and the alternative clock are input to the latch circuit 2723. The latch circuit 2723 is, for example, a D-type latch circuit. A latch circuit 2723 and an alternative clock are input to the logic circuit 2724. The logic circuit 2724 is an AND circuit. The output of the logic circuit 2724 becomes the output of the selection unit 272.

  According to the selection unit 272 of FIG. 3, since the output of the clock reception data relay unit 271 is appropriately latched, the influence of instantaneous noise fluctuation and the like can be suppressed.

  The logic circuit 275 receives the output of the selection unit 272 and the output of the logic circuit 273, and outputs a later-described logic value to the conversion unit 26 as a reception clock RC2. The logic circuit 275 is an OR circuit, and outputs “1” when the output of the selection unit 272 or the output of the logic circuit 273 is “1”, and the output of the selection unit 272 and the output of the logic circuit 273 are “0”. "0" is output when "." When the output of the clock reception data relay unit 271 is “0”, the selection unit 272 outputs “0”, and the logic circuit 273 outputs the transmission clock TC1. Therefore, at this time, the logic circuit 275 outputs the transmission clock TC1 to the conversion unit 26 as the reception clock RC2. On the other hand, when the output of the clock reception data relay unit 271 is “1”, the selection unit 272 outputs an alternative clock (for example, the bus clock BC2), and the logic circuit 273 outputs “0”. Therefore, at this time, the logic circuit 275 outputs the alternative clock to the conversion unit 26 as the reception clock RC2.

  The logic circuit 274 receives the output of the clock reception data relay unit 271 and the transmission data TD1, and outputs a logic value described later to the conversion unit 26 as reception data RD2. The logic circuit 274 is an (M + 1) -bit AND circuit, and outputs the same content as the M-bit transmission data TD1 when the clock reception data relay unit 271 outputs “0”. In other cases, the logic circuit 274 outputs M-bit “0”. Therefore, when it is determined that the transmission clock TC1 is not stopped, the logic circuit 274 outputs the transmission data TD1 to the conversion unit 26 as the reception data RD2. When it is determined that the transmission clock TC1 is stopped, “0” is output as the reception data RD2. This received data D2 corresponds to abnormality information.

  As described above, this abnormality information may be equal to information indicating that communication is not possible in the communication availability information.

<Clock Reception Data Relay Unit 271>
An example of the internal configuration of the clock reception data relay unit 271 is not limited to the aspect of FIG. The clock reception data relay unit 271 includes a frequency division unit 2711 and a determination unit 2712.

  The frequency divider 2711 divides the transmission clock TC1 by the frequency division ratio DIV to generate a determination clock C2, and outputs this to the determination unit 2712. The frequency division ratio DIV is set in advance, for example.

  The determination clock 27 is input to the determination unit 2712. The determination unit 2712 repeatedly samples the determination clock C2 at a predetermined sampling frequency f1 (see also FIG. 5). In FIG. 5, the determination clock C2 is shown, and the sampling timing is shown by a black circle. This sampling frequency f1 is higher than twice the frequency f2 of the determination clock C2. As a result, the sampling period (1 / f1) is shorter than the half period (1 / (2 · f2)) of the determination clock C2. Accordingly, at least one sampling can be performed in a half cycle of the determination clock C2.

  The determination unit 2712 counts the number of times F that the same sampling value is continuously taken. In the illustration of FIG. 5, the number of times F is 2 or 3. Then, the determination unit 2712 determines whether or not the number of times F is larger than the number of times reference value DETCT (for example, 3), and determines that the transmission clock TC1 has stopped when a positive determination is made.

  Here, a method of determining the number reference value DETCT will be described. First, consider the number of times F when the determination clock C2 is operating normally. As illustrated in FIG. 5, the number of times F is not necessarily constant. In the example of FIG. 5, the frequency F is 2 or 3. Therefore, in this case, a value of 3 or more may be adopted as the number reference value DETCT. Thereby, it is possible to appropriately determine whether the transmission clock TC1 is stopped.

  Next, the number of times F when the determination clock C2 operates normally is generalized. The number of times F can be understood based on the ratio (= f1 / (2 · f2)) between the sampling period (1 / f1) and the half period (1 / (2 · f2)) of the determination clock PC2. For example, when the ratio is a natural number, as shown in FIG. 6, the number of times F always matches the natural number (2 in the example of FIG. 6). When sampling is performed at the timing at which the determination clock PC2 transitions, for example, “1” may always be employed as the sampling value, or “0” may be always employed. On the other hand, in the example shown in FIG. 5, the ratio is about 2.2. In this case, the frequency F is 2 or 3. That is, when the ratio is a decimal having an integer part X and a decimal part Y (0 <Y <1), the number of times F is the integer part X and an integer (X + 1) obtained by adding 1 to the integer part X. Take either one.

  The rotation reference value DETCT may be equal to or greater than the maximum value of the number of times F when the determination clock C2 operates normally ((X + 1) in the example of FIG. 5). In other words, the count reference value DETCT may be an integer greater than or equal to a value obtained by dividing the sampling frequency f1 by twice the frequency f2.

  The number reference value DETCT can be determined as described above.

  The sampling frequency f1 is defined by the sampling clock. The sampling clock may be, for example, the bus clock BC2 or the generation clock PC2. Thus, it is not necessary to generate a new clock for sampling, and the circuit scale and manufacturing cost can be reduced.

  For example, the frequency ft of the transmission clock TC1 and the frequency fp of the generation clock PC2 may be individually changed based on the signal processing mode. For example, in the first mode, the frequency ft is set to its maximum value ftmax, the frequency fp is set to its minimum value fpmin, or in the second mode, the frequency ft is set to its minimum value ftmin, and the frequency fp is set to its maximum value fpmax Set to.

  As described above, when the frequencies ft and fp are individually changed between the minimum value and the maximum value, it is desirable to set the frequency division ratio DIV so as to satisfy the following expression.

  DIV> 2 ftmax / fpmin (1)

  Equation (1) can be modified as follows.

  1 / fpmin <1 / (2 · ftmax / DIV) (2)

  The left side of Expression (2) corresponds to the maximum value of the sampling period, and the right side of Expression (2) corresponds to the minimum value of the half period of the determination clock C2. Therefore, according to Expression (2), even when the sampling period is the maximum and becomes the minimum value of the half period of the determination clock C2, the sampling period can be made smaller than the half period of the determination clock C2. Therefore, by setting the frequency division ratio DIV so as to satisfy Expression (1), even if the frequency ft of the transmission clock TC1 and the frequency fp of the generation clock PC2 fluctuate, at least in the half cycle of the determination clock C2 One sampling can be performed.

  The number reference value DETCT is preferably an integer that satisfies the following equation.

  DETCT ≧ fpmax · DIV / (2 × ftmin) (3)

  The right side of Equation (3) is the ratio between the minimum value of the sampling period (1 / fpmax) and the maximum value of the period of the determination clock C2 (1 / (2 · ftmin / DIV)). The number of times F takes the maximum value when the sampling period is minimum and the period of the determination clock C2 is maximum. Therefore, the ratio on the right side of Equation (3) represents the maximum number of times F.

  According to Equation (3), the number reference value DETCT is larger than the maximum value of the number F. Therefore, even if the frequency ft of the transmission clock TC1 and the frequency fp of the generation clock PC2 fluctuate, it is possible to appropriately determine whether the operation of the determination clock C2 is stopped.

10, 20 Device 23 CPU bus 24 Processing unit 26 Conversion unit 27 Received data relay unit 28 Clock generation unit 30 Transmission path

Claims (4)

A communication system between processing devices comprising a first device, a second device, and a transmission line connecting the first device and the second device,
The first device transmits transmission data synchronized with a predetermined transmission clock to the second device via the transmission path in M (M is a natural number of 2 or more) bit parallel or 1 bit serial, and the transmission. Transmitting the transmission clock to the second device via a path;
The second device includes:
A group of signal lines in which data synchronized with a predetermined bus clock is transmitted in n (n is a natural number of 2 or more) bit parallel;
A processing unit that transmits and receives data to and from the signal line group;
The transmission clock and the transmission data are received from the transmission path, and it is determined whether or not the transmission clock has stopped. When a negative determination is made, the transmission clock and the transmission data are received as reception clock and reception data. A reception data relay unit that transmits a predetermined alternative clock as the reception clock and abnormal information that is synchronized with the alternative clock as the reception data, respectively,
The reception data is received from the reception data relay unit in M-bit parallel or 1-bit serial, the reception clock is received from the reception data relay unit, and the reception data is received using the predetermined bus clock and the reception clock. a conversion unit that converts the received data into n-bit parallel received data and transmits the received data after conversion to the processing unit via the signal line group ;
A clock generation unit for generating the bus clock and the generation clock ,
The reception data relay unit samples a determination clock that is equal to the transmission clock or is generated based on the transmission clock and repeatedly takes active / inactive at a sampling frequency higher than twice the frequency of the determination clock, It is determined that the transmission clock has stopped when the number of times that the sampling value continuously takes the same value is larger than a reference value that is an integer equal to or greater than a value obtained by dividing the sampling frequency by twice the frequency of the determination clock. And
The conversion unit generates a second transmission clock using the generation clock, receives second transmission data synchronized with the bus clock in n-bit parallel from the signal line group, and transmits the bus clock and the second transmission. The second transmission data is converted into M-bit parallel or 1-bit serial third transmission data using a clock, and the third transmission data and the second transmission clock are converted to the first transmission data via the transmission path. To one device,
The sampling frequency is defined based on the generation clock or the bus clock,
The sampling frequency is equal to the frequency of the generating clock;
The frequency of the transmission clock takes a value between the maximum value ftmax and the minimum value ftmin, the frequency of the generation clock takes a value between the maximum value fpmax and the minimum value fpmin,
The determination clock is generated by dividing the transmission clock by a predetermined division ratio DIV,
The division ratio DIV is
DIV> 2ftmax / fpmin
The filling,
The reference number of times DETCT is
DETCT> fpmax · DIV / (2 × ftmin)
The communication system between processing apparatuses satisfying the requirements . The inter-processor communication system according to claim 1, wherein the alternative clock is the bus clock or generated based on the bus clock . The alternative clock is generated based on some or the generated clock by the generating clock, processor communication system according to claim 1 or 2. The first device transmits communication enable / disable information indicating whether or not the first device can communicate to the second device as transmission information,
The communication system between processing apparatuses according to any one of claims 1 to 3 , wherein the abnormality information is equal to information indicating that communication is impossible in the communication availability information .

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