JP6009844B2 - Relay board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a relay board on which a semiconductor element mounting region for mounting a semiconductor element is set, and a method for manufacturing the same.

  In recent years, instead of directly connecting a wiring board (IC mounting board, IC package, etc.) on which an IC chip is mounted and a printed board such as a mother board, a relay board called an interposer is provided between the wiring board and the mother board. Various structures are known in which they are connected to each other. As the material for such an interposer, an inorganic material such as ceramic is used. Recently, an interposer for connecting at a level different from the above-described interposer, specifically, an interposer for connecting the IC chip and the wiring board has been proposed. In the present specification, for convenience, the former will be referred to as “motherboard side interposer” and the latter will be referred to as “IC chip side interposer”. As an example of the IC chip-side interposer, a structure in which a core substrate is formed of a polymer material and build-up layers are formed on the front surface and the back surface of the core substrate is conceivable (see, for example, Patent Document 1).

JP 2010-93088 A (FIG. 3 etc.)

  However, the conventional technique described in Patent Document 1 has the following problems. That is, the core substrate described in Patent Document 1 has a notch for filling a crack preventing resin at the outer edge. However, the core substrate is formed of a material that easily generates cracks, such as glass or ceramic. Therefore, even if it is going to form a notch, it is difficult because the core substrate is likely to break. As a result, there is a problem that the predetermined reliability required for the relay board cannot be given.

  The present invention has been made in view of the above problems, and a first object of the invention is to provide a relay board capable of imparting high reliability by preventing damage to the relay board body. . A second object is to provide a method for manufacturing a relay board capable of realizing the above-described excellent relay board.

As means (means 1) for solving the above-mentioned problem, a substantially plate-shaped relay substrate having a substrate main surface, a substrate back surface, and a substrate side surface and made of an insulating material or a material subjected to an insulation treatment on the surface is used. A semiconductor element mounting region comprising a main body and a plurality of conductor pillars penetrating between the substrate main surface and the substrate back surface, wherein a plurality of semiconductor element connection terminals for mounting a semiconductor element exist on the substrate main surface Is formed on the side surface of the substrate, and a covering material that covers at least a part of the side surface of the substrate is formed in close contact with the back surface side of the substrate in addition to the main surface side of the substrate. Protruding portions that protrude and are arranged around the semiconductor element mounting region, and the height of the protruding portion protruding to the back side of the substrate is lower than the height of the protruding portion protruding to the substrate main surface side There is a relay board characterized by .

  Therefore, according to the relay substrate of the means 1, at least a part of the substrate side surface of the relay substrate body is covered with the covering material, so that it is difficult for large stress to act directly on the relay substrate body. Therefore, even if the relay substrate body is formed of a material having low strength, cracks and the like are hardly generated. Therefore, since the breakage of the relay board body is prevented, high reliability can be imparted to the relay board.

  In addition, the covering material includes a convex portion that protrudes toward the main surface of the substrate and is disposed around the semiconductor element mounting region. For this reason, even when a part of the underfill material that seals the gap between the relay substrate body and the semiconductor element flows out onto the main surface of the substrate when the semiconductor element is mounted, the flow of the underfill material is Stop by touching the protrusions located around the area. As a result, since the underfill material is prevented from protruding to the outer region of the convex portion, it is possible to prevent problems caused by the underfill material adhering to the substrate on which the relay substrate is mounted. Examples of the semiconductor element include a semiconductor integrated circuit chip (IC chip) made of silicon.

The relay board includes a substantially plate-shaped relay board body made of an insulating material or a material whose surface is insulated. The material for forming the relay substrate body is not particularly limited, and can be appropriately selected in consideration of cost, workability, insulation, mechanical strength, and the like. Therefore, examples of the relay board body include a relay board body made of ceramic, a relay board body made of resin, a relay board body made of metal, a relay board body made of glass, and a relay board body made of silicon. As a material for forming the relay substrate body made of ceramic, alumina, aluminum nitride, silicon nitride, boron nitride, beryllia, mullite, low-temperature fired glass ceramic, glass ceramic and the like are preferably used. Moreover, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), PPE resin (polyphenylene ether resin), etc. are suitably used as the material for forming the relay substrate body made of resin. Is done. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used. Alternatively, a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used. Furthermore, suitable examples of the relay substrate body made of metal include, for example, a substrate made of copper, a substrate made of a copper alloy, a substrate made of a single metal other than copper, and a substrate made of an alloy other than copper. In addition, when the relay substrate body is made of silicon which is a semiconductor, it is preferable that the surface is subjected to an insulation process (for example, formation of a SiO ₂ film). Furthermore, when the relay substrate body is a core substrate, a build-up layer as shown in Patent Document 1 may be formed.

  The thickness of the relay substrate main body is not particularly limited, but is preferably 50 μm or more and 500 μm or less. If the thickness is less than 50 μm, there is a possibility that the effect due to the interposition of the relay substrate body, that is, the stress reduction effect cannot be obtained sufficiently. On the other hand, if the thickness exceeds 500 μm, not only the thickness of the entire structure composed of the substrate on which the relay substrate is mounted, the relay substrate and the semiconductor element is increased, but also the formation of small-diameter conductor pillars becomes difficult and the manufacturing cost is reduced. May be expensive.

  The relay substrate has a plurality of conductor pillars penetrating between the substrate main surface and the substrate back surface. A plurality of semiconductor element connection terminals are arranged on the main surface of the relay substrate. The conductor pillar and the semiconductor element connection terminal are, for example, one or more selected from gold, silver, copper, platinum, palladium, nickel, tin, lead, titanium, tungsten, molybdenum, tantalum, niobium, and the like. The conductive metal is filled or printed. Examples of the conductive metal composed of two or more metals include solder that is an alloy of tin and lead. Lead-free solder (for example, Sn-Ag solder, Sn-Ag-Cu solder, Sn-Ag-Bi solder, Sn-Ag-Bi-Cu solder) as a conductive metal composed of two or more metals Of course, Sn—Zn solder, Sn—Zn—Bi solder, etc.) may be used. As a specific method for filling the conductive metal, for example, a non-solid material containing a conductive metal (for example, a conductive metal paste) is produced and placed in a plurality of through holes formed in the relay substrate body. In addition to printing and filling methods, there are methods such as conducting metal plating. Moreover, you may employ | adopt the method of embedding solid material, specifically, a metal lump, a metal pillar, etc. in a through-hole. In addition, when forming a conductor pillar by filling with a conductive metal, it is preferable to fill the through hole almost completely so as not to form a cavity inside. The reason is to reduce the resistance of the conductor column and increase the strength of the conductor column itself. However, the conductor column does not necessarily have a solid structure in which the entire through hole is filled with a conductor, but has a hollow structure in which a conductor is provided only on the inner wall surface of the through hole (for example, a structure like a plated through hole). May be.

  Further, a covering material is formed in close contact with the side surface of the relay substrate body. The covering material can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. When the coating material is formed of, for example, a polymer material, examples of the polymer material for forming the coating material include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. UV curable resin such as epoxy acrylate resin, thermoplastic resin such as polycarbonate resin, acrylic resin, polyacetal resin, and polypropylene resin. In addition, mixed materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamides, or heat such as epoxy resins on a three-dimensional network fluorine-based resin substrate such as continuous porous PTFE. A resin-resin composite material impregnated with a curable resin may be used.

  Here, the thickness of the covering material is preferably 2 μm or more and 50 μm or less, for example. If the thickness of the covering material is less than 2 μm, the covering material becomes too thin, and the stress directly applied to the relay substrate may not be sufficiently relaxed. On the other hand, if the thickness of the covering material is larger than 50 μm, a large amount of material for forming the covering material is required, which may increase the manufacturing cost of the relay substrate.

  The covering material covers at least a part of the side surface of the substrate. Here, when the relay substrate main body has, for example, a substantially rectangular shape in plan view, that is, when there are four substrate side surfaces, the covering material may cover only one substrate side surface, or two or more substrates. The side may be covered. Further, the covering material may be in close contact with only the side surface of the substrate, but in addition, a part of the covering material may be in close contact with the outer edge portion of the main surface of the substrate. Furthermore, a part of the covering material may be in close contact with both the outer edge portion of the substrate main surface and the outer edge portion of the substrate back surface. If the surface to which the coating material adheres is only the side surface of the substrate, if a part of the underfill material that seals the gap between the relay substrate body and the semiconductor element flows out onto the main surface of the substrate, the outflowed underfill There is a possibility that the material protrudes to the outer region of the main surface of the substrate.

  Further, the covering material includes a convex portion that protrudes toward the substrate main surface side and is disposed around the semiconductor element mounting region. Here, as a method of arranging the convex portion around the semiconductor element mounting region, an annular convex portion that completely surrounds the semiconductor element mounting region or a plurality of convex portions that surround the semiconductor element mounting region can be used. For example, the parts may be arranged in a scattered manner. In addition, it is preferable that the height of a convex part is higher than the height of the several semiconductor element connection terminal, for example, it is preferable that they are 10 micrometers or more and 500 micrometers or less. If the height of the convex portion is less than 10 μm, when the part of the underfill material that seals the gap between the relay substrate body and the semiconductor element flows out onto the main surface of the substrate, the outflowed underfill material is convex. There is a risk of overcoming the portion and protruding to the outside region of the main surface of the substrate. On the other hand, when the height of the convex portion is larger than 500 μm, the stress applied to the relay substrate body when the resin is cured and becomes a coating material increases, and the relay substrate body may be warped.

Incidentally, projections, it is also projected to the back side of the substrate in addition to the substrate main surface. The height of the convex portion protruding substrate rear side is lower Kuna' than the height of the protrusion protruding to the substrate main surface. If the height of the convex portion protruding to the back side of the substrate is higher than the height of the convex portion protruding to the main surface side of the substrate, the convex portion protruding to the back side of the substrate comes into contact with the substrate on which the relay substrate is mounted and relays. There is a possibility that the mounting of the substrate on the substrate may be hindered.

As another means (means 2) for solving the above-mentioned problem, a substantially plate-like shape made of an insulating material or a material having an insulating treatment applied to the surface has a substrate main surface, a substrate back surface, and a substrate side surface. A semiconductor element comprising a relay substrate body and a plurality of conductor pillars penetrating between the substrate main surface and the substrate back surface, wherein a plurality of semiconductor element connection terminals for mounting a semiconductor element exist on the substrate main surface In the method for manufacturing a relay board in which a mounting area is set, a relay board body preparing step for preparing the relay board body, a conductor pillar forming step for forming the plurality of conductor pillars on the relay board body, and the board main surface includes a convex portion which is arranged around the semiconductor element mounting region with protruding side, viewed contains a coating material forming step of contact forming at least a portion of the cover coating material of the substrate side, the covering material forming step The feeling A resin film affixing step for affixing a resin film having a property on the main surface of the substrate; and by heating and pressurizing the resin film to melt and flow part of the resin film, A laminating step of attaching a portion to the side surface of the substrate, and an exposing step of removing the resin film attached to a region excluding the outer peripheral portion of the main surface of the substrate by exposing the resin film. And developing the exposed resin film so that the resin film becomes the coating material and the resin film affixed to the outer peripheral portion of the main surface of the substrate is the convex portion. There is a method of manufacturing a relay board characterized by this.

  Therefore, according to the method of manufacturing the relay substrate of the means 2, the covering material forming step is performed to cover at least part of the substrate side surface of the relay substrate body with the covering material, so that a large stress is not easily applied directly to the relay substrate body. . Therefore, even if the relay substrate body is formed of a material having low strength, cracks and the like are not easily generated. Therefore, since the breakage of the relay board main body is prevented, a relay board having high reliability can be obtained.

  In addition, in the covering material forming step, a covering material that protrudes toward the main surface of the substrate and includes a convex portion that is disposed around the semiconductor element mounting region is formed. For this reason, even when a part of the underfill material that seals the gap between the relay substrate body and the semiconductor element flows out onto the main surface of the substrate when the semiconductor element is mounted, the flow of the underfill material is Stop by touching the protrusions located around the area. As a result, since the underfill material is prevented from protruding to the outer region of the convex portion, it is possible to prevent problems caused by the underfill material adhering to the substrate on which the relay substrate is mounted.

  Hereinafter, a method for manufacturing the relay board will be described.

  In the relay substrate main body preparation step, the relay substrate main body is prepared by a conventionally known technique and prepared in advance. In the subsequent conductor pillar forming step, a plurality of conductor pillars are formed on the relay substrate body. In addition, in the relay substrate body preparation step, a plurality of substrates are prepared in which a plurality of substrate formation regions to be the relay substrate body are arranged along the plane direction, after the conductor pillar formation step and before the coating material formation step, It is preferable to perform a dividing step of obtaining a plurality of relay substrate bodies by cutting the multi-piece substrate along the outline of the substrate formation region. In this way, since a plurality of relay board bodies can be obtained simultaneously, the relay board can be manufactured efficiently.

  In the subsequent covering material forming step, a covering material that protrudes toward the main surface of the substrate and is provided around the semiconductor element mounting region and covers at least a part of the side surface of the substrate is formed in close contact. As a result, the relay board is completed.

  Here, as the covering material forming step, for example, a resin coating step of applying a liquid curable resin to the side surface of the substrate, and a relay substrate main body is arranged so that the substrate main surface faces downward, thereby Including a curing process in which the sag droops downward from the main surface of the substrate due to its own weight, and then the curable resin is cured to make the curable resin a coating material and the liquid sag to be a convex part. Is mentioned. In such a case, since the convex portion can be formed only by curing the dripping generated by the weight of the curable resin, the convex portion can be easily formed. When the curable resin is a thermosetting resin, the curing step includes heating the curable resin in an uncured state. When the curable resin is an ultraviolet curable resin, the curing step includes irradiating the uncured curable resin with ultraviolet rays.

The covering material forming step includes a resin film sticking step of sticking a photosensitive resin film on the main surface of the substrate, and by melting and flowing a part of the resin film by heating and pressurizing, A laminating process in which a part of the resin film that has flowed is attached to the side surface of the substrate, and an exposure that removes the resin film that is attached to the substrate main surface except for the outer peripheral portion of the substrate main surface by exposing the resin film. a step, by developing the exposed resin film, as well as the resin film and the covering material, and Nde including a development step of the resin film is adhered to the outer peripheral portion of the substrate main surface and the convex portion. In this case, since a convex part can be formed only by exposing and developing a resin film, formation of a convex part becomes easy.

1 is a schematic sectional view showing a semiconductor package of a first embodiment embodying the present invention. Similarly, the schematic sectional drawing which shows an interposer. Similarly, the schematic plan view which shows an interposer. Explanatory drawing which similarly shows the manufacturing method of an interposer. Explanatory drawing which similarly shows the manufacturing method of an interposer. Explanatory drawing which similarly shows the manufacturing method of an interposer. Explanatory drawing which similarly shows the manufacturing method of an interposer. The schematic sectional drawing which shows the interposer of 2nd Embodiment. Explanatory drawing which similarly shows the manufacturing method of an interposer. Explanatory drawing which similarly shows the manufacturing method of an interposer. FIG. 3 is a schematic cross-sectional view showing an interposer of Comparative Example 1. FIG. 6 is a schematic cross-sectional view showing an interposer of Comparative Example 2. The schematic sectional drawing which shows the interposer of other embodiment. The schematic sectional drawing which shows the interposer of other embodiment. The principal part sectional view showing the interposer of other embodiments. The principal part sectional view showing the interposer of other embodiments.

[First Embodiment]
Hereinafter, a first embodiment embodying the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, a semiconductor package 11 (structure) of this embodiment includes an LGA (land grid array) including an IC chip 21 (semiconductor element), an interposer 31 (relay substrate), and a wiring substrate 41. It is. Note that the form of the semiconductor package 11 is not limited to LGA alone, and may be, for example, BGA (ball grid array), PGA (pin grid array), or the like. The IC chip 21 having a function as an MPU has a rectangular flat plate shape of 11.0 mm long × 11.0 mm wide × 0.4 mm thick, and is made of silicon having a thermal expansion coefficient of about 2.6 ppm / ° C. Circuit elements (not shown) are formed on the lower surface layer of the IC chip 21. A plurality of surface connection terminals 22 are provided in a lattice shape on the lower surface side of the IC chip 21, and solder bumps 23 are formed on the surface connection terminals 22.

  The wiring board 41 is a so-called multilayer wiring board made of a rectangular flat plate member having a front surface 42 and a back surface 43 and having a structure in which resin insulating layers 44 and conductor layers 45 are alternately laminated. In the case of this embodiment, specifically, the resin insulating layer 44 is formed of an insulating base material obtained by impregnating a glass cloth with an epoxy resin, and the conductor layer 45 is formed of a copper foil or a copper plating layer. The thermal expansion coefficient of the wiring board 41 is 13.0 ppm / ° C. or more and less than 16.0 ppm / ° C. A plurality of surface connection pads 46 are formed in a lattice pattern on the surface 42 of the wiring substrate 41, and solder bumps 49 are formed on the surface connection pads 46. Each surface connection pad 46 and each solder bump 49 are for electrical connection with the interposer 31 side. On the back surface 43 of the wiring board 41, a plurality of surface connection pads 47 are formed in a lattice shape for electrical connection with a mother board (not shown). The surface connection pads 47 for connecting the motherboard have a wider pitch than the surface connection pads 46 for interposer connection. Via hole conductors 48 are provided in the resin insulating layer 44, and the conductor layers 45 of different layers and the surface connection pads 46, 47 are electrically connected to each other via these via hole conductors 48. In addition to the interposer 31, a semiconductor element and other electronic components (both not shown) are mounted on the surface 42 of the wiring board 41.

  The interposer 31 of this embodiment is to be called an IC chip side interposer, and includes one substrate main surface 32 (upper surface in FIG. 2), one substrate rear surface 33 (lower surface in FIG. 2), and four substrates. A substantially rectangular plate-shaped interposer body 39 (relay substrate body) having a side surface 34 is provided. The interposer body 39 is made of an insulating material (glass in this embodiment). The size of the interposer body 39 is preferably larger than the IC chip 21 to be connected. In the present embodiment, the size is set to 15.0 mm long × 15.0 mm wide. The thickness of the interposer body 39 is set to 50 μm or more and 500 μm or less (300 μm in this embodiment). In the present embodiment, the thermal expansion coefficient of the interposer body 39 is less than 15 ppm / ° C., specifically about 4 to 5 ppm / ° C. The coefficient of thermal expansion of the interposer body 39 is an average value of measured values between 30 ° C. and 400 ° C.

  As shown in FIG. 2, the interposer body 39 is formed with a plurality of through holes 35 penetrating between the substrate main surface 32 and the substrate back surface 33 in a lattice shape. These through holes 35 correspond to the positions of the surface connection pads 46 of the wiring board 41. In the through hole 35, a conductor column 36 made of copper is provided.

  Semiconductor element connection terminals 37 having a height (thickness) of 10 μm are provided at a plurality of locations on the substrate main surface 32. The semiconductor element connection terminal 37 is mainly composed of copper, and is connected to an end portion of each conductor column 36 on the substrate main surface 32 side. Each semiconductor element connection terminal 37 is for mounting the IC chip 21 and is electrically connected to the solder bump 23 on the IC chip 21 side. The area where each semiconductor element connection terminal 37 exists is an IC chip mounting area 24 (semiconductor element mounting area). The IC chip mounting area 24 is set on the board main surface 32 of the wiring board 41. In addition, substrate connection terminals 38 having a height (thickness) of 10 μm are provided at a plurality of locations on the substrate back surface 33. The board connection terminal 38 is mainly composed of copper, and is connected to the end of the conductor pillar 36 on the board back surface 33 side. These board connection terminals 38 protrude from the board back surface 33 and are connected to solder bumps 49 on the wiring board 41 side.

  Therefore, in the semiconductor package 11 having such a structure, the wiring substrate 41 side and the IC chip 21 side are electrically connected via the conductor pillar 36 of the interposer 31. Therefore, signals are input / output between the wiring board 41 and the IC chip 21 via the interposer 31, and power for operating the IC chip 21 as an MPU is supplied.

  As shown in FIGS. 1 to 3, a covering material 61 that covers the entire substrate side surface 34 is formed in close contact with the four substrate side surfaces 34 of the interposer body 39. The covering material 61 is arranged on the substrate main surface 32 so as to surround the IC chip mounting region 24. That is, the covering material 61 when the interposer body 39 is viewed from the thickness direction has a rectangular ring shape. Moreover, the coating | covering material 61 of this embodiment is formed with the polyimide resin which is a thermosetting resin. Specifically, the thermal expansion coefficient of the covering material 61 is set to about 10 to 90 ppm / ° C. (specifically, about 60 ppm / ° C.). Further, the thickness of the covering material 61 covering the substrate side surface 34 gradually increases from the substrate back surface 33 side to the substrate main surface 32 side. And the maximum value t1 of the thickness of the coating | covering material 61 is set to 2 micrometers or more and 50 micrometers or less (20 micrometers in this embodiment).

  Further, a part of the covering material 61 is in close contact with the outer edge portion of the substrate main surface 32. More specifically, the upper end portion of the covering material 61 covers the entire outer edge portion of the substrate main surface 32. The covering material 61 that is in close contact with the substrate main surface 32 and the covering material 61 that is in close contact with the substrate side surface 34 are connected to each other. The covering material 61 includes a convex portion 62 that protrudes toward the substrate main surface 32 and is disposed around the IC chip mounting region 24. On the other hand, the covering material 61 does not protrude toward the substrate rear surface 33 side. As shown in FIG. 2, the height h1 of the convex portion 62 is higher than the height (10 μm) of each semiconductor element connection terminal 37 and each substrate connection terminal 38, specifically, 10 μm. It is set to 500 μm or less (100 μm in this embodiment). And the vertex P1 of the convex part 62 is located on the virtual line L1 extended from the board | substrate side surface 34 and protruded in the board | substrate main surface 32 side.

  As shown in FIG. 1, an underfill material 51 is filled in a gap between the substrate main surface 32 and the IC chip 21. As a result, the interposer 31 and the IC chip 21 are fixed to each other with the gap sealed. The underfill material 51 is filled in an inner region of the covering material 61 that surrounds the IC chip mounting region 24. That is, the covering material 61 has a function as a dam that prevents the underfill material 51 from protruding to the outer region of the covering material 61. In the present embodiment, the size of the gap between the interposer 31 and the IC chip 21 is 80 μm. The underfill material 51 of the present embodiment is made of an epoxy resin having a thermal expansion coefficient of about 20 to 200 ppm / ° C. (specifically, 25 ppm / ° C.).

  Here, a procedure for manufacturing the semiconductor package 11 having the above structure will be described.

  First, an interposer body 39 is prepared by a conventionally known method by performing a relay substrate body preparation step, and prepared in advance. In the relay substrate body preparation step of this embodiment, a multi-piece substrate is prepared in which a plurality of substrate formation regions to be the interposer body 39 are arranged vertically and horizontally along the plane direction.

  The interposer body 39 is manufactured as follows. First, a commercially available thin glass substrate is prepared. Examples of the glass substrate include OA-10G manufactured by Nippon Electric Glass Co., Ltd. and PEG-3C manufactured by HOYA Co., Ltd.

  In the subsequent conductor column forming step, a large number of through holes 35 are formed through the thin glass substrate by a known method such as laser irradiation or sandblasting, and the conductor column 36 is formed by a known method such as copper plating. When the interposer body 39 is formed using a glass ceramic green sheet, after forming the through holes 35, the copper paste for conductor pillars is put into the respective through holes 35 by using a paste press-fitting and filling device (not shown). Fill. Thereafter, the green sheet is dried to solidify the green sheet to some extent. Next, the green sheet is degreased and further fired at a predetermined temperature for a predetermined time. As a result, the interposer body 39 in which the glass ceramic and the copper in the paste are simultaneously sintered to form the plurality of conductor columns 36 may be used.

  Further, after the conductor pillar forming step, before the covering material forming step described later, a connection terminal forming step is performed, and the semiconductor element connecting terminals 37 connected to the end portions of the conductor pillars 36 on the substrate main surface 32 side are provided. In addition to the formation, the board connection terminals 38 connected to the end portions of the respective conductor pillars 36 on the board rear surface 33 side are formed. Specifically, the semiconductor element connection terminal 37 and the substrate connection terminal 38 are formed by a known method such as a subtractive method or a semi-additive method.

  Further, the dividing step is performed after the conductor pillar forming step and before the covering material forming step. Specifically, the multi-piece substrate is cut along the outline of the substrate forming region using a conventionally known cutting device (laser processing machine, dicing device, etc.). As a result, it is possible to simultaneously obtain a plurality of interposer bodies 39 in which a material that easily generates cracks (glass in this embodiment) is exposed on the cut end face.

  In the subsequent covering material forming step, the covering material 61 is formed in close contact with the substrate side surface 34 of the interposer body 39. The coating material forming process includes a resin coating process and a curing process. First, in the resin coating process, a masking tape 71 (see FIG. 4) is attached to the substrate back surface 33 of the interposer body 39. The interposer body 39 is affixed and temporarily fixed to the adhesive surface of the masking tape 71. In the present embodiment, a polyimide tape having excellent heat resistance is used as the masking tape 71. Next, the interposer body 39 is arranged with one of the four substrate side surfaces 34 constituting the interposer body 39 facing downward, and the substrate side surface 34 facing downward is liquid-cured. A functional resin 63 is applied. Specifically, dip coating is performed, and the substrate side surface 34 facing downward is immersed in the curable resin 63 in the container 72 and then pulled up (see FIGS. 4 and 5). As a result, the curable resin 63 adheres to the immersed substrate side surface 34 (see FIG. 5). The application of the curable resin 63 to the other three substrate side surfaces 34 is performed in the same manner, and the curable resin 63 is applied to all the substrate side surfaces 34. In order to prevent sagging of the curable resin 63 during the coating material forming process, heat treatment (about 100 ° C.) is performed every time the curable resin 63 is attached to the substrate side surface 34 so that the curable resin 63 is cured to some extent. May be. Further, as the curable resin 63 of the present embodiment, a polyimide resin having a viscosity of 1.8 Pa · s is used.

  In the subsequent curing step, first, the interposer body 39 is arranged so that the substrate main surface 32 faces downward, thereby generating a dripping 64 that hangs down from the substrate main surface 32 due to the weight of the curable resin 63 (FIG. 6). reference). Thereafter, the masking tape 71 is peeled off (see FIG. 7). At this time, since the portion 65 (see FIG. 6) attached to the masking tape 71 in the curable resin 63 is also removed together with the masking tape 71, the curable resin 63 is formed on the entire substrate side surface 34 and the substrate main surface 32. It comes to adhere to the outer edge. Then, the curable resin 63 is cured. Specifically, after heat treatment at 140 ° C. in the atmosphere for 3 minutes, heat curing at 320 ° C. in nitrogen is performed for 60 minutes. As a result, the curable resin 63 becomes the covering material 61, and the liquid dripping 64 portion becomes the convex portion 62. At this point, the interposer 31 shown in FIG. 2 is completed.

  Thereafter, the substrate connection terminals 38 on the substrate rear surface 33 of the completed interposer 31 and the solder bumps 49 on the wiring substrate 41 side are aligned, and the interposer 31 is placed on the wiring substrate 41. Then, by heating and reflowing each solder bump 49, the board connection terminal 38 and the solder bump 49 are joined.

  Next, the IC chip 21 is placed on the substrate main surface 32 of the interposer 31. At this time, the solder bumps 23 on the IC chip 21 side and the semiconductor element connection terminals 37 on the interposer 31 side are aligned. Then, by heating and reflowing each solder bump 23, the semiconductor element connection terminal 37 and the solder bump 23 are joined. Then, if the gap between the interposer 31 and the IC chip 21 is sealed using the underfill material 51, the semiconductor package 11 shown in FIG. 1 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the interposer 31 of the present embodiment, since the entire substrate side surface 34 of the interposer body 39 is covered with the covering material 61, it is difficult for large stress to act directly on the interposer body 39. Therefore, even if the interposer body 39 is formed of a low-strength material (such as glass or glass ceramic), cracks and the like are unlikely to occur. Therefore, the interposer body 39 is prevented from being damaged, so that the interposer 31 can be given high reliability.

  In addition, the covering material 61 includes a convex portion 62 that protrudes toward the substrate main surface 32 and is disposed around the IC chip mounting region 24. For this reason, when the IC chip 21 is mounted, even if a part of the underfill material 51 that seals the gap between the interposer body 39 and the IC chip 21 flows out onto the substrate main surface 32, the flow of the underfill material 51. However, it stops by contacting the convex part 62 surrounding the IC chip mounting region 24. That is, the underfill material 51 is prevented from protruding to the outer region of the convex portion 62. Therefore, it is possible to prevent problems caused by the underfill material 51, which is an insulator, covering the surface connection pads 46 of the wiring substrate 41.

  (2) In the present embodiment, the liquid dripping 64 that hangs downward from the substrate main surface 32 is generated by the dead weight of the curable resin 63, and then the convex portion 62 is formed only by curing the liquid dripping 64. That is, since it is not necessary to form the convex part 62 separately from the covering material 61 made of the curable resin 63, the convex part 62 can be easily formed.

  (3) In this embodiment, since a part of the covering material 61 is in close contact with the outer edge portion of the substrate main surface 32, even if the covering material 61 is formed, an IC chip mounting region having a large area on the substrate main surface 32. 24 is easily secured. Therefore, it is possible to mount a plurality of IC chips 21 in the IC chip mounting area 24.

  (4) The IC chip 21 of the present embodiment is disposed directly above the interposer body 39. As a result, the conduction path for electrically connecting the IC chip 21 and the interposer body 39 is the shortest. Therefore, the power supply to the IC chip 21 can be performed smoothly. Further, since noise entering between the IC chip 21 and the interposer body 39 can be suppressed to a very low level, high reliability can be obtained without causing malfunctions such as malfunctions.

  In the present embodiment, since the IC chip mounting area 24 is set on the substrate main surface 32 of the interposer body 39, the IC chip 21 mounted on the IC chip mounting area 24 is highly rigid and has a low coefficient of thermal expansion. Supported by the body 39. Therefore, in the IC chip mounting area 24, the interposer body 39 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 24 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.

[Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Here, the description will focus on the parts that are different from the first embodiment, and the common parts will not be described in place of the same member numbers.

  In this embodiment, the structure of the covering material of the interposer is different from that of the first embodiment. Specifically, as shown in FIG. 8, the interposer 131 (relay board) of the present embodiment includes an interposer body 139 (relay board body), and the four substrate side surfaces 134 of the interposer body 139 include the side surfaces of each substrate. A covering material 161 that covers the entire 134 and covers the entire outer edge of the substrate main surface 132 is formed in close contact. The covering material 161 includes a convex portion 162 that protrudes toward the substrate main surface 132. In addition, the coating material 161 of this embodiment is formed with the polyimide resin which has photosensitivity. The thickness t2 of the covering material 161 is set to 10 μm or more and 50 μm or less (in this embodiment, 50 μm). Furthermore, the height h2 of the convex portion 162 is set to 10 μm or more and 50 μm or less (50 μm in this embodiment).

  Next, a procedure for manufacturing the interposer 131 having the above structure will be described.

  In the present embodiment, the coating material forming step is different from that of the first embodiment. More specifically, the coating material forming step includes a resin film sticking step, a laminating step, an exposure step, and a developing step. First, in the resin film sticking step, a resin film 163 (thickness: 50 μm), which is an uncured coating material 161, is stuck on the substrate main surface 132 of the interposer body 139 (see FIG. 9). In addition, the polyimide resin which has photosensitivity is used as a forming material of the resin film 163 of this embodiment. In addition, the resin film 163 is larger than the substrate main surface 132, specifically, has a size that can cover the entire substrate side surface 134 in addition to the substrate main surface 132.

  In the subsequent laminating step, a part of the resin film 163 that has flowed is pasted on the substrate side surface 134 by melting and flowing part of the resin film 163 by heating and pressing (see FIG. 10). In addition, in order to prevent a part of the resin film 163 from wrapping around the substrate back surface 133, the substrate back surface 133 may be protected in advance with an adhesive tape or the like.

  In the subsequent exposure step, the interposer body 139 laminated with the resin film 163 is fixed on a conventionally known exposure machine (not shown). Next, a photomask is disposed on the entire surface of the resin film 163 (not shown). Then, the surface of the resin film 163 is irradiated with ultraviolet light through a photomask to expose the resin film 163. As a result, the resin film 163 attached to the substrate main surface 132 excluding the outer peripheral portion of the substrate main surface 132 is removed, and the opening 164 that exposes the IC chip mounting region 124 (semiconductor element mounting region) (see FIG. 8) is formed on the resin film 163. Thereafter, the resin film 163 is peeled off.

  In the subsequent development process, the exposed resin film 163 is developed. As a result, the resin film 163 becomes the covering material 161, and the resin film 163 attached to the outer peripheral portion of the substrate main surface 132 becomes the convex portion 162. At this point, the interposer 131 shown in FIG. 8 is completed.

  Therefore, in this embodiment, since the convex part 162 can be formed only by exposing and developing the resin film 163, formation of the convex part 162 becomes easy.

  Next, an interposer evaluation method and the results will be described.

  First, a measurement sample was prepared as follows. The same interposer 31 as in the first embodiment was prepared, and this was taken as Example 1. Further, the same interposer 131 as that of the second embodiment was prepared, and this was taken as Example 2. Furthermore, an interposer 231 (see FIG. 11) in which the covering material 261 was formed in close contact only with the substrate side surface 234 was prepared, and this was designated as Comparative Example 1. The interposer 231 is obtained by applying a masking tape to both the substrate main surface 232 and the substrate back surface 233, applying a curable resin to the substrate side surface 234, and then peeling the masking tape. Moreover, the interposer 331 (refer FIG. 12) obtained without forming a coating | covering material was prepared, and this was made into the comparative example 2. FIG. In addition, 20 measurement samples were prepared for each.

Next, a dummy chip was mounted on each measurement sample (Examples 1 and 2, Comparative Examples 1 and 2), and the appearance yield and the mounting yield were evaluated. In addition, in the “appearance yield” evaluation, the state of the substrate side surface of the interposer body was observed, and those that could visually confirm the occurrence of cracks were judged as “failed”, and those that could not be confirmed visually by “ “Pass”. In the evaluation of “mounting yield”, the mounting state of the interposer on the wiring board and the mounting state of the IC chip on the interposer were observed. Then, if the connection failure occurs between the interposer and the wiring board, or if the underfill material flows out of the interposer when the IC chip is mounted, it is determined as “failed” and the others are determined as “passed”. Judged. In each measurement sample, the ratio (%) of the measurement sample determined to be “pass” was calculated for each evaluation. The results are shown in Table 1.

  As a result, in Comparative Example 1, the appearance yield was 95%, and the mounting yield was 60%. That is, in Comparative Example 1, it was confirmed that the appearance yield was relatively high, but the mounting yield was low. In Comparative Example 2, the appearance yield was 70%, and the mounting yield was 55%. That is, in Comparative Example 2, it was confirmed that the appearance yield and the mounting yield were lowered.

  On the other hand, in Example 1, the appearance yield was 100%, and the mounting yield was 90%. In Example 2, the appearance yield and the mounting yield were both 95%. In other words, in Examples 1 and 2, it was confirmed that the yield of each evaluation was relatively high, being 90% or more.

  From the above, it was confirmed that if the covering material is formed on the side surface of the substrate of the interposer body, the occurrence of cracks in the interposer body can be prevented, that is, the improvement of the appearance yield can be expected. Further, it was confirmed that if a convex portion protruding toward the substrate main surface side is formed on the covering material, it is possible to prevent the underfill material from flowing out from the interposer, that is, to improve the mounting yield.

  In addition, you may change this embodiment as follows.

  As shown in the interposer 431 in FIG. 13, the convex portion may protrude on the substrate back surface 433 side in addition to the substrate main surface 432 side. In this case, it is preferable that the height h4 of the convex portion 463 protruding toward the substrate back surface 433 is lower than the height h3 of the convex portion 462 protruding toward the substrate main surface 432. If the height h4 of the convex portion 463 is higher than the height h3 of the convex portion 462, the convex portion 463 may come into contact with the wiring board on which the interposer 431 is mounted, which may prevent the interposer 431 from being mounted on the wiring board. is there. As shown in FIG. 13, a part of the covering material 461 may be in close contact with both the outer edge portion of the substrate main surface 432 and the outer edge portion of the substrate back surface 433.

  In the interposers 31 and 131 of the above embodiments, the covering materials 61 and 161 that are in close contact with the substrate main surfaces 32 and 132 and the covering materials 61 and 161 that are in close contact with the substrate side surfaces 34 and 134 are connected to each other. However, as shown in the interposer 531 in FIG. 14, the covering material 561 that is in close contact with the substrate main surface 532 and the covering material 561 that is in close contact with the substrate side surface 534 may be separated from each other.

  In the interposer 31 of the first embodiment, the covering material 61 includes the convex portion 62 that protrudes toward the substrate main surface 32, and a part of the covering material 61 is in close contact with the outer edge portion of the substrate main surface 32. However, as shown in the interposer 631 in FIG. 15, even when the covering material 661 includes the convex portion 662, the covering material 661 does not adhere to the substrate main surface 632 but adheres only to the substrate side surface 634. It may be a thing.

  In the interposer 31 of the first embodiment, the apex P1 of the convex portion 62 of the covering material 61 is located on the virtual line L1 extending from the substrate side surface 34. However, as shown in the interposer 731 in FIG. 16, the covering material 761 is such that the apex P2 of the convex portion 762 is located closer to the center side of the substrate main surface 732 than the virtual line L2 extending from the substrate side surface 734. Also good.

  In the interposers 31 and 131 of the above embodiments, the four substrate side surfaces 34 and 134 are covered with the covering materials 61 and 161, but only one substrate side surface 34 and 134 are covered with the covering materials 61 and 161. Alternatively, two or three substrate side surfaces 34 and 134 may be covered with the covering materials 61 and 161. The covering materials 61 and 161 may completely cover the surfaces (substrate side surfaces 34 and 134) covered by the covering materials 61 and 161, or the surfaces covered by the covering materials 61 and 161 (substrate side surfaces 34 and 134). You may cover only a part of.

  In each of the above embodiments, the interposers 31 and 131 are used as relay boards, but it is also acceptable to use other structures as relay boards. For example, a buildup multilayer wiring board having a buildup layer formed by alternately laminating interlayer insulating layers and conductor layers on one side or both sides of the core board may be used as the relay board. This makes it easy to increase the density of the relay board. Note that examples of the material for forming the interlayer insulating layer include an epoxy resin and a polyimide resin. Moreover, copper etc. can be mentioned as a forming material of a conductor layer.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) In the above means 1, a part of the covering material is in close contact with an outer edge portion of the substrate main surface, and the covering material in close contact with the substrate main surface and the covering in close contact with the substrate side surface A relay board characterized in that the materials are connected to each other.

  (2) In the above means 1, a part of the covering material is in close contact with the outer edge portion of the substrate main surface, and the covering material in close contact with the substrate main surface and the covering in close contact with the substrate side surface A relay substrate characterized in that the materials are separated from each other.

  (3) In the above means 1, the height of the convex part is 10 μm or more and 500 μm or less.

  (4) In the above means 1, the relay board is characterized in that the covering material does not protrude toward the back side of the board.

  (5) In the above means 1, the relay substrate body is made of any one of glass, ceramic and glass ceramic.

  (6) In the above means 1, a wiring layer is connected to at least one of the end of the plurality of conductor columns on the substrate main surface side and the end of the plurality of conductor columns on the substrate back surface side. A relay board characterized by

  (7) In the above means 1, the relay substrate is characterized in that the covering material covering the side surface of the substrate gradually increases in thickness from the back surface side of the substrate toward the main surface side of the substrate.

  (8) In the above means 1, the relay substrate is characterized in that the vertex of the convex portion is located on an imaginary line extending from the side surface of the substrate.

  (9) In said means 2, after said conductor pillar formation process and before said coating | covering material formation process, the said board | substrate main surface side edge part in these conductor pillars, and the said board | substrate back surface side in these conductor pillars A method for manufacturing a relay substrate, comprising performing a connection terminal forming step of forming a wiring layer connected to at least one of the end portions of the substrate.

  (10) A relay substrate with a semiconductor element, comprising the relay substrate of the means 1 and a semiconductor element having a surface connection terminal.

  (11) A structure comprising a semiconductor element, a relay substrate, and a substrate, comprising the relay substrate of the means 1 and a semiconductor element having a surface connection terminal, and further including a substrate having a surface connection pad.

21... IC chip 24 as a semiconductor element, 124. IC chip mounting area 31, 131, 431, 531, 631, 731 as a semiconductor element mounting area. Interposer 32, 132, 432, 532, 632, 732 as a relay substrate ... substrate main surfaces 33, 133, 433 ... substrate back surfaces 34, 134, 534, 634, 734 ... substrate side surfaces 36 ... conductor pillars 37 ... semiconductor element connection terminals 39, 139 ... interposer bodies 61, 161 as relay substrate bodies 461, 561, 661, 761... Covering material 62, 162, 462, 762... Convex part 463 projecting to the substrate main surface side. Convex part 63 projecting to the substrate back surface side. h1, h2, h3... height of the protrusion protruding to the substrate main surface side h4... height of the protrusion protruding to the substrate back surface side

Claims (6)

A substrate main surface, a substrate back surface, and a substrate side surface, and has a substantially plate-shaped relay substrate body made of an insulating material or a material whose surface is insulated, and penetrates between the substrate main surface and the substrate back surface. A relay board comprising a plurality of conductor pillars, and a semiconductor element mounting region in which a plurality of semiconductor element connection terminals for mounting a semiconductor element are present on the main surface of the board;
A covering material covering at least a part of the side surface of the substrate is formed in close contact with the side surface of the substrate,
The covering material includes a convex portion that protrudes to the substrate back surface side in addition to the substrate main surface side and is arranged around the semiconductor element mounting region ,
The relay substrate according to claim 1, wherein a height of the convex portion protruding toward the back surface side of the substrate is lower than a height of the convex portion protruding toward the main surface side of the substrate.   The relay substrate according to claim 1, wherein a part of the covering material is in close contact with an outer edge portion of the substrate main surface.   The relay substrate according to claim 1, wherein a height of the convex portion is higher than a height of the plurality of semiconductor element connection terminals. The portion of the dressing, the relay substrate according to any one of claims 1 to 3, characterized in that is in close contact with the both the outer edge of the outer portion and the substrate rear surface of the substrate main surface. A substrate main surface, a substrate back surface, and a substrate side surface, and has a substantially plate-shaped relay substrate body made of an insulating material or a material whose surface is insulated, and penetrates between the substrate main surface and the substrate back surface. In a method for manufacturing a relay board comprising a plurality of conductor pillars, and a semiconductor element mounting region in which a plurality of semiconductor element connection terminals for mounting a semiconductor element are present on the main surface of the board.
A relay board body preparation step of preparing the relay board body;
A conductor pillar forming step of forming the plurality of conductor pillars on the relay substrate body;
Wherein comprises a convex portion disposed around the semiconductor element mounting region with protruding board main surface side, viewed contains a coating material forming step of contact forming at least a portion of the cover coating material of the substrate side,
The coating material forming step includes
A resin film pasting step of pasting a photosensitive resin film on the main surface of the substrate;
A laminating step of applying a part of the resin film that has flowed to the side surface of the substrate by melting and flowing part of the resin film by heating and pressurizing, and
By exposing the resin film, an exposure step of removing the resin film attached to a region excluding the outer peripheral portion of the substrate main surface in the substrate main surface;
Developing the exposed resin film to make the resin film the covering material, and developing the resin film affixed to the outer peripheral portion of the substrate main surface as the convex portion;
The manufacturing method of the relay board | substrate characterized by including . In the relay substrate main body preparation step, preparing a substrate for multi-cavity in which a plurality of substrate formation regions to be the relay substrate main body are arranged along a planar direction,
After the conductor pillar forming step and before the covering material forming step, a dividing step of obtaining the plurality of relay substrate bodies by cutting the multi-piece substrate along the outline of the substrate forming region. The relay board manufacturing method according to claim 5 , wherein the relay board is manufactured.

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