JP6026756B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a through hole penetrating a semiconductor substrate is formed.

  In response to the recent increase in communication technology speed and capacity, there are expectations for semiconductor devices such as transistors that can be operated at high speed using InP materials instead of GaAs materials that have been used in the past. It is increasing. In such a semiconductor device, in order to bring out sufficient performance in a high frequency band such as a millimeter wave band, a through-hole that enables ground reinforcement, improved heat dissipation of the semiconductor device, and easy mounting on a substrate ( Through via) formation technology becomes important.

  In order to realize this via technology, an etching technology for forming a through via in a substrate (for example, an InP substrate) of a semiconductor device thinned to a thickness of about 50 to 100 μm, and a wiring in the formed through via The technology for forming (depositing) the metal becomes important. Here, since the InP substrate thinned to a thickness of about 50 to 100 μm is very fragile, each process is performed by being attached to a supporting substrate such as glass using an adhesive. The heat resistance of adhesives used for such applications is generally as low as 200 ° C. or lower. For this reason, considering the process margin, the thermal load applied in the above-described through via formation process is desirably 180 ° C. or less.

  The thermal load applied in the formation process of the through via is applied by an etching process for forming the through via or a metal deposition process. Among these, the metal deposition process can be performed without exceeding the above-described upper temperature limit by using a sputtering method, a plating method, or the like. Further, if the etching process is performed by a wet etching method, it can be performed at about room temperature (23 ° C.). For example, in the case of an InP substrate, etching can be performed at about room temperature by a wet etching method.

  However, as is well known, in the wet etching method, the amount of side etching in which etching proceeds in the plane direction of the substrate is large. In addition, since a crystal substrate such as InP has a higher etching rate anisotropy depending on the crystal plane direction than GaAs, it is difficult to form a via hole having a practical size.

  On the other hand, as is well known, the dry etching method can perform anisotropic etching and reduce the amount of side etching. Further, according to the dry etching method, crystal anisotropy is not a problem. However, for example, when chlorine gas that enables dry etching of InP is used, the vapor pressure of indium chloride, which is a reaction product of InP and chlorine gas, is low. Is needed. For this reason, in order to obtain an appropriate etching rate, the upper limit temperature limit of the adhesive described above is exceeded. On the other hand, there is a problem that a sufficient etching rate cannot be obtained at a low temperature of 200 ° C. or less that does not exceed the upper limit of the heat resistance temperature of the adhesive.

  In response to the above-mentioned problem of dry etching using chlorine gas, dry etching of an In substrate or the like can be performed at a lower temperature (about 100 ° C.) using hydrogen iodide gas, hydrogen bromide gas, or a mixed gas containing these gases. A technique for making it possible has been proposed (see Non-Patent Document 1).

K. Kotani et.al., "High Etch Rate and Low Temperature InP Backside Via Etching Using HI-based Inductively Coupled Plasma", 2004 International Conference on Indium Phosphide and Related Materials Conference proceedings, 16th IPRM, pp.717-720, 2004 .

  However, dry etching has a problem that the etching rate varies depending on the diameter of the through via to be formed. For example, when a through via is formed on an InP substrate at a temperature condition of 100 ° C. by dry etching using hydrogen bromide, the etching rate varies depending on the diameter of the through via. As shown in FIG. Becomes slower. This phenomenon is considered to occur because the reaction product in the through via becomes harder to vaporize and the rate decreases as the through via diameter decreases.

  Here, in the formation of the through via, the wiring formed on one surface (front surface) of the substrate is exposed to the etching region. For example, dry etching using hydrogen iodide gas and hydrogen bromide gas is performed. Then, these wirings are also etched. On the other hand, if the etching time until reaching the wiring is the same in each through via, the etching amount of the wiring described above is common to each through via portion, and it is easy to adjust the etching time. Can be controlled.

  However, in general, the diameters of the through vias are not common and are different from each other. For this reason, as described above, the etching rate differs according to the diameter, and the etching amount of the wiring portion that reaches each through via differs. For example, if the etching time is shared with the processing time of the through-via having the smallest diameter, an over-etching state occurs in the through-via having a larger diameter. In such a state, when forming through vias of various diameters at the same time, if the etching time is adjusted to the minimum diameter, the wiring already formed is etched for a longer time with a large diameter. Had the problem of penetrating the wiring.

  As a method for solving this, a method of increasing the film thickness of the wiring is conceivable. However, it takes a long time to form the wiring and increases the cost. In particular, when Au is used as the wiring material, the increase in cost is significant. Moreover, since the unevenness of the wiring increases as the wiring becomes thicker, there is a problem that processing becomes difficult. On the other hand, a method of forming each through via having the same size diameter is also conceivable, but the number of through via forming steps becomes very large, resulting in a decrease in productivity and an increase in manufacturing cost.

  The present invention has been made to solve the above-described problems, and allows a plurality of through-holes having different hole diameters to be formed in a semiconductor substrate without increasing the number of steps and increasing the cost. With the goal.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming an etching stop layer made of an insulating material on a surface of a semiconductor substrate made of InP, and forming a first surface wiring and a second surface wiring on the etching stop layer. Forming a mask pattern for forming a first through hole reaching the first surface wiring having a different hole diameter and a second through hole reaching the second surface wiring on the back surface side of the semiconductor substrate; and a mask Using the pattern as a mask, the semiconductor substrate is selectively etched by dry etching using hydrogen iodide gas, hydrogen bromide gas, or a mixed gas thereof to reach the first through hole and the second through hole to the etching stop layer. And the etching stop layer are selectively etched, and the first through hole and the second through hole reach the first surface wiring and the second surface wiring. A first back wiring connected to the first through wiring, a step of forming the first through wiring, forming a first through wiring in the first through hole, forming a second through wiring in the second through hole, And forming a second back surface wiring connected to the two through wirings on the back surface of the semiconductor substrate.

  In the semiconductor device manufacturing method, after forming the first surface wiring and the second surface wiring, a step of attaching a support substrate to the front surface side of the semiconductor substrate, and after attaching the support substrate, the semiconductor substrate from the back side A mask pattern may be formed after the semiconductor substrate is thinned. Note that the support substrate may be attached in a temperature range of 0 to 180 ° C.

  The etching stop layer can be made of silicon oxide or silicon oxynitride. The mask pattern is composed of at least an organic insulating material, and the organic insulating material is selected from polyimide, benzocyclobutene, polybenzoxazole, arylene ether-based polymer, siloxane-based polymer, and aromatic hydrocarbon-based polymer. Anything can be used.

The first through wiring, the second through wiring, the first back wiring, and the second back wiring are formed by forming a seed layer by a sputtering method and depositing a metal on the seed layer by a plating method. The seed layer is preferably formed under sputtering conditions with a low pressure of 0.05 Pa or more and 0.2 Pa or less and a low discharge power density of 0.1 W / cm ² or more and 2 W / cm ² or less. The first through wiring, the second through wiring, the first back wiring, and the second back wiring are formed by depositing a metal by a plating method using a selective plating resist pattern, and a selective plating resist pattern. Is preferably formed by applying a negative type photoresist by a spray coating method.

  As described above, according to the present invention, it is possible to obtain an excellent effect that a plurality of through holes having different hole diameters can be formed in a semiconductor substrate without causing an increase in process and cost.

FIG. 1A is a cross-sectional view schematically showing a state in each step for describing a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1B is a cross-sectional view schematically showing a state in each step for explaining the method of manufacturing a semiconductor device in the embodiment of the present invention. FIG. 1C is a cross-sectional view schematically showing a state in each step for explaining the method of manufacturing a semiconductor device in the embodiment of the present invention. FIG. 1D is a cross sectional view schematically showing a state in each step for describing the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 1E is a cross sectional view schematically showing a state in each step for describing the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 1F is a cross sectional view schematically showing a state in each step for describing the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 1G is a cross sectional view schematically showing a state in each step for describing the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 1H is a cross sectional view schematically showing a state in each step for describing the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 1I is a cross-sectional view schematically showing a state in each step for explaining a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 1J is a cross-sectional view schematically showing a state in each step for explaining the method for manufacturing a semiconductor device in the embodiment of the present invention. FIG. 2 is a correlation diagram showing the relationship between the diameter of the through via and the etching rate.

  Embodiments of the present invention will be described below with reference to FIGS. 1A to 1J. 1A to 1J are cross-sectional views schematically showing states in respective steps for explaining a method for manufacturing a semiconductor device in an embodiment of the present invention.

  First, as shown in FIG. 1A, an etching stop layer 102 made of an insulating material is formed on the surface of the semiconductor substrate 101, and a first surface wiring 103a and a second surface wiring 103b are formed on the etching stop layer 102. . The semiconductor substrate 101 is, for example, an InP substrate whose resistance is increased by doping iron. The etching stop layer 102 may be made of, for example, silicon oxide, and may be formed by a sputtering method. The etching stopper layer 102 may be about 0.3 μm thick.

  Further, the first surface wiring 103a and the second surface wiring 103b may be formed by patterning the deposited metal film by a known lithography technique and etching technique. For example, a metal film such as titanium (Ti), platinum (Pt), and gold (Au) is formed (deposited) by vapor deposition, sputtering, plating, or the like, and the metal film is patterned to obtain a thickness. The first surface wiring 103a and the second surface wiring 103b may be about 1 μm. For example, elements (not shown) such as transistors are formed on the surface of the semiconductor substrate 101, and the first surface wiring 103a and the second surface wiring 103b are connected to any of these elements. The etching stopper layer 102 is formed on, for example, an interlayer insulating layer (not shown) formed so as to cover the element.

  Next, as shown in FIG. 1B, a protective layer 104 that covers the periphery of the first surface wiring 103a and the second surface wiring 103b is formed. The protective layer 104 may be made of SiN, for example. For example, the protective layer 104 may be formed by patterning a SiN film deposited by a CVD method using a known lithography technique and etching technique.

  Next, as illustrated in FIG. 1C, a support substrate 106 is attached to the surface side of the semiconductor substrate 101 on which the first surface wiring 103 a and the second surface wiring 103 b are formed using an adhesive layer 105. The support substrate 106 may be a glass substrate, for example. Thereafter, the semiconductor substrate 101 is ground and thinned from the back side. For example, the thickness may be about 100 μm. Note that the grinding process may not be necessary depending on the use and specifications of the final product and the initial thickness of the semiconductor substrate 101.

  Next, as illustrated in FIG. 1D, the first insulating layer 107 and the second insulating layer 108 are formed on the back surface of the semiconductor substrate 101. In addition, an opening 108 a and an opening 108 b are formed in the second insulating layer 108, and an opening 107 a and an opening 107 b are formed in the first insulating layer 107. The opening 108a and the opening 107a are arranged corresponding to a portion serving as the first through hole reaching the first surface wiring 103a, and the opening 108b and the opening 107b are the second reaching the second surface wiring 103b. It arrange | positions corresponding to the part used as a through-hole. The opening 108a and the opening 107a are used to form a first through hole that reaches the first surface wiring 103a, and are formed to have a diameter of about 100 μm, for example. The opening 108b and the opening 107b are used to form a second through hole that reaches the second surface wiring 103b, and have a diameter of, for example, about 50 μm.

  In other words, the first through-hole reaching the first surface wiring 103a is formed by the first insulating layer 107 in which the opening 107a and the opening 107b are formed and the second insulating layer 108 in which the opening 108a and the opening 108b are formed. And the mask pattern for forming the 2nd through-hole which reaches the 2nd surface wiring 103b is constituted.

  The first insulating layer 107 is made of, for example, silicon oxide deposited by a sputtering method, and may be formed with a layer thickness of about 0.2 μm. The second insulating layer 108 may be formed of a film of an organic insulating material formed by a spin coating method. As the organic insulating material, photosensitive polybenzoxazole may be used. For example, the organic insulating material may be applied to a thickness of about 15 μm to form the second insulating layer 108.

The opening 108a and the opening 108b can be formed by patterning the second insulating layer 108 made of the photosensitive organic insulating material described above by a known photolithography technique. Note that after forming the opening 108a and the opening 108b by patterning, the second insulating layer 108 is heat-cured under a processing condition of 180 ° C. for 1 hour. The opening 107a and the opening 107b can be formed by selectively etching the first insulating layer 107 using the second insulating layer 108 formed with the opening 108a and the opening 108b as a mask. For example, the first insulating layer 107 may be selectively etched by the RIE method using C ₂ F ₆ gas.

  As a mask pattern for selectively etching the semiconductor substrate 101, only the second insulating layer 108 may be used. However, in general, the adhesion between the organic insulating material and a compound semiconductor such as InP is not so good. For this reason, when the layer of the organic insulating material is formed in direct contact with the semiconductor substrate 101, the layer is easily peeled off. On the other hand, since the first insulating layer 107 has high adhesion to both the semiconductor substrate 101 and the second insulating layer 108, the second insulating layer 107 is provided by providing the first insulating layer 107 as described above. Separation of the insulating layer 108 can be suppressed. As described above, the first insulating layer 107 is formed to improve adhesion, and may be formed to a uniform thickness. As described above, the first insulating layer 107 is formed to have a layer thickness of about 0.2 μm. do it.

  Next, the semiconductor substrate 101 is selectively etched using the first insulating layer 107 in which the opening 107a and the opening 107b are formed and the second insulating layer 108 in which the opening 108a and the opening 108b are formed as a mask pattern. As shown to 1E, the 1st board | substrate through-hole 101a and the 2nd board | substrate through-hole 101b are formed in the state which reaches | attains the etching stop layer 102. FIG.

  For example, the semiconductor substrate 101 may be selectively etched by a reactive ion etching method using hydrogen bromide gas at a temperature condition of about 100 ° C. By this etching, a first substrate through hole 101a having a diameter of 100 μm and a second substrate through hole 101b having a diameter of 50 μm can be formed in the semiconductor substrate 101. Here, the etching time may be a time during which the second substrate through hole 101b having a small hole diameter can be formed. In this processing time, in the formation of the first substrate through hole 101a having a large hole diameter, so-called over-etching is performed. However, since the etching stop layer 102 is provided, the above-described etching is stopped by the etching stop layer 102. Even if the first substrate through hole 101a is formed, the first surface wiring 103a does not touch the region where this etching is performed. Therefore, the first surface wiring 103a in the region where the first substrate through hole 101a is formed is not etched.

Next, following the formation of the first substrate through hole 101a and the second substrate through hole 101b described above, the first insulating layer 107 in which the opening 107a and the opening 107b are formed, and the opening 108a and the opening 108b are formed. Using the second insulating layer 108 as a mask pattern, the etching stop layer 102 is selectively etched to form a first opening 102a and a second opening 102b in the second insulating layer 108 as shown in FIG. 1F. . For example, the etching stop layer 102 may be selectively etched by the RIE method using C ₂ F ₆ gas. In this etching, the first surface wiring 103a and the second surface wiring 103b are exposed to the etching region. However, according to the above etching, the etching stop layer 102 is selectively etched, and the first surface wiring 103a and the second surface wiring 103b are hardly etched.

  In this manner, by forming the first opening 102a and the second opening 102b, first, the first surface is formed from the first substrate through-hole 101a and the first opening 102a, and the first surface from the back side of the semiconductor substrate 101. The first through hole 109a reaching the wiring 103a is formed. In addition, the second through hole 109b, which is configured by the second substrate through hole 101b and the second opening 102b and reaches the second surface wiring 103b from the back surface side of the semiconductor substrate 101, is formed. The first insulating layer 107 and the second insulating layer 108 used as masks for forming the above-described through holes are made of a material used for an interlayer insulating layer in a known semiconductor device, and are left as they are. There is no problem with the condition, and there is no need to remove it.

  Next, as shown in FIG. 1G, a seed layer 110 is formed on the surface of the second insulating layer 108 including the bottom and side walls of the first through hole 109a and the second through hole 109b. For example, the seed layer 110 may be formed by depositing W and Au by sputtering. The W layer is used to improve the adhesion between the Au layer and the semiconductor substrate 101. The Au layer may be formed to a thickness of about 1 to 2 μm.

Here, it is important that the seed layer 110 is formed on the bottom and the side wall of the through hole. For this reason, the metal deposition described above may be performed under the condition that the metal particles by the sputtering method reach the bottom of the through hole and the metal particles by the sputtering method adhere to the side wall of the through hole. Specifically, the pressure at the time of sputtering film formation may be about 0.1 Pa, and the power density at the time of sputtering film formation may be about 1 W / cm ² . If sputter deposition is performed under these conditions, the seed layer 110 can be formed on the bottom and side walls of the through hole.

  In general, when a plating seed layer is deposited in a through hole by sputtering, it is necessary to deposit metal on the side wall of the hole, and therefore, a high pressure (for example, 1 Pa) at which a lateral component increases is set as a sputtering condition. However, when the depth of the through hole is 50 μm or more, there is a problem that the sputter metal does not reach the bottom of the through hole because the vertical component is small. In order to solve this, a biased sputtering method has been proposed, but a biased sputtering apparatus is more expensive than a general sputtering apparatus.

On the other hand, as described above, the pressure during sputtering film formation is lowered in the range of 0.05 to 0.2 Pa, and in addition, the power density during sputtering film formation is 0.1 W / cm ^{2 to} 0.2 W. By appropriately setting within the range of / cm ² , a metal layer can be formed on the bottom and side walls of the through hole. By lowering the pressure at the time of sputtering film formation, the mean free path of the sputtered particles becomes longer and the sputtered particles reach the bottom of the deep through hole. Further, by setting the power density not to be so high, a part of the sputtered particles can be attached to the side wall.

  Next, as shown in FIG. 1H, a selective plating resist pattern 111 is formed. For example, using a spray coating method, a negative type photoresist is applied to a thickness of about 10 μm to form a coating film. Next, the selective coating resist pattern 111 may be formed by patterning the formed coating film by a known photolithography technique.

  Here, when such a resist pattern is formed, if a liquid resist material is applied by a normal spin coating method, a through hole having a depth of 100 μm is filled with the resist. In such a state, at the time of development by photolithography, a phenomenon in which the resist in the through hole cannot be completely developed and remains is likely to occur. If the resist remains, it causes plating failure and causes problems such as disconnection. In order to solve this problem, a dry film resist has been proposed. However, when the dry film resist is applied to the substrate, air voids are likely to be generated, which causes a pattern defect.

  By using a spray coating method for these film formation techniques, a coating film can be formed without filling the through hole with a resist, and therefore, resist residue in the through hole during development can be suppressed. Further, since a negative type resist is used, the unexposed portion is dissolved and removed by development. As a result, even if underexposure occurs, there is no shortage of dissolution during development in the through-hole portion to be removed by development, and in this respect as well, resist residue in the through-hole during development is suppressed. become able to.

  When the selective plating resist pattern 111 is formed as described above, Au is selectively plated on the exposed seed layer 110 that is not covered thereby, so that the first through wiring 109a is formed in the first through hole 109a. 112a is formed, and the second through wiring 112b is formed in the second through hole 109b. At the same time, the first back surface wiring 113a continuous to the first through wiring 112a is formed, and the second back surface wiring 113b continuous to the second through wiring 112b is formed. The first through wiring 112a is connected to the first surface wiring 103a in the first through hole 109a, and the second through wiring 112b is connected to the second surface wiring 103b in the second through hole 109b.

  Next, after removing the selective plating resist pattern 111, as shown in FIG. 1I, the seed layer 110 is selectively removed by etching using the first back surface wiring 113a and the second back surface wiring 113b as a mask. The seed layer 110a in the 109a formation region and the seed layer 110b in the second through-hole 109b formation region are separated.

  Finally, if the adhesive layer 105 is removed and the support substrate 106 is peeled off, the surface wiring formed on the surface of the semiconductor substrate 101 and the back wiring formed on the back surface of the semiconductor substrate 101 are formed as shown in FIG. 1J. Thus, the connected state is obtained by the through wiring formed in each through hole. The first front surface wiring 103a is connected to the first back surface wiring 113a by a first through wiring 112a formed in the first through hole 109a having a larger hole diameter. The second front surface wiring 103b is connected to the second back surface wiring 113b by the second through wiring 112b formed in the second through hole 109b having a smaller hole diameter.

  As described above, according to the present invention, since the surface wiring layer is formed on the surface of the semiconductor substrate via the etching stop layer made of an insulating material, the through hole is formed in the semiconductor substrate. It is easy to form a plurality of through holes having different hole diameters at the same time, and the productivity and design flexibility of a semiconductor device having a through hole can be improved. As a result, according to the present invention, a plurality of through holes having different hole diameters can be formed in the semiconductor substrate without increasing the number of steps and increasing the cost.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, in the above description, the etching stop layer and the first insulating layer are made of silicon oxide. However, the present invention is not limited to this. For example, the etching stop layer and the first insulating layer may be made of an inorganic insulating material containing silicon and oxygen such as silicon oxynitride. .

  In the above-described embodiment, the temperature condition is 100 ° C. in the dry etching of the semiconductor substrate made of InP using hydrogen bromide gas. However, the temperature condition is not limited to this, and the temperature condition is 0 ° C. to 180 ° C. It may be in the range. This temperature condition may be set appropriately in accordance with the heat resistance temperature of the layer made of an organic material having the lowest heat resistance temperature, such as an adhesive layer already formed in the step of forming the through hole in the semiconductor substrate. Note that this temperature condition is not limited to the through-hole forming step, but relates to the step after the support substrate is pasted, and the step after the support substrate is pasted is in the temperature range of 0 to 180 ° C. It should be done.

  In the above-described embodiment, an example in which dry etching of a semiconductor substrate made of InP is performed using hydrogen bromide gas is not limited to this, but hydrogen iodide gas or hydrogen iodide gas is used. A mixed gas of hydrogen bromide gas may be used, or a mixed gas containing hydrogen iodide or hydrogen bromide as a main gas and added with argon, helium, nitrogen or oxygen may be used.

  In the above-described embodiment, polybenzoxazole is used as the organic insulating material. However, the present invention is not limited to this, and polyimide, benzocyclobutene, arylene ether-based polymer, siloxane-based polymer, or aromatic hydrocarbon-based material is used. An organic insulating material such as a polymer can be used. These organic insulating materials may be photosensitive or non-photosensitive, and may have a heat resistance temperature equal to or higher than the temperature condition in the dry etching process of the InP substrate using hydrogen iodide gas or hydrogen bromide gas.

  In the above-described embodiment, for example, the photosensitive organic insulating material is used for the second insulating layer. However, the present invention is not limited to this, and the second insulating layer may be made of a non-photosensitive material. In this case, the opening may be formed by patterning the second insulating layer using an RIE method using a photoresist as a mask. Further, the through wiring may be formed in a state in which the inside of the through hole is filled. In the above-described embodiment, the case where an InP substrate is used as a semiconductor substrate has been described as an example. However, the present invention is not limited to this, and the present invention can also be applied to other semiconductor substrates such as a GaN substrate. Needless to say.

DESCRIPTION OF SYMBOLS 101 ... Semiconductor substrate, 101a ... 1st substrate through-hole, 101b ... 2nd substrate through-hole, 102 ... Etching stop layer, 103a ... 1st surface wiring, 103b ... 2nd surface wiring, 104 ... Protective layer, 105 ... Adhesion layer , 106 ... support substrate, 107 ... first insulating layer, 107a, 107b ... opening, 108a, 108b ... opening, 109a ... first through hole, 110, 110a, 110b ... seed layer, 111 ... resist pattern for selective plating 112a, first through wiring, 112b, second through wiring, 113a, first back wiring, 113b, second back wiring.

Claims (7)

Forming an etching stop layer made of an insulating material on the surface of a semiconductor substrate made of InP;
Forming a first surface wiring and a second surface wiring on the etching stop layer;
Forming a mask pattern for forming a first through hole reaching the first surface wiring having a different hole diameter and a second through hole reaching the second surface wiring on the back surface side of the semiconductor substrate;
Using the mask pattern as a mask, the semiconductor substrate is selectively etched by dry etching using hydrogen iodide gas, hydrogen bromide gas, or a mixed gas thereof to form the first through hole and the second through hole. Forming to reach the etching stop layer; and
Selectively etching the etch stop layer to form the first through hole and the second through hole in a state of reaching the first surface wiring and the second surface wiring;
A first through wiring is formed in the first through hole, a second through wiring is formed in the second through hole, a first back surface wiring connected to the first through wiring, and a second through wiring And forming a second back surface wiring to be connected to the back surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 1,
After forming the first surface wiring and the second surface wiring, attaching a support substrate to the surface side of the semiconductor substrate;
After pasting the support substrate, comprising the step of grinding and thinning the semiconductor substrate from the back side,
A method of manufacturing a semiconductor device, wherein the mask pattern is formed after the semiconductor substrate is thinned. The method of manufacturing a semiconductor device according to claim 2.
A method for manufacturing a semiconductor device, wherein the step after attaching the support substrate is performed in a temperature range of 0 to 180 ° C. In the manufacturing method of the semiconductor device of any one of Claims 1-3,
The method for manufacturing a semiconductor device, wherein the etching stop layer is made of silicon oxide or silicon oxynitride. In the manufacturing method of the semiconductor device given in any 1 paragraph of Claims 1-4,
The mask pattern is composed of at least an organic insulating material,
The organic insulating material is selected from polyimide, benzocyclobutene, polybenzoxazole, arylene ether-based polymer, siloxane-based polymer, and aromatic hydrocarbon-based polymer. Method. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The first through wiring, the second through wiring, the first back surface wiring, and the second back surface wiring are formed by forming a seed layer by a sputtering method and depositing a metal on the seed layer by a plating method. To do
The seed layer is formed under sputtering conditions with a low pressure of 0.05 Pa or more and 0.2 Pa or less and a low discharge power density of 0.1 W / cm 2 or more and 2 W / cm 2 or less. . The method of manufacturing a semiconductor device according to claim 6.
The first through wiring, the second through wiring, the first back surface wiring, and the second back surface wiring are formed by depositing a metal by a plating method using a selective plating resist pattern. The method for manufacturing a semiconductor device, wherein the resist pattern is formed by applying a negative type photoresist by a spray coating method.

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