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JP6028864B2 - Semiconductor device - Google Patents
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JP6028864B2 - Semiconductor device - Google Patents

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JP6028864B2
JP6028864B2 JP2015526034A JP2015526034A JP6028864B2 JP 6028864 B2 JP6028864 B2 JP 6028864B2 JP 2015526034 A JP2015526034 A JP 2015526034A JP 2015526034 A JP2015526034 A JP 2015526034A JP 6028864 B2 JP6028864 B2 JP 6028864B2
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semiconductor device
recess
termination region
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JPWO2015004716A1 (en
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詠子 大月
詠子 大月
康史 貞松
康史 貞松
康博 吉浦
康博 吉浦
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

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Description

本発明は、パワーモジュールに使われるダイオードなどの半導体装置に関する。   The present invention relates to a semiconductor device such as a diode used in a power module.

ダイオードでは、ｐ＋型アノード層とｎ＋型カソード層の間で順方向に電流を流すと、ｎ−型ドリフト層に多数のキャリアが蓄積する。その後、スイッチをオフすると、蓄積されたキャリアが排出され、リカバリー電流（逆回復電流）が流れる。リカバリー動作時に活性領域と終端領域に蓄積されたキャリアの両方がｐ＋型アノード層に流れ込む。このため、ｐ＋型アノード層の端部は、リカバリー電流が集中して電界が高くなり、温度が上昇して破壊され易い。これを防ぐために終端領域においてｎ＋型カソード層を掘り込んで凹部を形成したダイオードが提案されている（例えば、特許文献１の図３参照）。In the diode, when a forward current is passed between the p + type anode layer and the n + type cathode layer, a large number of carriers accumulate in the n − type drift layer. Thereafter, when the switch is turned off, the accumulated carriers are discharged and a recovery current (reverse recovery current) flows. During the recovery operation, both carriers accumulated in the active region and the termination region flow into the p + type anode layer. For this reason, the end portion of the p + -type anode layer is likely to be destroyed due to the concentration of the recovery current, the electric field being increased, and the temperature rising. In order to prevent this, a diode in which a recess is formed by digging an n + -type cathode layer in the termination region has been proposed (see, for example, FIG. 3 of Patent Document 1).

日本特開２００９−０９４１０５号公報Japanese Unexamined Patent Publication No. 2009-094105

従来のダイオードでは凹部内にカソード電極を形成しない。従って、基板裏面に選択的にカソード電極を形成する必要があるため、製造工程数が増える。また、凹部内でシリコンが露出しているが、シリコンと半田は合金化しない。従って、半田を用いたダイオードの実装時にオーミック不良が発生する。さらに、半田ボイドと濡れ性の不具合も発生する。   In the conventional diode, the cathode electrode is not formed in the recess. Therefore, it is necessary to selectively form the cathode electrode on the back surface of the substrate, increasing the number of manufacturing steps. Although silicon is exposed in the recess, silicon and solder are not alloyed. Therefore, an ohmic defect occurs when a diode using solder is mounted. In addition, solder voids and wettability defects also occur.

本発明は、上述のような課題を解決するためになされたもので、その目的は製造工程を簡略化し、破壊耐量と歩留まりを向上させることができる半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device capable of simplifying a manufacturing process and improving breakdown resistance and yield.

本発明に係る半導体装置は、活性領域と、前記活性領域よりも外側に配置された終端領域とを有する基板と、前記活性領域において前記基板の上面の一部に形成されたｐ＋型アノード層と、前記終端領域において前記基板の上面の一部に形成された複数のｐ＋型ガードリング層と、前記基板の下面に形成されたｎ＋型カソード層と、前記ｐ＋型アノード層に接続されたアノード電極と、前記ｎ＋型カソード層に接続された金属製のカソード電極とを備え、前記終端領域において前記ｎ＋型カソード層が掘り込まれて凹部が形成され、前記カソード電極は前記凹部内にも形成され、平面視において前記基板のコーナー部分のみに前記凹部が形成されていることを特徴とする。
A semiconductor device according to the present invention includes a substrate having an active region and a termination region disposed outside the active region, and a p + -type anode layer formed on a part of the upper surface of the substrate in the active region. A plurality of p + -type guard ring layers formed on a part of the upper surface of the substrate in the termination region, an n + -type cathode layer formed on the lower surface of the substrate, and the p + -type anode layer an anode electrode that is, the a n + -type cathode layer connected to the metal of the cathode electrode, the n + -type cathode layer is engraved recess in the termination region is formed, the cathode electrode is the It is also formed in a recess, and the recess is formed only in a corner portion of the substrate in plan view .

本発明により、製造工程を簡略化し、破壊耐量と歩留まりを向上させることができることができる。   According to the present invention, the manufacturing process can be simplified, and the breakdown tolerance and the yield can be improved.

本発明の実施の形態１に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. 比較例に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on a comparative example. 比較例に係る半導体装置のリカバリー波形を示す図である。It is a figure which shows the recovery waveform of the semiconductor device which concerns on a comparative example. 本発明の実施の形態１に係る半導体装置のリカバリー波形を示す図である。It is a figure which shows the recovery waveform of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る半導体装置を示す下面図である。It is a bottom view which shows the semiconductor device which concerns on Embodiment 4 of this invention.

本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。ｎ−型半導体基板１は、活性領域と、活性領域よりも外側に配置された終端領域とを有する。活性領域においてｎ−型半導体基板１（ドリフト層）の上面の一部にｐ＋型アノード層２が形成されている。Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. The n − type semiconductor substrate 1 has an active region and a termination region disposed outside the active region. A p + type anode layer 2 is formed on a part of the upper surface of the n − type semiconductor substrate 1 (drift layer) in the active region.

終端領域においてｎ−型半導体基板１の上面に、フローティングした複数のｐ＋型ガードリング層３が形成されている。この複数のｐ＋型ガードリング層３は、ｐ＋型アノード層２の端部から外側に向かって配置され、ｐ＋型アノード層２の端部の電界を弱める機能を有する。A plurality of floating p + -type guard ring layers 3 are formed on the upper surface of the n − -type semiconductor substrate 1 in the termination region. The plurality of p + -type guard ring layer 3 is disposed from the end portion of the p + -type anode layer 2 toward the outside has a function to weaken the electric field in the end portion of the p + -type anode layer 2.

ｎ−型半導体基板１の上面の最外周部にｎ＋型チャネルストッパ層４が形成されている。ｎ−型半導体基板１の下面に、ｎ−型半導体基板１よりも高い不純物濃度を持つｎ＋型カソード層５が形成されている。ｐ＋型アノード層２にアノード電極６が接続されている。ｎ＋型カソード層５にカソード電極７が接続されている。カソード電極７は半田との密着性がよいニッケルなどの金属製である。An n + type channel stopper layer 4 is formed on the outermost peripheral portion of the upper surface of the n − type semiconductor substrate 1. n - type on the lower surface of the semiconductor substrate 1, the n - type n + -type cathode layer 5 having a higher impurity concentration than the semiconductor substrate 1 is formed. An anode electrode 6 is connected to the p + type anode layer 2. A cathode electrode 7 is connected to the n + -type cathode layer 5. The cathode electrode 7 is made of a metal such as nickel having good adhesion to the solder.

本実施の形態の特徴として、終端領域においてｎ＋型カソード層５が掘り込まれて凹部８が形成されている。カソード電極７が凹部８内にも形成されている。即ち、カソード電極７は、活性領域ではｎ＋型カソード層５の下面に接触し、終端領域では凹部８内においてｎ−型半導体基板１の下面に接触している。As a feature of the present embodiment, the n + -type cathode layer 5 is dug in the terminal region to form the recess 8. A cathode electrode 7 is also formed in the recess 8. That is, the cathode electrode 7 is in contact with the lower surface of the n + -type cathode layer 5 in the active region, and is in contact with the lower surface of the n − -type semiconductor substrate 1 in the recess 8 in the termination region.

続いて本実施の形態の効果を比較例と比較して説明する。図２は比較例に係る半導体装置を示す断面図である。比較例には凹部８が設けられていない。比較例では、アノードから注入された正孔と、カソードから注入された電子が、活性領域だけでなく終端領域にも拡散することで、多数のキャリアが蓄積される。リカバリー動作時に活性領域と終端領域に蓄積されたキャリアの両方がｐ＋型アノード層２に流れ込む。このため、ｐ＋型アノード層２の端部は、リカバリー電流が集中して電界が高くなり、温度が上昇して破壊され易い。Next, the effect of this embodiment will be described in comparison with a comparative example. FIG. 2 is a cross-sectional view showing a semiconductor device according to a comparative example. In the comparative example, the recess 8 is not provided. In the comparative example, the holes injected from the anode and the electrons injected from the cathode are diffused not only in the active region but also in the termination region, so that a large number of carriers are accumulated. Both carriers accumulated in the active region and the termination region flow into the p + type anode layer 2 during the recovery operation. For this reason, the end portion of the p + -type anode layer 2 tends to be destroyed due to the concentration of the recovery current, the electric field being increased, and the temperature rising.

本実施の形態では終端領域においてｎ＋型カソード層５を掘り込むことで、順バイアス印加時にアノードから注入された正孔とカソードから注入された電子が、終端領域に蓄積されるのを抑制する。終端領域のｎ−型半導体基板１に蓄積されるキャリア量が低減されるので、リカバリー動作時にｐ＋型アノード層２の端部へのリカバリー電流の集中を緩和し、破壊耐量を向上することができる。In the present embodiment, the n + -type cathode layer 5 is dug in the termination region, thereby suppressing accumulation of holes injected from the anode and electrons injected from the cathode during forward bias application in the termination region. . Since the amount of carriers accumulated in the n − type semiconductor substrate 1 in the termination region is reduced, it is possible to alleviate the concentration of the recovery current at the end of the p + type anode layer 2 during the recovery operation and improve the breakdown tolerance. it can.

また、基板裏面の全面にカソード電極７を形成するため、凹部８に形成しないようにカソード電極７をパターニングする従来技術に比べて製造工程を簡略化できる。さらに、金属製のカソード電極７と半田は密着性が高いため、半田を用いた実装時にオーミック不良等を防いで歩留まりを向上させることができる。なお、凹部８においてカソード電極７に段差ができるが、ダイオードを製品フレームにダイボンドする際に１００μｍ厚程度の半田などが段差部分にも入り込むため、段差による不具合は生じない。   Further, since the cathode electrode 7 is formed on the entire back surface of the substrate, the manufacturing process can be simplified as compared with the conventional technique in which the cathode electrode 7 is patterned so as not to be formed in the recess 8. Furthermore, since the metal cathode electrode 7 and the solder have high adhesion, it is possible to prevent the ohmic defect and the like during mounting using the solder and improve the yield. Although there is a step in the cathode electrode 7 in the concave portion 8, when the diode is die-bonded to the product frame, solder having a thickness of about 100 μm also enters the step portion, so that there is no problem due to the step.

図３は比較例に係る半導体装置のリカバリー波形を示す図である。図４は本発明の実施の形態１に係る半導体装置のリカバリー波形を示す図である。本実施の形態では比較例に比べて最高温度が低いことが分かる。   FIG. 3 is a diagram illustrating a recovery waveform of the semiconductor device according to the comparative example. FIG. 4 is a diagram showing a recovery waveform of the semiconductor device according to the first embodiment of the present invention. It can be seen that the maximum temperature is lower in this embodiment than in the comparative example.

なお、本実施の形態では終端領域においてｎ＋型カソード層５が全て除去されているが、これに限らずｎ＋型カソード層５の一部のみが除去されていてもよい。ただし、ｎ＋型カソード層５の残し厚が少ないほど効果が増す。In the present embodiment, all of the n + -type cathode layer 5 is removed in the termination region. However, the present invention is not limited to this, and only a part of the n + -type cathode layer 5 may be removed. However, the effect increases as the remaining thickness of the n + -type cathode layer 5 decreases.

実施の形態２．
図５は、本発明の実施の形態２に係る半導体装置を示す断面図である。終端領域においてｎ＋型カソード層５だけでなく、ｎ−型半導体基板１の途中まで掘り込まれて凹部８が形成されている。これにより、終端領域においてｎ−型半導体基板１の体積が減少するため、蓄積されるキャリア量が更に低減され、更に破壊耐量を向上することができる。なお、凹部８が深いほど効果が上がるため、耐圧仕様によって凹部８の深さを調整する。Embodiment 2. FIG.
FIG. 5 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. In the termination region, not only the n + -type cathode layer 5 but also the n − -type semiconductor substrate 1 is dug into the middle to form a recess 8. Thereby, since the volume of the n − type semiconductor substrate 1 decreases in the termination region, the amount of accumulated carriers can be further reduced, and the breakdown tolerance can be further improved. In addition, since an effect goes up so that the recessed part 8 is deep, the depth of the recessed part 8 is adjusted with pressure | voltage resistant specification.

実施の形態３．
図６は、本発明の実施の形態３に係る半導体装置を示す断面図である。凹部８が終端領域だけでなく活性領域（ｐ＋型アノード層２の直下）の途中まで延びている。これにより、ｐ＋型アノード層２の端部に集中するリカバリー電流が更に減少するため、更に破壊耐量を向上することができる。なお、凹部８の幅が広いほど効果があるため、ＶＦ電特仕様によって凹部８の幅を調整する。Embodiment 3 FIG.
FIG. 6 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. The recess 8 extends not only to the termination region but also to the middle of the active region (directly below the p + -type anode layer 2). As a result, the recovery current concentrated at the end of the p + -type anode layer 2 is further reduced, so that the breakdown resistance can be further improved. In addition, since the effect is so large that the recessed part 8 is wide, the width | variety of the recessed part 8 is adjusted with VF electrical specification.

実施の形態４．
図７は、本発明の実施の形態４に係る半導体装置を示す下面図である。平面視において基板のコーナー部分のみに凹部８が形成されている。これにより、破壊が起こりやすいコーナー部の破壊とＶＦの上昇を効率的に抑制することができる。Embodiment 4 FIG.
FIG. 7 is a bottom view showing a semiconductor device according to Embodiment 4 of the present invention. Concave portions 8 are formed only in the corner portions of the substrate in plan view. Thereby, it is possible to efficiently suppress the breakage of the corner portion where the breakage easily occurs and the increase in VF.

なお、実施の形態１〜４では１２００［Ｖ］のＦＺ薄ウエハダイオードに本発明を適用した場合について説明したが、耐圧クラスに関わらず同様の効果を得ることができる。   In the first to fourth embodiments, the case where the present invention is applied to a 1200 [V] FZ thin wafer diode has been described. However, the same effect can be obtained regardless of the withstand voltage class.

また、実施の形態１〜４に係る半導体装置は珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成された半導体装置は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された装置を用いることで、この装置を組み込んだ半導体モジュールも小型化できる。また、装置の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。また、素子の電力損失が低く高効率であるため、半導体モジュールを高効率化できる。   The semiconductor devices according to the first to fourth embodiments are not limited to those formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A semiconductor device formed of such a wide band gap semiconductor has high voltage resistance and high allowable current density, and thus can be miniaturized. By using this miniaturized device, a semiconductor module incorporating this device can also be miniaturized. Moreover, since the heat resistance of the device is high, the heat dissipating fins of the heat sink can be reduced in size, and the water cooling part can be cooled in the air, so that the semiconductor module can be further reduced in size. Further, since the power loss of the element is low and the efficiency is high, the efficiency of the semiconductor module can be increased.

１ ｎ−型半導体基板（基板）、２ ｐ＋型アノード層、３ ｐ＋型ガードリング層、５ ｎ＋型カソード層、６ アノード電極、７ カソード電極、８ 凹部1 n − type semiconductor substrate (substrate), 2 p + type anode layer, 3 p + type guard ring layer, 5 n + type cathode layer, 6 anode electrode, 7 cathode electrode, 8 recess

Claims (3)

活性領域と、前記活性領域よりも外側に配置された終端領域とを有する基板と、
前記活性領域において前記基板の上面の一部に形成されたｐ＋型アノード層と、
前記終端領域において前記基板の上面の一部に形成された複数のｐ＋型ガードリング層と、
前記基板の下面に形成されたｎ＋型カソード層と、
前記ｐ＋型アノード層に接続されたアノード電極と、
前記ｎ＋型カソード層に接続された金属製のカソード電極とを備え、
前記終端領域において前記ｎ＋型カソード層が掘り込まれて凹部が形成され、
前記カソード電極は前記凹部内にも形成され、
平面視において前記基板のコーナー部分のみに前記凹部が形成されていることを特徴とする半導体装置。 A substrate having an active region and a termination region disposed outside the active region;
A p + -type anode layer formed on a part of the upper surface of the substrate in the active region;
A plurality of p + type guard ring layers formed on a part of the upper surface of the substrate in the termination region;
An n + type cathode layer formed on the lower surface of the substrate;
An anode electrode connected to the p + -type anode layer;
A metal cathode electrode connected to the n + type cathode layer,
In the termination region, the n + -type cathode layer is dug to form a recess,
The cathode electrode is also formed in the recess ,
A semiconductor device , wherein the recess is formed only in a corner portion of the substrate in plan view . 前記終端領域において前記ｎ＋型カソード層だけでなく、前記基板の途中まで掘り込まれて前記凹部が形成されていることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein not only the n + -type cathode layer but also the recess is formed in the termination region by digging partway through the substrate. 前記凹部は前記終端領域だけでなく前記活性領域の途中まで延びていることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the recess extends not only in the termination region but also in the middle of the active region.
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