JP6314905B2 - Power semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device such as a high breakdown voltage pn junction diode.

When the high-breakdown-voltage diode is in the recovery state in the process of rapidly changing from the ON state to the OFF state (in the recovery operation), the carriers accumulated in the diode are discharged from the P ⁺ -type anode layer all at once. P ⁺ -type anode layer portion of the carrier can be discharged directly to the anode electrode from the P ⁺ -type anode layer. However, since the carriers immediately below the FLR (Field Limiting Ring) region are not discharged from the FLR region, they are discharged from the P ⁺ -type anode layer. At that time, the carrier immediately below the FLR region in some cases leading to concentrate on the end portion of the P ⁺ -type anode layer, destruction increases the electric field at the end portion of the P ⁺ -type anode layer (outer peripheral portion).

Therefore, in the current high breakdown voltage diode, a high recovery breakdown resistance is realized by performing local lifetime control from the end of the P ⁺ type anode layer to the FLR region. Conventionally, since the P ⁺ type layer in the FLR region is formed deeper than the P ⁺ type anode layer (see, for example, Patent Document 1), both of them must be formed by different processes.

JP 2006-210667 A

  In a power semiconductor device such as a high breakdown voltage pn junction diode, the FLR region is large in order to maintain a breakdown voltage. As the withstand voltage class increases, the ratio of the FLR region to the chip effective area (anode portion) increases, and the processing of carriers immediately below the FLR region must be considered. The conventional local lifetime control can secure a high recovery breakdown tolerance, but in the manufacturing process, the reverse recovery safe operation area (RRSOA) varies greatly. For this reason, it is necessary to select the recovery tolerance of the power semiconductor device, and there is a problem that the cost is high and the variation in characteristics is increased.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a power semiconductor device capable of ensuring high recovery breakdown tolerance while suppressing cost and characteristic variation.

The power semiconductor device according to the present invention includes an N-type semiconductor substrate, a P ⁺ -type anode layer formed on the surface of the N-type semiconductor substrate, and a peripheral portion of the P ⁺ -type anode layer on the surface of the N-type semiconductor substrate. is said as P ⁺ -type anode layer is formed between the P ⁺ -type peripheral anode layer, an impurity concentration than the P ⁺ -type anode layer and formed P ⁺ -type peripheral anode layer, the surface of the N-type semiconductor substrate A low resistance and high resistance P ⁻ type high resistance layer is formed on the surface of the N type semiconductor substrate so as to surround the P ⁺ type anode layer, the P ⁺ type peripheral anode layer and the P ⁻ type high resistance layer. FLR (Field Limiting Ring) region having a plurality of ring-shaped P ⁺ -type layers spaced apart, an anode electrode connected to the P ⁺ -type anode layer, the P ⁺ -type peripheral anode layer, and the P ⁻ -type high resistance Layer and Serial and an insulating film formed between the anode electrode and the P ⁺ -type anode layer, the P ⁺ -type peripheral anode layer, and Ri the P ⁺ -type layer depth equal der of the FLR region, In the chip corner portion, the P ⁺ -type peripheral anode layer has a dot shape .

In the present invention, since local life lime control is not performed in the FLR region, cost and characteristic variations can be suppressed. Further, by forming the P ⁻ type high resistance layer and the P ⁺ type peripheral anode layer, the P ⁻ type high resistance layer exists between the anode electrode and the FLR region. Accordingly, the carriers immediately below the FLR region accumulated in the steady ON state are suppressed from flowing into the outer end portion of the P ⁺ -type peripheral anode layer during the recovery operation in the process of becoming the OFF state. For this reason, the heat generation at the outer end of the P ⁺ -type peripheral anode layer during the recovery operation is reduced, and the breakdown resistance is improved.

It is a top view which shows the high voltage | pressure-resistant pn junction diode which is a power semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in alignment with I-II of FIG. It is the figure which expanded the chip | corner corner part of FIG. It is a top view which shows the power semiconductor device which concerns on a comparative example. It is sectional drawing along I-II of FIG. It is a top view which shows the high voltage | pressure-resistant pn junction diode which is a power semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing along I-II of FIG. It is the figure which expanded the peripheral part structure of the anode layer in FIG. It is the figure which expanded the chip | corner corner part of the high voltage | pressure-resistant pn junction diode which is a power semiconductor device which concerns on Embodiment 5 of this invention. It is a top view which shows the high voltage | pressure-resistant pn junction diode which is a power semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing along I-II of FIG. It is the figure which expanded the chip | corner corner part of FIG.

  A power semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view showing a high voltage pn junction diode which is a power semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along the line I-II in FIG. FIG. 3 is an enlarged view of the chip corner portion of FIG.

A P ⁺ -type anode layer 2 a is formed at the center of the surface of the N-type semiconductor substrate 1. As a peripheral structure of the anode layer, a P ⁻ type high resistance layer 5 and a P ⁺ type peripheral anode layer 2 b are formed on the periphery (outer end) of the P ⁺ type anode layer 2 a on the surface of the N type semiconductor substrate 1. ing. The P ⁻ type high resistance layer 5 is formed between the P ⁺ type anode layer 2a and the P ⁺ type peripheral anode layer 2b. The P ⁺ -type peripheral anode layer 2b has the same impurity concentration as the P ⁺ -type anode layer 2a, whereas the P ⁻ -type high resistance layer 5 has a higher resistance value by making the impurity concentration lower than that of the P ⁺ -type anode layer 2a. doing. A plurality of ring-shaped Ps separated from each other so as to surround the P ⁺ type anode layer 2a and the peripheral structure (P ⁺ type peripheral anode layer 2b and P ⁻ type high resistance layer 5) on the surface of the N type semiconductor substrate 1 An FLR (Field Limiting Ring) region 3 having a ⁺ -type layer 4 is formed. The P ⁺ type anode layer 2a, the P ⁺ type peripheral anode layer 2b, and the P ⁺ type layer 4 in the FLR region 3 have the same depth.

An anode electrode 6 is formed on the anode layer and connected to the P ⁺ -type anode layer 2a. An insulating film 7 such as an oxide film is formed between the P ⁻ type high resistance layer 5, which is the peripheral part of the anode layer, and the anode electrode 6 immediately above the P ⁺ type peripheral anode layer 2 b. As a result, carriers in the P ⁺ -type peripheral anode layer 2b are not directly discharged to the anode electrode 6, but always pass through the P ⁻ -type high resistance layer 5 and the P ⁺ -type anode layer 2a. An N ⁺ type layer 8 is formed on the back surface of the N type semiconductor substrate 1. A cathode electrode 9 is connected to the N ⁺ type layer 8. The anode electrode 6 is made of Al or the like, and the cathode electrode 9 is made of Au or the like.

Subsequently, the effect of the present embodiment will be described in comparison with a comparative example. FIG. 4 is a plan view showing a power semiconductor device according to a comparative example. FIG. 5 is a cross-sectional view taken along the line I-II in FIG. In the comparative example, the P ⁻ type high resistance layer 5 and the P ⁺ type peripheral anode layer 2b, which are the peripheral structure of the anode layer, are not provided, and local life lime control (X portion in the figure) is performed in the FLR region 3. In the comparative example, since local lifetime control is performed, the cost increases and the variation in characteristics increases. On the other hand, in this embodiment, since local life lime control is not performed on the FLR region 3, it is possible to suppress cost and characteristic variations.

Further, in order to provide a higher breakdown voltage in the high breakdown voltage diode, it is necessary to make the FLR region 3 large, and the carriers accumulated immediately below the FLR region 3 during the recovery operation concentrate on the anode end. Therefore, in the present embodiment, the P ⁻ type high resistance layer 5 and the P ⁺ type peripheral anode layer 2b are formed at the peripheral portion of the P ⁺ type anode layer 2a, so that the FLR region 3 directly under the steady ON state is formed. Carrier flows into the outer end of the P ⁺ -type peripheral anode layer 2b during the recovery operation in the process of being turned off by the presence of the P ⁻ -type high resistance layer 5 between the anode electrode 6 and the carrier. Therefore, the heat generation at the outer end portion of the P ⁺ -type peripheral anode layer 2b during the recovery operation is reduced, and the breakdown resistance is improved.

Further, since the P ⁺ type anode layer 2a, the P ⁺ type peripheral anode layer 2b, and the P ⁺ type layer 4 in the FLR region 3 have the same impurity concentration and depth, they can be simultaneously formed in the same process. . The concentration of the P ⁻ type high resistance layer 5 can be adjusted by adjusting the distance between the P ⁺ type anode layer 2 a and the P ⁺ type peripheral anode layer 2 b during impurity implantation, that is, the mask width. .

Embodiment 2. FIG.
FIG. 6 is a plan view showing a high voltage pn junction diode which is a power semiconductor device according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line I-II in FIG. FIG. 8 is an enlarged view of the peripheral structure of the anode layer in FIG.

In the first embodiment, the peripheral structure of the anode layer consists of a pair of P ⁻ type high resistance layer 5 and a P ⁺ type peripheral anode layer 2b. In the second embodiment, the P ⁻ type high resistance layer 5 and P ^A plurality of sets (n sets) of ⁺ type peripheral anode layers 2b are arranged side by side. A plurality of diffusion layers including the P ⁻ type high resistance layer 5 and the P ⁺ type peripheral anode layer 2b are concentrically arranged on the entire outer periphery of the P ⁺ type anode layer 2a.

The relationship between the width a of the P ⁻ type high resistance layer 5 and the width b of the P ⁺ type peripheral anode layer 2b is 4a <b. Thereby, the P ⁻ type high resistance layer 5 that contributes to the improvement of the recovery breakdown tolerance can be formed. Note that the width a and the width b are derived based on the conditions shown in FIG. Therefore, in the same figure, the mask 50 at the time of impurity implantation which is not seen in the actual cross section is drawn with a broken line. Specifically, the width a corresponds to the width of a mask (resist or oxide film) used for impurity implantation in the N-type semiconductor substrate 1 to form the P ⁻ type high resistance layer 5, and the width b corresponds to the same mask. This corresponds to the interval between adjacent masks when there are a plurality of masks, that is, the opening width.

Embodiment 3 FIG.
In the third embodiment, the relationship between the width a of the P ⁻ type high resistance layer 5 and the depth c of the P ⁺ type anode layer 2a is a <c (the dimensional relationship in the second embodiment is not questioned). As a result, the P ⁻ type high resistance layer 5 is reliably formed between the P ⁺ type anode layer 2a and the P ⁺ type peripheral anode layer 2b, or between each of the plurality of P ⁺ type peripheral anode layers 2b. Therefore, electric field concentration can be reduced.

Embodiment 4 FIG.
In the fourth embodiment, the number n of the diffusion layers of the P ⁻ type high resistance layer 5 and the P ⁺ type peripheral anode layer 2b in the second embodiment is 7 or less (n ≦ 7). Thereby, an ideal P ⁻ type high resistance layer 5 that maximizes the recovery breakdown tolerance can be formed.

Embodiment 5. FIG.
FIG. 9 is an enlarged view of a chip corner portion of a high voltage pn junction diode which is a power semiconductor device according to the fifth embodiment of the present invention. The P ⁺ -type peripheral anode layer 2b is arranged in a dot shape at the chip corner portion. Thereby, the resistance in the chip corner portion where the electric field is higher than that in the straight portion becomes higher than that in the region other than the chip corner portion, so that the recovery breakdown resistance can be further improved.

Further, the P ⁺ -type peripheral anode layer 2b may be formed in a dot shape not only at the chip corner but also at the entire outer periphery of the chip. As a result, the resistance is increased on the entire outer periphery of the chip including the straight portion, so that the recovery breakdown resistance can be further improved.

Embodiment 6 FIG.
FIG. 10 is a plan view showing a high voltage pn junction diode which is a power semiconductor device according to Embodiment 6 of the present invention. FIG. 11 is a cross-sectional view taken along the line I-II in FIG. FIG. 12 is an enlarged view of the chip corner portion of FIG. Here, the structure of the P ⁺ -type anode layer 2a is the same as that of the second embodiment, but other structures may be used.

Here, the distance from the connection portion of the P ⁺ -type anode layer 2a and the anode electrode 6 in the linear portion other than the chip corner portion to the outer end portion of the P ⁺ -type anode layer 2a and the first distance d1 (see FIG. 2 ). A distance from the connection portion of the P ⁺ type anode layer 2a and the anode electrode 6 at the chip corner portion to the outer end portion of the P ⁺ type anode layer 2a is defined as a second distance d2 (see FIG. 11).

In the present embodiment, the second distance d2 is longer than the first distance d1. As a result, the concentration of heat generation at the chip corner portion is suppressed, and the recovery breakdown tolerance is improved. However, it is desirable that the second distance d2 is smaller than the curvature radius R of the P ⁺ -type anode layer 2a at the chip corner portion (d2 <R).

  In the first to sixth embodiments described above, the case of a high breakdown voltage pn junction diode has been described. However, the present invention is not limited to this and can be applied to other power semiconductor devices such as IGBTs and MOSFETs.

  The N-type semiconductor substrate 1 is not limited to being formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A power semiconductor element formed of such a wide band gap semiconductor can be miniaturized because of its high voltage resistance and allowable current density. By using this miniaturized element, a semiconductor module incorporating this element can also be miniaturized. Further, since the heat resistance of the element is high, the heat dissipating fins of the heat sink can be miniaturized and the water cooling part can be air cooled, so that the semiconductor module can be further miniaturized. In addition, since the power loss of the element is low and the efficiency is high, the efficiency of the semiconductor module can be increased.

1 N type semiconductor substrate, 2a P ⁺ type anode layer, 2b P ⁺ type peripheral anode layer, 3 FLR region, 4 P ⁺ type layer, 5 P ⁻ type high resistance layer, 6 anode electrode, 7 insulating film

Claims (7)

An N-type semiconductor substrate;
A P ⁺ type anode layer formed on the surface of the N type semiconductor substrate;
A P ⁺ -type peripheral anode layer formed on the periphery of the P ⁺ -type anode layer on the surface of the N-type semiconductor substrate;
A P ⁻ type high resistance layer formed between the P ⁺ type anode layer and the P ⁺ type peripheral anode layer on the surface of the N type semiconductor substrate and having a lower impurity concentration and higher resistance than the P ⁺ type anode layer;
A plurality of ring-shaped P ⁺ -type layers formed on the surface of the N-type semiconductor substrate so as to surround the P ⁺ -type anode layer, the P ⁺ -type peripheral anode layer, and the P ⁻ -type high-resistance layer are separated from each other. A FLR (Field Limiting Ring) region,
An anode electrode connected to the P ⁺ -type anode layer;
An insulating film formed between the P ⁺ type peripheral anode layer and the P ⁻ type high resistance layer and the anode electrode,
The P ⁺ -type anode layer, the P ⁺ -type peripheral anode layer, and Ri the P ⁺ -type layer depth equal der of the FLR region,
The power semiconductor device according to claim ¹ , wherein the P ⁺ -type peripheral anode layer has a dot shape at a chip corner portion .   An N-type semiconductor substrate;
  P formed on the surface of the N-type semiconductor substrate ⁺ A mold anode layer;
  On the surface of the N-type semiconductor substrate, the P ⁺ P formed on the periphery of the mold anode layer ⁺ A mold peripheral anode layer;
  On the surface of the N-type semiconductor substrate, the P ⁺ Type anode layer and P ⁺ Formed between the mold peripheral anode layers and the P ⁺ P with lower impurity concentration and higher resistance than type anode layer ⁻ Type high resistance layer,
  On the surface of the N-type semiconductor substrate, the P ⁺ Type anode layer, P ⁺ Mold peripheral anode layer and P ⁻ A plurality of ring-shaped Ps formed so as to surround the mold high resistance layer and spaced apart from each other ⁺ FLR (Field Limiting Ring) region having a mold layer;
  P ⁺ An anode electrode connected to the mold anode layer;
  P ⁺ Mold peripheral anode layer and P ⁻ An insulating film formed between the mold high resistance layer and the anode electrode,
  P ⁺ Type anode layer, P ⁺ Mold peripheral anode layer, and P in the FLR region ⁺ The mold layer has the same depth,
  P on the entire outer periphery of the chip ⁺ A power semiconductor device, wherein the mold peripheral anode layer is in the form of dots.   An N-type semiconductor substrate;
  P formed on the surface of the N-type semiconductor substrate ⁺ A mold anode layer;
  On the surface of the N-type semiconductor substrate, the P ⁺ P formed on the periphery of the mold anode layer ⁺ A mold peripheral anode layer;
  On the surface of the N-type semiconductor substrate, the P ⁺ Type anode layer and P ⁺ Formed between the mold peripheral anode layers and the P ⁺ P with lower impurity concentration and higher resistance than type anode layer ⁻ Type high resistance layer,
  On the surface of the N-type semiconductor substrate, the P ⁺ Type anode layer, P ⁺ Mold peripheral anode layer and P ⁻ A plurality of ring-shaped Ps formed so as to surround the mold high resistance layer and spaced apart from each other ⁺ FLR (Field Limiting Ring) region having a mold layer;
  P ⁺ An anode electrode connected to the mold anode layer;
  P ⁺ Mold peripheral anode layer and P ⁻ An insulating film formed between the mold high resistance layer and the anode electrode,
  P ⁺ Type anode layer, P ⁺ Mold peripheral anode layer, and P in the FLR region ⁺ The mold layer has the same depth,
  The P in the straight portion other than the chip corner portion ⁺ P from the connecting portion of the mold anode layer and the anode electrode ⁺ The distance to the outer end of the mold anode layer is the first distance,
  P at the tip corner ⁺ P from the connecting portion of the mold anode layer and the anode electrode ⁺ The distance to the outer edge of the mold anode layer is the second distance,
  The power semiconductor device, wherein the second distance is longer than the first distance.   The second distance is the P at the chip corner portion. ⁺ The power semiconductor device according to claim 3, wherein the power semiconductor device is smaller than a radius of curvature of the mold anode layer. A plurality of sets of the P ⁺ type peripheral anode layer and the P ⁻ type high resistance layer are arranged side by side,
The P ^- power according to any one of claims 1 to 4, the relationship between the width a of the type high-resistance layer and the width b of the P ⁺ -type peripheral anode layer is characterized in that it is a 4a <b Semiconductor apparatus. A plurality of sets of the P ⁺ type peripheral anode layer and the P ⁻ type high resistance layer are arranged side by side,
The P ^- power according to any one of claims 1 to 4, wherein the relationship between the depth c of the width a of the type high-resistance layer and the P ⁺ -type anode layer is a <c semiconductor apparatus. 7. The power semiconductor device according to claim 5 , wherein the number of sets of diffusion layers of the P ⁺ -type peripheral anode layer and the P ⁻ -type high-resistance layer is 7 or less.

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