JP6035038B2 - Semiconductor memory device, in-vehicle device, vehicle - Google Patents

Description

  The present invention relates to a semiconductor memory device, and an in-vehicle device and a vehicle using the same.

  Conventionally, EEPROM (electrically erasable programmable read only memory)) has been widely put into practical use as a nonvolatile semiconductor memory device.

  As an example of the related art related to the above, Patent Document 1 can be cited.

Japanese Patent Laid-Open No. 11-87660

  By the way, when reading data from a memory cell, the read / write circuit of the semiconductor memory device compares a read current Imem flowing through the memory cell with a predetermined reference current Iref and outputs an output data signal having a logic level according to the comparison result. DOUT is generated.

  More specifically, the output data signal DOUT has a logic level (for example, low level) corresponding to data “0” if the read current Imem is larger than the reference current Iref, and conversely, the read current Imem becomes the reference current Iref. If it is smaller than this, a logic level (for example, a high level) corresponding to data “1” is obtained (see the left side of FIG. 11).

  By the way, when reading data from a large capacity EEPROM at a high temperature, not only the read current Imem flows through the memory cell to be accessed, but also the parasitic leak current Ileak flows through the non-accessed memory cell connected thereto. If the parasitic leakage current Ileak is larger than the reference current Iref, the sum of the read current Imem and the parasitic leakage current Ileak always exceeds the reference current Iref regardless of the data content of the memory cell. 1 ") cannot be read correctly (see the right side of FIG. 11).

  Note that the parasitic leakage current Ileak tends to increase as the capacity of the EEPROM increases and the operating environment increases in temperature. For this reason, in-vehicle non-volatile memory ICs that require high-temperature operation guarantees and general-purpose non-volatile memory ICs that require large capacity, it is necessary to solve the above-described problems caused by the parasitic leakage current Ileak. It was.

  In view of the above-described problems found by the inventors of the present application, an object of the present invention is to provide a semiconductor memory device capable of improving data reading accuracy, and an in-vehicle device and a vehicle using the same. To do.

  In order to achieve the above object, a semiconductor memory device disclosed in this specification includes a memory bank including a plurality of memory cells and a read that flows to a memory cell to be accessed when data is read from the memory bank. A read / write circuit that compares an electric current with a predetermined reference current to generate an output data signal, and the read / write circuit stores a memory cell that is not an access target before reading data from the memory bank. A configuration (first configuration) is provided in which a parasitic leakage current that flows is detected and the reference current is variably controlled.

  In the semiconductor memory device having the first configuration, the read / write circuit is configured to precharge a precharge current to a bit line connected to the memory cell before the memory cell to be accessed is selected. A current generation unit; a reference current generation unit that detects the parasitic leakage current and performs variable control of the reference current before the memory cell to be accessed is selected; and the read current that flows through the memory cell to be accessed and variable control A configuration (second configuration) including a sense amplifier unit that generates the output data signal by comparing with the already-referenced current.

  In the semiconductor memory device having the second configuration, the reference current generation unit includes a constant current source that generates a constant first reference current, a variable current source that generates a variable second reference current, A sense resistor for detecting a current flowing through the bit line; a differential amplifier for amplifying a voltage across the sense resistor; and a current control unit for controlling the variable current source based on an output signal of the differential amplifier. In addition, a configuration (third configuration) that outputs the sum of the first reference current and the second reference current as the reference current may be used.

  In the semiconductor memory device having the third configuration, the current control unit includes an analog / digital converter that converts an output signal of the differential amplifier into a digital value, and a register that stores the digital value. And the variable current source may be configured to perform variable control of the second reference current based on the digital value stored in the register (fourth configuration).

  In the semiconductor memory device having the fourth configuration, the digital value stored in the register may be reset every time data is read from the memory cell to be accessed (fifth configuration). .

  In the semiconductor memory device having any one of the second to fifth configurations, the read / write circuit selects one of a plurality of bit lines provided in the memory bank and connects to the sense amplifier unit. A configuration (sixth configuration) may be included that further includes a multiplexer connected to the line.

  In the semiconductor memory device having the sixth configuration, the read / write circuit further includes a switch unit (seventh configuration) that conducts / cuts off between the sense amplifier unit and the data line. Good.

  In the semiconductor memory device having the seventh configuration, a plurality of the data lines are provided, and the sense amplifier section generates the output data signal for each of the plurality of data lines and outputs it in parallel. A configuration (eighth configuration) is preferable.

  In addition, the in-vehicle device disclosed in the present specification is a microcomputer that comprehensively controls the operation of the in-vehicle device, and the first used as a storage area or a work area for various programs executed by the microcomputer. A semiconductor storage device having any one of the eighth to eighth aspects, a controlled device controlled by the microcomputer, and a power supply unit that generates a power supply voltage from a battery supply voltage and supplies the power supply voltage to each unit of the in-vehicle device. The configuration is the ninth configuration.

  Further, the vehicle disclosed in the present specification has a configuration (tenth configuration) including an in-vehicle device having the ninth configuration and a battery for supplying electric power to the in-vehicle device.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor memory device which can improve a data reading precision, and the vehicle equipment and vehicle using this can be provided.

1 is a block diagram illustrating a configuration example of a semiconductor memory device The block diagram which shows schematic structure of the memory bank 11 and the read / write circuit 14 Circuit diagram showing one configuration example of the memory bank 11 Vertical sectional view showing the vertical structure of the memory cell MC Distribution diagram of threshold voltage Vth Circuit diagram showing one configuration example of the read / write circuit 14 Timing chart showing an example of read operation Diagram showing how conventional issues are resolved The block diagram which shows one structural example of the vehicle equipment which mounts the semiconductor memory device 10 External view showing a configuration example of a vehicle equipped with the in-vehicle device 1 Diagram showing how conventional issues occur

<Semiconductor memory device>
FIG. 1 is a block diagram illustrating a configuration example of a semiconductor memory device. The semiconductor memory device 10 of this configuration example includes a memory bank 11, a memory controller 12, a data register 13, a read / write circuit 14, an address register 15, an address decoder 16, a power supply voltage detector 17, a high voltage This is an SPI (serial peripheral interface) type serial EEPROM chip having a voltage generation unit 18.

  The memory bank 11 is an aggregate (for example, 1 to 32 k bits) of memory cells that are read / write controlled by the memory controller 12.

The memory controller 12 performs SPI serial data communication with a master (not shown) outside the apparatus, and performs read / write control of the memory bank 11 according to various commands given from the master. In addition, as a serial data communication system, instead of the 4-wire (CSB, SCK, SI, SO) SPI system, a 3-wire (CS, SK, DIO) microwire system or 2-wire (SDA, SCL) ) I ² C method or the like may be adopted.

  The data register 13 temporarily stores read data and write data of the memory bank 11 based on an instruction from the memory controller 12. More specifically, read data read from the memory bank 11 is temporarily stored in the data register 13 and then externally output from the data output terminal SO. On the other hand, write data externally input from the data input terminal SI is temporarily stored in the data register 13 and then written in the memory bank 11.

  The read / write circuit 14 includes a sense amplifier and a write voltage application circuit, and performs a read / write operation on the memory bank 11 based on an instruction from the memory controller 12. The present invention relates to a sense amplifier system for reading data mainly from the memory bank 11 among the circuit systems included in the read / write circuit 14.

  The address register 15 temporarily stores address data externally input from the data input terminal SI based on an instruction from the memory controller 12.

  The address decoder 16 reads the address data temporarily stored in the address register 15 based on an instruction from the memory controller 12 and drives the word lines and sense lines of the memory bank 11.

  The power supply voltage detector 17 detects whether or not the power supply voltage Vcc applied to the power supply terminal VCC exceeds a predetermined threshold voltage Vth, and outputs the detection result to the memory controller 12. Upon receiving this detection result, the memory controller 12 prohibits the write operation to the memory bank 11 while the power supply voltage Vcc is lower than the threshold voltage Vth, for example. By adopting such a configuration, it is possible to prevent erroneous writing to the memory bank 11 when power reduction is abnormal.

  The high voltage generator 18 generates a high voltage HV (> Vcc) from the power supply voltage Vcc based on an instruction from the memory controller 12, and supplies this to the read / write circuit 14 and the address decoder 16. As the high voltage generator 18, a charge pump circuit or the like can be used. The high voltage generator 18 is driven only during a write operation to the memory bank 11.

  Although not shown in FIG. 1, the semiconductor memory device 10 also incorporates a power-on reset unit that initializes the memory controller 12, the data register 13, and the address register 15 when the power is turned on.

<Memory bank and read / write circuit>
[Schematic configuration]
FIG. 2 is a block diagram showing a schematic configuration of the memory bank 11 and the read / write circuit 14. The memory bank 11 has x word lines WL1 to WLx and y sense lines SL1 to SLy, and is arbitrarily set for each of (xxy) addresses ADR (1, 1) to ADR (x, y). Data (1 byte (= 8 bits)) can be stored. When the microwire method is adopted as the serial data communication method, a configuration in which 2-byte data is stored in one address is the mainstream.

  The read / write circuit 14 is a sense amplifier system for reading data from the memory bank 11, and includes a precharge current generation unit 141, a reference current generation unit 142, a sense amplifier unit 143, a switch unit 144, and a multiplexer unit 145. And including. Although not shown in FIG. 2, the read / write circuit 14 includes a write voltage application circuit for writing data into the memory bank 11.

  The precharge current generator 141 supplies the precharge current Ipre to the bit line to which the memory cell is connected before the memory cell to be accessed is selected.

  The reference current generator 142 performs variable control of the reference current Iref by detecting the parasitic leakage current Ileak flowing in the memory cell that is not the access target before the access target memory cell is selected. This new feature will be described in detail later.

  The sense amplifier unit 143 generates an output data signal DOUT by comparing the read current Imeem flowing through the memory cell to be accessed with the variably controlled reference current Iref. The sense amplifier unit 143 generates the output data signals DOUT1 to DOUT4 for each of the four data lines DL1 to DL4 and outputs them in parallel. That is, the sense amplifier unit 143 can simultaneously read the upper or lower 4 bits of the data (1 byte (= 8 bits)) stored in the memory cell to be accessed.

  The switch unit 144 conducts / cuts off between the sense amplifier unit 143 and the data lines DL1 to DL4.

  The multiplexer unit 145 selects four of the bit lines BL1 to BLz (where z = 8 × y) provided in the memory bank 11 and connects them to the data lines DL1 to DL4 connected to the sense amplifier unit 143. . For example, when only the switch group 145 (1H) forming the multiplexer unit 145 is turned on and the other switch groups 145 (1L, 2H / 2L,..., YH / yL) are all turned off. , Bit lines BL1 to BL4 corresponding to the upper 4 bits of the address ADR (*, 1) (* = 1, 2,..., X) are connected to the data lines DL1 to DL4. When only the switch group 145 (1L) is turned on and the other switch groups 145 (1H, 2H / 2L,..., YH / yL) are all turned off, the address ADR (*, Bit lines BL5 to BL8 corresponding to the lower 4 bits of 1) are connected to the data lines DL1 to DL4.

[Memory Bank]
Next, the internal configuration of the memory bank 11 will be described in detail. FIG. 3 is a circuit diagram showing a configuration example of the memory bank 11. As shown in FIG. 3, a word line WL, a sense line SL, a bit line BL, and a common source line ASG are stretched around the memory bank 11, and these control lines include memory cell transistors MT and A plurality of memory cells MC composed of bit selection transistors ST are connected.

  The connection relationship will be described by paying attention to the memory cells MC1 to MC8 for 1 byte specified by the address ADR (1, 1). The drains of the bit selection transistors ST1 to ST8 are connected to the bit lines BL1 to BL8, respectively. The sources of the bit selection transistors ST1 to ST8 are connected to the drains of the memory cell transistors MT1 to MT8, respectively. The gates of the bit selection transistors ST1 to ST8 are all connected to the word line WL1. The sources of the memory cell transistors MT1 to MT8 are all connected to the common source line ASG. The common source line ASG is connected to the ground terminal via the common transistor CT. The gates (corresponding to the control line CL1) of the memory cell transistors MT1 to MT8 are all connected to the sense line SL1 via the byte selection transistor BT1. The gate of the byte selection transistor BT1 is connected to the word line WL1.

  FIG. 4 is a vertical sectional view showing the vertical structure of the memory cell MC. As described above, the memory cell MC includes the bit selection transistor ST and the memory cell transistor MT.

  The memory cell transistor MT has a structure having a floating gate (gate insulated from the surroundings) FG between a conduction channel in the silicon substrate sandwiched between the drain DM and the source SM and the control gate CG. Data is stored by utilizing the fact that the threshold voltage Vth of the memory cell transistor MT as viewed from the control gate CG changes according to the amount of charge accumulated in the floating gate FG.

  Note that a part of the insulator sandwiched between the floating gate FG and the drain DM of the memory cell transistor MT is thin, and electrons are injected into the floating gate FG by the tunnel effect through this part (tunnel insulating film). And release takes place.

  Then, by controlling the amount of charge accumulated in the floating gate FG of the memory cell transistor MT, the threshold voltage Vth of the memory cell transistor MT is distributed in two states as shown in FIG. By making “0” and “1” correspond to each other, 1-bit data is stored in one memory cell MC.

  For example, when data “1” is written in the memory cell MC1 (when data in the memory cell MC1 is erased), a high voltage HV (for example, 16 V) is applied to the word line WL1 and the sense line SL1 (control line CL1). Thus, the ground voltage is applied to the bit line BL1, and the common source line ASG is brought into the ground state. At this time, the bit selection transistor ST1 is turned on, and the high voltage HV is applied to the tunnel insulating film of the memory cell transistor MT1. Accordingly, electrons are injected into the floating gate FG, and the floating gate FG is in a state of accumulating electrons. At this time, the threshold voltage Vth of the memory cell transistor MT1 becomes higher than the read voltage VRD (eg, 1.2 V) in FIG. This state corresponds to a state where data “1” is written in the memory cell MC1 (a state where data in the memory cell MC1 is erased).

  On the other hand, when data “0” is written in the memory cell MC1, the high voltage HV is applied to the word line WL1 and the bit line BL1, the ground voltage is applied to the sense line SL1 (control line CL1), and the common source Line ASG is opened. At this time, the bit selection transistor ST1 is turned on, and the high voltage HV is applied to the tunnel insulating film of the memory cell transistor MT1. Accordingly, electrons are emitted from the floating gate FG, and the floating gate FG is in a state of being deficient in electrons. At this time, the threshold voltage Vth of the memory cell transistor MT1 is lower than the read voltage VRD of FIG. This state corresponds to a state where data “0” is written (a state where data “1” is erased).

  When data is read from the memory cell MC1, the read voltage VRD is applied to the sense line SL1 (control line CL1), the power supply voltage Vcc is applied to the word line WL1, and the ground voltage is applied to the common source line ASG. In this state, it may be determined whether or not a current flows through the bit line BL1 that is set to high impedance. If no current flows through the bit line BL1, it can be determined that the threshold voltage Vth of the memory cell transistor MT1 is higher than the read voltage VRD (that is, a state where data “1” is written). On the other hand, when a current flows through the bit line BL1, it can be determined that the threshold voltage Vth of the memory cell transistor MT1 is lower than the read voltage VRD (that is, a state where data “0” is written).

[Read / write circuit]
FIG. 6 is a circuit diagram showing an example of the configuration of the read / write circuit 14, and in particular, the components connected to the bit line BL1 and the data line DL1 are typically depicted. As described above, the read / write circuit 14 serves as a sense amplifier system for reading data from the memory bank 11 as a precharge current generation unit 141, a reference current generation unit 142, a sense amplifier unit 143, and a switch unit 144. And a multiplexer unit 145.

  The precharge current generator 141 includes a P-channel MOS [metal oxide semiconductor] field effect transistor 141a. The source and back gate of the transistor 141a are connected to the application terminal of the power supply voltage Vcc. The gate of the transistor 141a is connected to the application terminal of the precharge control signal PCHAB (low active). The drain of the transistor 141 a is connected to the input terminal of the sense amplifier unit 143. When the precharge control signal PCHAB is at a high level, the transistor 141a is turned off and the precharge current Ipre is stopped. Conversely, when the precharge control signal PCHAB is at a low level, the transistor 141a is turned on and the precharge current Ipre is supplied.

  The reference current generator 142 includes a constant current source 142a, a variable current source 142b, a sense resistor 142c, a differential amplifier 142d, an analog / digital converter 142e, and a register 142f.

The constant current source 142a generates a first reference current Iref1 (corresponding to a conventional reference current Iref) having a constant value. Based on the n-bit digital value (corresponding to the detected value of the parasitic leakage current Ileak) stored in the register 142f, the variable current source 142b is a variable value (2 ⁿ gradation value) second reference current Iref2 (parasitic leakage). (Corresponding to an offset current corresponding to the current Ileak). Note that the sum of the first reference current Iref1 and the second reference current Iref2 is the reference current Iref.

  The sense resistor 142c is inserted between the precharge current generation unit 141 and the switch unit 144. A current flowing from the data line DL1 to the bit line BL1 through the switch unit 144 and the multiplexer unit 145 is a voltage signal (a voltage between both ends). ) To detect.

  The differential amplifier 142d amplifies the voltage across the sense resistor 142c. A current detection control signal ADCEN is input to the differential amplifier 142d. When the current detection control signal ADCEN is at a high level, the differential amplifier 142d is enabled (operation permitted state), and when the current detection control signal ADCEN is at a low level, the differential amplifier 142d is disabled (operation disabled state). The

  The analog / digital converter 142e converts the output signal of the differential amplifier 142d into an n-bit digital value. A current detection control signal ADCEN is input to the analog / digital converter 142e. When the current detection control signal ADCEN is at a high level, the analog / digital converter 142e is enabled (operation permitted state), and when the current detection control signal ADCEN is at a low level, the analog / digital converter 142e is disabled (operation prohibited). State).

  The register 142f stores an n-bit digital value triggered by the rising edge of the register set signal NSET. The register 142f resets the n-bit digital value at the low level of the register reset signal NRSTB (low active).

  The analog / digital converter 142e and the register 142f form a current control unit that digitally controls the variable current source 142b based on the output signal of the differential amplifier 142d. With such a configuration, it is possible to finely variably control the second reference current Iref2. However, it is theoretically possible to analog-control the second reference current Iref2 based on the output signal of the differential amplifier 142d.

  The sense amplifier unit 143 includes a sense amplifier 143a for the data line DL1. The sense amplifier 143a compares the read current Imeem flowing through the memory cell to be accessed with a predetermined reference current Iref, and generates an output data signal DOUT1 having a logic level corresponding to the comparison result.

  Switch unit 144 includes N-channel MOS field effect transistors 144a and 144b and an inverter 144c. The drain of the transistor 144a is connected to the sense resistor 142. The source of the transistor 144 a is connected to the multiplexer unit 145. The gate of the transistor 144a is connected to the output terminal of the inverter 144c. An input end of the inverter 144c is connected to an application end of a sense amplifier enable signal SAENB (low active). The back gate of the transistor 144a is connected to the ground terminal. The drain of the transistor 144b is connected to the gate of the transistor 144a. The source and back gate of the transistor 144b are connected to the ground terminal. The gate of the transistor 144b is connected to the source of the transistor 144a. When the sense amplifier enable signal SAENB is at a high level, the transistor 144a is turned off, and the sense amplifier unit 143 and the data line DL1 are disconnected. On the other hand, when the sense amplifier enable signal SAENB is at a low level, the transistor 144a is turned on, and the sense amplifier unit 143 and the data line DL1 are conducted. Note that the transistor 144b functions as a clamp element for suppressing the upper limit potential of the data line DL1 to about 1V.

  The switch group 145 (1H) forming the multiplexer unit 145 includes an N-channel MOS field effect transistor 145a. The drain of the transistor 145a is connected to the data line DL1. The source of the transistor 145a is connected to the bit line BL1. The gate of the transistor 145a is connected to the application terminal of the multiplexer control signal YMUX (1H). The back gate of the transistor 145a is connected to the ground terminal. When the multiplexer control signal YMUX (1H) is at a high level, the transistor 145a is turned on, and the bit line BL1 and the data line DL1 are conducted. On the other hand, when the multiplexer control signal YMUX (1H) is at the low level, the transistor 145a is turned off, and the bit line BL1 and the data line DL1 are disconnected.

  The switch group 145 (1L) forming the multiplexer unit 145 includes an N-channel MOS field effect transistor 145b. The drain of the transistor 145b is connected to the data line DL1. The source of the transistor 145b is connected to the bit line BL5. The gate of the transistor 145b is connected to the application terminal of the multiplexer control signal YMUX (1L). The back gate of the transistor 145b is connected to the ground terminal. When the multiplexer control signal YMUX (1L) is at a high level, the transistor 145b is turned on, and the bit line BL5 and the data line DL1 are conducted. On the other hand, when the multiplexer control signal YMUX (1L) is at a low level, the transistor 145b is turned off, and the bit line BL5 and the data line DL1 are disconnected.

  FIG. 7 is a timing chart showing an example of a read operation by the read / write circuit 14 (when data is read from the memory cells MC1 to MC8 specified by the address ADR (1, 1)). SCK, sense amplifier enable signal SAENB, multiplexer control signals YMUX (1H) and YMUX (1L), word line signal WL1, precharge control signal PCHAB, current detection control signal ADCEN, register set signal NSET, and register reset signal NRSTB It is depicted. In FIG. 7, it is assumed that time elapses in the order of times t1 to t18.

  The clock signal SCK rises to a high level at times t1, t3,..., T17, and falls to a low level at times t2, t4,.

  The sense amplifier enable signal SAENB rises to a high level at times t1, t9, and t17, and falls to a low level at times t2, t10, and t18.

  The multiplexer control signal YMUX (1H) rises to a high level at time t3 and falls to a low level at time t10. The multiplexer control signal YMUX (1L) rises to a high level at time t11 and falls to a low level at time t18.

  The word line signal WL1 falls to a low level at times t2, t10, and t18, and rises to a high level at times t6 and t14. In FIG. 7, only the word line signal WL1 is shown as a representative, but the word line signals WL1 to WLx are in the order of WL1 → WL2 →... → WLx every time 8y pulses are generated in the clock signal SCK. The driving target is switched.

  The precharge control signal PCHAB falls to a low level at times t2, t10, and t18, and rises to a high level at times t7 and t15.

  The current detection control signal ADCEN rises to a high level at times t3 and t11, and falls to a low level at times t6 and t14.

  The register set signal NSET rises to a high level at times t5 and t13, and falls to a low level at times t6 and t14.

  The register reset signal NRST falls to a low level at times t1, t9, and t17, and rises to a high level at times t2, t10, and t18.

  The read operation of FIG. 7 will be specifically described. First, in the first step, the sense amplifier enable signal SAENB and the precharge control signal PCHAB are both lowered to a low level, the conduction between the sense amplifier unit 143 and the data line DL1, and the precharge current Ipre. Is started (time t2).

  Next, in the second step, the multiplexer control signal YMUX (1H) and the current detection control signal ADCEN are both raised to a high level, and the bit line BL1 and the data line DL1 are made conductive and differential. The amplifier 142d and the analog / digital converter 142e are enabled (operation permission state) (time t3). At this time, since all the memory cells connected to the bit line BL1 are not selected, the parasitic leak current Ileak flows through the bit line BL1. Therefore, the larger the parasitic leakage current Ileak, the larger the voltage drop at the sense resistor 142c, and the greater the digital value generated by the analog / digital converter 142e according to the output signal of the differential amplifier 142d. . Although the parasitic leakage current also flows through the bit lines (BL5, BL9,...) Separated from the data line DL1 by the multiplexer 145, the current value is very small compared to the parasitic leakage current flowing through the bit line BL1, As the parasitic leak current Ileak detected by the reference current generator 142, the one that flows in the bit line BL1 becomes dominant.

  Next, in the third step, the register set signal NSET is raised to a high level, and the digital value (parasitic leakage current information) output from the analog / digital converter 142e is stored in the register 142f (time t5). . Therefore, the variable current source 142b generates the second reference current Iref2 corresponding to the parasitic leakage current Ileak based on the digital value read from the register 142f. As a result, the current value of the reference current Iref is variably controlled so as to cancel the influence of the parasitic leakage current Ileak.

  Next, in the fourth step, the word line signal WL1 is raised to a high level, and the memory cell MC1 to be accessed is selected (time t6).

  Next, in the fifth step, the precharge control signal PCHAB is raised to a high level, and the supply of the precharge current Ipre is stopped (time t7). At this time, the sense amplifier 143a compares the read current Imeem flowing through the memory cell to be accessed with a predetermined reference current Iref, and generates an output data signal DOUT1 having a logic level corresponding to the comparison result. The output data signal DOUT1 is temporarily stored in the data register 13 and then externally output from the data output terminal SO.

  Next, in the sixth step, the register reset signal NRST falls to the low level, and the stored contents of the register 142f are reset (time t9).

  Thereafter, the data read operation from the memory bank 11 is repeated every time four pulses of the clock signal SCK are input. At this time, the process of reading the data from the memory bank 11 and storing it in the data register 13 and the process of reading the data from the data register 13 and serially outputting the data to the data output terminal SO are performed in parallel while shifting the respective timings. can do.

  For example, when data is read from the memory cells MC1 to MC8 specified by the address ADR (1, 1), the data for the upper 4 bits is read from the memory bank 11 during the period T1 (time t2 to t10). In the period T2 (time t10 to t18), the upper 4 bits of data are read from the data register 13 and serially output to the data output terminal SO. 4-bit data can be read and stored in the data register 13.

  As described above, the read / write circuit 14 of this configuration example is configured to perform variable control of the reference current Iref so as to compensate for the parasitic leakage current Ileak. With such a configuration, data can be read correctly even at high temperatures (see FIG. 8). In addition, the parasitic leakage current Ileak increases as the capacity of the memory bank 11 increases even at room temperature, but with the above configuration, data can be read correctly even if the capacity of the memory bank 11 increases. It becomes. Therefore, it is preferable to employ the above-described configuration particularly in a vehicle-mounted nonvolatile memory IC that requires a high-temperature operation guarantee or a general-purpose nonvolatile memory IC that requires a large capacity.

  In addition, if the reference current Iref is variably controlled so as to compensate for the parasitic leakage current Ileak, the sense amplifier unit 143 can be designed with a common specification without depending on the storage capacity, the operating temperature, and the like. .

  In the read operation of FIG. 7, the contents stored in the register 142f are updated every time data is read from the memory cell to be accessed, so that the parasitic leakage current Ileak is detected for each bit line and canceled. The reference current Iref can be variably controlled. However, the configuration of the present invention is not limited to this. For example, the parasitic leakage current Ileak is detected only when the semiconductor memory device 10 is activated for the first time, and the reference current Iref adjusted based on the detection result is fixed. However, it may be configured to supply automatically.

<In-vehicle equipment>
FIG. 9 is a block diagram illustrating a configuration example of an in-vehicle device in which the semiconductor memory device 10 is mounted. The in-vehicle device 1 of this configuration example includes a semiconductor storage device 10, a microcomputer 20, a display unit 30, a human interface unit 40, and a power supply unit 50.

  The semiconductor storage device 10 is one of controlled devices controlled by the microcomputer 20 and includes storage areas and work areas for various programs executed by the microcomputer 20 together with ROM [read only memory] and RAM [random access memory]. Used as

  The microcomputer 20 comprehensively controls the operation of the in-vehicle device 1.

  The display unit 30 is one of controlled devices controlled by the microcomputer 20 and outputs images, characters, and the like. As the display unit 30, a liquid crystal display panel or the like can be suitably used.

  The human interface unit 40 is one of controlled devices controlled by the microcomputer 20 and accepts user operations. As the human interface unit 40, keys, buttons, a touch panel, and the like can be suitably used.

  The power supply unit 50 DC / DC converts the supply voltage Vbat from the battery 2 to generate a plurality of internal power supply voltages (such as the power supply voltage Vcc), and supplies these to each part of the in-vehicle device 1.

<Vehicle>
FIG. 10 is an external view showing a configuration example of a vehicle on which the in-vehicle device 1 is mounted. The vehicle X of this configuration example includes onboard devices X11 to X17 and a battery (not shown in FIG. 10) that supplies power to these onboard devices X11 to X17.

  The in-vehicle device X11 is an engine control unit that performs control related to the engine (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto cruise control).

  The in-vehicle device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The in-vehicle device X13 is a transmission control unit that performs control related to the transmission.

  The in-vehicle device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power Steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The in-vehicle device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The in-vehicle device X16 is an electronic device incorporated in the vehicle X at the factory shipment stage as a standard equipment item or a manufacturer option product such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, and an air conditioner.

  The in-vehicle device X17 is an electronic device that is arbitrarily attached to the vehicle X by the user, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [Electronic Toll Collection System].

  The semiconductor memory device 10 described above can be incorporated in any of the in-vehicle devices X11 to X17.

<Other variations>
In the above embodiment, the configuration in which the present invention is applied to an in-vehicle nonvolatile memory IC that requires high-temperature operation guarantee has been described as an example. However, the scope of application of the present invention is not limited to this. However, the present invention can be widely applied to general-purpose nonvolatile memory ICs that require a large capacity.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is indicated not by the description of the above-described embodiment but by the scope of the claims. It should be understood that all modifications that fall within the meaning and range equivalent to the terms of the claims are included.

  INDUSTRIAL APPLICABILITY The present invention is suitably used as a technique for improving the data reading accuracy of, for example, a vehicle-mounted nonvolatile memory IC that requires a high-temperature operation guarantee or a general-purpose nonvolatile memory IC that requires a large capacity. It is possible.

DESCRIPTION OF SYMBOLS 1 In-vehicle apparatus 2 Battery 10 Semiconductor memory device 11 Memory bank 12 Memory controller 13 Data register 14 Read / write circuit 141 Precharge current generation part 141a P channel type MOS field effect transistor 142 Reference current generation part 142a Constant current source 142b Variable current source 142c sense resistor 142d differential amplifier 142e analog / digital converter 142f register 143 sense amplifier unit 143a sense amplifier 144 switch unit 144a, 144b N-channel MOS field effect transistor 144c inverter 145 (1H / 1L, 2H / 2L,..., YH / YL) Multiplexer section 145a, 145b N-channel MOS field effect transistor 15 Address register 16 Address decoder 17 Power supply voltage detection Part 18 high voltage generator 20 the microcomputer 30 display unit 40 human interface unit 50 power supply unit VCC power supply terminal SCK clock terminal CSB chip select terminal (low active)
SI data input terminal SO data output terminal GND ground terminal WL word line CL control line SL sense line BL bit line ASG common source line MC memory cell ST bit selection transistor MT memory cell transistor BT byte selection transistor CT common transistor DS, DM drain SS , SM source G gate CG control gate FG floating gate X vehicle X11-X17 in-vehicle equipment

Claims (8)

A memory bank including a plurality of memory cells;
A read / write circuit for generating an output data signal by comparing a read current flowing through a memory cell to be accessed with a predetermined reference current when reading data from the memory bank;
Have
The read / write circuit performs a variable control of the reference current by detecting a parasitic leak current flowing in a memory cell that is not an access target before reading data from the memory bank .
The read / write circuit is
A precharge current generator for supplying a precharge current to a bit line to which the memory cell is connected before the memory cell to be accessed is selected;
A reference current generation unit that performs detection of the parasitic leakage current and variable control of the reference current before a memory cell to be accessed is selected;
A sense amplifier that generates the output data signal by comparing the read current flowing through the memory cell to be accessed and the reference current that has been variably controlled;
Including
The reference current generator is
A constant current source for generating a constant first reference current;
A variable current source for generating a variable value second reference current;
A sense resistor for detecting a current flowing in the bit line;
A differential amplifier that amplifies the voltage across the sense resistor;
A current control unit for controlling the variable current source based on an output signal of the differential amplifier;
A sum of the first reference current and the second reference current is output as the reference current.
A semiconductor memory device. The current controller is
An analog / digital converter that converts the output signal of the differential amplifier into a digital value;
A register for storing the digital value;
Including
The semiconductor memory device according to claim 1 , wherein the variable current source performs variable control of the second reference current based on the digital value stored in the register. 3. The semiconductor memory device according to claim 2 , wherein the stored contents of the register are reset every time data is read from a memory cell to be accessed. The read / write circuit according to claim 1 claims, characterized in that by selecting one of a plurality provided bit line to the memory banks further comprising a multiplexer connected to the data lines connected to the sense amplifier unit 4. The semiconductor memory device according to any one of 3 . 5. The semiconductor memory device according to claim 4 , wherein the read / write circuit further includes a switch unit that conducts / cuts off between the sense amplifier unit and the data line. A plurality of the data lines are provided,
The semiconductor memory device according to claim 5 , wherein the sense amplifier unit generates the output data signal for each of the plurality of data lines and outputs the output data signal in parallel. A microcomputer that comprehensively controls the operation of in-vehicle devices;
The semiconductor memory device according to any one of claims 1 to 6 which is used as a storage area or a working area for various programs executed by the microcomputer,
Controlled devices controlled by the microcomputer;
A power supply unit that generates a power supply voltage from a supply voltage of the battery and supplies the power supply unit to each part of the in-vehicle device; and
An in-vehicle device characterized by comprising: In-vehicle device according to claim 7 ,
A battery for supplying power to the in-vehicle device;
The vehicle characterized by having.

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