JP6064586B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As semiconductor devices (semiconductor devices, semiconductor elements), gallium nitride (GaN) -based semiconductor devices are known. A GaN-based semiconductor device includes an N-type semiconductor layer and a P-type semiconductor layer mainly made of GaN. The GaN-based N-type semiconductor layer contains silicon (Si) as a donor (dopant, impurity), and the GaN-based P-type semiconductor layer contains magnesium (Mg) as an acceptor (dopant, impurity).

  In general, an electrode (ohmic electrode) formed on a semiconductor layer of a semiconductor device is required to suppress contact resistance (contact resistance) while ensuring adhesion to the semiconductor layer. As the GaN-based N-type semiconductor layer, an electrode in which a layer made of aluminum (Al) is stacked on a layer made of titanium (Ti) is used (see, for example, Patent Document 1). Is an electrode in which a layer made of gold (Au) is laminated on a layer made of nickel (Ni) (see, for example, Patent Document 2).

JP 7-45867 A JP-A-9-64337

  In the GaN-based semiconductor devices in Patent Documents 1 and 2, the materials, structures, and processing conditions during manufacture of the electrodes used for the N-type semiconductor layer and the P-type semiconductor layer are different, resulting in a complicated manufacturing process. There is a problem that the cost increases. Further, in the GaN-based semiconductor devices disclosed in Patent Documents 1 and 2, overlay accuracy is ensured between photolithography for forming electrodes on the N-type semiconductor layer and photolithography for forming electrodes on the P-type semiconductor layer. Therefore, there is a problem that it is difficult to miniaturize the semiconductor device.

  For this reason, there has been a demand for a technique capable of sharing electrodes in an N-type semiconductor layer and a P-type semiconductor layer in a GaN-based semiconductor device. In addition, for semiconductor devices, there have been demands for cost reduction, miniaturization, ease of manufacture, resource saving, improved usability, and improved durability.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.
One embodiment of the present invention provides a semiconductor device. The semiconductor device includes a P-type semiconductor layer mainly made of gallium nitride (GaN); an N-type semiconductor layer mainly made of gallium nitride (GaN); a first electrode formed on the P-type semiconductor layer; A second electrode formed on the N-type semiconductor layer. The first and second electrodes include: a first component that is at least one of palladium (Pd), platinum (Pt), and nickel (Ni); a second component that is titanium (Ti); aluminum ( A depth T1 at which the distribution ratio of the first component becomes a maximum value P1 in the depth direction from the surface of the first and second electrodes toward the inside; The depth T2 at which the distribution ratio of the second component is the maximum value P2 in the depth direction is deeper than the depth T3 at which the distribution ratio of the third component is the maximum value P3 in the depth direction. The depth T1 is at a position deeper than the depth T2 in the depth direction; the maximum value P1 is higher than the distribution ratio of the second component at the depth T1, and Said first at depth T1 Lower than the distribution ratio of the components of the.
The present invention can also be realized as the following forms.

(1) According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a P-type semiconductor layer mainly made of gallium nitride (GaN); an N-type semiconductor layer mainly made of gallium nitride (GaN); and at least one of the P-type semiconductor layer and the N-type semiconductor layer. A first component that is at least one of palladium (Pd), platinum (Pt), and nickel (Ni); and a second component that is titanium (Ti); A depth T1 mainly composed of a third component that is aluminum (Al), and a distribution ratio of the first component is a maximum value P1 in a depth direction from the surface of the electrode toward the inside; The depth T2 at which the distribution ratio of the second component is the maximum value P2 in the depth direction is deeper than the depth T3 at which the distribution ratio of the third component is the maximum value P3 in the depth direction. Maximum value 1, along with higher distribution ratio of the second component in the depth T1, lower than the distribution ratio of the third component in the depth T1. According to the semiconductor device of this aspect, the contact resistance of the electrode with respect to each of the P-type semiconductor layer and the N-type semiconductor layer can be suppressed. Therefore, it is possible to make the electrodes common to the N-type semiconductor layer and the P-type semiconductor layer. Therefore, the number of steps for forming electrodes on the P-type semiconductor layer and the N-type semiconductor layer can be reduced, and as a result, the cost of the semiconductor device can be reduced.

(2) In the semiconductor device of the above aspect, the maximum value P2 may be higher than the distribution ratio of the first component at the depth T2 and lower than the distribution ratio of the third component at the depth T2. Good. According to the semiconductor device of this embodiment, the contact resistance of the electrode with respect to each of the P-type semiconductor layer and the N-type semiconductor layer can be sufficiently suppressed.

(3) In the semiconductor device of the above aspect, the relationship among the maximum value P1, the maximum value P2, and the maximum value P3 may satisfy P1 <P2 <P3. According to the semiconductor device of this embodiment, the contact resistance of the electrode with respect to each of the P-type semiconductor layer and the N-type semiconductor layer can be sufficiently suppressed.

(4) In the semiconductor device of the above aspect, the electrodes may be integrally formed from the P-type semiconductor layer to the N-type semiconductor layer. According to the semiconductor device of this aspect, it is possible to suppress the contact resistance of the electrodes formed integrally from the P-type semiconductor layer to the N-type semiconductor layer with respect to each semiconductor layer. Further, compared with the case where electrodes are individually formed on each of the P-type semiconductor layer and the N-type semiconductor layer, the overlay accuracy of photolithography can be relaxed, and as a result, the semiconductor device can be miniaturized. Can do.

(5) In the semiconductor device of the above aspect, the electrode is integrated from the first interface in the P-type semiconductor layer to the second interface having a step between the first interface in the N-type semiconductor layer. It may be formed automatically. According to the semiconductor device of this aspect, it is possible to suppress the contact resistance of the electrodes formed integrally from the P-type semiconductor layer over the N-type semiconductor layer across the step to each semiconductor layer. Further, compared with the case where electrodes are individually formed on each of the P-type semiconductor layer and the N-type semiconductor layer, the overlay accuracy of photolithography can be relaxed, and as a result, the semiconductor device can be miniaturized. Can do.

(6) According to one form of this invention, the manufacturing method of a semiconductor device which manufactures a semiconductor device provided with a P-type semiconductor layer and an N-type semiconductor layer is provided. The semiconductor device manufacturing method includes: (a) forming the P-type semiconductor layer and the N-type semiconductor layer mainly made of gallium nitride (GaN); and (b) the P-type semiconductor layer and the N-type semiconductor. Forming an electrode on at least one of the layers, wherein the step (b) includes (b1) a first metal layer made of at least one of palladium (Pd), platinum (Pt), and nickel (Ni). (B2) laminating a second metal layer made of titanium (Ti) on the first metal layer; and (b2) forming a layer on at least one of the P-type semiconductor layer and the N-type semiconductor layer; b3) a step of laminating a third metal layer made of aluminum (Al) on the second metal layer; and (b4) using an atmospheric gas mainly composed of nitrogen (N ₂ ) at 450 to 550 ° C., Said first metal layer, front By firing the second metal layer and the third metal layer, and forming the electrode. According to the method for manufacturing a semiconductor device of this aspect, the contact resistance of the electrode with respect to each of the P-type semiconductor layer and the N-type semiconductor layer can be suppressed. Therefore, it is possible to make the electrodes common to the N-type semiconductor layer and the P-type semiconductor layer. Therefore, the number of steps for forming electrodes on the P-type semiconductor layer and the N-type semiconductor layer can be reduced, and as a result, the cost of the semiconductor device can be reduced.

(7) In the method of manufacturing a semiconductor device according to the above aspect, the step (b1) is a step of forming the first metal layer with a thickness of 5 to 100 nm, and the step (b2) The second metal layer may be formed to a thickness of 5 to 50 nm, and the step (b3) may be a step of forming the third metal layer to a thickness of 100 nm or more. According to the method for manufacturing a semiconductor device of this embodiment, the contact resistance of the electrode with respect to each of the P-type semiconductor layer and the N-type semiconductor layer can be sufficiently suppressed.

(8) In the method of manufacturing a semiconductor device according to the above aspect, the step (b) may be a step of integrally forming the electrodes from the P-type semiconductor layer to the N-type semiconductor layer. According to the method for manufacturing a semiconductor device of this aspect, it is possible to suppress the contact resistance of each electrode formed integrally from the P-type semiconductor layer to the N-type semiconductor layer. Further, compared with the case where electrodes are individually formed on each of the P-type semiconductor layer and the N-type semiconductor layer, the overlay accuracy of photolithography can be relaxed, and as a result, the semiconductor device can be miniaturized. Can do.

(9) In the method for manufacturing a semiconductor device according to the above aspect, the step (b) has a step between the first interface in the P-type semiconductor layer and the first interface in the N-type semiconductor layer. It may be a step of integrally forming the electrodes over the second interface. According to the method for manufacturing a semiconductor device of this aspect, it is possible to suppress the contact resistance of the electrodes formed integrally over the N-type semiconductor layer across the step from the P-type semiconductor layer to each semiconductor layer. Further, compared with the case where electrodes are individually formed on each of the P-type semiconductor layer and the N-type semiconductor layer, the overlay accuracy of photolithography can be relaxed, and as a result, the semiconductor device can be miniaturized. Can do.

(10) According to one aspect of the present invention, there is provided a semiconductor device manufactured using the semiconductor device manufacturing method of the above aspect. According to the semiconductor device of this aspect, the contact resistance of the electrode with respect to each of the P-type semiconductor layer and the N-type semiconductor layer can be suppressed.

  The present invention can be realized in various forms other than the semiconductor device and the manufacturing method thereof. For example, it can be realized in the form of an electric device including the semiconductor device of the above form, an apparatus for manufacturing the semiconductor device of the above form, or the like.

  According to this invention, the contact resistance of the electrode with respect to each layer of a P-type semiconductor layer and an N-type semiconductor layer can be suppressed. Therefore, it is possible to make the electrodes common to the N-type semiconductor layer and the P-type semiconductor layer. Therefore, the number of steps for forming electrodes on the P-type semiconductor layer and the N-type semiconductor layer can be reduced, and as a result, the cost of the semiconductor device can be reduced.

It is sectional drawing which shows typically the structure of the semiconductor device in 1st Embodiment. It is process drawing which shows the manufacturing method of a semiconductor device. It is a graph which shows the result of having evaluated the influence which heat processing temperature has on contact resistance of an electrode. It is a graph which shows the result of having evaluated the influence which each layer thickness of palladium and titanium in an electrode has on contact resistance. It is sectional drawing which shows typically the structure of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 3rd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 4th Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device in 5th Embodiment. It is a graph which shows the distribution ratio of the component which comprises an electrode. It is a graph which shows the distribution ratio of the component which comprises the electrode in a 1st modification. It is a graph which shows the distribution ratio of the component which comprises the electrode in a 2nd modification.

A. First embodiment:
A1. Semiconductor device configuration:
FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device 10 in the first embodiment. The semiconductor device 10 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 10 is used for power control and is also called a power device or a high-frequency device.

  The semiconductor device 10 includes a substrate 110, a first N-type semiconductor layer 120, a P-type semiconductor layer 130, and a second N-type semiconductor layer 140. The semiconductor device 10 is an NPN-type semiconductor device, and has a structure in which a first N-type semiconductor layer 120, a P-type semiconductor layer 130, and a second N-type semiconductor layer 140 are sequentially joined.

  The substrate 110 of the semiconductor device 10 is formed on the first N-type semiconductor layer 120, the P-type semiconductor layer 130, and the first layer by crystal growth using a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus. Two N-type semiconductor layers 140 are sequentially stacked.

  FIG. 1 shows XYZ axes orthogonal to each other. Of the XYZ axes in FIG. 1, the X axis is an axis along the stacking direction in which the first N-type semiconductor layer 120 is stacked on the substrate 110. Among the X-axis directions along the X-axis, the + X-axis direction is a direction from the substrate 110 toward the first N-type semiconductor layer 120, and the −X-axis direction is a direction facing the + X-axis direction. Among the XYZ axes in FIG. 1, the Y axis and the Z axis are axes that are orthogonal to the X axis and orthogonal to each other. Among the Y-axis directions along the Y-axis, the + Y-axis direction is a direction from the left side to the right side in FIG. 1, and the −Y-axis direction is a direction facing the + Y-axis direction. Among the Z-axis directions along the Z-axis, the + Z-axis direction is a direction from the front side of the paper in FIG. 1 toward the back of the paper surface, and the −Z-axis direction is a direction facing the + Z-axis direction.

  The substrate 110 of the semiconductor device 10 has a plate shape extending along the Y axis and the Z axis. In the present embodiment, the substrate 110 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor at a higher concentration than the first N-type semiconductor layer 120.

  The substrate 110 has an interface 111 and an interface 112. The interface 111 of the substrate 110 is a surface parallel to the Y axis and the Z axis and facing the −X axis direction. The interface 112 of the substrate 110 is a surface parallel to the Y axis and the Z axis and facing the + X axis direction, and faces away from the interface 111. The interface 112 is adjacent to the first N-type semiconductor layer 120.

  In the present embodiment, an electrode 210, also called a drain electrode, is formed on the interface 111 of the substrate 110. In the present embodiment, the electrode 210 is an electrode in which a layer made of aluminum (Al) is laminated on a layer made of titanium (Ti).

  The thickness of the substrate 110 is a distance along the X-axis direction between the interface 111 and the interface 112, and is 320 μm (micrometers) in the present embodiment. In another embodiment, the thickness of the substrate 110 may be another value selected from the range of 10 μm to 10 mm (millimeters), or may be a value outside this range.

The first N-type semiconductor layer 120 in the semiconductor device 10 is formed in a state of being stacked on the substrate 110 and forms a layer extending along the Y axis and the Z axis. The first N-type semiconductor layer 120 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor. The first N-type semiconductor layer 120 is also referred to as “n ⁻ -GaN”.

  The first N-type semiconductor layer 120 has an interface 121 and an interface 122. The interface 121 in the first N-type semiconductor layer 120 is a surface parallel to the Y-axis and the Z-axis and facing the −X-axis direction. The interface 121 is adjacent to the substrate 110. The interface 122 in the first N-type semiconductor layer 120 is a surface parallel to the Y axis and the Z axis and facing the + X axis direction, and faces away from the interface 121. The interface 122 is adjacent to the P-type semiconductor layer 130.

  The thickness of the first N-type semiconductor layer 120 is a distance along the X-axis direction between the interface 121 and the interface 122, and is 10 μm in this embodiment. In other embodiments, the thickness of the first N-type semiconductor layer 120 may be another value selected from the range of 5 to 15 μm, or may be a value outside this range.

  The P-type semiconductor layer 130 of the semiconductor device 10 is formed in a state of being stacked on the first N-type semiconductor layer 120, and forms a layer extending along the Y axis and the Z axis. The P-type semiconductor layer 130 is mainly made of gallium nitride (GaN) and contains magnesium (Mg) as an acceptor. The P-type semiconductor layer 130 is also called “p-GaN”.

  The P-type semiconductor layer 130 has an interface 131 and an interface 132. The interface 131 of the P-type semiconductor layer 130 is a surface parallel to the Y axis and the Z axis and facing the −X axis direction. The interface 131 is adjacent to the first N-type semiconductor layer 120. The interface 132 of the P-type semiconductor layer 130 is a surface parallel to the Y axis and the Z axis and facing the + X axis direction, and faces away from the interface 131. A portion between the portion adjacent to the second N-type semiconductor layer 140 and the portion not adjacent to the second N-type semiconductor layer 140 at the interface 132 may be flat or stepped.

  In the present embodiment, an electrode 230, also called a P body electrode, is formed on the interface 132 of the P-type semiconductor layer 130 on the + Y-axis direction side of the second N-type semiconductor layer 140. Details of the electrode 230 will be described later.

  The thickness of the P-type semiconductor layer 130 is a distance along the X-axis direction between the interface 131 and the interface 132, and is 1 μm in this embodiment. In other embodiments, the thickness of the P-type semiconductor layer 130 may be another value selected from the range of 0.3 to 2 μm, or may be a value outside this range.

The second N-type semiconductor layer 140 in the semiconductor device 10 is formed in a state of being stacked on the P-type semiconductor layer 130, and forms a layer extending along the Y axis and the Z axis. The second N-type semiconductor layer 140 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor at a higher concentration than the first N-type semiconductor layer 120. The second N-type semiconductor layer 140 is also called “n ⁺ -GaN”.

  The second N-type semiconductor layer 140 has an interface 141, an interface 142, and an interface 143. The interface 141 in the second N-type semiconductor layer 140 is a surface parallel to the Y-axis and the Z-axis and facing the −X-axis direction. The interface 141 is adjacent to the P-type semiconductor layer 130. The interface 142 in the second N-type semiconductor layer 140 is a surface parallel to the Y axis and the Z axis and facing the + X axis direction, and faces away from the interface 141. The interface 143 in the second N-type semiconductor layer 140 is a surface parallel to the X axis and the Z axis and facing the + Y axis direction. The interface 143 is a surface that connects the interface 132 of the P-type semiconductor layer 130 and the interface 142 of the second N-type semiconductor layer 140. The interface 142 in the second N-type semiconductor layer 140 is a second interface having a step corresponding to the interface 143 with the interface 132 that is the first interface in the P-type semiconductor layer 130.

  In the present embodiment, an electrode 240 also called a source electrode is formed at the interface 142 of the second N-type semiconductor layer 140. Details of the electrode 240 will be described later.

  The thickness of the second N-type semiconductor layer 140 is a distance along the X-axis direction between the interface 141 and the interface 142, and is 0.2 μm in this embodiment. In another embodiment, the thickness of the second N-type semiconductor layer 140 may be another value selected from the range of 0.1 to 0.5 μm, and is a value outside this range. Also good.

In the present embodiment, an insulating film 330 is formed over each surface of the first N-type semiconductor layer 120 and the P-type semiconductor layer 130, and the first N-type semiconductor layer 120, the P-type semiconductor layer 130, and the second N-type semiconductor layer 130 are formed. An insulating film 340 is formed over each surface of the mold semiconductor layer 140. In the present embodiment, the insulating films 330 and 340 are layers made of silicon dioxide (SiO ₂ ).

  In this embodiment, the electrode 250, also called a gate electrode, sandwiches the insulating film 340 across the surfaces of the first N-type semiconductor layer 120, the P-type semiconductor layer 130, and the second N-type semiconductor layer 140. It is formed with. In the present embodiment, the electrode 250 is an electrode mainly made of aluminum (Al).

A2. Detailed electrode configuration:
The electrode 230 of the semiconductor device 10 includes, in order with respect to the interface 132 of the P-type semiconductor layer 130, a first metal layer made of palladium (Pd), a second metal layer made of titanium (Ti), and aluminum ( A third metal layer made of Al) is laminated, and then fired using an atmospheric gas mainly made of nitrogen (N ₂ ). In the present embodiment, the thickness of the first metal layer is 20 nm (nanometers), the thickness of the second metal layer is 35 nm, and the thickness of the third metal layer is 300 nm. In this embodiment, the temperature of the atmospheric gas for firing the electrode 230 is 500 ° C., and the time for firing the electrode 230 is 5 minutes.

  The electrode 230 is mainly composed of palladium (Pd) as the first component, titanium (Ti) as the second component, and aluminum (Al) as the third component. The depth direction from the surface of the electrode 230 toward the inside is the −X axis direction of FIG. 1. The electrode 240 of the semiconductor device 10 is the same as the electrode 230 except that the electrode 240 is formed with respect to the interface 142 of the second N-type semiconductor layer 140.

FIG. 9 is a graph showing the distribution ratio of components constituting the electrode 230. The vertical axis in the graph of FIG. 9 indicates the abundance ratio of elements. The horizontal axis in the graph of FIG. 9 indicates the sputter depth obtained by converting the depth from the surface of the electrode 230 into the etching rate of silicon oxide (SiO ₂ ). The position where the value of the horizontal axis in the graph of FIG. 9 indicates 0 corresponds to the surface of the electrode 230. Each component of gallium (Ga) and nitrogen (N) in FIG. 9 is a component derived from the P-type semiconductor layer 130. The distribution ratio of the components constituting the electrode 240 is the same as that of the electrode 230.

  The depth T1 is a depth at which the distribution ratio of Pd as the first component becomes the maximum value P1. The depth T2 is a depth at which the distribution ratio of Ti as the second component becomes the maximum value P2. The depth T3 is a depth at which the distribution ratio of Al as the third component becomes the maximum value P3. The depth T1 and the depth T2 are deeper than the depth T3. In the present embodiment, the depth T1 is at a position deeper than the depth T2.

  The maximum value P1 is higher than a value R2_T1 that is a distribution ratio of Ti at the depth T1. The maximum value P1 is lower than a value R3_T1 which is a distribution ratio of Al at the depth T1.

  The maximum value P2 is higher than a value R1_T2 that is a distribution ratio of Pd at the depth T2. The maximum value P2 is lower than a value R3_T2 that is a distribution ratio of Al at the depth T2.

  The relationship among the maximum value P1, the maximum value P2, and the maximum value P3 satisfies P1 <P2 <P3.

A3. Manufacturing method of semiconductor device:
FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device 10. When manufacturing the semiconductor device 10, the manufacturer firstly includes a semiconductor device in which the first N-type semiconductor layer 120, the P-type semiconductor layer 130, and the second N-type semiconductor layer 140 are formed on the substrate 110. Ten intermediate products are prepared (process P120).

  After preparing the intermediate product of the semiconductor device 10 (process P120), the manufacturer applies a photoresist to the surface facing the + X-axis direction of the intermediate product of the semiconductor device 10 (process P130).

  After applying the photoresist (process P130), the manufacturer forms openings corresponding to the electrodes 230, 240 in the photoresist by photolithography using a photomask in which the patterns of the electrodes 230, 240 are formed (step P130). Step P140).

  After photolithography (process P140), the manufacturer forms a first metal layer by vapor deposition on the surface of the intermediate product of the semiconductor device 10 on which the photoresist is formed (process P152). As a result, a first metal layer is formed at the interface 132 and the interface 142 exposed from the opening of the photoresist. The first metal layer formed in the process P152 is preferably a metal layer mainly composed of at least one of palladium (Pd), platinum (Pt), and nickel (Ni). In this embodiment, from the Pd A metal layer. The thickness of the first metal layer formed in the process P152 is preferably 5 to 100 nm, and in this embodiment, 20 nm.

  Subsequent to the formation of the first metal layer (process P152), the manufacturer makes a second made of titanium (Ti) with respect to the surface of the intermediate product of the semiconductor device 10 on which the first metal layer is formed. The metal layer is formed by vapor deposition (process P154). As a result, the second metal layer is laminated on the first metal layer formed at the interface 132 and the interface 142 exposed from the opening of the photoresist. The thickness of the second metal layer formed in the process P154 is preferably 5 to 50 nm, and in the present embodiment, it is 35 nm.

  Subsequent to the formation of the second metal layer (process P154), the manufacturer performs a third step of forming aluminum (Al) on the surface of the intermediate product of the semiconductor device 10 on which the second metal layer is formed. The metal layer is formed by vapor deposition (process P156). As a result, the third metal layer is laminated on the second metal layer formed at the interface 132 and the interface 142 exposed from the opening of the photoresist. The thickness of the third metal layer formed in the process P156 is preferably 100 nm or more, and in this embodiment, is 300 nm.

  After forming the third metal layer (process P154), the manufacturer removes the photoresist from the intermediate product of the semiconductor device 10 (process P160).

After removing the photoresist (process P160), the manufacturer heat-processes the intermediate product of the semiconductor device 10 using a baking apparatus, and removes the first metal layer, the second metal layer, and the third metal layer. By firing, the electrodes 230 and 240 are formed (process P170). In the present embodiment, the atmospheric gas used for the heat treatment in the process P170 is mainly made of nitrogen (N ₂ ) and may contain oxygen (O ₂ ). The atmospheric gas used for the heat treatment in the process P170 is preferably a temperature selected from a range of 450 to 550 ° C. In this embodiment, the temperature of the atmospheric gas (heat treatment temperature) is 500 ° C. The time for performing the heat treatment of the process P170 is preferably about several seconds to 10 minutes. In this embodiment, the time for performing the heat treatment is 5 minutes.

  In this embodiment, after forming the electrodes 230 and 240 (process P170), the manufacturer forms the electrodes 210 and 250 and the insulating films 330 and 340. Thereby, the semiconductor device 10 is completed. In other embodiments, the manufacturer may perform at least a portion of the process of forming the electrode 210 prior to the formation of the electrodes 230, 240 or simultaneously with the formation of the electrodes 230, 240. In other embodiments, the manufacturer may perform at least a portion of the process of forming the electrode 250 prior to the formation of the electrodes 230, 240 or simultaneously with the formation of the electrodes 230, 240. In another embodiment, the manufacturer may perform at least a part of the process of forming the insulating films 330 and 340 prior to the formation of the electrodes 230 and 240.

A4. Electrode evaluation test:
FIG. 3 is a graph showing the results of evaluating the influence of the heat treatment temperature on the contact resistance of the electrode. In the evaluation test of FIG. 3, the inventor baked eight samples S1 to S8, which are electrodes formed from different metal layers, by changing the heat treatment temperature in step P170, and the GaN-based P-type semiconductor layer. The contact resistance when formed on and the contact resistance when formed on a GaN-based N-type semiconductor layer were measured. Accordingly, the inventor changed the contact resistance according to the heat treatment temperature for the samples S1 to S8 formed on the GaN-based P-type semiconductor layer and the samples S1 to S8 formed on the GaN-based N-type semiconductor layer. confirmed. In the evaluation test of FIG. 3, the time for performing the heat treatment in the process P170 is 5 minutes.

  FIG. 3 shows a semilogarithmic graph showing the contact resistance of samples S1 to S8 according to the heat treatment temperature. In the graph of FIG. 3, the horizontal axis indicates the heat treatment temperature in step P158, and the vertical axis indicates the contact resistance using a logarithmic scale. In the graph of FIG. 3, the measurement value of each sample formed on the GaN-based P-type semiconductor layer is represented by a solid line, and the measurement value of each sample formed on the GaN-based N-type semiconductor layer is represented by a broken line. It is expressed as

  Each of the samples S1 to S6 includes a first metal layer made of palladium (Pd), a second metal layer made of titanium (Ti), and a third metal layer made of aluminum (Al). It is the electrode laminated in order from the side.

  In sample S1, the thickness of the first metal layer is 5 nm, the thickness of the second metal layer is 17.5 nm, and the thickness of the third metal layer is 300 nm. In sample S2, the thickness of the first metal layer is 5 nm, the thickness of the second metal layer is 35 nm, and the thickness of the third metal layer is 300 nm.

  In sample S3, the thickness of the first metal layer is 20 nm, the thickness of the second metal layer is 17.5 nm, and the thickness of the third metal layer is 300 nm. In sample S4, the thickness of the first metal layer is 20 nm, the thickness of the second metal layer is 35 nm, and the thickness of the third metal layer is 300 nm.

  In sample S5, the thickness of the first metal layer is 50 nm, the thickness of the second metal layer is 17.5 nm, and the thickness of the third metal layer is 300 nm. In sample S6, the thickness of the first metal layer is 50 nm, the thickness of the second metal layer is 35 nm, and the thickness of the third metal layer is 300 nm.

Sample S7 is an electrode made of palladium (Pd) and having a thickness of 50 nm. The measured value of the contact resistance of the sample S7 formed on the GaN-based N-type semiconductor layer exceeds 1 × 10 ² Ωcm ² and is not shown in FIG.

Sample S8 is an electrode in which a metal layer made of titanium (Ti) having a thickness of 17.5 nm and a metal layer made of aluminum (Al) having a thickness of 300 nm are stacked in this order from the semiconductor layer side. The measured value of the contact resistance of the sample S8 formed on the GaN-based P-type semiconductor layer exceeds 1 × 10 ² Ωcm ² and is not shown in FIG.

  From the result of FIG. 3, the first electrode formed in the GaN-based P-type semiconductor layer and the second electrode formed in the GaN-based N-type semiconductor layer have the same structure, and the contact resistance of each electrode. In the case of a structure in which a first metal layer made of Pd, a second metal layer made of Ti, and a third metal layer made of Al are laminated in this order from the semiconductor layer side, the process P170 is performed. The heat treatment temperature is preferably 450 to 550 ° C.

  FIG. 4 is a graph showing the results of evaluating the influence of palladium (Pd) and titanium (Ti) layer thickness on the contact resistance in the electrode. In the graph of FIG. 4, among the measured values confirmed in the evaluation test of FIG. 3, measured values for samples S1 to S6 formed at a heat treatment temperature of 500 ° C. are shown. FIG. 4 shows a semilogarithmic graph showing the contact resistance of samples S1 to S6 according to the layer thickness of Pd. In the graph of FIG. 4, the horizontal axis indicates the layer thickness of Pd, and the vertical axis indicates the contact resistance using a logarithmic scale. In the graph of FIG. 4, the measurement value of each sample formed on the GaN-based P-type semiconductor layer is represented by a solid line, and the measurement value of each sample formed on the GaN-based N-type semiconductor layer is represented by a broken line. It is expressed as

  From the results shown in FIG. 4, the electrode has a GaN-based P-type semiconductor layer and a GaN-based N-type semiconductor, with a Pd layer thickness of 20 nm, a Ti layer thickness of 35 nm, and an Al layer thickness of 300 nm. It was confirmed that the contact resistance with both the type semiconductor layer can be suppressed in a well-balanced manner.

A5. effect:
According to the first embodiment described above, each contact resistance of the electrode 230 and the electrode 240 can be suppressed while the electrode 230 and the electrode 240 have the same structure. Therefore, the electrode 230 and the electrode 240 can be shared. Therefore, the number of steps for forming the electrode 230 and the electrode 240 can be reduced, and as a result, the cost of the semiconductor device 10 can be reduced.

A6. First modification:
The semiconductor device 10 in the first modified example is the same as that in the above-described embodiment except that the detailed configurations of the electrodes 230 and 240 are different. The electrodes 230 and 240 in the first modified example are formed in the same manner as in the above embodiment except that the thickness of the second metal layer made of titanium (Ti) is 17.5 nm.

  FIG. 10 is a graph showing a distribution ratio of components constituting the electrodes 230 and 240 in the first modification. The vertical axis and the horizontal axis in the graph of FIG. 10 are the same as those in FIG.

  In the first modified example, the depth T1 and the depth T2 are at positions deeper than the depth T3, as in the above-described embodiment. In the first modification, the depth T1 is at a position deeper than the depth T2.

  In the first modification, as in the above-described embodiment, the maximum value P1 is higher than the value R2_T1, which is the Ti distribution ratio at the depth T1. The maximum value P1 is lower than a value R3_T1 which is a distribution ratio of Al at the depth T1.

  In the first modification, as in the above-described embodiment, the maximum value P2 is higher than the value R1_T2 that is the distribution ratio of Pd at the depth T2. The maximum value P2 is lower than a value R3_T2 that is a distribution ratio of Al at the depth T2.

  In the first modification, as in the above-described embodiment, the relationship among the maximum value P1, the maximum value P2, and the maximum value P3 satisfies P1 <P2 <P3. In the first modification, the maximum value P1 and the maximum value P2 are substantially equal.

  According to the first modification described above, the electrode 230 and the electrode 240 can be shared as in the above-described embodiment.

A7. Second modification:
The semiconductor device 10 in the second modification is the same as that in the above-described embodiment except that the detailed configurations of the electrodes 230 and 240 are different. In the electrodes 230 and 240 in the second modification, the thickness of the first metal layer made of palladium (Pd) is 5 nm, and the thickness of the second metal layer made of titanium (Ti) is 17.5 nm. Except for the point, it is formed in the same manner as the above-described embodiment.

  FIG. 11 is a graph showing a distribution ratio of components constituting the electrodes 230 and 240 in the second modification. The vertical axis and horizontal axis in the graph of FIG. 11 are the same as those in FIG.

  In the second modification, as in the above-described embodiment, the depth T1 and the depth T2 are at positions deeper than the depth T3. In the second modification, the depth T2 is at a position deeper than the depth T1.

  In the second modification, as in the above-described embodiment, the maximum value P1 is higher than the value R2_T1, which is the Ti distribution ratio at the depth T1. The maximum value P1 is lower than a value R3_T1 which is a distribution ratio of Al at the depth T1.

  In the second modification, as in the above-described embodiment, the maximum value P2 is higher than the value R1_T2 that is the distribution ratio of Pd at the depth T2. The maximum value P2 is lower than a value R3_T2 that is a distribution ratio of Al at the depth T2.

  In the second modification, as in the above-described embodiment, the relationship among the maximum value P1, the maximum value P2, and the maximum value P3 satisfies P1 <P2 <P3.

  According to the second modification described above, the electrode 230 and the electrode 240 can be shared as in the above-described embodiment.

B. Second embodiment:
FIG. 5 is a cross-sectional view schematically showing the configuration of the semiconductor device 10B in the second embodiment. The semiconductor device 10B according to the second embodiment is the same as the semiconductor device 10 according to the first embodiment, except that an electrode 260 is provided instead of the electrode 230 and the electrode 240.

  The electrode 260 of the semiconductor device 10B is integrally formed from the interface 132 of the P-type semiconductor layer 130 to the interface 142 of the second N-type semiconductor layer 140 through the interface 143 of the second N-type semiconductor layer 140. Electrode. The electrode 260 functions as a first electrode formed in the P-type semiconductor layer 130 and also functions as a second electrode formed in the second N-type semiconductor layer 140. In other words, the electrode 260 is composed of a first electrode formed on the P-type semiconductor layer 130 and a second electrode formed on the second N-type semiconductor layer 140. The detailed configuration and manufacturing method of the electrode 260 of the second embodiment are the same as those of the electrodes 230 and 240 of the first embodiment.

  According to the second embodiment described above, the contact resistance of each electrode 260 of the electrode 260 integrally formed across the second N-type semiconductor layer 140 across the step from the P-type semiconductor layer 130 can be suppressed. it can. As a result, the cost of the semiconductor device 10B can be reduced as in the first embodiment. Further, compared with the case where electrodes are individually formed on each of the P-type semiconductor layer 130 and the second N-type semiconductor layer 140, the overlay accuracy of photolithography can be relaxed, and as a result, the semiconductor device 10B. Can be miniaturized.

C. Third embodiment:
FIG. 6 is a cross-sectional view schematically showing the configuration of the semiconductor device 50 according to the third embodiment. The semiconductor device 50 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 50 is a light emitting element and is also called a light emitting diode (LED).

  The semiconductor device 50 includes an N-type semiconductor layer 510, a light emitting layer 520, and a P-type semiconductor layer 530. The semiconductor device 50 has a structure in which an N-type semiconductor layer 510, a light emitting layer 520, and a P-type semiconductor layer 530 are joined in order.

  The N-type semiconductor layer 510 of the semiconductor device 50 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor. The N-type semiconductor layer 510 is also referred to as “n-GaN”.

  An electrode 610 is formed on the N-type semiconductor layer 510. The detailed configuration and manufacturing method of the electrode 610 are the same as those of the electrode 240 of the first embodiment.

  The light emitting layer 520 of the semiconductor device 50 is a semiconductor layer configured to be capable of emitting light, and is mainly composed of indium gallium nitride (InGaN) in the present embodiment.

  The P-type semiconductor layer 530 of the semiconductor device 50 is mainly made of gallium nitride (GaN) and contains magnesium (Mg) as an acceptor. The P-type semiconductor layer 530 is also called “p-GaN”.

  An electrode 630 is formed on the P-type semiconductor layer 530. The detailed configuration and manufacturing method of the electrode 630 are the same as those of the electrode 230 of the first embodiment.

  According to the third embodiment described above, the contact resistances of the electrode 610 and the electrode 630 can be suppressed while the electrode 610 and the electrode 630 have the same structure. As a result, the cost of the semiconductor device 50 can be reduced as in the first embodiment.

D. Fourth embodiment:
FIG. 7 is a cross-sectional view schematically showing the configuration of the semiconductor device 70 in the fourth embodiment. The semiconductor device 70 is a GaN-based semiconductor device formed using gallium nitride (GaN). The semiconductor device 70 includes a P-type semiconductor layer 710, an N-type semiconductor layer 720, and an electrode 730. The semiconductor device 70 has a structure in which a part of the surface side of the P-type semiconductor layer 710 is replaced with an N-type semiconductor layer 720.

  The P-type semiconductor layer 710 of the semiconductor device 70 is mainly made of gallium nitride (GaN) and contains magnesium (Mg) as an acceptor. The P-type semiconductor layer 710 is also referred to as “p-GaN”.

  The N-type semiconductor layer 720 of the semiconductor device 70 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor. The N-type semiconductor layer 720 is also referred to as “n-GaN”.

  The electrode 730 of the semiconductor device 70 is an electrode formed integrally from the P-type semiconductor layer 710 to the N-type semiconductor layer 720. The electrode 730 functions as a first electrode formed in the P-type semiconductor layer 710 and also functions as a second electrode formed in the N-type semiconductor layer 720. In other words, the electrode 730 includes a first electrode formed on the P-type semiconductor layer 710 and a second electrode formed on the N-type semiconductor layer 720. The detailed configuration and manufacturing method of the electrode 730 of the fourth embodiment are the same as those of the electrodes 230 and 240 of the first embodiment.

  According to the fourth embodiment described above, the contact resistance of the electrode 730 formed integrally from the P-type semiconductor layer 710 to the N-type semiconductor layer 720 to each semiconductor layer can be suppressed. As a result, the cost of the semiconductor device 70 can be reduced as in the first embodiment. Further, compared with the case where electrodes are individually formed on each of the P-type semiconductor layer 710 and the N-type semiconductor layer 720, the overlay accuracy of photolithography can be relaxed, resulting in the miniaturization of the semiconductor device 70. Can be achieved.

E. Fifth embodiment:
FIG. 8 is a cross-sectional view schematically showing the configuration of the semiconductor device 80 in the fifth embodiment. The semiconductor device 80 is a GaN-based semiconductor device formed using gallium nitride (GaN). The semiconductor device 80 includes an N-type semiconductor layer 810, a P-type semiconductor layer 820, and an electrode 830. The semiconductor device 80 has a structure in which a part of the surface side of the N-type semiconductor layer 810 is replaced with a P-type semiconductor layer 820.

  The N-type semiconductor layer 810 of the semiconductor device 80 is mainly made of gallium nitride (GaN) and contains silicon (Si) as a donor. The P-type semiconductor layer 820 of the semiconductor device 80 is mainly made of gallium nitride (GaN) and contains magnesium (Mg) as an acceptor.

  The electrode 830 of the semiconductor device 80 is an electrode formed integrally from the N-type semiconductor layer 810 to the P-type semiconductor layer 820. The electrode 830 functions as a first electrode formed in the P-type semiconductor layer 820 and also functions as a second electrode formed in the N-type semiconductor layer 810. In other words, the electrode 830 includes a first electrode formed on the P-type semiconductor layer 820 and a second electrode formed on the N-type semiconductor layer 810. The detailed configuration and manufacturing method of the electrode 830 of the fifth embodiment are the same as those of the electrodes 230 and 240 of the first embodiment.

  According to the fifth embodiment described above, the contact resistance of the electrode 830 integrally formed from the N-type semiconductor layer 810 to the P-type semiconductor layer 820 to each semiconductor layer can be suppressed. As a result, the cost of the semiconductor device 80 can be reduced as in the first embodiment. Further, as compared with the case where electrodes are individually formed on each of the N-type semiconductor layer 810 and the P-type semiconductor layer 820, the overlay accuracy of photolithography can be relaxed, resulting in the miniaturization of the semiconductor device 80. Can be achieved.

F. Other embodiments:
The present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above-described effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

  For example, in the first and second embodiments described above, the NPN semiconductor devices 10 and 10B have been described. In other embodiments, the structure and manufacturing of the semiconductor devices 10 and 10B are included in the PNP semiconductor device. A method may be applied.

  In the above-described embodiment, the first component constituting the electrode may be at least one of platinum (Pt) and nickel (Ni) having electrical characteristics close to palladium (Pd).

  In the above-described embodiment, an intrinsic semiconductor layer (undoped semiconductor layer) may be formed between the substrate and the N-type semiconductor layer, or an intrinsic semiconductor layer is formed between the N-type semiconductor layer and the P-type semiconductor layer. May be.

  In the above-described embodiment, the material of the substrate is not limited to gallium nitride (GaN), but may be silicon (Si), sapphire, silicon carbide (SiC), or the like.

  In the above embodiment, the donor contained in the substrate and the N-type semiconductor layer is not limited to silicon (Si), but may be germanium (Ge), oxygen (O), or the like.

  In the above-described embodiment, the acceptor included in the P-type semiconductor layer is not limited to magnesium (Mg) but may be zinc (Zn), carbon (C), or the like.

In the above embodiment, the insulating film is made of silicon nitride (SiN), silicon nitride oxide (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum nitride oxide (AlON), zirconium dioxide (ZrO ₂ ), titanium oxide (TiO ₂ ). ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), niobium pentoxide (Nb ₂ O ₅ ), hafnium dioxide (HfO ₂ ), aluminum nitride (AlN), or the like.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 10B ... Semiconductor device 50 ... Semiconductor device 70 ... Semiconductor device 80 ... Semiconductor device 110 ... Substrate 111 ... Interface 112 ... Interface 120 ... First N-type semiconductor layer 121 ... Interface 122 ... Interface 130 ... P-type semiconductor layer 131 ... Interface 132 ... Interface 140 ... Second N-type semiconductor layer 141 ... Interface 142 ... Interface 143 ... Interface 210 ... Electrode 230 ... Electrode 240 ... Electrode 250 ... Electrode 260 ... Electrode 330 ... Insulating film 340 ... Insulating film 510 ... N Type semiconductor layer 520 ... Light emitting layer 530 ... P type semiconductor layer 610 ... Electrode 630 ... Electrode 710 ... P type semiconductor layer 720 ... N type semiconductor layer 730 ... Electrode 810 ... N type semiconductor layer 820 ... P type semiconductor layer 830 ... Electrode

Claims (5)

A semiconductor device,
A P-type semiconductor layer mainly composed of gallium nitride (GaN);
An N-type semiconductor layer mainly composed of gallium nitride (GaN);
A first electrode formed on the P-type semiconductor layer;
A second electrode formed on the N-type semiconductor layer,
The first and second electrodes are:
A first component that is at least one of palladium (Pd), platinum (Pt), and nickel (Ni);
A second component that is titanium (Ti);
A third component that is aluminum (Al) and
The depth T1 at which the distribution ratio of the first component reaches the maximum value P1 in the depth direction from the surface of the first and second electrodes toward the inside, and the distribution of the second component in the depth direction The depth T2 at which the ratio becomes the maximum value P2 is deeper than the depth T3 at which the distribution ratio of the third component becomes the maximum value P3 in the depth direction.
The depth T1 is at a position deeper than the depth T2 in the depth direction,
The maximum value P1 is higher than the distribution ratio of the second component at the depth T1 and lower than the distribution ratio of the third component at the depth T1.
Semiconductor device.   2. The semiconductor device according to claim 1, wherein the maximum value P <b> 2 is higher than a distribution ratio of the first component at the depth T <b> 2 and lower than a distribution ratio of the third component at the depth T <b> 2. The maximum value P3, as well as higher than the distribution ratio of the first component in the depth T3, greater than the distribution ratio of the second component in the depth T3, according to claim 1 or claim 2 Semiconductor device.   4. The semiconductor device according to claim 1, wherein the first and second electrodes are integrally formed from the P-type semiconductor layer to the N-type semiconductor layer. 5.   The first and second electrodes are integrally formed across a second interface having a step between the first interface in the P-type semiconductor layer and the first interface in the N-type semiconductor layer. The semiconductor device according to any one of claims 1 to 4.

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