JP6098937B2 - electric circuit - Google Patents

Description

  The present invention relates to an electric circuit.

  In an apparatus such as a printer, it is necessary to drive a plurality of motors. In such an apparatus, it is conceivable that the type of motor to be driven or the drive current is not unified. However, preparing a dedicated motor driver for each motor leads to an increase in the cost of the apparatus.

  Therefore, the motor drive circuit described in Patent Document 1 includes an H-bridge circuit and a setting unit that performs settings for driving each of a plurality of types of motors for the H-bridge circuit. The setting unit performs setting corresponding to each motor on the H bridge circuit based on a control signal generated by the controller in accordance with an instruction from the CPU.

JP 2005-65486 A

  The setting unit described in Patent Document 1 performs setting for designating a motor type or a drive current in the H-bridge circuit based on the control of the CPU and the controller.

  In the motor drive circuit described in Patent Literature 1, when the CPU does not give an instruction, the setting unit cannot set the H bridge circuit. For example, in the case where the setting unit is configured so that the H-bridge circuit can be used as both a switching regulator and a motor driver, and the CPU is operated by a voltage generated by the switching regulator, the switching regulator is turned on when the power is turned on. Does not generate a predetermined voltage, the CPU cannot output a setting instruction. For this reason, there is a problem that the setting unit cannot set the H bridge circuit when the power is turned on.

  The present invention has been made in view of the above-described problems, and an object thereof is to selectively drive an H bridge circuit according to a peripheral circuit to which the H bridge circuit is connected without using a control unit such as a CPU. To do.

  The electrical circuit of the present invention is configured to be connectable to each of a plurality of types of peripheral circuits, and is connected to at least one of the plurality of types of peripheral circuits, and one or a plurality of H bridge circuits and one or A transistor control unit that controls each of a plurality of transistor pairs included in each of the plurality of H bridge circuits, and at least one first H bridge circuit of the one or more H bridge circuits, the first H bridge circuit includes: A first setting storage unit that stores settings related to initial control performed by the transistor control unit, and the transistor control unit stores the first setting storage unit for at least one of the plurality of transistor pairs provided. After the control according to the setting, a plurality of fronts included in at least one of the H bridge circuits including the first H bridge circuit Connected to at least one H bridge circuit including a second setting storage unit that stores a plurality of settings related to control performed on each of the transistor pairs in association with each of a plurality of types of peripheral circuits, and the first H bridge circuit An IC having a first determination unit for determining the peripheral circuit, and when the electric circuit supplies a voltage to the IC, the transistor control unit follows a setting stored in the first setting storage unit, At least one of the plurality of transistor pairs included in the first H bridge circuit is controlled so that a voltage is supplied to a peripheral circuit connected to the first H bridge circuit, and the first determination unit is Supplied to the peripheral circuit connected to the first H-bridge circuit by the control of the transistor control unit according to the setting stored in the one setting storage unit The peripheral circuit connected to at least one of the H bridge circuits including the first H bridge circuit is determined according to the presence or absence of feedback of the voltage, and the transistor control unit is configured so that the first determination unit According to the setting stored in the second setting storage unit in association with the peripheral circuit specified by the first determination unit, for each of the plurality of transistor pairs included in the one or more H bridge circuits that specify the circuit Control is performed.

  According to the first aspect of the present invention, the electric circuit selectively selects the H bridge circuit included in the IC according to the peripheral circuit connected to the H bridge circuit without using the main control unit including the CPU or the like. Can be driven.

  In addition, according to the second and third aspects of the invention, a voltage is supplied to the peripheral circuit connected to the H-bridge circuit, and the peripheral circuit is discriminated based on the presence or absence of feedback of the supplied voltage. Can be determined.

  According to the fourth aspect of the invention, if the peripheral circuit connected to the first H bridge circuit is determined, the peripheral circuit connected to the second H bridge circuit can be determined indirectly. Therefore, when the IC includes a plurality of H bridge circuits, it is possible to simplify the determination process for a plurality of peripheral circuits.

  According to the invention described in claim 5, in an IC including a plurality of H bridge circuits, three or more combinations of peripheral circuits connected to each of the plurality of H bridge circuits can be provided.

1 is a schematic diagram illustrating a configuration of an image forming apparatus 1 according to a first embodiment. 1 is a schematic diagram illustrating a configuration of an image forming apparatus 1 according to a first embodiment. It is a figure which shows the switching unit 140 and its peripheral circuit. It is a figure which shows the switching unit 150 and its peripheral circuit. It is a figure which shows the switching unit 150 and its peripheral circuit. It is a figure which shows the switching unit 150 and its peripheral circuit. It is a figure which shows the switching unit 240 and its peripheral circuit. It is a figure which shows the switching unit 250 and its peripheral circuit. It is a figure which shows the switching unit 150 and its peripheral circuit. It is a figure which shows the switching unit 150 and its peripheral circuit. 4 is a timing chart showing peripheral circuit determination processing in the power management apparatus 100. 6 is a timing chart showing peripheral circuit determination processing in the power management apparatus 200. FIG. 6 is a schematic diagram illustrating a configuration of an image forming apparatus 1 according to a second embodiment. FIG. 6 is a schematic diagram illustrating a configuration of an image forming apparatus 1 according to a second embodiment. 5 is a diagram illustrating a VD / V1 recording unit 315. FIG. It is a figure which shows the VD / V1 recording part 415. FIG. It is a timing chart which shows the 2nd peripheral circuit discrimination | determination process.

  Hereinafter, main embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
<Image forming apparatus>
Hereinafter, a description will be given with reference to FIGS. The image forming apparatus 1 includes a power supply unit 10, a switch 11, a main control unit 20 including an ASIC and a CPU, a power management device 100, a power management device 200, a USB host I / F 30, a recording head 31, an EEPROM 32, a DDR memory 33, a carriage. A motor 40, a paper feed motor 41, and a flat bed motor 42 are provided. The power supply unit 10 includes a rectifier circuit, a transformer, and the like. When an AC voltage (for example, 100V) is supplied from an AC power supply, the power supply unit 10 converts the voltage to a DC voltage VD (for example, 31V). Supply to device 200. The switch 11 is a so-called hard switch, and when operated, switches the circuit of the power supply unit 10 to supply a voltage to the power management apparatus 100 and the power management apparatus 200.

  The power management apparatus 100 and the power management apparatus 200 are the same composite IC (Integrated Circuit). The power management apparatus 100 includes a determination unit 110, a setting unit 120, an internal CLK generation unit 130, an internal voltage generation unit 170, an activation unit 180, a boosting unit 190, a switching unit 140, a switching unit 150, a switching unit 160, and a terminal 100A. Prepare. The determination unit 110 includes a counter unit 111, a state acquisition unit 112, and a holding unit 113. The setting unit 120 includes a data control unit 121, an initial setting unit 122, and an operation setting unit 123. The internal CLK generation unit 130 generates an internal clock CLK1 and inputs the generated internal clock CLK1 to the counter unit 111. The counter unit 111 includes a register, and counts down the time written in the register in synchronization with the internal clock CLK1. The holding unit 113 is a register and sets a flag when the feedback voltage Vf1 is input from the switching unit 140. The state acquisition unit 112 determines whether or not the flag is set in the holding unit 113 at the timing when the countdown of the counter unit 111 ends. The data control unit 121 supplies internal enable signals ENABLE 10 to 19 to switching control units 144 a, 144 b, 154 a, 154 b, 164 a, 164 b, and comparison circuits 163 a, 163 b, and comparison circuits 168 a, 168 b, which will be described later. Can be entered. The initial setting unit 122 is a register that stores initial settings of the power management apparatus 100. The operation setting unit 123 is a register that is rewritten according to a connection circuit determination operation described later. The operation setting unit 123 stores two combinations of internal permission signals ENBLE 10 to 19 that are uniquely determined when the flag is set in the holding unit 113 and when the flag is not set. The internal voltage generator 170 is an LDO (Low Drop Out) regulator. When the DC voltage VD is input, the internal voltage generator 170 steps down the DC voltage VD (31 V) and generates an internal voltage Vin (5 V). The generated internal voltage Vin is supplied to the digital circuit as a driving voltage for various digital circuits included in the power management apparatus 100. When the DC voltage VD is supplied from the power supply unit 10 to the power management apparatus 100, the activation unit 180 is activated first and activates the internal voltage generation unit 170. When VD (31 V) is input, the booster 190 generates a boosted voltage Vp (36 V). The boosted voltage Vp is supplied to switching control units 144a, 144b, 154a, 154b, 164a, and 164b included in switching units 140 to 160 described later.

  The switching units 140 to 160 include H bridge circuits H11 to 13 and various digital circuits. Although details will be described later, the switching unit 140 is connected to the peripheral circuits 141a and 141b, the switching unit 150 is connected to the peripheral circuits 151a and 151b, and the switching unit 160 is connected to the peripheral circuits 161a and 161b. The peripheral circuit 141a is connected to the USB host I / F 30 and supplies the voltage V1. The peripheral circuit 141b is connected to the recording head 31 and supplies the voltage V2. The peripheral circuit 151a is connected to the EEPROM 32 and supplies the voltage V3. The peripheral circuit 151b is connected to the main control unit 20 including a CPU and an ASIC, and supplies a voltage V4. The peripheral circuit 161a is connected to the main control unit 20 and supplies the voltage V5. The peripheral circuit 161b is connected to the DDR memory 33 and supplies the voltage V6.

  The USB host I / F 30 includes a terminal to which a USB cable or a USB memory can be attached and detached. Then, the USB host I / F 30 supplies a voltage to the connected device. The recording head 31 ejects ink from nozzles (not shown) to form an image on recording paper. The EEPROM 32 is a rewritable nonvolatile memory. The DDR memory 33 is a rewritable volatile memory. The terminal 100A is connected to the switching unit 160. When the DC voltage VD is supplied to the power management apparatus 100, the DC voltage VD is supplied to the switching unit 140 and the H bridge circuits H11 and H12 included in the switching unit 150. On the other hand, the H bridge circuit H13 provided in the switching unit 160 is supplied with a voltage from a power source connected to the terminal 100A. In the present embodiment, since the terminal 100A is connected to the peripheral circuit 141a, the voltage V1 is supplied to the H bridge circuit H13.

  Since the power management apparatus 200 is the same IC as the power management apparatus 100, redundant description will be omitted and only different points will be described. A peripheral circuit 241 is connected to the switching unit 240, a peripheral circuit 251 is connected to the switching unit 250, and a peripheral circuit 261 is connected to the switching unit 260. The carriage motor 241 and the resistor constitute a peripheral circuit 241, the paper feed motor 41 and the resistor constitute a peripheral circuit 251, and the flat bed motor 42 and the resistor constitute a peripheral circuit 261. The carriage motor 40 applies driving force to a carriage (not shown) on which the recording head 31 is placed. When a driving force is applied, the carriage moves in the main scanning direction of the recording paper. The paper feed motor 41 is a motor that conveys recording paper. The flat bed motor 42 applies a driving force to a scan unit (not shown) and moves the scan unit. Since the terminal 200A is connected to the power supply unit 10, the DC voltage VD is supplied to the H bridge circuit H23 provided in the switching unit 260.

  The main control unit 20 controls various operations of the image forming apparatus 1. The main control unit 20 inputs permission signals ENABLE 1 to 3, rotation direction signals PHASE 1 to 3, and reference voltages REF 1 to REF 3 to the power management apparatus 200.

  In the first embodiment, the power management apparatus 100 is configured such that the three H bridge circuits are either of the following two types. On the other hand, the H bridge circuits H11 and H12 each function as a part of two DC / DC converters, and the H bridge circuit H13 functions as a part of LDO (Low Drop Out). That is, in the power management device 100, each of the H bridge circuits H11 and H12 is connected to a peripheral circuit (that is, a smoothing circuit and a voltage dividing circuit) for causing the H bridge circuit to function as a part of the DC / DC converter. The H bridge circuit H13 is connected to a peripheral circuit (voltage dividing circuit) for causing the H bridge circuit 13 to function as a part of the LDO. On the other hand, the H bridge circuits H11, H12, and H13 all function as motor drivers. That is, the power management apparatus 100 is configured such that a motor is connected to the H bridge circuits H11, H12, and H13. The two combinations of the internal enable signals ENBLE 10 to 19 stored in the operation setting unit 123 are associated with the two combinations of the peripheral circuits connected to the H bridge circuits H11 to H13, respectively. The same applies to the internal permission signals ENBLE 20 to 29 stored in the operation setting unit 223 included in the power management apparatus 200.

<Switching unit 140>
Hereinafter, a description will be given with reference to FIG. The switching unit 140 includes an H bridge circuit H11 including transistor switches 146a, 147a, 146b, and 147b, a switching control unit 144a, a switching control unit 144b, and a comparison circuit 145. One terminal of the H-bridge circuit H11 is connected to a terminal that supplies a DC voltage VD, and the other terminal is connected to a ground potential terminal. The transistor switches 146a, 146b, 147a, 147b are configured by NMOS (negative channel metal oxide semiconductor) transistors. The peripheral circuit 141a in FIG. 1 includes a smoothing circuit 142a and a voltage dividing circuit 143a, and the peripheral circuit 141b includes a smoothing circuit 142b and a voltage dividing circuit 143b. The H bridge circuit H11 is connected to the smoothing circuit 142a, the voltage dividing circuit 143a, the smoothing circuit 142b, and the smoothing circuit 143b. When the smoothing circuit 142a and the smoothing circuit 142b receive a pulse voltage generated by switching the DC voltage VD with the transistor switch 146a and the transistor switch 146b, the smoothing circuit 142a and the smoothing circuit 142b Lower voltages V1 and V2 are output. The voltage dividing circuit 143a and the voltage dividing circuit 143b divide the input voltages V1 and V2, respectively, to obtain feedback voltages Vf1 and Vf2. The feedback voltages Vf1 and Vf2 are input to the switching control units 144a and 144b, respectively.

  The switching control unit 144a controls switching of the transistor switches 146a and 147a by changing gate voltages input to the transistor switches 146a and 147a. The switching controller 144b controls the switching of the transistor switches 146b and 147b by changing the gate voltage input to the transistor switches 146b and 147b. The boosted voltage Vp generated by the booster 190 is input to the switching controllers 144a and 144b. The input of the boost voltage Vp is necessary because NMOS is used for the switching control units 146a and 146b. Specifically, when the switching controller 145a turns on the transistor switch, it is necessary to input a voltage (eg, 34V) higher than the DC voltage VD to the transistor switches 146a and 147a as the gate voltage. The switching control units 144a and 144b include a register (not shown), and the register stores both setting values when the switching unit 140 functions as a part of the DC / DC converter and when it functions as a motor driver. Has been. After the power supply to the image forming apparatus 1 is turned on, the switching control units 144a and 144b perform transistor switches 146a and 147a according to the set values instructed by the internal permission signals ENABLE10 and ENABLE11 input from the data control unit 121 (see FIG. 1). 146b and 147b are controlled.

  When the switching unit 140 functions as a part of the DC / DC converter, the switching control units 144a and 144b respectively set the voltages V1 and V2 based on the relationship between the feedback voltages Vf1 and Vf2 and the resistance values of the voltage dividing circuits 143a and 143b. calculate. The gate voltages input to the transistor switches 146a and 146b are controlled so that the duty ratios of the pulse voltages input to the smoothing circuits 142a and 142b change according to the calculated deviations of V1 and V2 from the target values. The feedback voltage Vf1 output from the voltage dividing circuit 143a is also input to the determination unit 110 and written to the holding unit 113 (see FIG. 1).

  Although the switching unit 140 can function as a motor driver, in this embodiment, it is not used as a motor driver. The operation of the switching control units 144a and 144b when the switching unit 140 functions as a motor driver, and the description of the comparison circuit 145, the operation of the switching control units 244a and 244b when the switching unit 240 functions as a motor driver, and Since it overlaps with the description of the comparison circuit 245, it will be omitted.

<Switching unit 150>
Hereinafter, a description will be given with reference to FIG. Since the switching unit 150 has substantially the same configuration as the switching unit 140, only the differences will be described. The enabling signal ENABLE12 is input to the switching control unit 154a, and the enabling signal ENABLE13 is input to the switching control unit 154b. Further, the feedback voltage Vf3 output from the voltage dividing circuit 153a is not input to the holding unit 113. The voltage V3 output from the smoothing circuit 152a is not supplied to the terminal 100A.

<Switching unit 160>
Hereinafter, a description will be given with reference to FIGS. The switching unit 160 includes an H-bridge circuit H13 including a transistor switch 166a, a transistor switch 167a, a transistor switch 167b, and a transistor switch 167b. The switching unit 160 includes a switching unit 163a, 163b, a switch 1630a, a switch 1631a, a switch 1630b, a switch 1631b, a switching control unit 164a, a switching control unit 164b, a comparison circuit 165, comparison circuits 168a, 168b, and an internal REF generation unit 169a. And an internal REF generation unit 169b.

  As shown in FIG. 1, one terminal of the H-bridge circuit H13 is connected to the terminal 100A, and the other terminal is connected to a ground potential terminal. Therefore, the H bridge circuit H13 is supplied with the voltage V1 unlike the H bridge circuits H11 and H12. Feedback voltages Vf5 and Vf6 are output from the voltage dividing circuit 161a and the voltage dividing circuit 161b, respectively. The feedback voltage Vf5 is input to the comparison circuit 168a, and the feedback voltage Vf6 is input to the comparison circuit 168b.

  The switching unit 163a outputs a switching signal according to the internal permission signal ENABLE16 input from the data control unit 121 (see FIG. 1) to switch the switches 1630a and 1631a. Similarly, the switching unit 163b outputs a switching signal according to the internal permission signal ENABLE17 input from the data control unit 121 to switch the switches 1630b and 1631b. The switching unit 160 can function as both a motor driver and an LDO (low dropout) regulator. When functioning as an LDO regulator, the switches 1630a and 1630b are connected to the transistor switch 166a and the comparison circuit 168a, and the transistor switch 166b and the comparison circuit 168b are connected to each other. The switching control unit 164a, the transistor switch 167b, and the switching control unit 164b are switched to be disconnected. On the other hand, when functioning as a motor driver, the switches 1630a and 1630b are connected to the transistor switch 166a and the switching control unit 164a, and the transistor switch 166b and the switching control unit 164b are connected to each other. Switching is performed such that the switch 167a and the switching control unit 164a, and the transistor switch 167b and the switching control unit 164b are disconnected.

  Like the H bridge circuits H11 and H12, the transistor switches 166a to 167b included in the H bridge circuit H13 are configured by NMOS, and therefore the boosted voltage Vp is input to the switching control unit 164a and the switching control unit 164b. The switching control units 164a and 164b include a register, and a setting value when functioning as a motor driver is stored in the register. When the internal enable signals ENABLE14 and ENABLE15 are input from the data control unit 121, the switching control units 164a and 164b input gate voltages to the transistor switches 166a, 167a, 166b, and 167b and control them. However, as will be described later, in the present embodiment, the internal permission signals ENABLE14 and ENABLE15 are not input to the switching control units 164a and 164b.

  The comparison circuit 168a starts operating when the internal permission signal ENABLE18 is input. The comparison circuit 168a compares the input feedback voltage Vf5 with the reference voltage REF1, and changes the gate voltage input to the transistor switch 166a over time. That is, the comparison circuit 168a can perform control to bring the voltage V5 closer to the reference voltage REF1. The comparison circuit 168b also starts to operate when the internal permission signal ENABLE19 is input. The comparison circuit 168b compares the input feedback voltage Vf6 with the reference voltage REF2, and changes the gate voltage input to the transistor switch 166b over time. That is, the comparison circuit 168b can perform control to bring the voltage V6 closer to the reference voltage REF2.

  The comparison circuit 165 has the same configuration as the comparison circuit 265, but the comparison circuit 165 is not used in this embodiment. The function of the comparison circuit will be described when the switching unit 260 is described.

<Switching unit 240>
Hereinafter, a description will be given with reference to FIG. The switching unit 240 has the same configuration as the switching unit 140. Therefore, detailed description of the corresponding circuit is omitted. However, the circuit connected to the switching unit 240 is different from the circuit connected to the switching unit 140.

  A carriage motor 40 and a peripheral circuit 241 including a resistor are connected to the H bridge circuit H21. The comparison circuit 245 receives the reference voltage REF1 and the feedback voltage Vf7 generated by the carriage motor 40 and the resistor 241. The comparison circuit 245 compares the feedback voltage Vf7 with the reference voltage REF1. When the feedback voltage Vf7 is higher than the reference voltage REF1, the comparison circuit 245 inputs a low signal to the switching control units 244a and 244b. On the other hand, when the feedback voltage Vf7 decreases to the reference voltage REF1, the comparison circuit 245 inputs a high signal to the switching control units 244a and 244b. When the switching control units 244a and 244b function according to the set value as the motor driver, the switching control units 244a and 244b follow the permission signal ENBLE1 and the rotation direction signal PHASE1 input from the main control unit 20. The main control unit 20 continues to input the permission signal ENABLE1 to the switching control units 244a and 244b at the time when the carriage motor 40 should be controlled. Therefore, the voltage VD is not supplied to the carriage motor 40 while the enable signal ENABLE1 is not input. The rotation direction signal PHASE1 is a signal indicating whether the carriage motor 40 should be rotated forward or backward.

<Switching unit 250>
Hereinafter, a description will be given with reference to FIG. Since the switching unit 250 has the same configuration as the switching unit 150, detailed description of various circuits is omitted. However, while the smoothing circuit 152a, the voltage dividing circuit 153a, the smoothing circuit 152b, and the voltage dividing circuit 153b are connected to the H bridge circuit H12, the paper feed motor 41 and the resistor are connected to the H bridge circuit H22. Is connected. The comparison circuit 255 compares the feedback voltage Vf8 with the reference voltage REF2. When the feedback voltage Vf8 is higher than the reference voltage REF2, the comparison circuit 255 inputs a low signal to the switching control units 254a and 254b. On the other hand, when the feedback voltage Vf8 decreases to the reference voltage REF2, the comparison circuit 255 inputs a high signal to the switching control units 254a and 254b. When the switching control units 254a and 254b function according to the set value as the motor driver, the switching control units 254a and 254b follow the permission signal ENBLE2 and the rotation direction signal PHASE2 input from the main control unit 20. The main control unit 20 continues to input the permission signal ENABLE2 to the switching control units 254a and 254b at the time when the paper feed motor 41 is to be controlled. Therefore, the voltage VD is not supplied to the paper feed motor 41 while the permission signal ENABLE2 is not input. The rotation direction signal PHASE2 is a signal indicating whether the paper feed motor 41 should be rotated forward or backward.

<Switching unit 260>
Hereinafter, a description will be given with reference to FIG. The switching unit 260 has the same configuration as the switching unit 160. Therefore, detailed description of circuits other than the comparison circuit 265 is omitted. However, the circuit connected to the switching unit 260 is different from the circuit connected to the switching unit 160.

  A flat bed motor 42 and a resistor 261 are connected to the H bridge circuit H23. The comparison circuit 265 receives the reference voltage REF3 and the feedback voltage Vf9 output from the flatbed motor 42 and stepped down by the resistor 261. The comparison circuit 265 compares the feedback voltage Vf9 with the reference voltage REF3. When the feedback voltage Vf9 is higher than the reference voltage REF3, the comparison circuit 265 inputs a low signal to the switching control unit 264a. On the other hand, when the feedback voltage Vf9 is lower than the reference voltage REF3, the comparison circuit 265 inputs a high signal to the switching control units 264a and 264b. When the switching control units 264a and 264b function according to the set value as the motor driver, the switching control units 264a and 264b follow the enable signals ENBLE3 and PHASE3 input from the main control unit 20. The main control unit 20 continues to input the permission signal ENABLE3 to the switching control units 264a and 264b at the time when the flatbed motor 42 should be controlled. Therefore, no voltage is supplied to the flat bed motor 42 while the enable signal ENABLE3 is not input. The rotation direction signal PHASE3 is a signal indicating whether the flatbed motor 42 should be rotated forward or backward.

<Peripheral Circuit Discrimination Processing in Power Management Devices 100 and 200>
When activation is instructed by the switch 11 while the image forming apparatus 1 (see FIG. 1A) is stopped, the power supply unit 10 supplies the DC voltage VD to the power management apparatus 100 and the power management apparatus 200. (T0). The power management apparatus 100 and the power management apparatus 200 are the same IC. However, the power management device 100 and the power management device 200 perform different processes depending on the connected circuits even though they are the same IC in a state where the main control unit 20 has not been activated yet. Can do. Hereinafter, operations of the power management apparatus 100 and the power management apparatus 200 when the DC voltage VD is supplied will be described with reference to FIGS. 8 and 9.

<Peripheral circuit discrimination processing of power supply circuit 100>
The DC voltage VD supplied to the power management apparatus 100 is first supplied to a terminal connected to the starter 180, the internal voltage generator 170, and one end of the H bridge circuits H11 and H12. However, internal voltage generation unit 180 does not start until a start instruction is received, and therefore does not start only by supplying DC voltage VD. In the H bridge circuits H11 and H12, no current flows because no gate voltage is applied to the transistor switches 146a, 146b, 156a, and 156b.

  The DC voltage VD is 0V at the start of supply and gradually increases to the target voltage (31V). Then, when the DC voltage VD becomes 15 V or higher, the activation unit 180 activates the internal voltage generation unit 170. When activated, the internal voltage generation unit 170 generates an internal voltage Vin from the supplied DC voltage VD, and various digital circuits included in the determination unit 110 and the setting unit 120, a booster unit 190, and switching units 140 and 150 , 160 supplies the internal voltage Vin to various digital circuits. Various digital circuits are activated when the internal voltage Vin is supplied.

  The data control unit 121 reads the time T1 to be measured from the initial setting unit 122. Then, the read time is written into the register of the counter unit 111. When the time T1 is written in the register, the counter unit 111 starts counting down in synchronization with the internal clock CLK1 (t1). The data control unit 120 refers to the initial setting unit 122 and reads an instruction to transmit the internal permission signal ENABLE10 indicating the DC / DC converter to the switching control unit 144a. And according to the read instruction | indication, the internal permission signal ENABLE10 which shows a DC / DC converter is output to the switching control part 144a. When the internal enable signal ENABLE10 signal indicating the DC / DC converter is input, the switching control unit 144a inputs the pulse voltage of the boost voltage Vp to the transistor switch 146a at the switching frequency stored in the register included in the switching control unit 144a. Then, a pulse voltage having a switching frequency is input to the smoothing circuit 142a. When the pulse voltage is input, the smoothing circuit 142a outputs the voltage V1. The voltage dividing circuit 143a outputs a feedback voltage Vf1 when the voltage V1 is inputted. The feedback voltage Vf1 is input to the holding unit 113 provided in the determination unit 110. When the feedback voltage Vf1 is input, the holding unit 113 sets a flag when the feedback voltage Vf1 exceeds a predetermined threshold value. On the other hand, when the counter unit 111 finishes counting the time T1, the state acquisition unit 112 determines whether or not the flag is set in the holding unit 113 (t2). When the state acquisition unit 112 determines that the flag is set, the data control unit 121 writes that fact in a predetermined area of the operation setting unit 123. As described above, the operation setting unit 123 is associated with the peripheral circuits connected to the H bridge circuits H11 to H13 that are uniquely determined when the flag is set in the state acquisition unit 112 and when the flag is not set. A combination of internal permission signals ENBLE10 to 19 is stored. When the flag is set, each of the H bridge circuits H11 and H12 is connected to a peripheral circuit (that is, a smoothing circuit and a voltage dividing circuit) for causing the H bridge circuit to function as a part of the DC / DC converter. The H bridge circuit H13 is connected to a peripheral circuit (voltage dividing circuit) for causing the H bridge circuit 13 to function as a part of the LDO. Then, the data control unit 121 sends an internal permission signal ENABLE10 indicating a DC / DC converter to the switching control unit 144a, an internal permission signal ENABLE11 indicating a DC / DC converter to the switching control unit 144b, and DC / DC to the switching control unit 154a. An internal enable signal ENABLE12 indicating a converter, an internal enable signal ENABLE13 indicating a DC / DC converter to the switching control unit 154b, an internal enable signal ENABLE18 to the comparison circuit 168a, and an internal enable signal ENABLE16 corresponding to the LDO regulator to the switching unit 163a The internal enable signal ENABLE19 is output to the comparison circuit 168b, and the internal enable signal ENABLE17 corresponding to the LDO regulator is output to the switching unit 163b.

<Peripheral Circuit Discrimination Processing of Power Management Device 200>
The DC voltage VD supplied to the power management apparatus 200 is first supplied to a terminal connected to one end of the starter 280, the internal voltage generator 270, and the H bridge circuits H21, H22, and H23. However, since internal voltage generation unit 280 does not start until a start instruction is received, it does not start only when DC voltage VD is supplied. In the H bridge circuits H21, H22, and H23, no current flows because no gate voltage is applied to the transistor switches.

  The DC voltage VD is 0V at the start of supply and gradually increases to the target voltage (31V). Then, when the DC voltage VD becomes 15 V or higher, the activation unit 280 activates the internal voltage generation unit 270. When activated, the internal voltage generator 270 generates an internal voltage Vin from the supplied DC voltage VD, and includes various digital circuits included in the determination unit 210 and the setting unit 220, a booster 290, and switching units 240 and 250. , 260 supplies the internal voltage Vin to various digital circuits. Various digital circuits are activated when the internal voltage Vin is supplied.

  The data control unit 221 reads the time T1 to be measured from the initial setting unit 222. Then, the read time is written into the counter unit 211. When the time is written, the counter unit 211 starts counting down in synchronization with the internal clock CLK2 (t1). The data control unit 220 refers to the initial setting unit 222 and reads an instruction to transmit the internal permission signal ENABLE20 indicating the DC / DC converter to the switching control unit 244a. And according to the read instruction | indication, the internal permission signal ENABLE20 which shows a DC / DC converter is output to the switching control part 244a. When the internal enable signal ENABLE20 indicating the DC / DC converter is input, the switching control unit 144a inputs the pulse voltage of the boosted voltage Vp to the transistor switch 246a at the switching frequency stored in the register included therein. Then, a pulse voltage having a switching frequency is input to the carriage motor 40. However, since the transistor switches 246b and 247b of the H bridge circuit to which the other end of the carriage motor 40 is connected are cut off, no current flows.

  On the other hand, when the counter unit 211 finishes counting the time T1, the state acquisition unit 212 determines whether or not a flag is set in the holding unit 213. If the state acquisition unit 212 determines that the flag is not set, the data control unit 221 writes that in a predetermined area of the operation setting unit 223. The operation setting unit 223 determines the internal enable signals ENBLE20 to 29 associated with the peripheral circuits connected to the H bridge circuits H21 to H23, which are uniquely determined when the state acquisition unit 212 is flagged and not present, respectively. Remember the combination. When the flag is not set, a motor is connected to the H bridge circuits H21, H22, and H23. Then, the data control unit 221 sends an internal permission signal ENABLE20 indicating the motor driver to the switching control unit 244a, an internal permission signal ENABLE21 indicating the motor driver to the switching control unit 244b, and an internal permission signal indicating the motor driver to the switching control unit 254a. ENABLE22, switching control unit 254b, internal permission signal ENABLE23 indicating a motor driver, switching unit 263a, internal permission signal ENABLE26 corresponding to the motor driver, switching unit 263b, internal permission signal ENABLE27 corresponding to the motor driver, switching control The internal permission signal ENABLE24 is output to the unit 264a, and the internal permission signal ENABLE25 is output to the switching control unit 264b.

<Effect of the first embodiment>
As described above, in the power management apparatus 100, the switching control unit 144a switches the transistor switches 146a and 147a included in the H bridge circuit H11 so that a voltage is supplied to the peripheral circuit 141a connected to the H bridge circuit H11. To control. The state acquisition unit 113 and the data control unit 121 are connected to the H bridge circuits H11, H12, and H13 depending on whether or not the voltage supplied to the peripheral circuit 141a is returned to the holding unit 113. Is determined. Then, the switching control units 144a, 144b, 154a, 154b, and the comparison circuits 168a, 168b perform control suitable for the peripheral circuits connected to H11, H12, and H13 determined by the state acquisition unit 113 and the data control unit 121. Internal permission signals ENABLE 10, 11, 12, 13, 18, and 19 are input so as to perform. The switching control units 144a, 144b, 154a, 154b and the comparison circuits 168a, 168b control the transistor switches 146a to 167b in accordance with the internal enable signals ENABLE10, 11, 12, 13, 18, 19.

  In the power management apparatus 200, the switching control unit 244a controls switching of the transistor switches 246a and 247a included in the H bridge circuit H21 so that a voltage is supplied to the peripheral circuit 241a connected to the H bridge circuit H21. Then, the state acquisition unit 213 and the data control unit 221 are connected to the H bridge circuits H21, H22, and H23 according to whether or not the voltage supplied to the peripheral circuit 241 is returned to the holding unit 213. Is determined. Then, the switching control units 244a to 264b perform internal control signals ENABLE2 to 25 so as to perform control suitable for the peripheral circuits connected to H21, H22, and H23 determined by the state acquisition unit 213 and the data control unit 221. Is entered. The switching controllers 244a to 268b control the transistor switches 146a to 167b in accordance with the internal permission signals ENABLE20 to 25.

  That is, both power management devices specify the peripheral circuit connected to the H bridge circuit included in each, and input the internal permission signal to the switching control unit or the comparison circuit so as to perform control suitable for the specified peripheral circuit. be able to. Therefore, the image forming apparatus 1 can selectively drive the H bridge circuit included in the power management apparatus without using a main control unit including a CPU or the like. For example, one of the power management device 100 and the power management device 200 can be used as a device that supplies power to the main control unit 20 and the other can be used as a motor driver.

  The switching control units 144a and 244a include transistor switches 146a and 147a and an H bridge circuit H21 included in the H bridge circuit H11 so that a pulse voltage is supplied to the peripheral circuits 141a and 241 connected to the H bridge circuits H11 and H21. The switching of the transistor switches 246a and 247a included in is controlled. The state acquisition unit 113, the data control unit 121, the state acquisition unit 213, and the data control unit 221 determine whether the pulse voltage is smoothed and returned to the holding units 113 and 213 according to whether or not the H bridge circuit H11, It is determined whether the peripheral circuit connected to H23 is a smoothing circuit and a voltage dividing circuit that constitute a switching regulator together with the H bridge circuit or a motor.

  That is, a voltage is actually supplied to the peripheral circuit, and the peripheral circuit is determined by feedback of the supplied voltage, so that the peripheral circuit can be accurately determined.

  The two combinations of the internal enable signals ENBLE10 to 19 stored in the operation setting unit 123 are associated with two combinations of peripheral circuits connected to the H bridge circuits H11 to H13, respectively. The same applies to the internal permission signals ENBLE 20 to 29 stored in the operation setting unit 223 included in the power management apparatus 200.

  That is, if a peripheral circuit connected to one H bridge circuit among the plurality of H bridge circuits included in the power management device is determined, it is possible to indirectly determine a peripheral circuit connected to another H bridge circuit. it can. Therefore, when the power management apparatus includes a plurality of H bridge circuits, the determination process for a plurality of peripheral circuits can be simplified.

<Second Embodiment>
In the above-described embodiment, when the feedback voltage Vf1 is input to the holding unit 113, the power management apparatus 100 has a peripheral circuit connected to the H bridge circuit H12 and the H bridge circuit H13 in addition to the H bridge circuit H11. Had decided. However, in the modification, the power management apparatus 100 further determines whether the peripheral circuit connected to the switching unit 160 is a motor or a voltage dividing circuit even when the feedback voltage Vf1 is input to the holding unit 113. Determine. Then, the operations of the transistor switches 166a, 167a, 166b, and 167b of the H bridge circuit H13 are made different according to the determined result.

  Since the image forming apparatus 1 according to the modification has substantially the same configuration as that of the above embodiment, only different points will be described. Unlike the above embodiment, the switching unit 160 is connected to the ADF motor 160. The terminal 100A is connected to the power supply unit. That is, the DC voltage VD is supplied to the H bridge circuit H13. The determination unit 110 included in the power management apparatus 100 further includes a second counter unit 314 and a VD / V1 recording unit 315. The internal clock CLK1 generated by the internal CLK generator 130 is input to the second counter unit 314. The second counter unit 314 includes a register, counts down the time written in the register in synchronization with the internal clock CLK1, and outputs a latch signal to the holding unit 3150 described later when the count reaches zero. Details of the VD / V1 recording unit 315 will be described below with reference to FIG.

  The VD / V1 recording unit 315 includes a second holding unit 3150, a comparison circuit 3151, and an internal REF generation unit 3152. The internal REF generator 3152 generates an internal reference voltage REF3 and inputs it to the comparison circuit 3151. The internal reference voltage REF3 is preferably between VD (31 V) and the voltage V1 (5 V), and is set to 10 V, for example. The comparison circuit 3151 is connected to the terminal 100A. That is, in the second embodiment, the DC voltage VD is supplied to the comparison circuit 3151. The comparison circuit 3151 compares the voltage supplied from the terminal 100A with the internal reference voltage REF3, and holds a signal indicating high when the voltage VD supplied from the terminal 100A is higher, and indicating low when the voltage VD is lower. To the part 3150. When a latch signal is input from the second counter unit 314, the second holding unit 3150 latches a signal indicating high or low input from the comparison circuit. The power management apparatus 200 includes the configuration of the power management apparatus 100. However, as shown in FIG. 12, the comparison circuit 4151 is connected to the terminal 200A.

<Second peripheral circuit discrimination processing>
Hereinafter, the second peripheral circuit determination process performed by the power management apparatus 100 will be described with reference to FIG. The second peripheral circuit determination process is performed in parallel with the peripheral circuit determination process described in the above embodiment. Therefore, the description overlapping with the peripheral circuit determination process is omitted.

  The data control unit 121 refers to the initial setting unit 122 and reads the time T2 that the second counter unit 314 should measure. Then, the read time is written into the second counter unit 314 (t1). When the time is written, the second counter unit 314 starts counting down in synchronization with the internal CLK1. Since the comparison circuit 3151 receives the DC voltage VD from the internal terminal 100 </ b> A, the comparison circuit 3151 inputs a signal indicating high to the holding unit 3150. When the count reaches 0 (t3), the second counter unit 314 inputs a latch signal to the second holding unit 3150. When the latch signal is input, the second holding unit 3150 latches data indicating high. The status acquisition unit 112 refers to the data latched in the second holding unit 3150 after referring to the holding unit 113. It is determined that data indicating high is latched in the second holding unit 3150. Then, the data control unit 121 writes that the flag is set in the holding unit 113 in a predetermined area of the operation setting unit 123 and that data indicating high is latched in the second holding unit 3150. Then, the data control unit 121 refers to the operation setting unit 123, and because the flag is set in the holding unit 113 and the data indicating high is latched in the second holding unit 3150, the data control unit 121 It is determined that the ADF motor 361 is connected. Then, the data control unit 121 sends an internal permission signal ENABLE10 indicating a DC / DC converter to the switching control unit 144a, an internal permission signal ENABLE11 indicating a DC / DC converter to the switching control unit 144b, and DC / DC to the switching control unit 154a. An internal permission signal ENABLE12 indicating a converter, an internal permission signal ENABLE13 indicating a DC / DC converter to the switching control unit 154b, an internal permission signal ENABLE14 to the switching control unit 164a, and an internal permission signal ENABLE16 corresponding to the motor driver to the switching unit 163a. The internal control signal ENABLE15 is output to the switching control unit 164b, and the internal control signal ENABLE17 corresponding to the motor driver is output to the switching unit 163b. In the second embodiment, when the peripheral circuit connected to the H bridge circuit H21 is a motor, the peripheral circuits of the H bridge circuit H22 and the H bridge circuit H23 are also motors. Therefore, if the flag is not set in the holding unit 213 (see FIG. 10B), the data stored in the second holding unit 4150 is not used to determine the peripheral circuit of the switching unit 260.

<Effects of Second Embodiment>
In the second embodiment, the state acquisition unit 112 and the data control unit 121 are configured such that the peripheral circuit connected to the H bridge circuit H11 forms a DC / DC converter together with the H bridge circuit (ie, the smoothing circuit and the separation circuit). If it is determined that the peripheral circuit connected to the H bridge circuit 13 is a peripheral circuit (that is, a voltage dividing circuit) that forms an LDO together with the H bridge circuit 13, it is further determined. Further, the peripheral circuit connected to the H bridge circuit 13 is determined based on whether the signal latched in the second holding unit 3150 is high or low. Therefore, in a power management device including a plurality of H bridge circuits, three or more combinations of peripheral circuits connected to each of the plurality of H bridge circuits can be provided.

<Modification>
In the first embodiment, the state acquisition unit 112, the data control unit 121, the state acquisition unit 212, and the data control unit 221 are the voltages supplied to the peripheral circuit 141a and the peripheral circuit 241 via the transistor switch 146a and the transistor switch 246a. Whether the peripheral circuit 141a and the peripheral circuit 241 are a smoothing circuit and a voltage dividing circuit that constitute a DC / DC converter together with an H bridge circuit or a motor depending on whether or not the feedback is returned to the holding unit 113 and the holding unit 213. It was determined. However, the peripheral circuit 141a and the peripheral circuit 241 may be configured to determine whether the peripheral circuit 141a and the peripheral circuit 241 are a voltage dividing circuit or a motor constituting the LDO together with the H bridge circuit.

  In the first embodiment, the H bridge circuit H11 depends on whether the voltage supplied to the peripheral circuit 141a and the peripheral circuit 241 via the transistor switch 146a and the transistor switch 246a is fed back to the holding unit 113 and the holding unit 213. And the peripheral circuit connected to the H bridge circuit H21 was determined. Further, the peripheral circuits of the switching units 150 and 160, the switching unit 250, and the switching 260 are indirectly connected due to the limitation of the combination of the determined peripheral circuit of the switching unit 140 and the switching unit 240 and the switching unit previously stored in the operation setting unit. Was estimated. However, all the switching units may be configured such that their peripheral circuits are discriminated based on the presence or absence of voltage feedback.

  In the second embodiment, in the power management apparatus 100, the H bridge circuit H11 and the H bridge circuit H12 are connected to peripheral circuits including a smoothing circuit and a voltage dividing circuit, and the H bridge circuit H13 includes an ADF motor 361 and a resistor. The peripheral circuit including the circuit is connected. However, as in the first embodiment, the peripheral circuit connected to the H bridge circuit H13 may be a voltage dividing circuit. In that case, the data control unit 121 refers to the operation setting unit 123, and since the flag is set in the holding unit 113 and the data indicating low is latched in the second holding unit 3150, the H bridge circuit It is determined that a smoothing circuit and a voltage dividing circuit are connected to H13.

  In the second embodiment, in the power management device 100, the H bridge circuit H13 includes a peripheral circuit including a motor and a resistor, and H, depending on whether the data latched in the second holding unit 3150 is high or low. The configuration is such that one of the voltage dividing circuits that form the LDO together with the bridge circuit H13 is determined. However, a configuration may be employed in which one of a peripheral circuit including a motor and a resistor, and a smoothing circuit and a voltage dividing circuit that form a DC / DC converter together with the H bridge circuit H13 may be used.

  The number of H bridge circuits included in the ICs constituting both power management apparatuses 100 and 200 may be less than three, or four or more. Further, the number of ICs functioning as a power management device may be one, or three or more. However, in any case, the initial setting unit, the operation setting unit, and the switching control unit need to store corresponding settings.

  The power management devices 100 and 200 are examples of the IC in the present invention. The H bridge circuits H11 to H23 are examples of the H bridge circuit. Transistor switch 146a, 147a, transistor switch 146b, 147b, transistor switch 156a, 157a, transistor switch 156b, 157b, transistor switch 166a, 167a, transistor switch 166b, 167b, transistor switch 246a, 247a, transistor The switches 246b and 247b, the transistor switches 256a and 257a, the transistor switches 256b and 257b, the transistor switches 266a and 267a, and the transistor switches 266b and 267b are examples of transistor pairs. The switching control units 144a to 264b and the comparison circuits 168a, 168b, 268a, 268b are examples of the transistor control unit. The initial setting units 122 and 222 are an example of a first setting storage unit. The operation setting units 123 and 223 are an example of a second setting storage unit. The peripheral circuits 141a to 161b and the peripheral circuits 241 to 261 are examples of the peripheral circuits. The state acquisition unit 113 and the data control unit 121, and the state acquisition unit 213 and the data control unit 221 are examples of the first determination unit.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 100 Power supply management apparatus 200 Power supply management apparatus 140 Switching unit 150 Switching unit 160 Switching unit 240 Switching unit 250 Switching unit 260 Switching unit

Claims (5)

One or more H bridge circuits configured to be connectable to each of a plurality of types of peripheral circuits and connected to at least one of the plurality of types of peripheral circuits;
A transistor controller that controls each of a plurality of transistor pairs provided in each of the one or more H-bridge circuits;
With respect to at least one first H bridge circuit among the one or more H bridge circuits, the initial control performed by the transistor control unit for at least one of the plurality of transistor pairs provided in the first H bridge circuit. A first setting storage unit for storing settings;
The transistor control unit relates to control performed on each of the plurality of transistor pairs provided in at least one of the H bridge circuits including the first H bridge circuit after the control according to the setting stored in the first setting storage unit. A second setting storage unit that stores a plurality of settings in association with each of a plurality of types of peripheral circuits;
An electrical circuit including an IC having a first determination unit for determining the peripheral circuit connected to at least one of the H bridge circuits including the first H bridge circuit,
When the electric circuit supplies a voltage to the IC, the transistor control unit supplies a voltage to a peripheral circuit connected to the first H bridge circuit according to the setting stored in the first setting storage unit. Controlling at least one of the plurality of transistor pairs included in the first H-bridge circuit;
The first discriminating unit is responsive to the presence or absence of feedback of the voltage supplied to the peripheral circuit connected to the first H bridge circuit under the control of the transistor control unit according to the settings stored in the first setting storage unit. Determining the peripheral circuit connected to at least one of the H bridge circuits including the first H bridge circuit;
The transistor control unit includes a peripheral circuit specified by the first determination unit for each of a plurality of transistor pairs included in one or a plurality of the H-bridge circuits whose peripheral circuit is specified by the first determination unit. An electric circuit that performs control according to the setting stored in the second setting storage unit in association with
The first discriminating unit is responsive to the presence or absence of feedback of the voltage supplied to the peripheral circuit connected to the first H bridge circuit under the control of the transistor control unit according to the settings stored in the first setting storage unit. A peripheral circuit connected to at least the first H-bridge circuit, a motor, or a first peripheral circuit that forms a switching regulator together with one of the plurality of transistor pairs included in the first H-bridge circuit; and 2. The electric circuit according to claim 1, wherein the electric circuit is determined to be any one of a second peripheral circuit constituting a linear regulator together with at least one of the plurality of transistor pairs included in the 1H bridge circuit.
The first setting storage unit includes at least one of the plurality of transistor pairs included in the first H bridge circuit in the transistor control unit so that a pulse voltage is supplied to the peripheral circuit connected to the first H bridge circuit. Remembers the settings to control the switching of the pair,
The first determination unit is connected to at least the first H bridge circuit according to the presence or absence of feedback of the voltage supplied to the peripheral circuit under the control of the transistor control unit according to the setting stored in the first storage unit. The peripheral circuit is determined to be either a motor or a first peripheral circuit constituting a switching regulator together with one of the plurality of transistor pairs provided in the first H bridge circuit. The electric circuit according to 1.
The IC is
At least one first H-bridge circuit and at least one second H-bridge circuit which is the H-bridge circuit different from the first H-bridge circuit;
The plurality of second setting storage units are included in the first H bridge circuit and the second H bridge circuit, which are associated with a combination of peripheral circuits predetermined for the first H bridge circuit and the second H bridge circuit. A plurality of setting groups including a plurality of the settings to be made for each of the transistor pairs are stored in association with each of the plurality of combinations,
The first determination unit is connected to the first H bridge circuit in accordance with the presence or absence of feedback of the voltage supplied to the peripheral circuit under the control of the transistor control unit according to the setting stored in the first setting storage unit. Discriminate the peripheral circuit,
The transistor control unit is a setting group stored in the second storage unit, and is associated with the combination including the peripheral circuit determined by the first determination unit as a peripheral circuit of the first H bridge circuit. The control according to the plurality of settings included in the setting group is performed on each of the plurality of transistor pairs included in the first H bridge circuit and the second H bridge circuit. The electric circuit according to claim 1.
The IC is
The third H bridge circuit different from the first H bridge circuit;
A second discriminating unit for discriminating a peripheral circuit connected to the third H bridge circuit;
The second determination unit includes:
A voltage supply is received from a terminal provided in the IC for supplying a voltage to the third H bridge circuit,
The peripheral circuit connected to the third H bridge circuit depending on whether the voltage supplied from the terminal is the same voltage as the voltage supplied to the IC or a voltage lower than the voltage supplied to the IC At least one pair of a plurality of transistor pairs included in a first peripheral circuit that constitutes a switching regulator together with one of the plurality of transistor pairs included in the motor or the third H bridge circuit, and the third H bridge circuit Together with the second peripheral circuit constituting the linear regulator,
The transistor control unit is a setting related to control performed on each of the plurality of transistor pairs included in the third H bridge circuit stored in the second setting storage unit, and the peripheral determined by the second determination unit 5. The electric circuit according to claim 1, wherein switching of a plurality of transistor pairs included in the third H bridge circuit is controlled according to a setting associated with the circuit. 6.

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