JP6159130B2 - Semiconductor light emitting device - Google Patents

Description

  The present invention relates to a semiconductor light emitting device, and more particularly to a semiconductor light emitting device having a via structure.

  A semiconductor light emitting device using a nitride semiconductor such as GaN can emit ultraviolet light or blue light, and can emit white light by using a phosphor. Such a semiconductor light emitting element is used for illumination, for example.

  The semiconductor light emitting device is, for example, an n-type GaN layer, an optical semiconductor laminate in which a light emitting active layer and a p-type GaN layer are laminated, and a voltage is applied to the optical semiconductor laminate in contact with the n-type and p-type GaN layers. And an electrode that can. Semiconductor light emitting devices are classified into a counter electrode type, a flip chip type, a junction down type, a via type, and the like according to the structure and arrangement position of the electrodes.

  In order to improve the light extraction efficiency (= the emission intensity emitted from the surface of the optical semiconductor layer / the electric power input to the optical semiconductor layer) of the semiconductor light emitting device, the electrode generally includes a member having a high light reflectance, such as Ag. An Ag alloy or the like is used. However, such an electrode tends to cause so-called migration, which may lead to problems relating to reliability, such as an electrical short circuit or leakage of the semiconductor light emitting element.

  In order to suppress migration, it is desirable to provide a cap layer (migration prevention layer) that covers the entire surface of the electrode. The cap layer includes, for example, a refractory metal or a metal nitride (for example, Patent Document 1).

JP 2008-192882 A

    An object of the present invention is to provide a via-type semiconductor light emitting device using a member such as Ag that easily causes migration in an electrode, and capable of effectively suppressing migration of the electrode. .

According to a main aspect of the present invention, a support substrate, and a first semiconductor layer that is disposed on the support substrate and includes at least a first-conductivity-type GaN-based semiconductor from the support substrate side, has light emitting properties. , An active layer containing a GaN-based semiconductor, and a second semiconductor layer containing a GaN-based semiconductor of a second conductivity type different from the first conductivity type, and the first semiconductor layer facing the support substrate And an optical semiconductor stack in which the first semiconductor layer and the active layer are excavated, and the second semiconductor layer includes a concave region facing the support substrate , the concave region in the plan view An optical semiconductor stack formed so as to be surrounded by a convex region, and a first semiconductor layer of the optical semiconductor multilayer disposed between the support substrate and the convex region of the optical semiconductor multilayer and in contact with the first semiconductor layer. One electrode and the first electrode are disposed so as to cover the first electrode. From electrode side, a transparent conductive layer containing light-transmitting member, and a metal conductive layer comprising a metal member is alternately laminated, a capping layer made of at least two layers of the multilayer structure is disposed on the innermost side The transparent conductive layer includes a cap layer formed so as not to contact the first semiconductor layer of the optical semiconductor stack, and a first layer of the optical semiconductor stack between the support substrate and the concave region of the optical semiconductor stack. There is provided a semiconductor light emitting device including the cap layer and a second electrode disposed in contact with the two semiconductor layers and at an interval smaller than 10 μm .

  A semiconductor light-emitting element that can effectively suppress electrode migration can be obtained.

and, 1A to 1D are a cross-sectional view and a plan view showing an LED element according to an embodiment. , , and, 2A to 2K are cross-sectional views illustrating how the LED element according to the embodiment is manufactured. 3A to 3C are cross-sectional views showing modifications of the LED element according to the embodiment. 4A and 4B are a cross-sectional view and a plan view showing another modification of the LED element according to the embodiment.

  Hereinafter, a configuration of a via type semiconductor light emitting device (LED device) according to an embodiment of the present invention will be described with reference to FIG.

  1A to 1D are a cross-sectional view and a plan view showing a via-type LED element 100 according to an embodiment. 1A is a cross-sectional view showing a cross-section IA-IA in FIG. 1C. FIG. 1B is an enlarged cross-sectional view of the region IB in FIG. 1A. In addition, the relative size of each component shown in the drawing is different from the actual one.

  FIG. 1A shows an overall cross-sectional structure of the LED element 100. The LED element 100 mainly includes a support substrate 12, an optical semiconductor stack 20, a first electrode (p-side electrode) 30, a cap layer (migration prevention layer) 40, and a second electrode (n-side electrode) 60. It is the structure containing these.

  The support substrate 12 is composed of a member having excellent heat dissipation (high thermal conductivity), for example, Si having electrical conductivity. An extraction electrode 12a is provided on the back surface of the support substrate 12 (the lower surface in the drawing).

  The optical semiconductor stack 20 is disposed above the support substrate 12 and has a multilayer structure in which at least the p-type semiconductor layer 25, the active layer (light-emitting layer) 24 having light emitting properties, and the n-type semiconductor layer 23 are stacked from the support substrate 12 side. Have. Further, the convex region 20 a where the p-type semiconductor layer 25 faces the support substrate 12, and the p-type semiconductor layer 25 and the active layer 24 are excavated (etched), and the n-type semiconductor layer 23 is a concave portion facing the support substrate 12. It has a region (via) 20b.

Each layer of the optical semiconductor stack 20 is composed of a GaN-based semiconductor represented by Al _x In _y Ga _z N (x + y + z = 1). The p-type semiconductor layer 25 and the n-type semiconductor layer 23 are made of, for example, p-type GaN and n-type GaN, respectively. The active layer 24 has a multiple quantum well structure including, for example, a barrier layer containing GaN and a well layer containing InGaN.

  The optical semiconductor stack 20 is not limited to such a configuration. For example, the optical semiconductor stack 20 may include a cladding layer (electron block layer) made of AlGaN between the p-type semiconductor layer 25 and the active layer 24. Further, for example, a structure including a superlattice structure layer (strain relaxation layer) in which GaN and InGaN are stacked may be provided between the active layer 24 and the n-type semiconductor layer 23. Furthermore, a so-called microcone structure layer (fine concavo-convex layer) may be formed on the surface of the n-type semiconductor layer 23 (upper surface in the drawing).

  The first electrode (p-side electrode) 30 is disposed in contact with the p-type semiconductor layer 25 between the support substrate 12 and the convex region 20 a of the optical semiconductor stack 20. The p-side electrode 30 includes a member having a high light reflectance, such as Ag or an Ag alloy, and a laminated structure including them.

  The cap layer 40 is disposed so as to cover the p-side electrode 30. By covering the p-side electrode 30 containing Ag or the like that easily causes migration with the cap layer 40, migration of the p-side electrode 30 can be suppressed. The cap layer 40 has a laminated structure including, for example, indium tin oxide (ITO) and TiW.

  The second electrode (n-side electrode) 60 is disposed in contact with the n-type semiconductor layer 23 between the support substrate 12 and the recessed region 20 b of the optical semiconductor stack 20. The n-side electrode 60 includes, for example, Al or Ti.

  The optical semiconductor multilayer 20, the p-side electrode 30, the cap layer 40, and the n-side electrode 60 are fixed on the support substrate 12 via a fusion layer 70 including first and second bonding layers 71 and 72. The fusion layer 70 (first and second bonding layers 71 and 72) has electrical conductivity and is electrically connected to the n-side electrode 60. That is, the n-side electrode 60 is electrically connected to the extraction electrode 12a through the fusion layer 60 and the support substrate 12.

Between the n-side electrode 60 and the fusion layer 70, the p-side electrode 30, the cap layer 40, and the p-type semiconductor layer 25 and the active layer 24 at the boundary between the convex region 20a and the concave region 20b, Is provided with an insulating layer 50 made of SiO ₂ or the like.

  FIG. 1B shows the vicinity of the convex region 20a / concave region 20b boundary of the optical semiconductor stack 20.

  The p-side electrode 30 has, for example, a two-layer structure in which a contact electrode 31 and a light reflecting electrode 32 are stacked from the optical semiconductor stacked layer 20 (p-type semiconductor layer 25) side. Contact electrode 31 is in ohmic contact with p-type semiconductor layer 25, and includes a member having conductivity and translucency, such as ITO. The light reflecting electrode 32 is disposed so as to cover the contact electrode 31 and includes a member having high light reflectance, such as Ag or an Ag alloy. The cross-sectional shape of the p-side electrode 30 (contact electrode 31 and light reflecting electrode 32) is a forward taper shape with respect to the optical semiconductor stack 20 (a shape in which the cross-sectional area decreases as the distance from the optical semiconductor stack 20 increases). It has a reverse taper shape with respect to the support substrate 12).

  The cap layer 40 is disposed so as to cover the p-side electrode 30 and has a multilayer structure in which transparent conductive layers 41 and metal conductive layers 42 are alternately stacked from the p-side electrode 30 side. For example, the first transparent conductive layer 41a, the first metal conductive layer 42a, the second transparent conductive layer 41b, and the second metal conductive layer 42b are stacked from the p-side electrode 30 side. The cross-sectional shape of the cap layer 40 (the transparent conductive layer 41 and the metal conductive layer 42) is a shape corresponding to the cross-sectional shape of the p-side electrode 30.

  The transparent conductive layer 41 includes, for example, ITO or ZnO made of a microcrystalline body or an amorphous body. Here, the microcrystalline body has an extremely small size of crystallites (maximum group that can be regarded as a single crystal), and specifically, it is 50 nm or less when measured by an X-ray diffraction method (Scherrer method). Let's say crystal. For the metal conductive layer 42, for example, a metal such as Pt, Ti, TiW, or TiN, an alloy thereof, or a metal nitride can be used.

  When the cap layer 40 is composed only of the metal conductive layer 42 (first and second metal conductive layers 42a and 42b), migration of the p-side electrode 30 containing Ag can be satisfactorily suppressed. However, there is a possibility that the cap layer (metal conductive layer 42) is distorted and broken (cracked) due to heat treatment performed when the LED element 100 is manufactured or heat generated when the LED element 100 is driven. Thereby, the effect (cap performance) of suppressing the migration of the p-side electrode 30 may be reduced.

  When the cap layer 40 is composed of only the transparent electrode layer 41 (first and second transparent conductive layers 41a and 41b), the cap layer (transparent electrode layer 41) is composed of a microcrystalline body or an amorphous body. Therefore, breakage due to heat distortion such as heat treatment or heat generation is relatively difficult to occur. However, the cap layer composed only of the transparent conductive layer 41 originally has a lower cap performance than the cap layer composed only of the metal conductive layer 42.

  When the cap layer 40 has a multilayer structure in which the transparent conductive layer 41 and the metal conductive layer 42 are alternately stacked as in the embodiment, the transparent conductive layer 41 relieves the thermal strain applied to the metal conductive layer 42 and the metal conductive layer 42 supplements the cap performance degradation due to the transparent conductive layer 41. By adopting such a structure for the cap layer 40, the cap performance is improved, and migration of the p-side electrode 30 containing Ag can be effectively suppressed.

  The cap layer 40 may have a two-layer structure in which the transparent conductive layer 41 and the metal conductive layer 42 are stacked, that is, a two-layer structure including the first transparent conductive layer 41a and the first metal conductive layer 42a. . Further, a transparent conductive layer 41 is further laminated, and the transparent conductive layer 41 sandwiches the metal conductive layer 42, that is, the first transparent conductive layer 41a, the first metal conductive layer 42a, and the second transparent conductive layer 41b. It may be a three-layer structure. Furthermore, a multilayer structure in which the metal conductive layer 42 and the transparent conductive layer 41 are alternately stacked from the p-side electrode 30 side may be used. In short, as long as the transparent conductive layer 41 and the metal conductive layer 42 are stacked, the number of stacks and the stacking order may be any. However, as shown in the examples, the cap layer 40 is formed into a multilayer structure of four or more layers in which the transparent conductive layer 41 and the metal conductive layer 42 are alternately stacked from the p-side electrode 30 side, thereby allowing the p-side containing Ag. Migration of the electrode 30 can be more effectively suppressed.

  The layer thickness of the transparent conductive layer 41 is preferably at least 10 nm or more. When the thickness of the transparent conductive layer 41 is less than 10 nm, the effect of reducing the thermal strain applied to the metal conductive layer 42 is reduced.

  From the viewpoint of improving the light extraction efficiency of the LED element 100, the n-side electrode 60 preferably includes a light reflective member, such as Al. However, Al, like Ag, is a member that easily undergoes migration. Therefore, a cap layer 71 a that covers the n-side electrode 60 containing Al and suppresses migration of the n-side electrode 60 may be provided. At this time, the cap layer 71 a may be configured as a part of the first bonding layer 71. Further, similarly to the cap layer 40 that suppresses migration of the p-side electrode 30, a multilayer structure in which transparent conductive layers and metal conductive layers are alternately stacked may be employed.

  1C and 1D show the overall planar shape of the LED element 100. FIG. FIG. 1C mainly shows the overall planar shape of the optical semiconductor stack 20, and FIG. 1D mainly shows the overall planar shape of the cap layer 40 (or the p-side electrode 30) and the n-side electrode 60. 1C corresponds to the cross-sectional view shown in FIG. 1A. In FIG. 1D, the optical semiconductor stack 20 is indicated by a broken line.

  As shown in FIG. 1C, the planar shape of the optical semiconductor stack 20 is a shape in which a square having a side of about 1 mm is partially cut away. The cap layer 40 (or the p-side electrode 30) is exposed from the part of the optical semiconductor stack 20 that is cut away (exposed portion 40e of the cap layer 40).

  The concave region 20b (region surrounded by the broken line in the figure) of the optical semiconductor stack 20 is, for example, a circular shape, and is formed so as to be surrounded by the convex region 20a of the optical semiconductor stack 20. Further, they are provided so as to be distributed uniformly in the surface of the optical semiconductor laminate 20, for example, in a 3 × 3 matrix. The planar shape of the recessed region 20b is not limited to a circular shape, and may be an elliptical shape or a rectangular shape. When the maximum width in the planar shape of the recessed region 20b is defined as the diameter, the diameter is, for example, about 40 μm.

  Note that the size, shape, distribution density, and the like of the concave region 20b (or the convex region 20a) affect the light emission intensity or luminance unevenness of the LED element 100. It is desirable to appropriately adjust the size, shape, distribution density, and the like of the recessed region 20b (or the protruding region 20a) according to the application of the LED element 100.

  As shown in FIG. 1D, the n-side electrode 60 (a region indicated by a hatched pattern with a relatively narrow pitch in the drawing) is, for example, a circular shape, and corresponds to the recessed region 20b (see FIG. 1C) of the optical semiconductor stack 20, respectively. It is arranged at the position to do.

  The cap layer 40 (the region indicated by the oblique line pattern having a relatively wide pitch in the figure) has the n-side electrode 60 (or the concave region 20b) at a position corresponding to the convex region 20a (see FIG. 1C) of the optical semiconductor stack 20. It is patterned to include a circular opening 40h that can be viewed. The distance between the cap layer 40 and the n-side electrode 60 disposed in the opening 40h is, for example, 10 μm or less, specifically about 2 to 3 μm. Note that the planar shape of the opening 40h is not limited to a circular shape, and may be an elliptical shape or a rectangular shape. When the maximum width in the planar shape of the opening 40 h is defined as the diameter, the diameter is about several μm larger than the diameter of the concave region 20 b of the optical semiconductor stack 20.

  Light is supplied to the active layer 24 by supplying electric power from the exposed portion 40e of the cap layer 40 and the extraction electrode 12a, that is, by passing a current between the p-type semiconductor layer 25 and the n-type semiconductor layer 23 of the optical semiconductor stack 20. Occurs (see FIG. 1A). In the light emitted from the active layer 24, a part is directly emitted from the surface of the n-type semiconductor layer 53, and the other part is reflected by the p-side electrode 30 (particularly the light reflecting electrode 32) or the n-side electrode 60. Thereafter, the light is emitted from the surface of the n-type semiconductor layer 53 (see FIG. 1A).

  Hereinafter, the manufacturing method of the LED element 100 will be described with reference to FIG. 2A to 2G are cross-sectional views showing how the LED element 100 is manufactured, and are cross-sectional views showing the vicinity of the boundary between the convex region 20a and the concave region 20b of the optical semiconductor laminate 20. FIG. 2H to 2K are cross-sectional views showing the entire LED element 100 after the step shown in FIG. 2G.

  First, as shown in FIG. 2A, a growth substrate 11 made of a C-plane sapphire substrate is prepared, and an optical semiconductor stack 20 made of a GaN-based semiconductor is formed using a metal organic chemical vapor deposition (MOCVD) method. Specifically, first, the growth substrate 11 is thermally cleaned to grow a low-temperature buffer layer 21 and a base layer 22 made of GaN. Subsequently, an n-type semiconductor layer 23 made of n-type GaN doped with Si or the like, an active layer (light emitting layer) 24 made of a multiple quantum well structure including a well layer (InGaN) and a barrier layer (GaN), and Mg etc. An optical semiconductor stack 20 is grown by sequentially stacking p-type semiconductor layers 25 made of p-type GaN doped with.

  The growth substrate 11 is a single crystal substrate having a lattice constant matching with the GaN crystal, and is 362 nm which is an absorption edge wavelength of the GaN crystal so that the growth substrate can be peeled off in a subsequent laser lift-off process (see FIG. 2I). Selected from those transparent to light. In addition to sapphire, spinel, ZnO, or the like can be used.

  In the optical semiconductor stack 20, a strain relaxation layer having a superlattice structure including an InGaN layer and a GaN layer may be grown between the n-type semiconductor layer 23 and the active layer 24. Furthermore, a clad layer made of p-type AlGaN may be grown between the active layer 24 and the p-type semiconductor layer 25.

  Next, as shown in FIG. 2B, a p-side electrode 30 having a desired shape is formed on the surface of the optical semiconductor laminate 20 (the surface of the p-type semiconductor layer 25).

  First, an ITO film having a thickness of 10 nm is formed by an electron beam evaporation method, a sputtering method, or the like, and patterned by a photolithography method, a lift-off method, or the like to form a contact electrode 31 having a predetermined shape. As the contact electrode 31, other than ITO, Ni, Pt, Pd, or the like can be used. In the case where a translucent member such as ITO is used for the contact electrode 31, it is preferable to heat-treat the contact electrode 31 in order to improve the contact property with the p-type semiconductor layer 25.

  Thereafter, an Ag film having a film thickness of 200 nm is formed on the optical semiconductor stack 20 and the contact electrode 31 by an electron beam evaporation method, a sputtering method, or the like, and is patterned by a photolithography method, a lift-off method, or the like to cover the contact electrode 31. The light reflecting electrode 32 is formed. As the light reflecting electrode 32, Ag alloy or the like can be used in addition to Ag.

  As described above, the p-side electrode 30 including the contact electrode 31 and the light reflecting electrode 32 is formed. Note that the overall cross-sectional structure of the p-side electrode 30 is forward tapered with respect to the optical semiconductor stack 20. Further, the overall planar shape of the p-side electrode 30 is, for example, the shape shown in FIG. 1D.

  Next, as shown in FIG. 2C, a cap layer 40 that covers the p-side electrode 30 is formed. The cap layer 40 has, for example, a four-layer structure in which transparent conductive layers 41 and metal conductive layers 42 are alternately stacked.

  First, on the optical semiconductor stack 20 and the p-side electrode 30, a film thickness of 50 nm made of a microcrystal or an amorphous body having a crystallite size of 50 nm or less is formed by electron beam evaporation or sputtering. An ITO film is formed. Subsequently, the ITO film is patterned by a lift-off method or the like to form a first transparent conductive layer 41 a that covers the p-side electrode 30.

  Thereafter, a TiW film having a thickness of 100 nm is formed on the optical semiconductor stack 20 and the first transparent conductive layer 41a by an electron beam evaporation method, a sputtering method, or the like. Subsequently, the TiW film is patterned by a lift-off method or the like to form a first metal conductive layer 42a that covers the first transparent conductive layer 41a.

  Thereafter, the same process is alternately repeated to sequentially form the second transparent conductive layer 41b and the second metal conductive layer 42b. The cap layer 40 may have a two-layer structure in which the transparent conductive layer 41 and the metal conductive layer 42 are stacked, or may have a multilayer structure in which six or more layers are stacked alternately. The number and order of lamination of the transparent conductive layer 41 and the metal conductive layer 42 can be changed as appropriate.

  In order for the transparent conductive layer 41 (ITO film) to include a microcrystalline body or an amorphous body, the film forming temperature of the ITO film should be 200 ° C. or less and the film thickness of the ITO film should be 100 nm or less. preferable. In light of thermal strain relaxation of the metal conductive layer 42, the thickness of the transparent conductive layer 41 is preferably about 10 nm to 100 nm.

  As the transparent conductive layer 41, a conductive oxide such as ZnO can be used in addition to ITO. However, depending on the member used for the transparent conductive layer 41, the manufacturing conditions for the transparent electrode layer 41 to include a microcrystalline body or an amorphous body are different. For this reason, it is desirable to adjust manufacturing conditions, such as growth temperature and growth time (film thickness) suitably, according to the member used for the transparent conductive layer 41.

  The layer thickness of the metal conductive layer 42 is preferably thicker than the layer thickness of the transparent conductive layer 41, and may be about twice the layer thickness of the transparent conductive layer 41. The surface of the transparent conductive layer 41 composed of a microcrystalline body or an amorphous body has a relatively low flatness. By setting the thickness of the metal conductive layer 42 to about twice the layer thickness of the transparent conductive layer 41, the undulations on the surface of the transparent conductive layer 41 are absorbed by the metal conductive layer 42, and the surface of the metal conductive layer 42 is flat. It will be relatively high.

  As the metal conductive layer 42, in addition to TiW, Pt, Ti or an alloy thereof, metal nitride, or the like can be used. Further, a stacked structure in which a plurality of Ti layers, Pt layers, or the like are stacked can also be used. In order to improve the adhesion between the metal conductive layer 42 and the transparent conductive layer 41, it is preferable to use a sputtering method for forming the metal conductive layer 42 (TiW film).

  Thus, the cap layer 40 in which the transparent conductive layers 41 and the metal conductive layers 42 are alternately stacked is formed. The total thickness of the cap layer 40 is preferably thicker than the total thickness of the p-side electrode 30 from the viewpoint of improving the cap performance, and is 1.5 times the thickness of the p-side electrode 30 or more. More preferably.

  Next, as shown in FIG. 2D, a region where the p-side electrode 30 and the cap layer 40 are not formed in the optical semiconductor stack 20 is etched by a dry etching method using a resist mask and chlorine gas, and the via 20d is formed. Form. The via 20d is formed through the p-type semiconductor layer 25 and the active layer 24, and the n-type semiconductor layer 23 is exposed on the bottom surface of the via 20d. Thereby, a concave region 20b corresponding to the via 20d and a convex region 20a which is a region other than the concave region 20b are defined in the optical semiconductor stack 20 (see FIG. 1C).

Next, as shown in FIG. 2E, an insulating layer 50 that covers the side surfaces of the cap layer 40 and the convex region 20a of the optical semiconductor stack is formed. First, an SiO ₂ film having a thickness of 900 nm is formed on the convex region 20a and the concave region 20b of the optical semiconductor stack 20 and the cap layer 40 by sputtering or the like. Subsequently, the SiO ₂ film located at the bottom portion of the recessed region 20b (via 20d) is etched by a dry etching method using a resist mask and a CF 4 / Ar mixed gas, thereby forming the insulating film 50. At this time, the n-type semiconductor layer 23 is exposed on the bottom surface of the recessed region 20b (via 20d).

Next, as illustrated in FIG. 2F, the n-side electrode 60 that contacts the n-type semiconductor layer 23 is formed in the recessed region 20 b of the optical semiconductor stack 20. First, a metal multilayer film made of Ti / Al / Ti / Pt / Au is formed on the surface of the insulating layer 50 and the region where the n-type semiconductor layer 23 in the concave region 20b is exposed by an electron beam vapor deposition method or a sputtering method. To do. Subsequently, the metal multilayer film is patterned by a lift-off method or the like to form a columnar n-side electrode 60. The member used for the n-side electrode 60 desirably has a low contact resistance, for example, 1 × 10 ⁻⁴ Ωcm ² or less, and preferably has light reflectivity.

  Next, as shown in FIG. 2G, a first bonding layer 71 that covers the insulating layer 50 and the n-side electrode 60 is formed. First, a Ti / Pt / Au laminated film is formed on the insulating layer 50 and the n-side electrode 60 by a sputtering method or the like, and is patterned by a lift-off method or the like to form the first bonding layer 71.

  Note that the first bonding layer 71 only needs to have an Au layer as the uppermost layer. Below the Au layer, Pt, Ti, W and their alloys, metal nitrides such as TaN, ITO, etc. A conductive oxide or the like can be disposed. Further, the first bonding layer 71 may include a cap layer 71 a that suppresses migration of the n-side electrode 60. As with the cap layer 40, the cap layer 71a may have a multilayer structure in which transparent conductive layers (ITO) and metal conductive layers (TiW) are alternately stacked.

  Hereinafter, for convenience, a structure in which the layers from the optical semiconductor stack 20 to the first bonding layer 71 are formed on the growth substrate 11 is referred to as a device structure 101.

  Next, as shown in FIG. 2H, a part of the optical semiconductor stack 20 is etched by a dry etching method using a resist mask and chlorine gas to divide the optical semiconductor stack 20 into a desired size. For example, a part of the optical semiconductor stack 20 is etched so that each of the divided optical semiconductor stacks 20 has a square shape with a side of about 1 mm in plan view (see FIG. 1C).

  Next, as illustrated in FIG. 2I, a support substrate 12 having a second bonding layer 72 having a desired shape formed on the surface is prepared, the support substrate 12 and the device structure 101 are bonded, and the bonded structure 102 is Form. Then, as shown in FIG. 2J, the growth substrate 11 is peeled and removed from the bonded structure 102 to expose the surface of the n-type semiconductor layer 23 of the optical semiconductor stack 20.

  First, the support substrate 12 having the second bonding layer 72 formed on the surface is prepared.

For the support substrate 12, a member having a thermal expansion coefficient close to that of sapphire (7.5 × 10 ⁻⁶ / K) or GaN (5.6 × 10 ⁻⁶ / K) is preferably used. For example, Si, Ge, Mo, CuW, AlN, etc. can be used.

  The second adhesive layer 72 includes a metal multilayer film made of, for example, Ti / Ni / Au / Pt / AuSn (Sn: 20 wt%). Note that members used for the first bonding layer 71 and the second bonding layer 72 (the uppermost film of the metal multilayer film) are Au-Sn, Au-In, Pd-In, Cu-In, which can be fusion bonded. A metal containing Cu—Sn, Ag—Sn, Ag—In, Ni—Sn, or the like, or a metal containing Au capable of diffusion bonding can be used.

  Thereafter, the prepared support substrate 12 and the device structure 101 are arranged so that the first and second bonding layers 71 and 72 are in contact with each other, and held for 10 minutes while being heated to 300 ° C. while being pressurized at 3 MPa. To do. Then, it cools to room temperature and the 1st, 2nd contact bonding layers 71 and 72 are fusion-bonded (fusion layer 70). Thereby, the bonded structure 102 is formed.

Thereafter, the growth substrate 11 is removed from the bonded structure 102 by a laser lift-off method. Specifically, the bonded structure 102 is irradiated with KrF excimer laser light (wavelength: 248 nm, irradiation energy density: 800 to 900 mJ / cm ² ) from the growth substrate 11 side, and one of the buffer layer 21 and the base layer 22 is irradiated. Pyrolyze part. As a result, the growth substrate 11 and the optical semiconductor stack 20 are separated, and the growth substrate 11 is removed from the bonded structure 102. Note that the growth substrate 11 may be removed by etching or polishing.

  Thereafter, Ga generated by thermal decomposition of the buffer layer 21 and the underlayer 22 (GaN crystal) is removed with hot water or the like, and the surface of the optical semiconductor stack 20 (underlayer 22 and n-type semiconductor layer 23 with hydrochloric acid, sodium hydroxide, or the like). Etch part of). As a result, as shown in FIG. 2J, the n-type semiconductor layer 23 of the optical semiconductor stack 20 is exposed. The removal of the base layer and part of the n-type semiconductor layer 23 may be performed by dry etching or polishing using Ar plasma or chlorine plasma.

  Next, as shown in FIG. 2K, a part of the optical semiconductor stack 20 is etched by a dry etching method using a resist mask and chlorine gas to expose a part of the cap layer 40 (exposed portion 40e). Thereafter, an extraction electrode 12 a is formed on the back surface of the support substrate 12. The extraction electrode 12a is formed by sequentially depositing Pt / Ti / Pt / Au using, for example, an electron beam vacuum deposition method. Finally, the support substrate 12 is divided by laser scribing or dicing.

A so-called microcone structure layer 23mc may be formed on the surface of the n-type semiconductor layer 23 of the optical semiconductor stack 20. When the microcone structure layer 23mc is formed on the surface of the n-type semiconductor layer 23, for example, the surface of the n-type semiconductor layer 23 is made of a TMAH (phenyltrimethylammonium hydroxide) aqueous solution (temperature of about 70 ° C., concentration of about 25%). Wet etching may be performed by the above. Further, a surface protective film 80 made of SiO ₂ or the like may be formed on the n-type semiconductor layer 23 (microcone structure layer 23mc).

  Thus, the LED element 100 is completed.

  In the cap layer 40, thermal strain due to heat treatment and heat generation occurs significantly at the interface with the p-side electrode 30 (light reflecting electrode 32). Accordingly, the innermost layer of the cap layer is preferably provided with the transparent conductive layer 41 (first transparent conductive layer 41 a) that reduces thermal strain, and is preferably provided in wide contact with the p-side electrode 30. However, according to further studies by the present inventors, when the transparent conductive layer 41 (first transparent conductive layer 41a) in the innermost layer of the cap layer 40 is provided in contact with the p-type semiconductor layer 25, the p side When a relatively high voltage is applied through the electrode 30 and the n-side electrode 60, a current flows intensively in the first transparent conductive layer 41 a, and the cap layer 40 or a part of the optical semiconductor stack 20 may be destroyed. I found out that Such a phenomenon has been remarkably confirmed particularly in a via-type LED element in which the gap between the cap layer 40 (or the p-side electrode 30) and the n-side electrode 60 is extremely narrow, specifically about 10 μm or less.

  The present inventors have continuously studied the structure of a highly reliable via type LED element in which the cap layer 40 or the optical semiconductor stack 20 is not destroyed even when a high voltage is applied.

  3A to 3C are cross-sectional views showing the vicinity of the convex region 20a / concave region 20b boundary of the optical semiconductor stack 20 as a modification of the LED element 100 according to the embodiment. According to the study by the inventors, a high voltage was applied by providing the transparent conductive layer 41 (first transparent conductive layer 41a) in the innermost layer of the cap layer 40 so as not to contact the p-type semiconductor layer 25. Even in this case, it has been found that the cap layer 40 or the optical semiconductor stack 20 is not easily destroyed.

  At this time, the cap layer 40 may be formed so that only the first transparent conductive layer 41a does not contact the p-type semiconductor layer 25, as shown in FIG. 3A. Further, as shown in FIG. 3B, the end of each layer of the cap layer 40 is aligned with the end of the p-side electrode 30 (light reflecting electrode 31), that is, the planar shape of each layer of the cap layer 40 is the p-side electrode 30 ( You may form so that it may overlap with the planar shape of the light reflection electrode 31). Moreover, as shown to FIG. 3C, you may form so that the edge part of each layer of the cap layer 40 may not contact the p side electrode 30 (light reflection electrode 31). The planar shape of each layer of the cap layer 40 can be easily adjusted by changing the shape of the resist mask to be used when the cap layer 40 is patterned by the lift-off method or the like (FIG. 2C).

  The modification shown in FIG. 3A suppresses the destruction of the cap layer 40 or the optical semiconductor stack 20 when a high voltage is applied, and the cap layer 40 has a certain thickness at the end of the p-side electrode 30. Cap performance is also excellent. In the modification shown in FIG. 3B, although the thickness of the cap layer 40 at the end of the p-side electrode 30 is not sufficient, the same resist from the patterning of the light reflecting electrode 32 to the patterning of the second metal conductive layer 42b is manufactured. Since a mask can be used, the manufacturing process is simplified.

  3C has a structure in which the end portion of the p-side electrode 30 is not covered with the cap layer 40. In the modification shown in FIG. When the p-side electrode 30 containing Ag is not completely covered by the cap layer 40, there is a concern about migration of the p-side electrode 30. However, since the end portion of the p-side electrode 30 that is not covered with the cap layer 40 is covered with the first bonding layer 71 that can include the insulating layer 50 and the cap layer 71a, migration hardly occurs. Even if the end portion of the p-side electrode 30 is not covered with the cap layer 40, if the distance between the end portion of the p-side electrode 30 and the end portion of the cap layer 40 is about 2 μm or less, the reliability of the LED element is improved. It is considered that there is no migration that has an impact.

  4A and 4B are a cross-sectional view and a plan view showing still another modification example of the LED element 100 according to the embodiment. 4A is a cross-sectional view showing a cross section IVA-IVA in FIG. 4B.

  The support substrate 12 of the LED element 100 is not limited to a member having electrical conductivity such as Si, and may be configured by a member having electrical insulation. When the support substrate 12 is formed of a member having electrical insulation, the extraction electrode formed on the back surface of the support substrate 12 is not necessary as shown in FIG. 4A. At this time, the fusion layer 70 is exposed from the insulating layer 50, the cap layer 40 (or the p-side electrode 30) and the optical semiconductor laminate 20 (exposed portion 70e of the fusion layer 70), and power is supplied from the exposed portion 70e. You can do it. The exposed portion 70e of the fusion layer 70 is preferably disposed away from the exposed portion 40e of the cap layer 40 from the viewpoint of current diffusion in the optical semiconductor stack 20, and for example, as shown in FIG. 4B, the cap layer It is preferable to be disposed on the diagonal of 40 exposed portions 40e.

  As mentioned above, although this invention was demonstrated along the Example and the modification, this invention is not limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

DESCRIPTION OF SYMBOLS 11 ... Growth substrate, 12 ... Support substrate, 20 ... Optical semiconductor lamination | stacking, 21 ... Buffer layer, 22 ... Underlayer, 23 ... N-type semiconductor layer, 24 ... Active layer (light emitting layer), 25 ... P-type semiconductor layer, 30 ... p-side electrode, 31 ... contact electrode, 32 ... light reflecting electrode, 40 ... cap layer (migration prevention layer), 41 ... transparent conductive layer, 42 ... metal conductive layer, 50 ... insulating layer, 60 ... n-side electrode, 70 DESCRIPTION OF SYMBOLS ... Fusion layer, 71 ... 1st joining layer, 72 ... 2nd joining layer, 80 ... Surface protective film, 100 ... LED element, 101 ... Device structure, 102 ... Bonding structure.

Claims (5)

A support substrate;
A first semiconductor layer that is disposed on the support substrate and includes at least a GaN-based semiconductor of a first conductivity type from the support substrate side; an active layer that has light-emitting properties and includes a GaN-based semiconductor; and A second semiconductor layer containing a GaN-based semiconductor of a second conductivity type different from the conductivity type is stacked, the convex region where the first semiconductor layer faces the support substrate, and the first semiconductor layer and the active layer are An optical semiconductor stack that is excavated and the second semiconductor layer includes a concave region facing the support substrate, and the concave region is formed so as to be surrounded by the convex region in plan view; ,
A first electrode including Ag disposed between the support substrate and the convex region of the optical semiconductor stack in contact with the first semiconductor layer of the optical semiconductor stack;
A multilayer structure of at least two or more layers, which is disposed so as to cover the first electrode, and from which the transparent conductive layer including the translucent member and the metal conductive layer including the metal member are alternately stacked. A cap layer made of a body, wherein the transparent conductive layer arranged on the innermost side is formed so as not to contact the first semiconductor layer of the optical semiconductor stack ;
A second electrode disposed between the support substrate and the concave region of the optical semiconductor stack, in contact with the second semiconductor layer of the optical semiconductor stack, and disposed at an interval narrower than 10 μm from the cap layer ;
A semiconductor light emitting device comprising: The transparent conductive layer of the cap layer, the semiconductor light emitting device according to claim 1, wherein comprised microcrystalline material or amorphous material crystallite size is at 50nm or less. The semiconductor light emitting element according to claim 1 or 2, wherein the transparent conductive layer of the cap layer has a thickness of 10 nm to 100 nm. The semiconductor light-emitting device according to claim 1, wherein the transparent conductive layer of the cap layer contains ITO or ZnO. Metal conductive layer of the cap layer, Ti, Pt and their alloys, as well, the semiconductor light emitting device according to any one of the preceding claims, comprising at least one member selected from the group consisting of a metal nitride.

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