JP6160822B2 - I/O expansion device group and I/O expansion device - Google Patents

Description

The present invention relates to an I/O expansion device that is connected to a CPU and expands the CPU's external interface.

The number of I/O (input/output) signals that can be directly controlled by the CPU is limited, so I/O expansion devices are used to increase the number of signals that can be input and output.

For example, Patent Document 1 discloses an I/O expansion device that can set whether each bit of a register is used as an input or output function. Patent Document 2 discloses a technology that cascade-connects multiple shift registers to a serial signal output port of a CPU and performs serial-to-parallel conversion, making it possible to output multiple output signals in parallel using a single serial signal output port.

However, if the number of I/Os to be controlled increases, it becomes difficult to handle them all with a single I/O expansion device. In this case, it may be possible to change to an I/O expansion device with more input/output pins, but this would increase costs.

As a technique for addressing such problems, Patent Document 3 discloses a technique for increasing the number of signals that can be output by connecting multiple slave mode I/O expansion devices under a master mode I/O expansion device connected to a CPU.

Japanese Unexamined Patent Publication No. 7-319592 JP 2011-197981 A JP 2009-123141 A

To comply with recent energy saving standards, there exists a state (power saving state) where the device is powered on but the CPU is turned off. Therefore, while the CPU is powered off, the I/O expansion device needs to perform I/O control without CPU intervention, or detect a change in the input signal and turn on the CPU power to transition to the normal state.

For example, when the I/O expansion device receives a specific trigger signal from an external device in a power saving state where the CPU is powered off, the I/O expansion device determines whether or not to transition to a normal state based on the current state and the type of trigger signal input, and if it determines to transition to the normal state, it outputs a start-up signal from the I/O expansion device to other external devices, or outputs a control signal to the power supply control unit to turn on the CPU power.

When multiple I/O expansion devices are used to deal with an increase in the number of input and output signals, each I/O expansion device controls the I/O of a different external device, so even if one I/O expansion device receives a trigger signal from an external device and determines that it should transition to a normal state and transitions its state, the other I/O expansion devices continue to operate in their original states, resulting in the problem that multiple I/O expansion devices cannot perform consistent (synchronized) operations corresponding to the same state.

For example, when a specific trigger signal changes while the CPU is powered off, it is necessary to perform sequence control such as outputting a start-up signal from the I/O expansion device to a specific external device other than the CPU, and then turning on the CPU after the external device has started. Then, for example, it is assumed that one I/O expansion device performs the process of determining the state transition based on the change in the input signal and the process of turning on the CPU's power, while another I/O expansion device is responsible for outputting the start-up signal to the specific external device other than the CPU.

In this configuration, even if one I/O expansion device determines that a state transition to the normal state should occur based on a change in the trigger signal and starts the CPU, other I/O expansion devices do not recognize the state transition and do not start the external devices. This can lead to a situation where a CPU that has been powered on and started up erroneously reads the output value of an external device that is not started.

The present invention seeks to solve the above problems and aims to provide an I/O expansion device group and an I/O expansion device that can synchronize the states of multiple I/O expansion devices without CPU intervention.

The gist of the present invention to achieve this objective lies in the following inventions:

[1] An I/O expansion device group including: a first I/O expansion device connected to a CPU that controls the operation of a specified device, and having an input function of setting a value of an input signal input from a specified component of the device in an input register readable by the CPU; and a second I/O expansion device connected to the CPU, and having an output function of outputting an output signal according to a value set in an output register by the CPU to the specified component of the device,
when a value of an input signal changes, the first I/O expansion device determines whether or not to transition the state of the device based on the change, and if it is determined that the state should be transitioned, outputs a state notification signal indicating a destination state to the second I/O expansion device;
the second I/O expansion device, upon receiving the state notification signal, changes a value of the output signal in accordance with the transition destination state notified by the state notification signal;
the second I/O expansion device has a noise filter circuit that removes noise contained in the state notification signal received from the first I/O expansion device;
A group of I/O expansion devices characterized in that the first I/O expansion device transitions its internal state to the destination state notified by the status notification signal when a delay time equal to the delay time generated by the noise filter circuit has elapsed since the output of the status notification signal .

In the above invention, when a first I/O expansion device that handles input functions detects a change in an input signal, it determines whether or not a state transition will occur due to this change, and if a state transition will occur, notifies a second I/O expansion device that handles output functions of the state after the transition. This makes it possible to match the states of the first I/O expansion device and the second I/O expansion device, thereby harmonizing (synchronizing) their operations.
In addition, since the status notification signal is propagated through wiring on the board, the receiving I/O expansion device removes noise to prevent malfunction. The I/O expansion device that outputs the status notification signal transitions its internal state to the state indicated by the status notification signal when a delay time equal to the delay time caused by the noise filter circuit of the I/O expansion device that receives the status notification signal has elapsed. This allows the timing of state transitions based on the status notification signal to be consistent between both I/O expansion devices.

[2] the state notification signal notifies a power state of the device,
The I/O expansion device group described in [1], characterized in that the number of signal lines used to transmit the status notification signal between the first I/O expansion device and the second I/O expansion device is set to a minimum number according to the number of types of power saving states that the device can be in when the CPU is stopped operating.

In the above invention and the invention described in [ 6 ] below, the number of signal lines used for the status notification signals is set to the minimum required.

[3] The I/O expansion device group described in [1] or [2], characterized in that when the transition destination state is a normal state in which the CPU has recovered from a stopped state and is operating, the second I/O expansion device, when changing the value of an output signal in accordance with the state notification signal received from the first I/O expansion device, changes an output signal for a specified component other than the CPU to a value in the normal state, and then changes the value of an output signal to restore the CPU to the normal state.

In the above invention , when the CPU is restored from the stopped state to the normal state, the change sequence of the output signal is controlled so that the CPU is restored to the normal state after components other than the CPU are restored to the normal state.

[ 4 ] The first I/O expansion device and the second I/O expansion device have the same configuration of output registers and input registers, and connection circuits that connect the output registers to output terminals and connection circuits that connect the input terminals to input registers are configured according to their respective roles. The I/O expansion device group described in any one of [1] to [ 3 ].

In the above invention and the invention described in [ 7 ] below, the register configuration of each I/O expansion device is identical, and the differences in the roles of each I/O expansion device are realized by differences in the configuration of the connection circuits that connect the registers and the input/output terminals.

[ 5 ] An I/O expansion device that is connected to a CPU that controls the operation of a specific device together with another I/O expansion device having an output function that outputs an output signal corresponding to a value set in an output register by the CPU to a specific component of the device,
an input function for setting a value of an input signal input from a predetermined part of the device to an input register readable by the CPU;
when the value of the input signal changes, it is determined whether or not to cause a state of the device to transition based on the change, and if it is determined that a transition should be made, it outputs a state notification signal indicating a destination state to the other I/O expansion device, and when a delay time equal to a delay time caused by a noise filter circuit that the other I/O expansion device has for removing noise contained in the state notification signal has elapsed since the output of the state notification signal, it changes the internal state of its own device to the destination state notified by the state notification signal;
In the other I/O expansion device that receives the state notification signal, the value of the output signal is changed according to the state notified by the state notification signal.

The above invention corresponds to the first I/O expansion device in the I/O expansion device group described in [1].

[ 6 ] The state notification signal notifies a power state of the device,
The I/O expansion device described in [5] is characterized in that the number of signal lines used for transmitting the status notification signal between the I/O expansion device and the other I / O expansion device is set to a minimum number according to the number of types of power saving states that the device can be in when the CPU is stopped.

[7] The I/O expansion device described in [5] or [6], characterized in that the I/O expansion device and the other I/O expansion device have the same configuration of output registers and input registers, and connection circuits that connect the output registers to output terminals and connection circuits that connect the input terminals to input registers are configured according to their respective roles.

The I/O expansion device group and I/O expansion device of the present invention can match the states of multiple I/O expansion devices without CPU intervention, and can coordinate the operation of multiple I/O expansion devices.

1 is a block diagram showing an example of a configuration of an image forming apparatus using an I/O expansion device group according to an embodiment of the present invention; 2 is a diagram showing signal lines etc. when a CPU makes write access to an I/O expansion device. 2 is a diagram showing signal lines etc. when a CPU performs read access to an I/O expansion device. 2 is a block diagram showing a schematic internal configuration of a first I/O expansion device and a second I/O expansion device. 2 is a diagram showing input/output signals of a first I/O expansion device and a second I/O expansion device. FIG. 2 is a diagram illustrating a register configuration of an I/O expansion device. 11 is a flowchart showing an operation when returning from a power saving state to a normal state. FIG. 11 is a sequence diagram showing an operation when returning from a power saving state to a normal state.

The following describes an embodiment of the present invention with reference to the drawings.

Figure 1 shows a schematic configuration of an image forming apparatus 10 as an apparatus to which an I/O expansion device according to an embodiment of the present invention is applied. The image forming apparatus 10 is a multifunction peripheral (MFP) equipped with a copy function for optically reading an original document and printing a duplicate image on recording paper, a scan function for saving image data of the read original document as a file or sending it to an external terminal via a network, a printer function for forming and printing out an image on recording paper according to print data received from a PC or the like via a network, and a facsimile function for sending and receiving image data according to facsimile procedures.

The image forming device 10 has a CPU (Central Processing Unit) 11 as a control unit that controls the overall operation of the image forming device 10. A first non-volatile memory 12, a second non-volatile memory 13, a RAM (Random Access Memory) 14, a hard disk drive 15, an automatic document feeder (ADF: Auto Document Feeder) 16, an image reading unit 17, an operation panel 18, an image processing unit 19, a printer unit 21, a network communication unit 22, a facsimile communication unit 23, a first I/O expansion device 30, a second I/O expansion device 50, and the like are connected to the CPU 11 via a bus. The image forming device 10 also has a power control unit 24 that can individually turn on and off the power supply to each unit. Note that in FIG. 1, the CPU bus is shown as one bus, but in reality, it is composed of multiple buses via bridges.

The CPU 11 runs an OS (Operating System) program, on top of which it executes middleware, application programs, etc.

The first non-volatile memory 12 and the second non-volatile memory 13 are memories (flash memories) whose stored contents are not destroyed even when the power is turned off. Boot data is stored in the first non-volatile memory 12, and various firmware (programs) other than the boot data are stored in the second non-volatile memory 13.

The CPU 11 starts up according to the boot data stored in the first non-volatile memory 12, and then executes various processes according to the firmware stored in the second non-volatile memory 13. In addition, various application programs are stored in the hard disk drive 15, and the CPU 11 loads these into the RAM 14 and executes them. The CPU 11 executes various programs to realize various functions of the image forming device 10.

RAM 14 is used as a work memory that temporarily stores various data when CPU 11 executes processing, an image memory that stores image data, etc.

The hard disk drive 15 is a large-capacity non-volatile storage device that stores various data such as print data and image files, as well as application programs.

The image reading unit 17 has the function of optically reading the document to obtain image data. The image reading unit 17 is configured with, for example, a light source that irradiates the document with light, a line image sensor that receives the reflected light and reads the document one line in the width direction, a moving unit that sequentially moves the reading position in line units in the length direction of the document, an optical path consisting of lenses and mirrors that guide the reflected light from the document to the line image sensor to form an image, and a conversion unit that converts the analog image signal output by the line image sensor into digital image data.

The automatic document feeder 16 feeds the documents set on the document tray one by one starting from the top one, passes them through the reading position of the image reader 17, and ejects them to a specified ejection position. The image reader 17 has the function of reading the documents placed on the platen glass and the function of sequentially reading the documents being transported by the automatic document feeder 16.

The operation panel 18 has the function of displaying various operation screens, setting screens, etc., and the function of accepting various operations such as job submission from the user. The operation panel 18 has a display unit such as a liquid crystal display (LCD), various hard keys such as a start button and a numeric keypad, and a touch panel provided on the display surface of the display unit.

The image processing unit 19 performs processes such as enlarging, reducing, and rotating the image, as well as rasterization to convert print data into image data, and compression and decompression of image data.

The printer unit 21 functions to form an image on recording paper according to image data. Here, the printer unit 21 has a recording paper transport device, a photosensitive drum, a charging device, a laser unit, a developing device, a transfer separation device, a cleaning device, and a fixing device, and is configured as a so-called laser printer that forms images by an electrophotographic process. Image formation may also be performed by other methods.

The network communication unit 22 performs the function of communicating with an external device (e.g., a PC, a server). The network communication unit 22 may be configured to enable both wired communication and wireless communication, or to enable only one of them.

The facsimile communication unit 23 functions to send and receive image data via a telephone line with an external device equipped with a facsimile function.

The first I/O expansion device 30 and the second I/O expansion device 50 perform the function of expanding the I/O that can be connected to the CPU 11. Here, the first I/O expansion device 30 has an input function of receiving input signals from each part (e.g., a sensor, etc.) of the image forming apparatus 10 and setting the values in a register that can be read by the CPU. The second I/O expansion device 50 has an output function of outputting output signals corresponding to the values set in the register by the CPU 11 to each part (e.g., the power supply control unit 24) of the image forming apparatus 10. Details of the first I/O expansion device 30 and the second I/O expansion device 50 will be described later.

The power supply control unit 24 controls the power supply to each unit of the image forming apparatus 10. Here, it controls the power supply to the CPU 11, the power supply to ASICs (application specific integrated circuits) such as the image processing unit 19, the power supply to the operation panel 18, the power supply to the network communication unit 22, the power supply to the facsimile communication unit 23, and the power supply to a timer IC (not shown). The second I/O expansion device 50 outputs a control signal to the power supply control unit 24 to instruct each of the above power supplies to be turned on or off.

Figures 2 and 3 show devices connected to the external interface channel of the CPU 11. Figure 2 shows the write operation, and Figure 3 shows the read operation.

The CPU 11 is a SoC (System-on-a-Chip) type semiconductor chip with an external interface function. The CPU 11 has ch1, ch2, and ch3 as channels for external interfaces. A first non-volatile memory 12 is connected to ch1, and a second non-volatile memory 13 is connected to ch2.

A first I/O expansion device 30 and a second I/O expansion device 50 are connected to ch3. Although multiple I/O expansion devices 30 and 50 are connected to one channel, the configuration is such that data is not output from multiple I/O expansion devices during read access, so there is no problem with data collisions. Here, the first I/O expansion device 30 is dedicated to input functions, and the second I/O expansion device 50 is dedicated to output functions. Therefore, it is sufficient for the CPU 11 to be able to read the registers of the first I/O expansion device 30, and the read signal is connected only to the first I/O expansion device 30.

In detail, the first I/O expansion device 30 is connected to the device bus of the CPU 11 with a ch3 select signal, write signal, read signal, 8-bit data bus signal, and 3-bit address signal. The second I/O expansion device 50 is connected to a ch3 select signal, write signal, 8-bit data bus signal, and 3-bit address signal. The second I/O expansion device 50 is dedicated to output functions, so no read signal is connected and there is no terminal for it.

When the address signal is 3 bits, the I/O expansion devices 30 and 50 can have a maximum of eight registers corresponding to each address. In a write access to ch3, as shown in FIG. 2, the same value is written to the registers at the same address in the first I/O expansion device 30 and the second I/O expansion device 50. In a read access to ch3, the read signal is input only to the first I/O expansion device 30, and not to the second I/O expansion device 50, so that at each address, only the first I/O expansion device 30 outputs data to the CPU bus, as shown in FIG. 3.

In addition, a read signal may be input to both the first I/O expansion device 30 and the second I/O expansion device 50, and either the first I/O expansion device 30 or the second I/O expansion device 50 may output data to the CPU bus exclusively by address. For example, the first I/O expansion device 30 may output data when the 3-bit address during read access is (000) or (001), and the second I/O expansion device 50 may output data when the 3-bit address during read access is (010) or (011).

In this embodiment, the data bus signal is 8 bits, but this is not limited to 8 bits. Also, the address signal is 3 bits, but this is not limited to 3 bits.

Figure 4 shows the general internal configuration of the first I/O expansion device 30 and the second I/O expansion device 50. The first I/O expansion device 30 includes a bus interface unit 31 that is connected to the bus of the CPU 11 for inputting and outputting data, an input control register 32, an output control register 33, a recovery condition determination unit 34, a delay circuit 35, and a sequence control unit 36.

The second I/O expansion device 50 includes a bus interface unit 51, an input control register 52, an output control register 53, a recovery condition determination unit 54, a noise filter circuit 55, and a sequence control unit 56.

The input control registers 32 and 52 are registers that can be read by the CPU 11, with each bit assigned to an input signal from the outside, and the value of the input signal being reflected in each bit. The output control registers 33 and 53 are registers in which the CPU 11 can set the value of each bit, and an output signal according to the set value is output to the outside.

When the value of the input signal changes, the return condition determination units 34 and 54 determine whether a state transition is necessary based on the value of the input signal after the change and the current state (here, the state related to power saving of the image forming device 10), and if it is determined that a state transition is necessary, they output a state notification signal indicating the state to which the state should be transitioned.

The sequence control units 36, 56 control the output sequence (output order, delay time, etc.) when the values set in the output control registers 33, 53 are output as output signals.

The noise filter circuit 55 is a circuit that removes noise from the status notification signal input from the first I/O expansion device 30. The status notification signal is transmitted from the first I/O expansion device 30 to the second I/O expansion device 50 via a pattern on the board, so the receiving second I/O expansion device 50 receives the status notification signal via its internal noise filter circuit 55 to remove noise.

The noise filter circuit 55 may be any known circuit, but here it is configured as a multi-stage shift register, and when all bits become "1", it operates to pass a state notification signal to the next stage circuit. Therefore, in the second I/O expansion device 50, the timing at which the transition destination state notified by the state notification signal is reflected internally is delayed by the number of stages of the shift register that constitutes the noise filter circuit 55.

The delay circuit 35 of the first I/O expansion device 30 is a circuit that delays the status notification signal output by the restoration condition determination unit 34 by a time equal to the delay time of the noise filter circuit 55 of the second I/O expansion device 50. The status notification signal output by the restoration condition determination unit 34 is delayed by the delay circuit 35 and input to each part of the first I/O expansion device 30 (such as the output control register 33 and sequence control unit 36). As a result, the timing of transition to the destination state indicated by the status notification signal is the same for the first I/O expansion device 30 and the second I/O expansion device 50.

In addition, the first I/O expansion device 30 and the second I/O expansion device 50 each have a control unit (not shown) that controls internal operations. The control unit performs functions such as rewriting the setting values of the output control registers 33 and 53 to values corresponding to the transition destination state indicated by the state notification signal.

Here, the first I/O expansion device 30 and the second I/O expansion device 50 are configured with a CPLD (Complex Programmable Logic Device). The first I/O expansion device 30 and the second I/O expansion device 50 are basically configured with a common circuit (a circuit described in RTL (Register Transfer Level)). In detail, the bus interface unit 31, input control register 32, output control register 33, recovery condition determination unit 34, and sequence control unit 36 of the first I/O expansion device 30 are respectively configured with the same circuits as the bus interface unit 51, input control register 52, output control register 53, recovery condition determination unit 54, and sequence control unit 56 of the second I/O expansion device 50.

However, the connections between the circuits and the connection circuits between the registers 32, 33, 52, and 53 and the terminals of the chip are different depending on the functions performed by the first I/O expansion device 30 and the second I/O expansion device 50. For example, in the second I/O expansion device 50 which performs the output function, the read signal is fixed internally to an inactive logic level. This means that the second I/O expansion device 50 does not respond to read access. Also, since the second I/O expansion device 50 does not require an input function, the input value to the input control register 52 is fixed to an inactive logic level. On the other hand, in the first I/O expansion device 30 which performs the input function, the output of the output control register 33 is not connected to the terminals of the chip.

The input control register 32 of the first I/O expansion device 30, which performs the input function, is read by the CPU 11. In a typical device bus, the host CPU periodically reads the input control register of the I/O expansion device to recognize the state of each input signal (such as a signal from a sensor) being input to the I/O expansion device.

This method is called polling. With the polling method, the CPU needs to perform read access at regular intervals, which increases the load on the CPU.

Another method besides the polling method is the interrupt method. In the interrupt method, the I/O expansion device detects changes in each input signal and outputs an interrupt signal to the CPU. When an interrupt signal is input, the CPU performs a read access to the input control register of the I/O expansion device.

In this way, the interrupt method reduces the load on the CPU, so the first I/O expansion device 30 of this embodiment employs the interrupt method. The first I/O expansion device 30 notifies of interrupts related to multiple input signals with a single interrupt signal. This type of interrupt is called a collective interrupt. The first I/O expansion device 30 has an interrupt cause register for indicating which input signal has changed, and an interrupt cause clear register for clearing the interrupt cause register.

When the CPU 11 receives a collective interrupt, it reads the interrupt cause register of the first I/O expansion device 30 to determine which input signal has changed. When the CPU 11 writes a "1" to the corresponding bit of the interrupt cause clear register, the corresponding bit of the interrupt cause register is cleared to a "0."

Next, we will explain the assignment of terminals between the first I/O expansion device 30 and the second I/O expansion device 50.

The first I/O expansion device 30 and the second I/O expansion device 50 are CPDLs in the same package. Both the first I/O expansion device 30 and the second I/O expansion device 50 require inputs such as power, GND, and clock, and each has 27 terminals that can be assigned by the user.

Figure 5 shows the signals assigned to the above 27 terminals in the first I/O expansion device 30 and the second I/O expansion device 50.

In the first I/O expansion device 30, there are a total of 15 lines, consisting of the ch3 select signal, write signal, read signal, 8-bit data bus signal, 3-bit address signal, and collective interrupt signal, of which two lines are used as status notification signals to the second I/O expansion device 50. The remaining 10 lines are used as input terminals for input signals related to the input function.

In the second I/O expansion device 50, the select signal of ch3, the write signal, the 8-bit data bus signal, and the 3-bit address signal make a total of 13 lines, of which two are used to receive status notification signals from the first I/O expansion device 30. The remaining 12 are used as output terminals for output signals related to the output function.

The two status notification signals indicate the power saving states that the image forming device 10 can assume when the CPU 11 is stopped. Specifically, they are a sleep notification signal indicating the sleep state, and an ErP notification signal representing the ErP state. The number of signal lines used for the status notification signals is set to the minimum number corresponding to the number of power saving states that the CPU 11 can assume when it stops operating. In this case, the sleep state and ErP state are power saving states, and two signal lines are used because it is necessary to notify three states, including the normal state.

The sleep state is a state in which the power to the CPU 11, ASIC, etc. is turned off, and only the power to the sensors, etc. is turned on. The ErP state is a state in which even less power is consumed than the sleep state, and only some of the sensors that were turned on in the sleep state are turned on. For example, in both states, the power to the CPU 11, the ASIC for image processing, and the control units of the mechanical parts of the image forming device 10 (image reading unit 17 and printer unit 21) are turned off, but in the sleep state, the power to the operation panel 18, facsimile communication unit 23, front cover sensor, scanner cover sensor, document detection sensor, wireless LAN device, and timer IC all remain on, and in the ErP state, only the operation panel 18 and timer are turned on.

Under normal circumstances, both of the two status notification signals are "0". When the image forming device 10 enters the sleep state, the sleep notification signal is "1" and the ErP notification signal is "0". When the image forming device 10 enters the ErP state, the sleep notification signal is "0" and the ErP notification signal is "1". The normal state is a state in which power is supplied to the CPU 11 and other components, and the image forming device 10 is able to execute jobs.

Figure 6 shows a list of registers possessed by the first I/O expansion device 30 and the second I/O expansion device 50. The register configurations of the first I/O expansion device 30 and the second I/O expansion device 50 are the same, and each has eight registers. The list in Figure 6 shows the correspondence between addresses, register names, and possible types of access.

The first I/O expansion device 30 and the second I/O expansion device 50 each have a first output control register and a second output control register as the output control register 33, and a first input control register and a second input control register as the input control register 32. In addition, corresponding to the first input control register and the second input control register, each have a first interrupt cause register, a second interrupt cause register, a first interrupt cause clear register, and a second interrupt cause clear register.

The first output control register is an 8-bit readable/writable register assigned to address (000). Each bit corresponds to an output signal from output 0 to output 7 of the second I/O expansion device 50, and the CPU 11 can control the corresponding output signal by rewriting each bit.

The second output control register is an 8-bit readable/writable register assigned to address (001). Each bit corresponds to an output signal from output 8 to output 11 of the second I/O expansion device 50, and the CPU 11 can control the corresponding output signal by rewriting each bit. The second output control register is 8 bits, but due to the limited number of output terminals, only the lowest 4 bits are actually used.

The objects controlled by the first output control register and the second output control register include the power supply for the CPU 11, the power supply for ASICs such as the image processing unit 19, the power supply for the operation panel 18, the power supply for the network communication unit 22, the power supply for the facsimile communication unit 23, the power supply for a timer IC (not shown), and a reset signal.

The first input control register is an 8-bit read-only register assigned to address (010). Each bit corresponds to input 0 to input 7 of the first I/O expansion device 30, and the CPU 11 can know the value of the input signal input to input 0 to input 7 of the first I/O expansion device 30 by reading each bit.

The second input control register is an 8-bit read-only register assigned to address (011). The lowest 2 bits correspond to inputs 8 and 9 of the first I/O expansion device 30, and the CPU 11 can know the values of the input signals input to inputs 8 and 9 of the first I/O expansion device 30 by reading each bit. The second output control register is 8 bits, but due to limitations on the number of input terminals, only the lowest 2 bits are actually used.

The signals input to the first input control register and the second input control register include the operation panel switch signal, the fax call signal, the cover sensor signal, the document sensor signal, the wireless LAN reception signal, and the timer signal.

The first interrupt cause register is an 8-bit read-only register assigned to address (100). When the state of any of the input signals of inputs 0 to 7 of the first I/O expansion device 30 reflected in the first input control register changes, the corresponding bit is set to "1." When any bit of the first interrupt cause register or a second interrupt cause register described below is "1," the first I/O expansion device 30 outputs a collective interrupt signal to the CPU 11. When the first I/O expansion device 30 receives a read request for address (100) from the CPU 11, it returns the value of the first interrupt cause register.

The second interrupt cause register is an 8-bit read-only register assigned to address (101). When the state of either the input signal of input 8 or input 9 of the first I/O expansion device 30 reflected in the second input control register changes, the corresponding bit is set to "1." When either bit of the first interrupt cause register or the second interrupt cause register described above is "1," the first I/O expansion device 30 outputs a collective interrupt signal to the CPU 11. When the first I/O expansion device 30 receives a read request for address (101) from the CPU 11, it returns the value of the second interrupt cause register.

The first interrupt cause clear register is an 8-bit write-only register assigned to address (110). The first interrupt cause clear register corresponds to the first interrupt cause register described above, and when a "1" is written to each bit of the first interrupt cause clear register, the corresponding bit of the first interrupt cause register is cleared to "0."

The second interrupt cause clear register is an 8-bit write-only register assigned to address (111). The second interrupt cause clear register corresponds to the second interrupt cause register described above, and when a "1" is written to each bit of the second interrupt cause clear register, the corresponding bit of the second interrupt cause register is cleared to "0."

Next, the operation of the first I/O expansion device 30 and the second I/O expansion device 50 will be described.

First, we will describe the case where the image forming device 10 transitions from the normal state to the sleep state or the ErP state. In the normal state, the CPU 11 has write access to the first I/O expansion device 30 and the second I/O expansion device 50, so the CPU 11 rewrites each bit of the output control registers 33, 53 according to the power state of the sleep state or the ErP state. Setting the power control bit of the CPU 11 to "0" turns off the power of the CPU 11, so the CPU 11 finally sets this bit to "0" to complete the state transition. The first I/O expansion device 30 and the second I/O expansion device 50 recognize the state of the device based on the values set by the CPU 11 in the output control registers 33, 53.

Next, we will explain the operation during sleep and ErP states, and the operation when returning to normal state.

Figure 7 is a flow diagram showing the operation when transitioning from the sleep state or ErP state to the normal state, and Figure 8 shows the operation sequence at that time.

When the value of any of the input signals input to the first I/O expansion device 30 changes in the sleep state or ErP state in which the CPU is stopped (FIG. 7; step S101, FIG. 8: P001), the recovery condition determination unit 34 of the first I/O expansion device 30 determines whether or not to transition the image forming device 10 to the normal state in response to this change in the input signal (FIG. 7; step S102, FIG. 8: P002).

The return condition determination unit 34 checks whether the combination of the current state and the changed input signal corresponds to a preset combination, and if so, determines that a transition to the normal state should occur.

For example, among the interrupt signals used in the image forming device 10, the operation panel switch signal, FAX call signal, front cover sensor, scanner cover sensor, document detection sensor, wireless LAN reception signal, timer interrupt signal, etc. are input as input signals to the first I/O expansion device 30. The value of each input signal is reflected in the input control register 32 of the first I/O expansion device 30.

The return condition determination unit 34 has a determination table that indicates in what state which input signal becomes active as the cause of a state transition. The return condition determination unit 34 recognizes the input signal that is active in the current state from this determination table, and when the value of the active input signal changes to a specified value, determines that a state transition to the normal state is necessary. The determination table may be set in the first I/O expansion device 30 by the CPU 11 before the power is turned off, or may be held in advance as a fixed value by the first I/O expansion device 30.

When the power supply to the sensor is turned off, the signal from the sensor becomes "0" (low), and if it was a low active signal, it becomes active. Therefore, the return condition determination unit 34 refers to a determination table to select what is valid. The determination table differs between the sleep state and the ErP state. For example, in the sleep state, the operation panel switch signal, FAX call signal, front cover sensor, scanner cover sensor, document detection sensor, wireless LAN reception signal, and timer interrupt signal are enabled, and in the ErP state, only the operation panel 18 and timer interrupt signal are enabled.

If the result of the determination indicates that a state transition has occurred (FIG. 7; step S102; Yes), the recovery condition determination unit 34 sets the bit in the interrupt cause register that corresponds to the input signal that caused the determination result to "1" (active value). This causes a collective interrupt signal to be output from the first I/O expansion device 30 to the CPU 11 (FIG. 7; step S103, FIG. 8; P003).

At the same time, the recovery condition determination unit 34 of the first I/O expansion device 30 outputs a state notification signal indicating a state transition to the normal state (FIG. 7; step S104, FIG. 8; P004). The second I/O expansion device 50 receives the state notification signal arriving from the first I/O expansion device 30 after removing noise using the noise filter circuit 55 (FIG. 8; P101). The first I/O expansion device 30 delays the state notification signal output from the recovery condition determination unit 34 using the delay circuit 35, and then allows it to reach various internal locations (output control register 33 and sequence control unit 36) (FIG. 8; P005).

As a result, the first I/O expansion device 30 and the second I/O expansion device 50 start operating at the same time, corresponding to the state after the transition (here, the normal state). Specifically, in each of the first I/O expansion device 30 and the second I/O expansion device 50, the values of the output control registers 33, 53 are autonomously rewritten to the values in the normal state (FIG. 7; step S105, FIG. 8; P006, P102).

Since the first I/O expansion device 30 does not have an output function, only the value of the output control register 33 is rewritten. On the other hand, when the value of the output control register 53 of the second I/O expansion device 50 is rewritten to the normal state value, the value of the output signal is changed accordingly. At this time, the sequence control unit 56 of the second I/O expansion device 50 controls the timing and order of changing the output signal (Figure 7; step S106).

Specifically, first the value of the corresponding output signal is changed so that the power of devices other than the CPU 11 is turned on (Fig. 8; P103), and then after a predetermined time has elapsed and those devices have started up, the value of the output signal for controlling the power supply of the CPU 11 is changed so that the CPU 11 is turned on (Fig. 8; P104). Note that the power supply of the CPU 11 may also be turned on at the same time as the other devices, and the reset signal of the CPU 11 may be controlled to be released once the startup of the other devices is complete. In other words, it is sufficient that the CPU 11 is able to operate once the peripheral devices have started up to their normal state.

Having started operation, the CPU 11 detects the collective interrupt signal (FIG. 7; step S107, FIG. 8; P201). The CPU 11 then reads the interrupt cause register of the first I/O expansion device 30 (FIG. 7; step S108, FIG. 8; P202, P007).

The CPU 11 determines whether any bit in the interrupt cause register is "1" (active) (FIG. 7; step S109), and if any bit is "1" (step S109; Yes), identifies the interrupt cause from the bit that is "1".

Next, the CPU 11 reads the value of the input control register 32 of the first I/O expansion device 30 (FIG. 7; step S110, FIG. 8; P203, P008). Then, after executing the process corresponding to the value of the input control register 32 that was read, it writes "1" to the corresponding interrupt cause clear register and clears the interrupt cause register to "0" (FIG. 7; step S111, FIG. 8; P204, P205, P009).

As mentioned above, peripheral devices other than CPU 11 start up before CPU 11, so when CPU 11 reads the value of input control register 32, the peripheral devices have already started up, and values from sensors and other devices in the peripheral devices can be correctly input. For example, if CPU 11 reads the value of input control register 32 before a sensor starts up, the input value will be incorrect. However, by starting up in the sequence described above, such erroneous input can be avoided.

Note that in the register configuration shown in FIG. 6, there are two interrupt cause registers, a first interrupt cause register and a second interrupt cause register, so the processing from steps S109 to S111 in FIG. 7 (P202 to P205, P007 to P009 in FIG. 8) is executed for each interrupt cause register.

Here is a specific example. Assume that the state of the input signal at input 4 of the first I/O expansion device 30 changes in step S101 of FIG. 7, as shown in FIG. 5. Here, the input signal at input 4 is a detection signal from a sensor that detects the opening and closing of the front cover of the image forming device 10.

When the state of the input signal of input 4 changes, bit 4 of interrupt cause register 1 becomes "1", and a collective interrupt is output to CPU 11 (step S103). In addition, the state notification signal to the second I/O expansion device 50 is changed to a value indicating the normal state (sleep notification signal "0", ErP notification signal "0").

When the second I/O expansion device 50 receives a status notification signal indicating a normal state, it rewrites the value of the output control register 53 to the value for the normal state, and while controlling the timing with the sequence control unit 56, outputs an output signal corresponding to the value of the output control register 53, thereby turning on the power to each device. The sequence for rewriting the values is performed so as to satisfy the order and waiting time specified for each device. The device to be powered on (the value of the output control register 33 corresponding to the normal state) may be stored in advance as an initial value inside the second I/O expansion device 50, or a register value indicating the power state of each device immediately before the CPU 11 was powered off may be held.

When the power is turned on and the CPU 11 detects a collective interrupt, it reads the first interrupt cause register and the second interrupt cause register to identify which input signal has changed. In this case, it identifies the input signal of input 4. After identifying it, it reads the first input control register corresponding to that input 4 to confirm whether the input signal of input 4 is currently in the state of "0" or "1". After confirmation, it performs the corresponding process, and finally clears the interrupt cause by writing "1" to bit 4 of the first interrupt cause clear register. In this example, since the front cover open/close sensor was the interrupt cause, the CPU 11 displays "Front cover is open" on the operation panel 18.

In this way, one I/O expansion device 30 notifies the other I/O expansion device 50 of any state changes that occur while the CPU 11 is stopped by using a state notification signal, so that the states managed by each I/O expansion device 30, 50 can be made consistent without the intervention of the CPU 11, and the operations of these multiple I/O expansion devices 30, 50 can be coordinated without the intervention of the CPU 11.

In addition, the number of signal lines used as status notification signals is kept to the minimum required, minimizing the reduction in the number of terminals available for actual I/O expansion.

When the CPU 11 is returned to its normal state, peripheral devices other than the CPU are returned to their normal state before the CPU 11 operates, which prevents the CPU 11 from erroneously inputting values from a sensor that is not powered immediately after booting up.

The second I/O expansion device 50 also removes noise from the status notification signal through the noise filter circuit 55, so it will not malfunction due to noise on the board. Furthermore, the first I/O expansion device 30 notifies each part of its own device of the status notification signal through a delay circuit 35 with the same delay time as the delay time generated by the noise filter circuit 55 of the second I/O expansion device 50, so the timing for starting to execute the operation corresponding to the state after the transition can be matched between the first I/O expansion device 30 and the second I/O expansion device 50.

In addition, the register configuration of the first I/O expansion device 30 and the second I/O expansion device 50 are common, and the connection circuits connecting the registers and the input/output terminals are different depending on the functions of the first I/O expansion device 30 and the second I/O expansion device 50, so the design work for the first I/O expansion device 30 and the second I/O expansion device 50 is reduced.

In addition, only the first I/O expansion device 30, which is assigned the input function, responds to a read access from the CPU 11, so that the state is equivalent to the CPU 11 seeing only one device connected, and the consistency of bus access can be maintained.

Although the embodiment of the present invention has been described above with reference to the drawings, the specific configuration is not limited to that shown in the embodiment, and the present invention includes modifications and additions that do not deviate from the gist of the present invention.

In the embodiment, an example is shown in which the I/O expansion device group is composed of a first I/O expansion device 30 and a second I/O expansion device 50, but it may be composed of three or more I/O expansion devices.

In addition, multiple I/O expansion devices may be configured to handle input functions, or multiple I/O expansion devices may be configured to handle output functions. Furthermore, one I/O expansion device in a group of I/O expansion devices may have both input and output functions. When the input function is distributed among multiple I/O expansion devices, it is sufficient to exclusively assign which device outputs data to the CPU bus for each address.

Furthermore, although an example has been shown in which multiple I/O expansion devices are connected to one channel of the CPU 11, the present invention can also be applied to a configuration in which multiple channels are used to connect multiple I/O expansion devices. In other words, even when multiple channels are used, matching the states using a status notification signal without CPU intervention is effective when using multiple I/O expansion devices.

In the embodiment, an example is shown in which an I/O expansion device is created using CPDL, but this is not limited to this. Furthermore, the device in which the I/O expansion device is used is not limited to the image forming device 10. Furthermore, the state is not limited to the power state of the device.

In the embodiment, examples are given of state transitions from the sleep state and the ErP state to the normal state, but the state transition destination determined by the recovery condition determination unit 34 is not limited to the normal state.

10... Image forming device 11... CPU
12: First non-volatile memory 13: Second non-volatile memory 14: RAM
15...Hard disk device 16...Automatic document transport unit 17...Image reading unit 18...Operation panel 19...Image processing unit 21...Printer unit 22...Network communication unit 23...Facsimile communication unit 24...Power supply control unit 30...First I/O expansion device 31...Bus interface unit 32...Input control register 33...Output control register 34...Restoration condition determination unit 35...Delay circuit 36...Sequence control unit 50...Second I/O expansion device 51...Bus interface unit 52...Input control register 53...Output control register 54...Restoration condition determination unit 55...Noise filter circuit 56...Sequence control unit

Claims (7)

An I/O expansion device group including: a first I/O expansion device connected to a CPU that controls the operation of a specified device, and having an input function of setting a value of an input signal input from a specified part of the device in an input register readable by the CPU; and a second I/O expansion device connected to the CPU, and having an output function of outputting an output signal according to a value set in an output register by the CPU to the specified part of the device,
when a value of an input signal changes, the first I/O expansion device determines whether or not to transition the state of the device based on the change, and if it is determined that the state should be transitioned, outputs a state notification signal indicating a destination state to the second I/O expansion device;
the second I/O expansion device, upon receiving the state notification signal, changes a value of the output signal in accordance with the transition destination state notified by the state notification signal;
the second I/O expansion device has a noise filter circuit that removes noise contained in the state notification signal received from the first I/O expansion device;
A group of I/O expansion devices characterized in that the first I/O expansion device transitions its internal state to the destination state notified by the status notification signal when a delay time equal to the delay time generated by the noise filter circuit has elapsed since the output of the status notification signal . The state notification signal notifies a power state of the device,
The I/O expansion device group according to claim 1, characterized in that the number of signal lines used to transmit the status notification signal between the first I/O expansion device and the second I/O expansion device is set to a minimum number according to the number of types of power saving states that the device can be in when the CPU is stopped operating. The I/O expansion device group according to claim 1 or 2, characterized in that when the transition destination state is a normal state in which the CPU has recovered from a stopped state and is operating, the second I/O expansion device, when changing the value of an output signal in accordance with the state notification signal received from the first I/O expansion device, changes an output signal for a specified component other than the CPU to a value in the normal state, and then changes the value of an output signal to restore the CPU to the normal state. The I/O expansion device group described in any one of claims 1 to 3, characterized in that the first I/O expansion device and the second I/O expansion device have the same configuration of output registers and input registers, and connection circuits that connect the output registers to output terminals and connection circuits that connect the input terminals to input registers are configured according to their respective roles. An I/O expansion device connected to a CPU that controls an operation of a predetermined device together with another I/O expansion device having an output function for outputting an output signal corresponding to a value set in an output register by the CPU to a predetermined component of the device,
an input function for setting a value of an input signal input from a predetermined part of the device to an input register readable by the CPU;
when the value of the input signal changes, it is determined whether or not to cause a state of the device to transition based on the change, and if it is determined that a transition should be made, it outputs a state notification signal indicating a destination state to the other I/O expansion device, and when a delay time equal to a delay time caused by a noise filter circuit that the other I/O expansion device has for removing noise contained in the state notification signal has elapsed since the output of the state notification signal, it changes the internal state of its own device to the destination state notified by the state notification signal;
In the other I/O expansion device that receives the state notification signal, the value of the output signal is changed according to the state notified by the state notification signal. The state notification signal notifies a power state of the device,
The I/O expansion device according to claim 5, characterized in that the number of signal lines used to transmit the status notification signal between the I/O expansion device and the other I/O expansion device is set to a minimum number according to the number of types of power saving states that the device can be in when the CPU is stopped operating. The I/O expansion device according to claim 5 or 6, characterized in that the I/O expansion device and the other I/O expansion device have the same configuration of output registers and input registers, and connection circuits that connect the output registers to output terminals and connection circuits that connect the input terminals to input registers are configured according to their respective roles.