JP6206092B2 - Electronic component and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic component and a manufacturing method thereof, for example, an electronic component in which a plurality of elements are resin-sealed and a manufacturing method thereof.

  Electronic components are required to have packaging technology that achieves both high density and low cost. For example, CSP (Chip-Size Package) is available as a package technology for realizing this. In recent years, the fan-in pitch of CSP has progressed, and WLP (Wafer Level Package) is used. WLP is also called WL-CSP (Wafer Level CSP) and W-CSP (Wafer CSP).

  WLP can perform the formation of packages in a wafer state. In this way, individualization is performed after the final test of the pass / fail judgment. As a result, the mounting area can be reduced to the chip size at a lower cost than conventional packages.

  WLP includes a fan-in type in which terminals formed around a bare chip are rearranged over the entire chip. As the number of terminals of a bare chip increases, it is difficult to rearrange terminals only in the chip area, and a fan-out type in which terminals are rearranged outside the chip area has been developed.

  A technique of covering a chip with a heat dissipation cap and resin molding is known (for example, Patent Document 1).

JP 2005-26373 A

  When a small element is mounted on a package, the element may be inclined or move when the element is sealed with resin. Thus, when resin-sealing a small element, the position accuracy of the element is poor.

  An object of the present electronic component and the manufacturing method thereof is to improve the positional accuracy of the element.

A step of mounting the first element on the support substrate; a step of forming a metal layer so as to cover a side surface of the first element from an upper surface of the support substrate; and the metal layer on the support substrate is not formed A step of mounting a second element in the region, a step of forming a resin layer for sealing the metal layer and the second element on the support substrate, the first element, the second element, and the metal layer And a method of peeling the resin layer from the support substrate.

A resin layer having a first surface and a second surface facing the first surface, first and second elements sealed by the resin layer and exposed from the second surface, and covering the first element A metal layer having one surface exposed from the first surface, and a rewiring layer formed on the second surface and electrically connected to the first and second elements, the metal layer comprising : An electronic component that covers a side surface of the first element from a surface of the rewiring layer on the metal layer side is used.

  According to this electronic component and its manufacturing method, the positional accuracy of the element can be improved.

FIG. 1A to FIG. 1D are cross-sectional views (part 1) illustrating the method of manufacturing the electronic component according to the first embodiment. 2A to 2C are cross-sectional views (part 2) illustrating the method of manufacturing the electronic component according to the first embodiment. FIG. 3A to FIG. 3C are cross-sectional views of an electronic component according to a comparative example. 4A to 4C are cross-sectional views (part 1) illustrating the method of manufacturing the electronic component according to the second embodiment. FIG. 5A to FIG. 5C are cross-sectional views (part 2) illustrating the method of manufacturing the electronic component according to the second embodiment. 6A to 6C are cross-sectional views (part 3) illustrating the method of manufacturing the electronic component according to the second embodiment. FIG. 7A to FIG. 7C are cross-sectional views (part 4) illustrating the method of manufacturing the electronic component according to the second embodiment. FIG. 8 is a cross-sectional view of the electronic component according to the second embodiment. FIG. 9A to FIG. 9C are cross-sectional views illustrating a method for manufacturing an electronic component according to the third embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1A to FIG. 2C are cross-sectional views illustrating a method for manufacturing an electronic component according to the first embodiment. As shown in FIG. 1A, an adhesive layer 42 is formed on the support substrate 40. The support substrate 40 is, for example, a metal substrate including stainless steel or aluminum, a semiconductor substrate including silicon, or an insulating substrate including glass or sapphire. The upper surface of the support substrate 40 is a flat surface, for example. The adhesive layer 42 is a layer for fixing the elements 12 and 16 to the support substrate 40, and is, for example, an adhesive sheet.

  As shown in FIG. 1B, the element 12 (first element) is mounted on the support substrate 40 via the adhesive layer 42. The element 12 is, for example, a semiconductor chip, and is a small chip such as an optical transmission element or a light emitting element, a transistor, or a sensor. Examples of the light transmission element or the light emitting element include a VCSEL (Vertical Cavity Surface Emitting Laser), a PD (Photodiode), and an LED (Light Emitting Diode). The element 12 is mounted so that the active region is on the support substrate 40 side, for example. For example, when the element 12 is a light emitting element, the light emitting surface is in contact with the adhesive layer 42. A plurality of elements 12 may be mounted on the support substrate 40. The plurality of elements 12 are mounted in a matrix.

  As shown in FIG. 1C, the metal layer 14 is formed on the support substrate 40 so as to cover the element 12 via the adhesive layer 42. The metal layer 14 includes, for example, Cu or Au, and is formed using, for example, a plating method, a sputtering method, or a vapor deposition method. The metal layer 14 is not formed outside the periphery of the element 12, and the adhesive layer 42 is exposed.

  As shown in FIG. 1D, the element 16 (second element) is mounted via an adhesive layer 42 in a region where the metal layer 14 is not formed on the support substrate 40. The element 16 is, for example, a semiconductor chip such as an integrated circuit mainly including silicon, a chip component including an inductor or a capacitor, an interposer, or a sensor. A plurality of elements 16 may be mounted on the support substrate 40. The plurality of elements 16 are mounted in a matrix.

  As shown in FIG. 2A, the resin layer 10 that seals the metal layer 14 and the element 16 is formed on the support substrate 40 via the adhesive layer 42. The resin layer 10 is a thermosetting resin or a thermoplastic resin. An epoxy resin or the like can be used as the resin. For example, the metal layer 14 is exposed from the upper surface of the resin layer 10 by polishing the resin layer 10. The resin layer 10 may cover the metal layer 14 without polishing the resin layer 10. As shown in FIG. 2B, the elements 12, 16, the metal layer 14, and the resin layer 10 are peeled from the support substrate 40. The resin layer 10 is turned upside down. As shown in FIG. 2C, a rewiring layer 20 that is electrically connected to the elements 12 and 16 is formed on the resin layer 10. When a plurality of elements 12 and 16 are mounted on the resin layer 10, the resin layer 10 is separated into pieces using, for example, a dicing method.

  FIG. 3A to FIG. 3C are cross-sectional views of an electronic component according to a comparative example. In the comparative example, the metal layer 14 is not formed. Other steps are the same as those in the first embodiment. As shown to Fig.3 (a), in the comparative example, the adhesiveness of the element 12 and the adhesion layer 42 is weak. For this reason, when the resin layer 10 is formed, the element 12 is inclined. As shown in FIG. 3B, the element 12 moves when the resin layer 10 is formed.

  According to Example 1, after covering the element 12 with the metal layer 14 as shown in FIG. 1C, the resin layer 10 seals the element 12 as shown in FIG. For this reason, the inclination and / or movement of the element 12 can be suppressed. Therefore, the positional accuracy of the element 12 can be improved. For example, since the area of the metal layer 14 and the element 12 bonded to the adhesive layer 42 is larger than the area of the element 12 of the comparative example, the inclination and / or movement of the element can be suppressed.

  In the adhesive layer 42, it is preferable that the elements 12 and 16 do not move in FIG. 2A, and the resin layer 10 can be easily peeled from the support substrate 40 in FIG. 2B. Therefore, as the adhesive layer 42, it is preferable to use a slightly adhesive sheet whose surface direction adhesiveness is greater than the longitudinal direction adhesiveness.

  When the element 12 is smaller than the element 16, particularly when the area of the surface of the element 12 mounted on the support substrate 40 is smaller than the element 16, the element 12 easily moves. Therefore, it is preferable to use Example 1 in such a case.

  As shown in FIG. 3C, when the element 12 generates heat, the heat 38 is conducted through the resin layer 10, so that the thermal resistance is increased.

  According to the first embodiment, heat can be efficiently radiated by using the metal layer 14 as a heat radiator. In FIG. 2B, the resin layer 10 is formed so that the metal layer 14 is exposed from the upper surface of the resin layer 10. Thereby, the heat generated in the element 12 can be radiated from the metal layer 14 exposed from the resin layer 10. For example, a heat sink can be brought into contact with the metal layer 14. Moreover, since the metal layer 14 covers the upper surface and side surface of the element 12, heat dissipation is further improved.

  In addition, as in Patent Document 1, when a chip covered with a heat dissipation cap is mounted on a substrate, the heat dissipation cap is aligned with the substrate. The chip is indirectly aligned with the substrate. Therefore, the positional accuracy of the chip with respect to the substrate is deteriorated. In the first embodiment, since the element 12 is directly aligned with the support substrate 40, the positional accuracy of the element 12 with respect to the support substrate 40 is improved.

  In FIG. 1B, the element 12 is mounted on the support substrate 40 so that the support substrate 40 side becomes the active region of the element 12. Thereby, it is possible to electrically connect to the element 12 from the surface of the element 12 exposed from the resin layer 10.

  The second embodiment is a specific example of the first embodiment. FIG. 4A to FIG. 7C are cross-sectional views illustrating a method for manufacturing an electronic component according to the second embodiment. As shown in FIG. 4A, a slightly adhesive sheet is attached to the upper surface of the support substrate 40 as the adhesive layer 42. The support substrate 40 is, for example, an 8-inch square stainless steel substrate. The adhesive layer 42 is, for example, a slightly adhesive sheet. As shown in FIG. 4B, the element 12 is mounted on the adhesive layer 42. The element 12 is, for example, a VCSEL having an upper surface of 0.25 × 1 mm and a height of 0.35 mm. The element 12 has the support substrate 40 side as the active region side. That is, light is emitted from the support substrate 40 side of the element 12.

  As shown in FIG. 4C, the seed layer 13 is formed on the adhesive layer 42 so as to cover the element 12. The seed layer 13 includes, for example, an adhesion layer and a conductive layer formed on the adhesion layer. The adhesion layer is, for example, a metal layer containing Ti, Cr, Ni, Au, or the like, or an insulating layer containing silicon oxide, titanium nitride, or the like, and is a layer for improving the adhesion between the adhesive layer 42 and the conductive layer. . The conductive layer includes, for example, Au or Cu, and is a metal layer having higher conductivity than the adhesion layer. The film thicknesses of the adhesion layer and the conductive layer are, for example, 0.1 μm and 0.3 μm, respectively. The adhesion layer and the conductive layer are formed using, for example, a sputtering method, a vapor deposition method, or an electroless plating method.

  As shown in FIG. 5A, a mask layer 44 is formed on the seed layer 13. The mask layer 44 has an opening 45 in the region of the element 12. The size of the opening 45 is, for example, 0.65 mm × 1.4 mm. The mask layer 44 is, for example, a photoresist, and is formed using a photolithography method.

  As shown in FIG. 5B, the metal layer 14 is formed in the opening 45. The metal layer 14 is, for example, Cu having a film thickness of 500 μm, and is formed using an electrolytic plating method. The seed layer 13 is used as a current path for electrolytic plating. As shown in FIG. 5C, the mask layer 44 is removed. As a result, the seed layer 13 is exposed in a region other than where the metal layer 14 is formed.

  As shown in FIG. 6A, the seed layer 13 is removed using the metal layer 14 as a mask. The seed layer 13 is removed using, for example, wet etching or dry etching. For example, when the conductive layer is a Cu film and the adhesion layer is a Ti film, the Cu film is removed using wet etching, and the Ti film is removed using dry etching.

  As shown in FIG. 6B, the elements 16a to 16c are mounted in a region where the adhesive layer 42 on the support substrate 40 is exposed. The element 16a is, for example, a silicon chip having an upper surface of 5 mm × 5 mm and a height of 0.4 mm. The silicon chip is, for example, an LSI (Large Scale Integrated circuit) chip. The element 16b and the element 16c are, for example, a 0603 (upper surface area is 0.6 mm × 0.3 mm) chip capacitor and a 1005 (upper surface area is 1.0 mm × 0.5 mm) chip inductor, respectively. The elements 16a to 16c are arranged in a matrix of 10 × 10 at coordinates corresponding to the elements 12, respectively.

  As shown in FIG. 6C, a mold resin is poured onto the adhesive layer 42. The mold resin is, for example, a thermosetting epoxy resin. The resin layer 10 is formed by curing the mold resin. The film thickness of the resin layer 10 is, for example, 600 μm. The 10 × 10 matrix elements 12, 16 a to 16 c form an integral mold wafer 48.

  As shown in FIG. 7A, the mold wafer 48 is peeled from the support substrate 40 by peeling from the adhesive layer 42. As shown in FIG. 7B, the mold wafer 48 is thinned by polishing the upper surface of the mold wafer 48. By setting the film thickness of the mold wafer 48 to 450 μm, for example, the upper surface of the metal layer 14 is exposed from the upper surface of the resin layer 10.

  As shown in FIG. 7C, the mold wafer 48 is turned upside down. As a result, the surface electrodes of the elements 12, 16 a to 16 c are exposed on the upper surface of the mold wafer 48. A rewiring layer 20 is formed on the upper surface of the mold wafer 48. The redistribution layer 20 includes, for example, insulating layers 22a and 22b, metal layers 24a and 24b, and via metals 26a and 26b.

  For example, a photosensitive epoxy varnish for spin coating is applied to the upper surface of the mold wafer 48. Pre-baking, exposure, development, curing, and oxygen plasma treatment are performed. Thereby, the insulating layer 22a having a film thickness of, for example, 8 μm is formed. By exposure and development, an opening having a diameter of 30 μm is formed in the insulating layer 22a, for example, on the surface electrodes of the elements 12, 16a to 16c. Further, an opening having a diameter of 100 μm is formed on the through via penetrating the element 16a. A seed layer is formed on the insulating layer 22 by sputtering. The seed layer is, for example, a Ti film having a thickness of 0.1 μm and a Cu film having a thickness of 0.3 μm. A photoresist mask having an opening is formed on the seed layer. For example, a Cu film having a film thickness of 5 μm is formed in the opening of the photoresist mask by using an electrolytic plating method. Strip the photoresist mask. The seed layer is removed using the Cu film as a mask. Thereby, the metal layer 24a is formed from the seed layer and the Cu film. When the metal layer 24a is formed, a via metal 26a is formed in the opening of the insulating layer 22a.

  An insulating layer 22b having an opening is formed on the insulating layer 22a so as to cover the metal layer 24a. The formation method of the insulating layer 22b is the same as that of the insulating layer 22a, and the description is omitted. A metal layer 24b is formed on the insulating layer 22b. At this time, the via metal 26b is formed in the opening of the insulating layer 22b. The method for forming the metal layer 24b and the via metal 26b is the same as the method for forming the metal layer 24a and the via metal 26a, and a description thereof will be omitted. Openings 30 are formed in the insulating layers 22a and 22b because the light emitted from the element 12 is not absorbed. The surface electrodes of the elements 12, 16a to 16c are electrically connected to the metal layer 24b through the metal layer 24a and the via metals 26a and 26b. The metal layer 24b includes a pad connected to the outside. The metal layer 24b is also formed outside the surface electrodes of the elements 12, 16a to 16c. Thus, the electronic component becomes a fan-out package.

  A package is completed by separating the mold wafer 48 into pieces using a die-singing method. For example, 100 packages can be formed from the mold wafer 48.

  FIG. 8 is a cross-sectional view of the electronic component according to the second embodiment. As shown in FIG. 8, the electronic component 100 includes a resin layer 10, elements 12, 16 a to 16 c, a metal layer 14, and a rewiring layer 20. The resin layer 10 includes a first surface 50 and a second surface 52 that faces the first surface 50. The elements 12, 16 a to 16 c are sealed with the resin layer 10, and the upper surface is exposed from the first surface 50. The metal layer 14 covers the element 12 and one surface is exposed from the second surface 52. The rewiring layer 20 is formed on the first surface 50, and is electrically connected to the elements 12, 16a to 16c. The redistribution layer 20 includes insulating layers 22a to 22c, metal layers 24a and 24b, and via metals 26a and 26b. Light emitted from the element 12 is applied to the optical waveguide 32 through the opening of the rewiring layer 20.

  In Example 2, when a VCSEL is used as the element 12, the temperature of the light emitting surface of the VCSEL is about 40 ° C. On the other hand, when the metal layer 14 is not provided, the temperature of the light emitting surface of the VCSEL is about 90 °. Thus, the metal layer 14 functions as a cooling structure for heat dissipation of the element 12.

  The third embodiment is another specific example of the first embodiment. FIG. 9A to FIG. 9C are cross-sectional views illustrating a method for manufacturing an electronic component according to the third embodiment. As shown in FIG. 9A, a metal layer 14 is formed on the entire surface of the seed layer 13 after FIG. 4C of the second embodiment. The metal layer 14 is, for example, Cu having a film thickness of 500 μm, and is formed using an electrolytic plating method.

  As shown in FIG. 9B, a mask layer 46 including the element 12 is formed on the metal layer 14. The mask layer 46 is, for example, a photoresist. As shown in FIG. 9C, the metal layer 14 is removed using the mask layer 46 as a mask. A wet etching method or a dry etching method is used to remove the metal layer 14. Then, the electronic component which concerns on Example 3 is manufactured by performing the process after Fig.6 (a) of Example 2. FIG.

  As in Examples 2 and 3, the metal layer 14 is formed using a plating method. Thereby, the thick metal layer 14 can be formed.

  Further, as shown in FIG. 4C of the second embodiment, the seed layer 13 is formed on the support substrate 40. As shown in FIG. 5A, a mask layer 44 having an opening 45 including the element 12 is formed on the seed layer 13. As shown in FIG. 5B, the metal layer 14 is formed in the opening 45 of the mask layer 44. As shown in FIG. 5C, the mask layer 44 is removed. As shown in FIG. 6A, the seed layer 13 is removed using the metal layer 14 as a mask. The metal layer 14 can be formed using such a semi-additive method. Thereby, the thick metal layer 14 can be formed.

  Further, as shown in FIG. 9A of the third embodiment, the metal layer 14 is formed on the entire surface of the support substrate 40. As shown in FIG. 9B, a mask layer 46 is formed on the metal layer 14 so as to include the element 12. As shown in FIG. 9C, at least the upper part of the metal layer 14 is removed using the mask layer 46 as a mask. By using such a method, the metal layer 14 can be formed with few man-hours.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Supplementary Note 1) A step of mounting a first element on a support substrate, a step of forming a metal layer so as to cover the first element, and a second region on the support substrate where the metal layer is not formed. A step of mounting an element, a step of forming a resin layer for sealing the metal layer and the second element on the support substrate, and the first element, the second element, the metal layer, and the resin layer. And a step of peeling from the support substrate.
(Supplementary note 2) The method of manufacturing an electronic component according to supplementary note 1, wherein the step of forming the resin layer includes a step of forming the resin layer so that the metal layer is exposed from an upper surface of the resin layer. .
(Supplementary Note 3) The step of mounting the first element includes a step of mounting the first element on the support substrate so that the support substrate side becomes an active region of the first element. The manufacturing method of the electronic component of Additional remark 1 or 2.
(Additional remark 4) The manufacturing method of the electronic component as described in any one of additional remark 1 to 3 including the process of forming a rewiring layer on the said resin layer.
(Additional remark 5) The process of forming the said metal layer includes the process of forming the said metal layer using a plating method, The manufacturing method of the electronic component any one of Additional remark 1 to 4 characterized by the above-mentioned.
(Supplementary Note 6) The step of forming the metal layer includes a step of forming a seed layer on the support substrate, a step of forming a mask layer including an opening including the first element on the seed layer, and the mask Appendices 1 to 4, further comprising: forming the metal layer in the opening of the layer; removing the mask layer; and removing the seed layer using the metal layer as a mask. The manufacturing method of the electronic component as described in any one of these.
(Additional remark 7) The said 1st element is a light receiving element, The manufacturing method of the electronic component as described in any one of additional marks 1-6 characterized by the above-mentioned.
(Supplementary Note 8) A resin layer having a first surface and a second surface facing the first surface, first and second elements sealed by the resin layer and exposed from the second surface, and the first element A metal layer covering one element and having one surface exposed from the first surface; and a rewiring layer formed on the second surface and electrically connected to the first and second elements. Features electronic components.
(Additional remark 9) The said 1st element is a light receiving element, The electronic component of Additional remark 8 characterized by the above-mentioned.

10 Resin layer 12, 16 Element 14 Metal layer 20 Rewiring layer 40 Support substrate

Claims (7)

Mounting the first element on the support substrate;
Forming a metal layer so as to cover the side surface of the first element from the upper surface of the support substrate ;
Mounting the second element in a region where the metal layer is not formed on the support substrate;
Forming a resin layer for sealing the metal layer and the second element on the support substrate;
Peeling the first element, the second element, the metal layer and the resin layer from the support substrate;
The manufacturing method of the electronic component characterized by including.   2. The method of manufacturing an electronic component according to claim 1, wherein the step of forming the resin layer includes a step of forming the resin layer so that the metal layer is exposed from an upper surface of the resin layer.   2. The step of mounting the first element includes a step of mounting the first element on the support substrate so that the support substrate side becomes an active region of the first element. 2. A method for producing an electronic component according to 2.   The method for manufacturing an electronic component according to claim 1, further comprising a step of forming a rewiring layer on the resin layer. A resin layer having a first surface and a second surface facing the first surface;
First and second elements sealed in the resin layer and exposed from the second surface; and
A metal layer covering the first element and having one surface exposed from the first surface;
A redistribution layer formed on the second surface and electrically connected to the first and second elements;
Equipped with,
The electronic component , wherein the metal layer covers a side surface of the first element from a surface of the redistribution layer on the metal layer side .   5. The electron according to claim 1, wherein an area of a surface of the first element mounted on the support substrate is smaller than an area of a surface of the second element mounted on the support substrate. A manufacturing method for parts.   The step of mounting the first element is a step of mounting the first element via an adhesive layer on the support substrate,
  The step of forming the metal layer is a step of forming the metal layer so as to cover the side surface of the first element from the upper surface of the adhesive layer.
  7. The electronic component according to claim 1, wherein the step of mounting the second element is a step of mounting the second element on the support substrate via an adhesive layer. Manufacturing method.

Images