JP6238475B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  A gaming machine having a function of resetting the control circuit unit when an abnormality occurs in the control circuit unit (CPU) is known (for example, see Patent Document 1 below).

Japanese Patent Laying-Open No. 2015-221910

  In the case of a gaming machine including a control circuit unit including a CPU and a peripheral circuit unit that operates in response to an instruction from the control circuit unit, even if an abnormality occurs in the peripheral circuit unit, the control circuit that is the center of control Will be reset. Depending on the gaming machine, when the control circuit unit is reset, it is configured to perform an operation when the power is turned on, and the player perceives it as if a malfunction occurred.

  An object of the present invention is to provide a gaming machine capable of preventing an unnecessary reset from occurring in a control circuit unit.

A gaming machine according to the present invention made to solve the above problems includes a control circuit unit including a CPU, a peripheral circuit unit that operates in response to a command from the control circuit unit, the control circuit unit, and the peripheral circuit A monitoring unit that monitors whether the unit is operating normally, and resets a target circuit unit when it is determined to be abnormal, and transmits a signal transmitted from the control circuit unit to the monitoring unit As a mode, a normal mode that is a mode at normal time and an abnormal mode that is set when an abnormality signal is received from the peripheral circuit unit when an abnormality occurs in the peripheral circuit unit are set, The monitoring means resets the peripheral circuit unit without resetting the control circuit unit when it becomes a situation of receiving the signal of the abnormal mode,
The control circuit unit is configured to be reset when no signal is received from the control circuit unit .

  According to the present invention, when an abnormality occurs in the peripheral circuit unit, the peripheral circuit unit is reset without resetting the control circuit unit. That is, it is possible to prevent the occurrence of a situation in which a control circuit unit having no abnormality is reset.

Also, it is necessary to reset the peripheral circuit unit without resetting the control circuit unit when an abnormality occurs in the peripheral circuit unit, and to reset the control circuit unit when an abnormality occurs in the control circuit unit. It is possible to construct a mechanism for resetting only a simple circuit unit (no unnecessary reset occurs).

  According to the present invention, it is possible to prevent an unnecessary reset from occurring in the control circuit unit.

1 is a front view of a gaming machine according to an embodiment of the present invention. It is a control block diagram of the gaming machine according to one embodiment of the present invention. It is the block diagram which showed the relationship between a control circuit part, a peripheral circuit part, and a timer part. It is a block diagram for explaining an abnormality monitoring function, and is a diagram showing a signal transmission mode when both a control circuit unit and a peripheral circuit unit are normal. It is a block diagram for explaining an abnormality monitoring function, and is a figure showing a signal transmission mode when abnormality occurs in a peripheral circuit section. It is a block diagram for explaining an abnormality monitoring function, and is a figure showing a signal transmission mode when abnormality occurs in a control circuit unit.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings. First, the overall configuration of the gaming machine 1 will be briefly described with reference to FIG. The gaming machine 1 has a frame-shaped machine casing 90, and a front frame 91 is rotatably supported by the machine casing 90. The front frame 91 is provided with a transparent plate that allows the game board 92 to be viewed from the front side.

  The game board 92 is formed of a substantially square plywood and is detachably attached to the front frame 91. The game board 92 is provided with a strip-shaped guide rail 923 made of a thin metal plate for guiding a game ball launched by operating the launcher 94 (handle) to the game area 922 so as to have a substantially arc shape. Yes.

  The game area 922 is provided with a first start winning opening 924, a second starting winning opening 925, a big winning opening 926, an out opening 927, and the like. The display device 93 displays an identification symbol or the like for informing whether or not the jackpot is successful. The display screen of the display device 93 is visible through an opening 921 formed in the game board 92.

  In addition, the game area 922 is provided with a plurality of game nails (not shown) as obstacles that change the flow-down mode of the game balls when the flowing-down game balls collide. The game ball flowing down the game area 922 changes to various modes depending on the condition when it collides with the game nail.

  In such a gaming machine 1, a game ball is launched toward the game area 922 by operating the launching device 94 (handle). When a game ball flowing down the game area 922 wins a winning opening such as a start winning opening 924, 925 or a big winning opening 926, a predetermined number of winning balls are paid out by the payout device. Other configurations and the like can be the same as those of a known gaming machine, and thus descriptions other than those related to the present invention are omitted.

  FIG. 2 is a control block diagram of the gaming machine 1 (however, illustration of monitoring means 50 described later is omitted). The gaming machine 1 includes a main control board 10 and a sub control board 20. Similar to known gaming machines, the main control board 10 has a jackpot lottery based on winning game balls in the start winning ports 924 and 925 and game balls based on winning game balls in various winning ports. A main control circuit unit for controlling the payout is constructed.

  The sub-control board 20 mainly receives a signal from the main control board 10 (success / failure of a big hit flag, a signal notifying that a game ball has won a predetermined winning area, etc.), and determining an effect to be executed. A circuit to be controlled (hereinafter referred to as a control circuit unit 21) is constructed. Specifically, the control circuit unit 21 controls the various devices 40 via the peripheral circuit unit 30 by transmitting an operation command to the peripheral circuit unit 30. Examples of the various devices 40 include various lights, lamps, movable accessories, speakers, and the like. The control circuit unit 21 is a circuit including a CPU 211 for performing arithmetic processing. The peripheral circuit unit 30 does not include a CPU, and is a circuit (driver) that controls the various devices 40 based on a control signal transmitted from the control circuit unit 21 (in the example shown in FIG. 2, a lamp control circuit). And a sound control circuit and a drive circuit correspond to the peripheral circuit unit 30). As long as the circuit satisfies such conditions, the peripheral circuit unit 30 may have any function or specific configuration.

  FIG. 3 is a block diagram showing the relationship between the control circuit unit 21, the peripheral circuit unit 30, and the monitoring unit 50 (note that only one peripheral circuit unit 30 is shown in FIG. 3). When an abnormality occurs in the peripheral circuit unit 30, the peripheral circuit unit 30 outputs an abnormality signal to the control circuit unit 21 (CPU 211). The control circuit unit 21 is a circuit including a ROM 211, a RAM, and the like in which various data for control are stored in addition to the CPU 211.

  As shown in FIG. 3, the gaming machine 1 according to the present embodiment includes monitoring means 50 that monitors whether the control circuit unit 21 and the peripheral circuit unit 30 are operating normally. As will be described later, when the monitoring unit 50 recognizes that an abnormality has occurred, the target circuit unit is reset. The monitoring unit 50 includes a first timer unit 51 and a second timer unit 52. Both timer units are watchdog timers that time up when a signal (clear signal) is not continuously received from the control circuit unit 21 for a predetermined time. The first timer unit 51 and the second timer unit 52 can receive a clear signal from the control circuit unit 21 (CPU 211), the first timer unit 51 provides a reset signal to the control circuit unit 21, and the second timer unit 52 is peripheral. A circuit is constructed so that a reset signal can be transmitted to the circuit unit 30.

  The first timer unit 51 is triggered by the time up resetting the control circuit unit 21. The time until the time-up of the first timer unit 51 (monitoring time) is set to the first time. That is, the first timer unit 51 is timed up when a clear signal for clearing (resetting) and restarting the timer is not received from the control circuit unit 21 until the first time elapses. . On the other hand, in the second timer unit 52, the time-up is an opportunity to reset the peripheral circuit unit 30. The second time, which is the time until the second timer unit 52 times out, is set shorter than the first time, which is the time until the first timer unit 51 times out. That is, when the second timer unit 52 does not receive a clear signal for clearing (resetting) and restarting the timer from the control circuit unit 21 until the second time shorter than the first time elapses. Time is up.

  A clear signal (clock pulse) is transmitted from the control circuit unit 21 to the first timer unit 51 and the second timer unit 52 at predetermined time intervals. During normal operation, a clear signal is transmitted from the control circuit unit 21 at intervals such that both the first timer unit 51 and the second timer unit 52 do not time up (the transmission mode of such a clear signal is Corresponds to the normal mode). That is, the clear signal is transmitted to both timer units at an interval shorter than the second time (an interval shorter than both the first time and the second time).

  On the other hand, when the control circuit unit 21 receives an abnormal signal from the peripheral circuit unit 30, the first timer unit 51 does not time up from the control circuit unit 21, but the second timer unit 52 times up. The clear signal is transmitted in (The transmission mode of such a clear signal corresponds to the abnormal mode in the present invention). That is, the clear signal is transmitted to both timer units at intervals shorter than the first time and longer than the second time.

  Hereinafter, the abnormality monitoring function of the control circuit unit 21 and the peripheral circuit unit 30 of the gaming machine 1 according to the present embodiment will be described in detail although partially overlapping with the above description.

  As shown in FIG. 4, when both the control circuit unit 21 and the peripheral circuit unit 30 are normal, the control circuit unit 21 (CPU 211) causes the first timer unit 51 and the second timer unit to be spaced at intervals shorter than the second time. A clear signal is transmitted to 52. An interval shorter than the second time means an interval shorter than the first time. Therefore, both the first timer unit 51 and the second timer unit 52 do not time up. That is, neither the control circuit unit 21 nor the peripheral circuit unit 30 is reset.

  FIG. 5 sequentially illustrates signal transmission modes in the case where the control circuit unit 21 is normal but an abnormality is recognized in the peripheral circuit unit 30. First, the peripheral circuit unit 30 in which an abnormality has occurred transmits an abnormal signal to the control circuit unit 21 (CPU 211) (see FIG. 5A). Receiving this, the control circuit unit 21 (CPU 211) transmits a clear signal to the first timer unit 51 and the second timer unit 52 at intervals longer than the second time and shorter than the first time (FIG. 5). (See (b)). Since the time until the time is up is set to the second time, the second timer unit 52 times up when the clear signal transmission interval changes to such an interval. When the second timer unit 52 times out, a reset signal is transmitted to the peripheral circuit unit 30 (see FIG. 5C), and the peripheral circuit unit 30 is reset. On the other hand, the first timer unit 51 does not time up, and no reset signal is transmitted to the control circuit unit 21.

  Thus, in this embodiment, although the control circuit unit 21 is normal, when an abnormality is recognized in the peripheral circuit unit 30, only the peripheral circuit unit 30 is reset, and the control circuit unit 21 is not reset. That is, when an abnormality is recognized only in the peripheral circuit unit 30 that does not include the CPU and a minor abnormality that does not require resetting the control circuit unit 21 that controls the peripheral circuit unit 30 occurs, only the peripheral circuit unit 30 is reset. Therefore, it is possible to prevent the occurrence of a situation in which an initial operation (operation when power is turned on) occurs when the control circuit unit 21 is reset.

  FIG. 6 sequentially illustrates signal transmission modes in the case where an abnormality is recognized in the peripheral circuit unit 30. When an abnormality occurs in the control circuit unit 21 (for example, when the CPU 211 goes out of control), a clear signal is completely transmitted from the control circuit unit 21 (CPU 211) to the first timer unit 51 and the second timer unit 52. (See FIG. 6A). Accordingly, the first timer unit 51 times out and a reset signal is transmitted to the control circuit unit 21. As a result, the control circuit unit 21 (CPU 211, ROM, etc. constituting the control circuit unit 21) is reset (see FIG. 6B). Since the clear signal is not transmitted at all, the second timer unit 52 also times up, and the peripheral circuit unit 30 is reset regardless of whether there is an abnormality (see FIG. 6B).

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.

  The gaming machine 1 according to the above embodiment is a so-called pachinko gaming machine, but can be applied to other gaming machines such as a rotating gaming machine.

In the gaming machine 1 according to the above embodiment, the circuit (control circuit unit 21) including the CPU 211 formed on the sub-control board 20 that controls the effects and the peripheral circuit unit 30 that does not include the CPU controlled thereby are abnormal. Although it has been explained that a function for monitoring the presence or absence of a device is provided, if there is a relationship between a circuit including a CPU and a peripheral circuit that operates according to a command transmitted from the circuit, the same technology is applied to these circuits. The idea is applicable. For example, the same technical idea may be applied to a circuit including a CPU formed on the main control board 10 and a peripheral circuit controlled thereby .
Specific means obtained from the above embodiment are listed below.
The gaming machine according to means 1 includes a control circuit unit including a CPU, a peripheral circuit unit that operates in response to a command from the control circuit unit, and whether the control circuit unit and the peripheral circuit unit are operating normally. And monitoring means for resetting a target circuit unit when it is determined to be abnormal, and when an abnormality occurs in the peripheral circuit unit, the monitoring unit resets the control circuit unit. Without resetting the peripheral circuit portion.
According to the gaming machine according to the means 1, when an abnormality occurs in the peripheral circuit unit, the peripheral circuit unit is reset without resetting the control circuit unit. That is, it is possible to prevent the occurrence of a situation in which a control circuit unit having no abnormality is reset.
In the gaming machine according to means 1, in the gaming machine according to means 1, as a mode of a signal transmitted from the control circuit unit to the monitoring unit, a normal mode which is a normal mode and an abnormality in the peripheral circuit unit Is set when triggered by the reception of an abnormal signal from the peripheral circuit unit, and the monitoring means is configured to receive the abnormal mode signal when the control is The peripheral circuit unit is reset without resetting the circuit unit, and the control circuit unit is reset when no signal is received from the control circuit unit.
When the abnormality is generated in the peripheral circuit unit by the configuration like the gaming machine according to the means 2, the peripheral circuit unit is reset without resetting the control circuit unit, and the control circuit unit is abnormal Therefore, it is possible to construct a mechanism for resetting only necessary circuit parts (no unnecessary reset occurs), such as resetting the control circuit part.
The gaming machine according to means 3 is the gaming machine according to means 2, wherein the monitoring means is a timer section that times up when a signal is not continuously received from the control circuit section for a predetermined time, The first timer unit that triggers resetting the control circuit unit, and the second timer that triggers the resetting of the peripheral circuit unit is set shorter than the first timer unit. A timer unit, and the normal mode is a mode in which signals are transmitted at intervals such that both the first timer unit and the second timer unit do not time up, and the abnormal mode is Although the first timer unit does not time up, the signal is transmitted at intervals such that the second timer unit times up.
As in the gaming machine according to the means 3, by using two timer units that trigger the resetting of the circuit unit, a mechanism for resetting only the necessary circuit unit (no unnecessary reset occurs) is constructed. It is possible.

1 gaming machine 20 sub control board 21 control circuit unit 211 CPU
30 Peripheral circuit unit 50 Monitoring means 51 First timer unit 52 Second timer unit

Claims (1)

A control circuit unit including a CPU;
A peripheral circuit unit that operates in response to a command from the control circuit unit;
Monitoring means for monitoring whether the control circuit unit and the peripheral circuit unit are operating normally, and resetting a target circuit unit when it is determined to be abnormal,
Equipped with a,
As an aspect of a signal transmitted from the control circuit unit to the monitoring unit,
A normal mode which is a normal mode;
When an abnormality occurs in the peripheral circuit unit, an abnormal mode that is set when triggered by the reception of an abnormal signal from the peripheral circuit unit;
Is set,
The monitoring means includes
When it becomes the situation to receive the abnormal signal, the peripheral circuit unit is reset without resetting the control circuit unit,
The control circuit unit is reset when no signal is received from the control circuit unit.
A gaming machine that is configured as described above .

Images