JP6286169B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
- Publication number
- JP6286169B2 JP6286169B2 JP2013200631A JP2013200631A JP6286169B2 JP 6286169 B2 JP6286169 B2 JP 6286169B2 JP 2013200631 A JP2013200631 A JP 2013200631A JP 2013200631 A JP2013200631 A JP 2013200631A JP 6286169 B2 JP6286169 B2 JP 6286169B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- hole
- wiring
- surface side
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
- H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
- H10W70/692—Ceramics or glasses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
- H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
- H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
Description
[第1の実施の形態に係る配線基板の構造]
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する断面図である。図1を参照するに、配線基板1は、基板本体11と、絶縁膜12と、密着層13と、金属層14と、配線層15と、密着層23と、金属層24と、配線層25とを有する。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2〜図5は、第1の実施の形態に係る配線基板の製造工程を例示する図である。なお、図2〜図5では、主に貫通孔11xの周辺部分を拡大して例示している。
第2の実施の形態では、基板本体として樹脂を主成分とする基材を用いる例を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する。
11、31 基板本体
11a、31a 基板本体の一方の面
11b、31b 基板本体の他方の面
11x、31x 貫通孔
12 絶縁膜
13、23 密着層
14、24 金属層
15、25 配線層
15a、15b 導電層
15x、15y 凹部
25x 凸部
100 保護膜
110 レジスト層
Claims (7)
- 基板本体と、
前記基板本体の一方の面から他方の面に貫通する貫通孔と、
前記貫通孔内に形成された貫通配線と、を有し、
前記貫通配線は、
前記貫通孔の内側面の前記一方の面側に形成された第1金属層と、
前記第1金属層を被覆して前記貫通孔の前記一方の面側を埋める第1配線層と、
前記貫通孔の内側面の前記他方の面側及び前記第1配線層の前記他方の面側の端部に連続的に形成された第2金属層と、
前記第2金属層を被覆して前記貫通孔の前記他方の面側を埋める第2配線層と、を備え、
前記貫通孔内の前記第1配線層の前記他方の面側の端部には前記他方の面側に開口する凹部が形成され、
前記貫通孔内の前記第2配線層の前記一方の面側の端部には前記一方の面側に突起する凸部が形成され、
前記凸部は前記凹部内に配され、
前記第1配線層と前記第2配線層とが、前記貫通孔内で前記第2金属層を介して導通し、
前記第1配線層は、前記第2配線層の前記一方の面側の端部上に、複数の導電層が積層された構造を有する配線基板。 - 前記複数の導電層は、前記貫通孔の一方の面側の端部を埋めるように形成された第1導電層と、前記第1導電層の前記第2配線層側に形成された第2導電層と、を含み、
前記第1導電層の下端面は、前記第2導電層の上端面と全面で接し、
前記第2導電層の側面の前記第1導電層側の領域は、前記第1金属層と接している請求項1記載の配線基板。 - 前記基板本体と前記第1金属層との間に第1密着層が形成され、
前記基板本体と前記第2金属層との間、及び、前記第1配線層の前記他方の面側の端部と前記第2金属層との間に第2密着層が形成され、
前記第1配線層と前記第2配線層とは、前記貫通孔内で前記第2密着層及び前記第2金属層を介して導通している請求項1又は2記載の配線基板。 - 前記基板本体の材料はシリコンであり、
前記貫通孔の内側面はシリコン酸化膜で被覆され、
前記第1密着層は、前記第1金属層よりも前記シリコン酸化膜との密着性が良好な材料から構成され、
前記第2密着層は、前記第2金属層よりも前記シリコン酸化膜との密着性が良好な材料から構成されている請求項3記載の配線基板。 - 前記貫通孔の内側面に形成された前記第1金属層の厚さは、前記一方の面側から前記貫通孔の深い部分にいくにつれて薄くなり、
前記貫通孔の内側面に形成された前記第2金属層の厚さは、前記他方の面側から前記貫通孔の深い部分にいくにつれて薄くなる請求項1乃至4の何れか一項記載の配線基板。 - 基板本体の一方の面から他方の面に貫通する貫通孔を形成する工程と、
前記貫通孔内に貫通配線を形成する工程と、を有し、
前記貫通配線を形成する工程は、
前記貫通孔の内側面の前記一方の面側に第1金属層を形成する工程と、
前記第1金属層を給電層とする電解めっき法により、前記第1金属層を被覆して前記貫通孔の前記一方の面側を埋める第1配線層を形成する工程と、
前記貫通孔の内側面の前記他方の面側及び前記第1配線層の前記他方の面側の端部に連続的に第2金属層を形成する工程と、
前記第2金属層を給電層とする電解めっき法により、前記第2金属層を被覆して前記貫通孔の前記他方の面側を埋める第2配線層を形成する工程と、を備え、
前記第1配線層を形成する工程では、コンフォーマルめっきにより、前記貫通孔内の前記第1配線層の他部となる導電層の前記他方の面側の端部に前記他方の面側に開口する凹部を形成し、
前記第2配線層を形成する工程では、前記貫通孔内の前記第2配線層の前記一方の面側の端部に前記一方の面側に突起する凸部を形成し、前記凸部を前記凹部内に配し、
前記第1配線層と前記第2配線層とを、前記貫通孔内で前記第2金属層を介して導通させ、
前記第1配線層を形成する工程は、
前記基板本体の一方の面側に、前記貫通孔の前記一方の面側の端部を塞ぐ保護膜を形成する工程と、
前記貫通孔の内側面の前記他方の面側、前記第1金属層、及び前記保護膜の前記貫通孔内に露出する部分を連続的に被覆するレジスト層を形成する工程と、
前記保護膜を除去し、前記レジスト層の一部を前記貫通孔の前記一方の面側の端部から露出させる工程と、
前記レジスト層の前記貫通孔の前記一方の面側の端部から露出する部分上に、前記第1金属層を給電層とする電解めっき法により前記第1配線層の一部となる導電層を形成する工程と、
前記レジスト層を除去した後、前記第1金属層を給電層とする電解めっき法により、前記貫通孔の前記一方の面側を埋めるように、前記第1配線層の一部となる導電層の前記他方の面側に、前記第1配線層の他部となる導電層を形成する工程と、を含む配線基板の製造方法。 - 前記第1金属層及び前記第2金属層は、スパッタ法により形成される請求項6記載の配線基板の製造方法。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013200631A JP6286169B2 (ja) | 2013-09-26 | 2013-09-26 | 配線基板及びその製造方法 |
| US14/471,209 US9392705B2 (en) | 2013-09-26 | 2014-08-28 | Wiring board with through wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013200631A JP6286169B2 (ja) | 2013-09-26 | 2013-09-26 | 配線基板及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015070007A JP2015070007A (ja) | 2015-04-13 |
| JP2015070007A5 JP2015070007A5 (ja) | 2016-08-25 |
| JP6286169B2 true JP6286169B2 (ja) | 2018-02-28 |
Family
ID=52689960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013200631A Active JP6286169B2 (ja) | 2013-09-26 | 2013-09-26 | 配線基板及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9392705B2 (ja) |
| JP (1) | JP6286169B2 (ja) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016073658A1 (en) | 2014-11-05 | 2016-05-12 | Corning Incorporated | Bottom-up electrolytic via plating method |
| KR101898404B1 (ko) * | 2014-12-17 | 2018-09-12 | 미쓰이 가가쿠 가부시키가이샤 | 기판 중간체, 관통 비어 전극 기판 및 관통 비어 전극 형성 방법 |
| EP3307035B1 (en) * | 2015-05-31 | 2020-02-26 | Kiyokawa Plating Industry Co., Ltd. | Method for manufacturing wiring board |
| JP6563317B2 (ja) * | 2015-11-25 | 2019-08-21 | 新光電気工業株式会社 | プローブガイド板及びその製造方法とプローブ装置 |
| US9966371B1 (en) | 2016-11-04 | 2018-05-08 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
| US9966361B1 (en) | 2016-11-04 | 2018-05-08 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
| US10700035B2 (en) * | 2016-11-04 | 2020-06-30 | General Electric Company | Stacked electronics package and method of manufacturing thereof |
| US10312194B2 (en) | 2016-11-04 | 2019-06-04 | General Electric Company | Stacked electronics package and method of manufacturing thereof |
| US10917966B2 (en) | 2018-01-29 | 2021-02-09 | Corning Incorporated | Articles including metallized vias |
| US11152294B2 (en) * | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
| US12200875B2 (en) | 2018-09-20 | 2025-01-14 | Industrial Technology Research Institute | Copper metallization for through-glass vias on thin glass |
| CN111511102B (zh) * | 2019-01-31 | 2023-12-15 | 奥特斯奥地利科技与系统技术有限公司 | 在通孔中具有符合最小距离设计原则的桥结构的部件承载件 |
| KR20250083587A (ko) | 2019-02-21 | 2025-06-10 | 코닝 인코포레이티드 | 구리-금속화된 쓰루 홀을 갖는 유리 또는 유리 세라믹 물품 및 이를 제조하기 위한 공정 |
| IT201900006736A1 (it) * | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di fabbricazione di package |
| IT201900006740A1 (it) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di strutturazione di substrati |
| US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
| US11257790B2 (en) | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
| US11851321B2 (en) * | 2021-03-01 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro-electro mechanical system and manufacturing method thereof |
| US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
| US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
| US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
| US12408475B2 (en) * | 2020-12-28 | 2025-09-02 | Suzhou Institute Of Nano-Tech And Nano-Bionics (Sinano) , Chinese Academy Of Sciences | Interconnected electrode structure having multi-conductive through hole and method of manufacturing same |
| CN115621192B (zh) * | 2021-07-13 | 2025-10-21 | 长鑫存储技术有限公司 | 一种半导体结构及其形成方法 |
| CN114899197B (zh) * | 2022-06-20 | 2023-07-18 | 业成科技(成都)有限公司 | 显示面板、显示面板制造方法以及显示装置 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6016012A (en) * | 1996-11-05 | 2000-01-18 | Cypress Semiconductor Corporation | Thin liner layer providing reduced via resistance |
| US6498381B2 (en) * | 2001-02-22 | 2002-12-24 | Tru-Si Technologies, Inc. | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same |
| US6954984B2 (en) * | 2002-07-25 | 2005-10-18 | International Business Machines Corporation | Land grid array structure |
| US6716737B2 (en) * | 2002-07-29 | 2004-04-06 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
| JP4098673B2 (ja) | 2003-06-19 | 2008-06-11 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
| JP4634735B2 (ja) * | 2004-04-20 | 2011-02-16 | 大日本印刷株式会社 | 多層配線基板の製造方法 |
| JP4298601B2 (ja) * | 2004-07-06 | 2009-07-22 | 東京エレクトロン株式会社 | インターポーザおよびインターポーザの製造方法 |
| KR100632552B1 (ko) * | 2004-12-30 | 2006-10-11 | 삼성전기주식회사 | 내부 비아홀의 필 도금 구조 및 그 제조 방법 |
| JP2007005404A (ja) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | 半導体基板への貫通配線の形成方法 |
| US7795134B2 (en) * | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
| US7429529B2 (en) * | 2005-08-05 | 2008-09-30 | Farnworth Warren M | Methods of forming through-wafer interconnects and structures resulting therefrom |
| JP4801078B2 (ja) * | 2005-09-01 | 2011-10-26 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| TWI272886B (en) * | 2006-02-27 | 2007-02-01 | Advanced Semiconductor Eng | Substrate with multi-layer PTH and method for forming the multi-layer PTH |
| US7749899B2 (en) * | 2006-06-01 | 2010-07-06 | Micron Technology, Inc. | Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces |
| JPWO2011062037A1 (ja) * | 2009-11-20 | 2013-04-04 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
| JP5360494B2 (ja) * | 2009-12-24 | 2013-12-04 | 新光電気工業株式会社 | 多層配線基板、多層配線基板の製造方法、及びヴィアフィル方法 |
| KR101167466B1 (ko) * | 2010-12-30 | 2012-07-26 | 삼성전기주식회사 | 다층 인쇄회로기판 그 제조방법 |
| JP5613620B2 (ja) * | 2011-05-27 | 2014-10-29 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| JP2013077807A (ja) * | 2011-09-13 | 2013-04-25 | Hoya Corp | 基板製造方法および配線基板の製造方法 |
-
2013
- 2013-09-26 JP JP2013200631A patent/JP6286169B2/ja active Active
-
2014
- 2014-08-28 US US14/471,209 patent/US9392705B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20150083469A1 (en) | 2015-03-26 |
| JP2015070007A (ja) | 2015-04-13 |
| US9392705B2 (en) | 2016-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6286169B2 (ja) | 配線基板及びその製造方法 | |
| JP4611943B2 (ja) | 半導体装置 | |
| JP4787559B2 (ja) | 半導体装置およびその製造方法 | |
| JP4937842B2 (ja) | 半導体装置およびその製造方法 | |
| JP6251629B2 (ja) | 配線基板及び配線基板の製造方法 | |
| JP5568357B2 (ja) | 半導体装置及びその製造方法 | |
| JP6041731B2 (ja) | インターポーザ、及び電子部品パッケージ | |
| JP2014013810A (ja) | 基板、基板の製造方法、半導体装置、及び電子機器 | |
| JP5775747B2 (ja) | 配線基板及びその製造方法 | |
| CN107567651B (zh) | 具有贯通电极的布线基板及其制造方法 | |
| CN101183668A (zh) | 电解电镀形成突起电极的半导体装置及其制造方法 | |
| JP6619294B2 (ja) | 配線基板及びその製造方法と電子部品装置 | |
| US8349736B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| TW202013608A (zh) | 半導體裝置及其製造方法 | |
| US9548280B2 (en) | Solder pad for semiconductor device package | |
| JP2008210933A (ja) | 半導体装置 | |
| CN103456715A (zh) | 中介基材及其制作方法 | |
| JP4506767B2 (ja) | 半導体装置の製造方法 | |
| TWI512923B (zh) | 中介板及其製法 | |
| JP5608430B2 (ja) | 配線基板及び配線基板の製造方法 | |
| CN102376677B (zh) | 半导体封装结构及半导体封装结构的制作方法 | |
| JP6712136B2 (ja) | 電子部品の製造方法 | |
| TWM629323U (zh) | 覆晶封裝結構 | |
| JP2011238742A (ja) | 配線基板の製造方法及び配線基板 | |
| JP2012134526A (ja) | 半導体装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160707 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160707 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170516 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170613 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170809 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180116 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180205 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6286169 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |