JP6318975B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a multilayer wiring layer is disposed on one surface of a substrate, and a capacitor is configured in the multilayer wiring layer.

  2. Description of the Related Art Conventionally, there has been known a semiconductor device in which a multilayer wiring layer is disposed on a substrate such as silicon and a capacitor is configured in the multilayer wiring layer (see, for example, Patent Document 1). Specifically, in such a semiconductor device, the multilayer wiring layer is configured by alternately laminating wiring layers and interlayer insulating films. The lower electrode is composed of the nth (n is a natural number) wiring layer from the substrate side, and the upper electrode is composed of the (n + 1) th wiring layer. A capacitor is configured by using an insulating film therebetween as a dielectric film.

  Such a semiconductor device includes a step of preparing a substrate and forming a metal film on the substrate, a step of patterning the metal film to form a wiring layer, a step of forming an interlayer insulating film, and an interlayer insulating film. It is manufactured by repeatedly performing a process of flattening the opposite side of the substrate side by a CMP (Chemical Mechanical Polishing) method.

JP 2004-146632 A

  By the way, in the semiconductor device as described above, a plurality of capacitors having the same capacitance may be formed in the multilayer wiring layer. Such a semiconductor device changes the way of patterning the metal film in the manufacturing method. Manufactured by.

  However, when the interlayer insulating film is planarized by the CMP method, the CMP method is affected by the wiring layer (underlying film) covered by the interlayer insulating film to be polished. Specifically, since the CMP method is elastically deformed by the pressure from the portion in contact with the polishing pad, the interlayer insulating film tends to be thick on the portion where the wiring layer is dense, and the wiring layer becomes sparse. It tends to be thin on the part where it is. That is, for example, when three lower electrodes are sequentially arranged along one direction in the surface direction of the substrate in the multilayer wiring layer, the interlayer insulating film tends to be thick on the central lower electrode, and the lower electrode 2 is sandwiched between the lower electrodes. The interlayer insulating film tends to be thin on the two lower electrodes. That is, the interlayer insulating film tends to be thick in the center capacitor, and the interlayer insulating film tends to be thin in the two outer capacitors. Therefore, there is a problem that the capacitance of each capacitor formed in the interlayer insulating film varies.

  In view of the above, an object of the present invention is to provide a semiconductor device capable of suppressing variations in capacitance of capacitors formed in a multilayer wiring layer.

  In order to achieve the above object, according to the invention described in claim 1, the substrate (10) having one surface (10a), the wiring layers (40, 60), and the interlayer insulating film (50) are alternately laminated. The semiconductor device having the multilayer wiring layer (30) disposed on one surface of the substrate is characterized by the following points.

  That is, the wiring layer of the nth layer (n is a natural number) from the substrate side of the wiring layers is a plurality of lower electrodes (41a) that are three or more arranged in order along the first direction in the surface direction of the substrate. In the plurality of lower electrodes, a region sandwiched between other lower electrodes becomes a dense region and a region different from the dense region becomes a sparse region, and the interlayer insulating film is formed on the lower electrode of the dense region. The thickness of the portion located is thicker than the thickness of the portion located on the lower electrode of the sparse region, and the (n + 1) th wiring layer from the substrate side of the wiring layer faces the plurality of lower electrodes, respectively. A plurality of lower electrodes, a plurality of upper electrodes, and a plurality of interlayer insulating films between the plurality of lower electrodes and the plurality of upper electrodes in the multilayer wiring layer. Capacitors (C1 to C3) are formed, and the lower part of the dense region Opposing area between the lower electrode and the upper electrode of the dense capacitors having electrode is characterized in that it is larger than the opposing area between the lower electrode and the upper electrode sparse capacitor having a lower electrode of low-density regions.

  According to this, by adjusting the facing area between the lower electrode and the upper electrode of the dense capacitor and the facing area between the lower electrode and the upper electrode of the sparse capacitor, the capacity of the dense capacitor and the capacity of the sparse capacitor vary. Can be suppressed.

  Further, as in the invention described in claim 6, the nth wiring layer has four lower electrodes (41a to 41d) along the first direction, and in the multilayer wiring layer, A dense capacitor and a sparse capacitor are connected to form a composite capacitor (C1 ′, C2 ′).

  According to this, two composite capacitors are configured by connecting a dense capacitor and a sparse capacitor. For this reason, each composite capacitor includes both a component of a dense capacitor having a lower electrode in a dense region and a component of a sparse capacitor having a lower electrode in a sparse region, thereby suppressing variations in capacitance. it can.

  Furthermore, since the voltage dependency of the capacitance changes depending on the film thickness, connecting the dense capacitor and the sparse capacitor to form two composite capacitors suppresses variation in the voltage dependency of the capacitance of each composite capacitor. it can.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing of the semiconductor device in 1st Embodiment of this invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. It is a figure which shows the relationship between the capacity | capacitance per unit area, and a temperature characteristic. It is sectional drawing of the semiconductor device in 2nd Embodiment of this invention. FIG. 6 is a plan view of the semiconductor device shown in FIG. 5. It is a top view of the semiconductor device in a 3rd embodiment of the present invention. It is a top view of the semiconductor device in a 4th embodiment of the present invention. It is a top view of the semiconductor device in a 5th embodiment of the present invention. It is a top view of the semiconductor device in the modification of 5th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the semiconductor device includes a substrate 10 such as a silicon substrate, and semiconductor elements such as diodes and transistors (not shown) are formed on the substrate 10. A multilayer wiring layer 30 is disposed on one surface 10a of the substrate 10 with an oxide film 20 interposed therebetween. In this embodiment, first to third capacitors C1 to C3 are formed in the multilayer wiring layer 30. Yes.

  Specifically, the multilayer wiring layer 30 of the present embodiment is configured by sequentially laminating a first wiring layer 40, an interlayer insulating film 50, and a second wiring layer 60, and the first wiring layer 40 is formed of the oxide film 20. Formed on top.

  The first wiring layer 40 is made of Al or the like, and as shown in FIGS. 1 and 2, one direction in the surface direction of the substrate 10 is the first direction (the left and right direction in FIG. 1 and FIG. 2), When the second direction is a direction orthogonal to the first direction and parallel to the surface direction of the substrate 10, first to third lower electrodes 41 a to 41 c arranged in order along the first direction; The first to third lower electrodes 41a to 41c have wiring patterns (not shown) connected as appropriate. In the present embodiment, each of the first to third lower electrodes 41a to 41c has a planar rectangular shape (square shape) and the same area, and the length between them is equal.

  In the present embodiment, the first to third lower electrodes 41a to 41c are arranged as described above, and the second lower electrode 41b is sandwiched between the first and third lower electrodes 41a and 41c. Therefore, the second lower electrode 41b becomes a dense region of the present invention, and the first and third lower electrodes 41a and 41c become sparse regions of the present invention. 1 corresponds to the II cross section in FIG. 2, and FIG. 2 is a plan view in which the interlayer insulating film 50 and the protective film 70 are omitted.

  The interlayer insulating film 50 is made of TEOS (Tetra Ethyl Ortho Silicate) or the like and is disposed so as to cover the first wiring layer 40. The side opposite to the substrate 10 side is polished by the CMP method. For this reason, in the interlayer insulating film 50, the film thickness on the second lower electrode 41b which is a dense region is thicker than the film thickness on the first and third lower electrodes 41a and 41c which are sparse regions. The interlayer insulating film 50 on the first and third lower electrodes 41a and 41c has the same film thickness.

  The second wiring layer 60 is made of Al or the like and is disposed on the interlayer insulating film 50. And it has the 1st-3rd upper electrode 61a-61c facing the 1st-3rd lower electrode 41a-41c, and the wiring pattern which is not illustrated suitably connected with the 1st-3rd upper electrode 61a-61c. ing. Accordingly, the first to third lower electrodes 41a to 41c, the first to third upper electrodes 61a to 61c, the first to third lower electrodes 41a to 41c, and the first to third upper electrodes 61a to 61c. The first to third capacitors C <b> 1 to C <b> 3 are formed in the multilayer wiring layer 30 by the interlayer insulating film 50 as a dielectric film disposed therebetween.

  In the present embodiment, the second capacitor C2 has the second lower electrode 41b in which the dense region is formed, and the first and third lower electrodes 41a, 41c in which the first and third capacitors C1, C3 are formed in the sparse region are provided. Have. Therefore, the second capacitor C2 is a dense capacitor according to the present invention, and the first and third capacitors C1 and C3 are sparse capacitors according to the present invention.

  In addition, the first to third upper electrodes 61a to 61c have a planar rectangular shape (square shape) in the present embodiment. The second upper electrode 61b has a larger area than the first and third upper electrodes 61a and 61c, and the first and third upper electrodes 61a and 61c have the same area. That is, the facing area between the second lower electrode 41b and the second upper electrode 61b is larger than the facing area between the first and third lower electrodes 41a and 41c and the first and third upper electrodes 61a and 61c.

  That is, as is well known, the capacitance of the capacitor is proportional to the size of the area of the counter electrode and inversely proportional to the length between the counter electrodes. That is, the capacitances of the first to third capacitors C1 to C3 are proportional to the opposing areas of the first to third lower electrodes 41a to 41c and the first to third upper electrodes 61a to 61c, respectively, It is inversely proportional to the length between the lower electrodes 41a to 41c and the first to third upper electrodes 61a to 61c (film thickness of the interlayer insulating film 50). For this reason, since the second capacitor C2 has a longer length between the counter electrodes than the first and third capacitors C1 and C3 (the interlayer insulating film 50 is thick), the capacitance of the second capacitor C2 is larger than that of the first and third capacitors C1 and C3. The opposing area is increased by increasing the area of the second upper electrode 61b so as to be equal.

  The areas of the first to third upper electrodes 61a to 61c are areas when the first to third upper electrodes 61a to 61c are viewed from the normal direction to the one surface 10a of the substrate 10. That is, the areas of the first to third upper electrodes 61a to 61c are the areas of the first to third upper electrodes 61a to 61c shown in FIG.

  A protective film 70 made of polyimide or the like is disposed on the multilayer wiring layer 30 so as to cover the second wiring layer 60.

  The above is the configuration of the semiconductor device in this embodiment. Next, a method for manufacturing the semiconductor device will be described.

  First, as shown in FIG. 3A, a substrate 10 on which semiconductor elements such as diodes and transistors (not shown) are formed is prepared, and an oxide film is formed on one surface 10a of the substrate 10 by a CVD (Chemical Vapor Deposition) method or the like. 20 is formed. Next, as shown in FIG. 3B, a metal film such as Al is formed on the oxide film 20 by a CVD method, a PVD (Physical Vapor Deposition) method, or the like. Then, by patterning the metal film by etching or the like, the first wiring layer 40 having the first to third lower electrodes 41a to 41c is formed.

  Subsequently, as illustrated in FIG. 3C, an interlayer insulating film 50 is formed by CVD or the like so as to cover the first wiring layer 40, and then the interlayer insulating film 50 is formed from the side opposite to the substrate 10. Planarization is performed by CMP. In this case, the interlayer insulating film 50 is affected by the covering first wiring layer 40 (underlying film), and tends to be thick on the portion where the first wiring layer 40 is dense, and the first wiring layer 40 is sparse. It tends to be thin on some parts. Therefore, the interlayer insulating film 50 has a film thickness on the second lower electrode 41b larger than that on the first and third lower electrodes 41a and 41c.

  Subsequently, as shown in FIG. 3D, a metal film such as Al is formed on the interlayer insulating film 50 by a CVD method, a PVD method, or the like. Then, by patterning the metal film by etching or the like, the second wiring layer 60 having the first to third upper electrodes 61a to 61c having the above shape is formed.

  Thereafter, as shown in FIG. 3E, a protective film 70 is formed so as to cover the second wiring layer, whereby the semiconductor device shown in FIG. 1 is manufactured.

  As described above, in this embodiment, the interlayer insulating film 50 has a film thickness on the second lower electrode 41b larger than that on the first and third lower electrodes 41a and 41c. The opposing area between the second lower electrode 41b and the second upper electrode 61b is larger than the opposing area between the first and third lower electrodes 41a and 41c and the first and third upper electrodes 61a and 61c. For this reason, it can suppress that the capacity | capacitance of the 1st-3rd capacitor C1-C3 varies by adjusting the area of the 1st-3rd upper electrode 61a-61c.

  Further, the capacitance of the capacitor has temperature dependence, and as shown in FIG. 4, the change in temperature characteristic (absolute value of the slope in FIG. 4) increases as the capacitor size increases. In other words, the capacitance of the capacitor is proportional to the area of the counter electrode and inversely proportional to the length between the counter electrodes (the film thickness of the dielectric film). Therefore, per unit area, the length between the counter electrodes decreases. Increases temperature dependency. For this reason, in the present embodiment, the first and third capacitors C1 and C3 have a shorter length between the counter electrodes than the second capacitor C2 (though the interlayer insulating film 50 is thin). Therefore, it is possible to suppress variation in the temperature dependence of the capacities of the first to third capacitors C1 to C3 as a whole.

  In FIG. 4, the capacitor size is changed so that a predetermined capacitance is configured. In FIG. 4, the large capacitor size is a single capacitor configured to have a predetermined capacity. In addition, the capacitor size is a composite capacitor configured by connecting several tens of capacitors so as to have a predetermined capacity, and the small capacitor size connects several hundred capacitors so as to have a predetermined capacity. This is a composite capacitor constituted by the above.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, through-holes are formed in the first to third upper electrodes 61a to 61c with respect to the first embodiment, and the other aspects are the same as those of the first embodiment, and thus the description thereof is omitted here. To do.

In the present embodiment, as shown in FIGS. 5 and 6, the first to third upper electrode 61a~61c are their respective there is a contour equal planar rectangular shape. The first to third upper electrodes 61a to 61c are formed with cylindrical through holes 62a to 62c at substantially the center.

  Specifically, the diameter of the through hole 62a formed in the second upper electrode 61b is smaller than the diameter of the through holes 62a and 62c formed in the first and third upper electrodes 61a and 61c. In other words, the through-hole 62b formed in the second upper electrode 61b has a cross-sectional area perpendicular to the normal direction to the one surface 10a of the substrate 10 and the through-hole 62a formed in the first and third upper electrodes 61a and 61c. 62c. In other words, in the through holes 62a to 62c, the opposing area between the second lower electrode 41b and the second upper electrode 61b is opposite to the first and third lower electrodes 41a and 41c and the first and third upper electrodes 61a and 61c. The diameter is adjusted to be larger than the area.

  The through holes 62a to 62c formed in the first and third upper electrodes 61a and 61c have the same diameter. 5 corresponds to the VV cross section of FIG. 6, and FIG. 6 is a plan view in which the interlayer insulating film 50 and the protective film 70 are omitted.

  In this way, by forming the through holes 62a to 62c, the opposing area between the second lower electrode 41b and the second upper electrode 61b is such that the first and third lower electrodes 41a and 41c and the first and third upper electrodes 61a. , 61c, the same effect as in the first embodiment can be obtained.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the configurations of the first wiring layer 40 and the second wiring layer 60 are changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment, and thus the description thereof is omitted here. To do.

  In the present embodiment, as shown in FIG. 7, the first wiring layer 40 includes first to ninth lower electrodes 41 a to 41 i, and the first to ninth lower electrodes 41 a to 41 i are respectively The area is equal to a flat rectangular shape (square shape). The first to third lower electrodes 41a to 41c, the fourth to sixth lower electrodes 41d to 41f, and the seventh to ninth lower electrodes 41g to 41i are sequentially arranged along the first direction, and the first , Fourth, seventh lower electrodes 41a, 41d, 41g, second, fifth, eighth lower electrodes 41b, 41e, 41h, third, sixth, ninth lower electrodes 41c, 41f, 41i in the second direction Are arranged in order. Further, the first to ninth lower electrodes 41a to 41i are equal in length to each other. That is, the first to ninth lower electrodes 41a to 41i are centered on the fifth lower electrode 41e, and the first to fourth lower electrodes 41a to 41d and the sixth to ninth lower electrodes are arranged around the fifth lower electrode 41a. 41f-41i are arrange | positioned equally. FIG. 7 is a plan view in which the interlayer insulating film 50 and the protective film 70 are omitted.

  In the present embodiment, the fifth lower electrode 41e is sandwiched between the fourth and sixth lower electrodes 41d and 41f in the first direction, and is sandwiched between the second and eighth lower electrodes 41b and 41h in the second direction. It is. For this reason, the fifth lower electrode 41e is a dense region of the present invention. In the first direction, the second lower electrode 41b is sandwiched between the first and third lower electrodes 41a and 41c, and the eighth lower electrode 41h is sandwiched between the seventh and ninth lower electrodes 41g and 41i. Similarly, in the second direction, the fourth lower electrode 41d is sandwiched between the first and seventh lower electrodes 41a and 41g, and the sixth lower electrode 41f is sandwiched between the third and ninth lower electrodes 41c and 41i. For this reason, the second, fourth, sixth, and eighth lower electrodes 41b, 41d, 41f, and 41h are the low-density regions of the present invention. The first, third, seventh, and ninth lower electrodes 41a, 41c, 41g, and 41i are not sandwiched between the other lower electrodes 41b, 41d to 41f, and 41h in the first and second directions. Therefore, the first, third, seventh, and ninth lower electrodes 41a, 41c, 41g, and 41i are sparse regions of the present invention.

  The interlayer insulating film 50 has the largest film thickness on the fifth lower electrode 41e, which is a dense region. Then, the film thickness on the second, fourth, sixth, and eighth lower electrodes 41b, 41d, 41f, and 41h, which are the low-density regions, becomes the second largest, and the first, third, seventh, and ninth lower electrodes The film thickness on 41a, 41c, 41g, 41i is the thinnest.

  The second wiring layer 60 includes first to ninth upper electrodes 61a to 61i facing the first to ninth lower electrodes 41a to 41i. For this reason, in the present embodiment, the first to ninth capacitors C <b> 1 to C <b> 9 are configured in the multilayer wiring layer 30.

  In the present embodiment, the fifth capacitor C5 has the fifth lower electrode 41b that becomes a high-density region, and the second, fourth, sixth, and eighth capacitors C2, C4, C6, and C8 become low-density regions. First, third, seventh, and ninth capacitors C1, C3, C7, and C9 are sparse regions having second, fourth, sixth, and eighth lower electrodes 41b, 41d, 41f, and 41h. , Fourth, seventh, and ninth lower electrodes 41a, 41c, 41g, and 41i. Therefore, the fifth capacitor C5 becomes the high-density capacitor of the present invention, and the second, fourth, sixth, and eighth capacitors C2, C4, C6, and C8 become the low-density capacitor of the present invention, and the first, third, and third capacitors. The seventh and ninth capacitors C2 are sparse capacitors of the present invention.

The first to ninth upper electrodes 61a to 61i have the largest area of the fifth upper electrode 61e, and the second, fourth, sixth, and eighth upper electrodes 61b, 61d, 61f, and 61h have the following areas. The area of the first, third, seventh, and ninth upper electrodes 61a, 61c, 61g, and 61i is minimized. As described above, in the present embodiment, the film thickness of the interlayer insulating film 50 is increased. Are the parts located on the fifth lower electrode 41e, the parts located on the second, fourth, sixth and eighth lower electrodes 41b, 41d, 41f and 41h, the first, third, seventh and ninth It becomes thinner in the order of the portions located on the lower electrodes 41a, 41c, 41g, 41i. The first to ninth upper electrodes 61a to 61i include a fifth upper electrode 61e, second, fourth, sixth, and eighth upper electrodes 61b, 61d, 61f, 61h, first, third, seventh, The areas are made smaller in the order of the ninth upper electrodes 61a, 61c, 61g, 61i. For this reason, by adjusting the areas of the first to ninth upper electrodes 61a to 61i, the same effects as those of the first embodiment can be achieved while suppressing variations in the capacitances of the first to ninth capacitors C1 to C9. Can be obtained.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In this embodiment, a capacitor is formed by connecting capacitors to the first embodiment, and the others are the same as those in the first embodiment. Therefore, the description thereof is omitted here.

  In the present embodiment, as shown in FIG. 8, the first wiring layer 40 includes first to fourth lower electrodes 41 a to 41 d that are sequentially arranged along the first direction and have the same area. Yes. The second lower electrode 41b is sandwiched between the first and third lower electrodes 41a and 41c, and the third lower electrode 41c is sandwiched between the second and fourth lower electrodes 41b and 41d. Therefore, the second and third lower electrodes 41b and 41c are the dense regions of the present invention, and the first and fourth lower electrodes 41a and 41d are the sparse regions of the present invention. The first to fourth lower electrodes 41a to 41d have the same length between each other. FIG. 8 is a plan view in which the interlayer insulating film 50 and the protective film 70 are omitted.

  In the interlayer insulating film 50, the film thickness on the second and third lower electrodes 41b and 41c which are dense regions is thicker than the film thickness on the first and fourth lower electrodes 41a and 41d which are sparse regions. The film thickness of the interlayer insulating film 50 on the second and third lower electrodes 41b and 41c is equal to each other, and the film thickness of the interlayer insulating film 50 on the first and fourth lower electrodes 41a and 41d is Are equal to each other.

  The second wiring layer 60 includes first to fourth upper electrodes 61a to 61d facing the first to fourth lower electrodes 41a to 41d. As a result, the first to fourth capacitors C <b> 1 to C <b> 4 are configured in the multilayer wiring layer 30.

  In the first to fourth upper electrodes 61a to 61d, the areas of the second and third upper electrodes 61b and 61c are larger than the areas of the first and fourth upper electrodes 61a and 61d.

  As described above, the capacitances of the first to fourth capacitors C1 to C4 vary by forming the first to fourth upper electrodes 61a to 61d and adjusting the areas of the first to fourth upper electrodes 61a to 61d. Can be suppressed. However, the first to fourth capacitors C1 to C4 include the second and third capacitors C2 having the second and third lower electrodes 41b and 41c which are dense regions among the first to fourth lower electrodes 41a to 41d. Capacitance variation occurs between C3 and the first and fourth capacitors C1 and C4 having the first and fourth lower electrodes 41a and 41d, which are the sparse regions of the first to fourth lower electrodes 41a to 41d. There are things to do.

  Therefore, in the present embodiment, the first combined capacitor C1 ′ is configured by connecting the first and second capacitors C1 and C2 in parallel through the wiring patterns of the first and second wiring layers 40 and 60. Yes. Similarly, the second composite capacitor C2 ′ is configured by connecting the third and fourth capacitors C3 and C4 in parallel via the wiring patterns of the first and second wiring layers 40 and 60. That is, in the present embodiment, the first and second composite capacitors C1 ′ and C2 ′ are configured in the multilayer wiring layer 30.

  As described above, in the present embodiment, in the multilayer wiring layer 30, the second, third lower electrodes 41b, 41c having the second and third lower electrodes 41b, 41c, which are dense regions among the first to fourth lower electrodes 41a-41d. The third capacitors C2 and C3 are connected to the first and fourth capacitors C1 and C4 having the first and fourth lower electrodes 41a and 41d which are sparse regions of the first to fourth lower electrodes 41a to 41d. First and second composite capacitors C1 ′ and C2 ′ are configured. For this reason, the first and second composite capacitors C1 ′ and C2 ′ include both a capacitor component having a dense lower electrode and a capacitor component having a sparse lower electrode. It is possible to suppress variation in the capacitances of the first and second composite capacitors C1 ′ and C2 ′.

  Further, it is known that the capacitor has a voltage dependency that decreases as the film thickness increases. Therefore, as described above, the first capacitor C1 in which the interlayer insulating film 50 is thin, the second capacitor C2 in which the interlayer insulating film 50 is thick, and the fourth capacitor C4 in which the interlayer insulating film 50 is thin By connecting the third capacitor C3 having a thick interlayer insulating film 50 to form the first and second composite capacitors C1 'and C2', the capacitance voltage of the first and second capacitors C1 'and C2' is obtained. It is also possible to suppress variations in dependence.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In this embodiment, the number of lower electrodes and upper electrodes is changed with respect to the fourth embodiment, and the other parts are the same as those in the first embodiment, and thus the description thereof is omitted here.

  In the present embodiment, as shown in FIG. 9, the first wiring layer 40 includes first to sixteenth lower electrodes 41 a to 41 p, and these first to sixteenth lower electrodes 41 a to 41 p are respectively The area is equal to a flat rectangular shape (square shape). Specifically, the first to fourth lower electrodes 41a to 41d, the fifth to eighth lower electrodes 41e to 41h, the ninth to twelfth lower electrodes 41i to 41l, and the thirteenth to sixteenth lower electrodes 41m to 41o are: It arrange | positions in order along a 1st direction, and the length between each is made equal. The first, fifth, ninth, and thirteenth lower electrodes 41a, 41e, 41i, and 41m, the second, sixth, tenth, and fourteenth lower electrodes 41b, 41f, 41j, 41n, the third, the seventh, The eleventh, fifteenth lower electrodes 41c, 41g, 41k, 41o, the fourth, eighth, twelfth, sixteenth lower electrodes 41d, 41h, 41l, 41p are sequentially arranged along the second direction, and The lengths between are equal. That is, the first to sixteenth lower electrodes 41a to 41p are centered on the sixth, seventh, tenth, and eleventh lower electrodes 41f, 41g, 41j, and 41k, and the sixth, seventh, tenth, and eleventh electrodes. The first to fifth, eighth, ninth, twelfth to sixteenth lower electrodes 41a to 41e, 41h, 41i, and 41l to 41p are equally arranged around the lower electrodes 41f, 41g, 41j, and 41k. FIG. 9 is a plan view in which the interlayer insulating film 50 and the protective film 70 are omitted.

  In the present embodiment, the sixth, seventh, tenth, and eleventh lower electrodes 41f, 41g, 41j, and 41k are arranged in the first and second directions in the second, third, fifth, eighth, ninth, The twelfth, fourteenth, and fifteenth lower electrodes 41b, 41c, 41e, 41h, 41i, 41l, 41n, and 41o are appropriately sandwiched. Therefore, the sixth, seventh, tenth, and eleventh lower electrodes 41f, 41g, 41j, and 41k are the high-density regions of the present invention. The second, third, fourteenth, and fifteenth lower electrodes 41b, 41c, 41n, and 41o are appropriately connected to the first, fourth, thirteenth, and sixteenth lower electrodes 41a, 41d, 41m, and 41p in the first direction. It is sandwiched. Similarly, the fifth, eighth, ninth, and twelfth lower electrodes 41e, 41h, 41i, and 41l are arranged in the second direction with respect to the first, fourth, thirteenth, and sixteenth lower electrodes 41a, 41d, 41m, and 41p. Is sandwiched as appropriate. Therefore, the second, third, fourteenth, and fifteenth lower electrodes 41b, 41c, 41n, and 41o, and the fifth, eighth, ninth, and twelfth lower electrodes 41e, 41h, 41i, and 41l are low in the present invention. It becomes a dense area. The first, fourth, thirteenth, and sixteenth lower electrodes 41a, 41d, 41m, and 41p are sandwiched between the other lower electrodes 41b, 41c, 41e to 41l, 41n, and 41o in the first and second directions. Not. Therefore, the first, fourth, thirteenth, and sixteenth lower electrodes 41a, 41d, 41m, and 41p are sparse regions of the present invention.

  The interlayer insulating film 50 has the largest film thickness on the sixth, seventh, tenth, and eleventh lower electrodes 41f, 41g, 41j, and 41k that are the dense regions. And the film | membrane on the 2nd, 3rd, 5th, 8th, 9th, 12th, 14th, 15th lower electrode 41b, 41c, 41e, 41h, 41i, 41l, 41n, 41o which is a low-density area | region The thickness is then increased, and the film thickness on the first, fourth, thirteenth, and sixteenth lower electrodes 41a, 41d, 41m, and 41p is the smallest.

  The second wiring layer 60 includes first to sixteenth upper electrodes 61a to 61p facing the first to sixteenth lower electrodes 41a to 41p. Thus, the first to sixteenth capacitors C1 to C16 are configured in the multilayer wiring layer 30.

  In the present embodiment, the sixth, seventh, tenth, and eleventh capacitors C6, C7, C10, and C11 are the dense regions, and the sixth, seventh, tenth, and eleventh lower electrodes 41f, 41g, 41j, 41k, and the second, third, fifth, eighth, ninth, twelfth, fourteenth, and fifteenth capacitors C2, C3, C5, C8, C9, C12, C14, and C15 are low-density regions. The second, third, fifth, eighth, ninth, twelfth, fourteenth and fifteenth lower electrodes 41b, 41c, 41e, 41h, 41i, 41l, 41n, 41o are provided, and the first, fourth, The thirteenth and sixteenth capacitors C1, C4, C13, and C16 have first, fourth, thirteenth, and sixteenth lower electrodes 41a, 41d, 41m, and 41p that are sparse regions. Therefore, the sixth, seventh, tenth, and eleventh capacitors C6, C7, C10, and C11 are the high-density capacitors of the present invention, and the second, third, fifth, eighth, ninth, twelfth, and fourteenth capacitors. , Fifteenth capacitors C2, C3, C5, C8, C9, C12, C14, C15 are the low-density capacitors of the present invention, and the first, fourth, thirteenth, and sixteenth capacitors C1, C4, C13, C16 are the present invention. This is a sparse capacitor.

  The first to sixteenth upper electrodes 61a to 61p have the largest areas of the sixth, seventh, tenth, and eleventh upper electrodes 61f, 61g, 61j, and 61k, and the second, third, fifth, The areas of the eighth, ninth, twelfth, fourteenth, and fifteenth upper electrodes 61b, 61c, 61e, 61h, 61i, 61l, 61n, and 61o are increased to the next, and the first, fourth, thirteenth, and sixteenth, respectively. The areas of the upper electrodes 61a, 61d, 61m, and 61p are the smallest.

  And like the said 4th Embodiment, each capacitor is connected in parallel and the synthetic | combination capacitor is comprised. Specifically, in the present embodiment, the thickness of the interlayer insulating film 50 is different in three steps as described above, and the first to sixteenth upper electrodes 61a to 61p have an area in three steps as described above. Is different.

  For this reason, in this embodiment, a capacitor having the longest length between the counter electrodes and a capacitor having the shortest length between the counter electrodes are connected in parallel to form a composite capacitor, and the length between the counter electrodes is Intermediate capacitors are connected in parallel to form a composite capacitor. In other words, a capacitor having the largest area of the counter electrode and a capacitor having the smallest area of the counter electrode are connected in parallel to form a composite capacitor, and those having an intermediate area of the counter electrode are connected in parallel to form a composite capacitor. . That is, a high-density capacitor and a sparse capacitor are connected in parallel to form a composite capacitor, and low-density capacitors are connected in parallel to form a composite capacitor.

  Specifically, the first, sixth capacitors C1, C6, fourth, seventh capacitors C4, C7, tenth, thirteenth capacitors C10, C13, eleventh, sixteenth capacitors C11, C16 are connected to each other. The fourth synthesis capacitors C1 ′ to C4 ′ are used. Further, the second, fifth capacitors C2, C5, the third, eighth capacitors C3, C8, the ninth, the fourteenth capacitors C9, C14, the twelfth, the fifteenth capacitors C12, C15 are connected, and the fifth to eighth capacitors are connected. The combined capacitors C5 ′ to C8 ′ are used.

  As described above, in the present embodiment, the sixth, seventh, tenth, and eleventh lower electrodes 41f, 41g, 41j, and 41k that are the dense regions are the sixth, seventh, tenth, and eleventh capacitors C6, C7, C10, C11 and first, fourth, thirteenth, sixteenth capacitors C1, C4, C13, C16 having first, fourth, thirteenth, and sixteenth lower electrodes 41a, 41d, 41m, 41p that are sparse regions. Are connected to form first to fourth synthesis capacitors C1 ′ to C4 ′. Further, the second, third, fifth, eighth, ninth, twelfth, fourteenth, and fifteenth lower electrodes 41b, 41c, 41e, 41h, 41i, 41l, 41n, and 41o, which are low-density regions, are provided. Second, third, fifth, eighth, ninth, twelfth, fourteenth, and fifteenth capacitors C2, C3, C5, C8, C9, C12, C14, and C15 are appropriately connected to provide fifth to eighth synthetic capacitors. C5 'to C8'. For this reason, it can suppress that the capacity | capacitance of 1st-8th synthetic | combination capacitor C5 '-C8' varies.

(Modification of the fifth embodiment)
In the fifth embodiment, the example in which the composite capacitor is configured by combining two capacitors has been described. However, the composite capacitor can also be configured by combining four capacitors.

  Specifically, in this modification, two capacitors having the longest length between the counter electrodes and two capacitors having the shortest length between the counter electrodes are connected in parallel to form a composite capacitor. The four capacitors with intermediate lengths between are connected in parallel to form a composite capacitor. In other words, two capacitors having the largest counter electrode area and two capacitors having the smallest counter electrode area are connected in parallel to form a composite capacitor, and four capacitors having the counter electrode area in the middle are connected in parallel. This is a composite capacitor. That is, two high density capacitors and two sparse capacitors are connected in parallel to form a composite capacitor, and four low density capacitors are connected in parallel to form a composite capacitor. FIG. 10 is a plan view in which the interlayer insulating film 50 and the protective film 70 are omitted.

  Specifically, as shown in FIG. 10, the first, sixth, eleventh, and sixteenth capacitors C1, C6, C11, and C16 are connected in parallel to form a first composite capacitor C11 ′. In addition, the fourth, seventh, tenth, and thirteenth capacitors C4, C7, C10, and C13 are connected in parallel to form a second composite capacitor C12 ′. The fifth, ninth, fourteenth, and fifteenth capacitors C5, C9, C14, and C15 are connected in parallel to form a third composite capacitor C13 ′. Further, the second, third, eighth, and twelfth capacitors C2, C3, C8, and C12 are connected in parallel to form a fourth composite capacitor C14 ′.

  As described above, even when the four capacitors are connected in parallel, the same effect as in the fifth embodiment can be obtained. In FIG. 10, for the sake of easy understanding, the reference numerals C11 ′ are assigned between the first, sixth, eleventh, and sixteenth capacitors C1, C6, C11, and C16. The first, sixth, eleventh, and sixteenth capacitors C1, C6, C11, and C16 are connected in parallel to form one first composite capacitor C11 ′. The same applies to the second to fourth synthesis capacitors C12 ′ to C14 ′.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in the above embodiments, the shapes of the lower electrode and the upper electrode can be changed as appropriate.

  In the first embodiment, the areas of the first to third upper electrodes 61a to 61c are equal to each other, and the areas of the first to third lower electrodes 41a to 41c are changed to change the areas of the first to third capacitors C1. The capacities of .about.C3 may be equal. Similarly, in the second to fifth embodiments, the area of the lower electrode may be changed.

  In each of the above embodiments, the multilayer wiring layer 30 may further include an interlayer insulating film and a wiring layer stacked on the first and second wiring layers 40 and 60.

  In the first to third embodiments, the number of lower electrodes can be changed as appropriate.

  Furthermore, in the said 2nd Embodiment, the place which forms the through-holes 62a-62c can be changed suitably. That is, the through holes 62a to 62c may be formed at the corners of the first to third upper electrodes 61a to 61c, respectively. Further, the through holes 62a to 62c may be cylindrical instead of cylindrical.

  And in the said 4th, 5th embodiment, when comprising a synthetic | combination capacitor, you may connect each capacitor in series.

  Moreover, it is also possible to combine said each embodiment suitably. For example, the second embodiment may be combined with the third to fifth embodiments, and a through hole may be formed in each upper electrode.

DESCRIPTION OF SYMBOLS 10 Board | substrate 10a One surface 30 Multilayer wiring layer 40 1st wiring layer 41a-41p 1st-16th lower electrode 50 Interlayer insulating film 60 2nd wiring layer 61a-61p 1st-16th upper electrode

Claims (7)

A substrate (10) having one surface (10a);
In a semiconductor device having a multilayer wiring layer (30) configured by alternately stacking wiring layers (40, 60) and interlayer insulating films (50) and disposed on one surface of the substrate,
Among the wiring layers, the nth layer (n is a natural number) of the wiring layers from the substrate side is a plurality of lower electrodes (three or more arranged in order along the first direction in the surface direction of the substrate). 41a to 41c), in the plurality of lower electrodes, a region sandwiched between other lower electrodes becomes a dense region and a region different from the dense region becomes a sparse region,
In the interlayer insulating film, the thickness of the portion located on the lower electrode of the dense region is thicker than the thickness of the portion located on the lower electrode of the sparse region,
The wiring layer of the (n + 1) th layer from the substrate side of the wiring layer has a plurality of upper electrodes (61a to 61c) respectively opposed to the plurality of lower electrodes,
In the multilayer wiring layer, there are a plurality of capacitors (C1 to C3) having the plurality of lower electrodes, the plurality of upper electrodes, and the interlayer insulating film between the plurality of lower electrodes and the plurality of upper electrodes. Configured,
The facing area of the lower electrode and the upper electrode of the dense capacitor having the lower electrode of the dense region is larger than the facing area of the lower electrode and the upper electrode of the sparse capacitor having the lower electrode of the sparse region. A semiconductor device characterized by comprising:   2. The semiconductor device according to claim 1, wherein the plurality of lower electrodes have the same area and the same length between each other. The semiconductor device according to claim 2, wherein an area of the upper electrode of the dense capacitor is larger than that of the upper electrode of the sparse capacitor. The plurality of upper electrodes have outer shapes that are equal to each other, and are formed with through holes (62a to 62c) penetrating in a normal direction to one surface of the substrate,
The through hole formed in the upper electrode of the dense capacitor has a cross-sectional area in a plane perpendicular to the normal direction smaller than the through hole formed in the upper electrode of the sparse capacitor. 2. The semiconductor device according to 2 or 3. The n-th wiring layer includes three or more lower electrodes (41d to 41d) in a second direction along a plane direction of the substrate from the plurality of lower electrodes in a direction orthogonal to the first direction. 41i), and in the plurality of lower electrodes, a region sandwiched between other lower electrodes in the first and second directions becomes a high-density region, and one of the first direction and the second direction The region sandwiched between the other lower electrodes only in the direction of becomes the low-density region, the high-density region and the region different from the low-density region is the sparse region,
The interlayer insulating film becomes thinner in the order of the portion located on the lower electrode of the dense region, the portion located on the lower electrode of the dense region, the portion located on the lower electrode of the sparse region,
The opposing area between the lower electrode and the upper electrode of the dense capacitor having the lower electrode in the dense region is larger than the opposing area between the lower electrode and the upper electrode of the dense capacitor having the lower electrode in the dense region. The semiconductor device according to claim 1, wherein: The nth wiring layer has four lower electrodes (41a-41d) along the first direction,
The composite capacitor (C1 ', C2') is configured by connecting the dense capacitor and the sparse capacitor in the multilayer wiring layer, according to any one of claims 1 to 4. The semiconductor device described. The n-th wiring layer includes four lower electrodes (41e to 41e) extending from the four lower electrodes in a direction perpendicular to the first direction and in a second direction along the surface direction of the substrate. 41p) having 16 lower electrodes, in the plurality of lower electrodes, a region sandwiched between other lower electrodes in the first and second directions becomes a highly dense region, and the first direction And a region sandwiched between other lower electrodes only in either one of the second directions becomes a low-density region, and the region different from the high-density region and the low-density region becomes the sparse region,
A high-capacitance capacitor having the lower electrode in the dense region and the sparse capacitor are connected to form a composite capacitor (C1 ′ to C4 ′, C11 ′, C12 ′), and the lower electrode in the dense region is provided 5. The semiconductor device according to claim 1, wherein the low-density capacitors are connected to each other to form a composite capacitor (C5 ′ to C8 ′, C13 ′, C14 ′).

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