JP6336554B2 - 半導体本体上の接触層形成 - Google Patents
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- JP6336554B2 JP6336554B2 JP2016233767A JP2016233767A JP6336554B2 JP 6336554 B2 JP6336554 B2 JP 6336554B2 JP 2016233767 A JP2016233767 A JP 2016233767A JP 2016233767 A JP2016233767 A JP 2016233767A JP 6336554 B2 JP6336554 B2 JP 6336554B2
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
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- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
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- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
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- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
- H10P30/2042—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into crystalline silicon carbide
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- H10P30/218—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type
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Description
21 金属原子含有領域
32 ソース領域
34 ドレイン領域
61 第1のエミッタ領域
63 第2のエミッタ領域
100 半導体本体
101 第1の表面
200 金属層
300 注入マスク
301 開口部
400 さらなる金属層
Claims (20)
- 炭化ケイ素を含む半導体本体の第1の表面に金属層を形成するステップと、
前記金属層から前記半導体本体の中に金属原子を移動させて前記半導体本体の中に金属原子含有領域を形成するように、前記金属層に粒子を照射するステップと、
前記半導体本体を焼鈍するステップであって、少なくとも前記金属原子含有領域を500℃より低い温度に加熱するステップを含む、焼鈍するステップと、
を含む方法であって、前記焼鈍するステップにおいて、前記半導体本体からのシリコン原子及び前記金属原子含有領域の金属原子が、前記金属層に隣接するケイ化物層を形成する、方法。 - 前記温度は350℃より高い、請求項1に記載の方法。
- 前記焼鈍の持続時間は、30秒〜30分の範囲から選択される、請求項1または2に記載の方法。
- 前記半導体本体は、前記第1の表面に隣接する領域にドープ領域を含む、請求項1〜3のいずれか一項に記載の方法。
- 前記ドープ領域のドーピング濃度は、2E17cm−3〜2E20cm−3の範囲から選択される、請求項4に記載の方法。
- 前記粒子は、希ガスイオンを含む、請求項1〜5のいずれか一項に記載の方法。
- 前記粒子は、半導体イオンおよび金属イオンのうちの1つを含む、請求項1〜5のいずれか一項に記載の方法。
- 前記粒子は、ドーパントイオンを含む、請求項1〜4のいずれか一項に記載の方法。
- 前記ドーパントイオンは、
アルミニウムイオンと、
窒素原子と、
からなる群から選択される、請求項8に記載の方法。 - 前記金属層に照射するステップは、前記金属層に異なるタイプの粒子を照射するステップを含む、請求項1〜9のいずれか一項に記載の方法。
- 前記焼鈍するステップの後に前記金属層を除去するステップ
をさらに含む、請求項1〜10のいずれか一項に記載の方法。 - 前記第1の表面にさらなる金属層を形成するステップ
をさらに含む、請求項11に記載の方法。 - 前記さらなる金属層は、ショットキー金属を含む、請求項12に記載の方法。
- 前記ショットキー金属は、n型SiCに対して0.7eV〜1.6eVの障壁高さのショットキー接触を形成するように構成される、請求項13に記載の方法。
- 前記ショットキー金属は、
チタン(Ti)、
モリブデン(Mo)、
ニッケル(Ni)、
タンタル(Ta)、
窒化モリブデン(MoN)、
窒化チタン(TiN)
からなる群から選択される、請求項13または14に記載の方法。 - 前記金属層に粒子を照射するステップは、開口部を含み、前記金属層を部分的に覆う、マスクを使用するステップを含む、請求項1〜15のいずれか一項に記載の方法。
- 前記ドープ領域は、トランジスタデバイスのソース領域およびドレイン領域のうちの1つである、請求項4または5に記載の方法。
- 前記ドープ領域は、バイポーラダイオードのエミッタ領域である、請求項4または5に記載の方法。
- 前記ドープ領域は、統合されたバイポーラ・ショットキー・ダイオードのエミッタ領域である、請求項4または5に記載の方法。
- 前記半導体本体は、広バンドギャップ半導体材料を含む、請求項1に記載の方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102015120848.2 | 2015-12-01 | ||
| DE102015120848.2A DE102015120848B4 (de) | 2015-12-01 | 2015-12-01 | Herstellen einer Kontaktschicht auf einem Halbleiterkörper |
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| Publication Number | Publication Date |
|---|---|
| JP2017118104A JP2017118104A (ja) | 2017-06-29 |
| JP6336554B2 true JP6336554B2 (ja) | 2018-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2016233767A Active JP6336554B2 (ja) | 2015-12-01 | 2016-12-01 | 半導体本体上の接触層形成 |
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| Country | Link |
|---|---|
| US (1) | US10002930B2 (ja) |
| JP (1) | JP6336554B2 (ja) |
| DE (1) | DE102015120848B4 (ja) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786447B (zh) * | 2017-11-13 | 2022-06-21 | 比亚迪半导体股份有限公司 | 一种P型SiC欧姆接触材料及其制备方法 |
| JP7135443B2 (ja) * | 2018-05-29 | 2022-09-13 | 富士電機株式会社 | 炭化ケイ素半導体装置及びその製造方法 |
| JP2025020887A (ja) * | 2023-07-31 | 2025-02-13 | 株式会社東芝 | 半導体装置の製造方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3562022A (en) * | 1967-12-26 | 1971-02-09 | Hughes Aircraft Co | Method of doping semiconductor bodies by indirection implantation |
| US3600797A (en) * | 1967-12-26 | 1971-08-24 | Hughes Aircraft Co | Method of making ohmic contacts to semiconductor bodies by indirect ion implantation |
| US3887994A (en) * | 1973-06-29 | 1975-06-10 | Ibm | Method of manufacturing a semiconductor device |
| US4551908A (en) * | 1981-06-15 | 1985-11-12 | Nippon Electric Co., Ltd. | Process of forming electrodes and interconnections on silicon semiconductor devices |
| JPS5972181A (ja) | 1982-10-18 | 1984-04-24 | Toshiba Corp | シヨツトキ−・バリヤ・ダイオ−ドの形成方法 |
| JPS59177926A (ja) | 1983-03-28 | 1984-10-08 | Nec Corp | 半導体装置の製造方法 |
| JPS60153121A (ja) | 1984-01-20 | 1985-08-12 | Nec Corp | 半導体装置の形成方法 |
| JPS625635A (ja) | 1985-07-02 | 1987-01-12 | Nec Corp | 電子デバイスの電極の形成方法 |
| JPS62166512A (ja) | 1986-01-20 | 1987-07-23 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2001135591A (ja) * | 1999-11-05 | 2001-05-18 | Matsushita Electric Ind Co Ltd | 半導体素子の製造方法 |
| US6365446B1 (en) * | 2000-07-03 | 2002-04-02 | Chartered Semiconductor Manufacturing Ltd. | Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process |
| WO2008016619A1 (en) | 2006-07-31 | 2008-02-07 | Vishay-Siliconix | Molybdenum barrier metal for sic schottky diode and process of manufacture |
| US9111985B1 (en) * | 2007-01-11 | 2015-08-18 | Cypress Semiconductor Corporation | Shallow bipolar junction transistor |
| JP5567830B2 (ja) * | 2009-12-22 | 2014-08-06 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
| JP5613640B2 (ja) | 2011-09-08 | 2014-10-29 | 株式会社東芝 | 半導体装置の製造方法 |
| JP5646527B2 (ja) | 2012-03-02 | 2014-12-24 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
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2015
- 2015-12-01 DE DE102015120848.2A patent/DE102015120848B4/de active Active
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2016
- 2016-11-30 US US15/365,627 patent/US10002930B2/en active Active
- 2016-12-01 JP JP2016233767A patent/JP6336554B2/ja active Active
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| Publication number | Publication date |
|---|---|
| US10002930B2 (en) | 2018-06-19 |
| JP2017118104A (ja) | 2017-06-29 |
| US20170162390A1 (en) | 2017-06-08 |
| DE102015120848B4 (de) | 2017-10-26 |
| DE102015120848A1 (de) | 2017-06-01 |
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