JP6354527B2 - Manufacturing method of semiconductor wafer - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor wafer.

  A semiconductor wafer is generally manufactured by cutting a semiconductor crystal grown by various growth methods. As a method of cutting a semiconductor crystal, cutting methods using various wire saws have been proposed.

  For example, Patent Document 1 discloses a method of obtaining a GaN as-sliced wafer by slicing a GaN (gallium nitride) ingot along a direction parallel to the c-axis using a piano wire having a diameter of 0.16 mm as a wire saw. (See paragraphs [0033] and [0034] etc. of Patent Document 1). According to the method described in Patent Document 1, no saw mark is observed on the cut surface of the as-sliced wafer (paragraph [0034] of Patent Document 1).

  In order to obtain a larger number of semiconductor wafers from one semiconductor crystal by cutting the semiconductor crystal using a wire saw, it is important to reduce kerf loss (cutting allowance).

  However, in the method described in Patent Document 1, since a wire having a large line width such as a diameter of 0.16 mm is used, the kerf loss is about 0.2 mm to 0.3 mm. Therefore, it has been impossible to manufacture a semiconductor wafer with a high yield.

  In particular, semiconductor crystals such as GaN and SiC (silicon carbide) are generally very expensive because the crystal growth rate is low and the manufacturing process is complicated. Therefore, in order to improve the yield of such an expensive semiconductor crystal semiconductor wafer, it is extremely important to reduce the kerf loss at the time of cutting the semiconductor crystal.

  Further, when a semiconductor wafer is manufactured by cutting a semiconductor crystal by a cutting method using a wire saw, there is a problem that the semiconductor wafer is warped.

  Therefore, for example, in Patent Document 2, a gallium nitride crystal is fixed to a metal holder with a conductive adhesive, and a wire with a diameter of 0.1 mm made of tungsten is used to insulate water with an electrical resistance controlled to 70000Ω. A method of cutting a gallium nitride crystal by wire electric discharge machining in a state where the gallium nitride crystal is immersed is disclosed (paragraph [0038] in Patent Document 2). Here, the feed speed of the wire is 12 m / s, the set value of the machining current is 7, and the machining voltage is 60V. Further, it is said that cutting is performed in 5 hours by feeding back the voltage and cutting under a constant discharge condition.

JP 2013-126939 A JP 2007-30155 A

  For example, as a wire used for wire electric discharge machining as described in Patent Document 2, generally, for example, a wire having a thin wire diameter is used as compared with a wire saw described in Patent Document 1, Cutting is done without contact. Therefore, when the semiconductor crystal is cut by wire electric discharge machining, kerf loss at the time of cutting the semiconductor crystal can be reduced as compared with the case where the semiconductor crystal is cut by a wire saw.

  Further, in a semiconductor wafer obtained by cutting a semiconductor crystal by wire electric discharge machining, it is possible to reduce the occurrence of warping as compared with a semiconductor wafer obtained by cutting a semiconductor crystal with a wire saw.

  Furthermore, in the semiconductor wafer obtained by cutting the semiconductor crystal by wire electric discharge machining, the variation in the thickness of the semiconductor wafer can be reduced compared to the semiconductor wafer obtained by cutting the semiconductor crystal by the wire saw. it can.

  By the way, when a semiconductor crystal is cut by wire electric discharge machining, for example, as described in Patent Document 2, the semiconductor crystal is attached to a metal holder with a conductive adhesive. Then, after cutting the semiconductor crystal, the metal holder is heated to melt the conductive adhesive, and the semiconductor wafer is removed from the metal holder.

  However, at this time, cracks may occur in the semiconductor wafer, and there has been a demand for improvement.

  There has also been a demand for reducing semiconductor wafer processing loss (the portion of the semiconductor crystal that does not become a semiconductor wafer, which occurs during processing such as kerf loss and polishing loss).

  In view of the above circumstances, an object of the present invention is to provide a semiconductor wafer manufacturing method capable of reducing the occurrence of cracks in a semiconductor wafer.

  It is another object of the present invention to provide a method for manufacturing a semiconductor wafer that can reduce processing loss of the semiconductor wafer.

  According to an embodiment which is an example of the present invention, the method includes a step of attaching a semiconductor crystal on a support plate, a step of processing the semiconductor crystal, and a step of heating the support plate, and the support plate and the semiconductor It is possible to provide a method for manufacturing a semiconductor wafer in which the difference in thermal expansion coefficient from the crystal is 40% or less.

  The method for manufacturing a semiconductor wafer according to one aspect of the present invention includes a step of attaching a semiconductor crystal on a support plate and a step of processing the semiconductor crystal, wherein the step of processing the semiconductor crystal includes the semiconductor crystal The length of the support plate in the longitudinal direction of the wire is 102% or more and 125% or less of the length of the semiconductor crystal in the longitudinal direction of the wire.

  According to said embodiment, the manufacturing method of the semiconductor wafer which can reduce that a crack generate | occur | produces in a semiconductor wafer can be provided.

  Moreover, according to the above, it is possible to provide a method for manufacturing a semiconductor wafer that can reduce a processing loss of the semiconductor wafer.

3 is a flowchart of a method for manufacturing the semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a part of an example of a composite substrate preparation step in the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a part of an example of a composite substrate preparation step in the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a part of an example of a composite substrate preparation step in the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a part of an example of a composite substrate preparation step in the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a part of an example of a composite substrate preparation step in the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a part of an example of a composite substrate preparation step in the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of an attaching step of the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating an example of a processing step in the method for manufacturing a semiconductor wafer according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating another example of the processing step of the semiconductor wafer manufacturing method of the first embodiment. 3 is a schematic plan view of a GaN single crystal wafer obtained in Experimental Example 1. FIG. 6 is a schematic plan view of a GaN single crystal wafer obtained in Experimental Example 5. FIG. 6 is a flowchart of a semiconductor wafer manufacturing method according to the second embodiment. FIG. 6 is a schematic perspective view of an example of a wire used in a wire preparation step of a semiconductor wafer manufacturing method according to a second embodiment. It is typical sectional drawing along XV-XV of FIG. (A) is a typical plane perspective view illustrating an example of a wire installation step in the wire traveling direction of the semiconductor wafer manufacturing method of the second embodiment, and (b) is a longitudinal direction of the wire in the wire traveling direction. It is a figure for illustrating deviation with respect to the perpendicular direction. (A) is a typical plane perspective view illustrating an example of a wire installation step in a direction orthogonal to the wire traveling direction of the semiconductor wafer manufacturing method of the second embodiment, and (b) illustrates the wire traveling direction. It is a figure for demonstrating the shift | offset | difference with respect to the perpendicular direction of the longitudinal direction of the wire in the orthogonal direction. (A) is a typical plane perspective view illustrating an example of a semiconductor crystal installation step in the method of manufacturing a semiconductor wafer according to the second embodiment, and (b) illustrates the thickness direction of the semiconductor crystal and the longitudinal direction of the wire. It is a figure for demonstrating that it is perpendicular | vertical, (c) is a figure for demonstrating that the longitudinal direction of a wire and the length direction of the support plate in the longitudinal direction of a wire are parallel. (A)-(c) is a typical top view illustrating an example of the wire position adjustment process of the manufacturing method of the semiconductor wafer of Embodiment 2. FIGS. It is a typical top view for illustrating an example of the calculation method of the amount of wire movement in a wire position adjustment process. FIG. 10 is a schematic perspective view illustrating an example of a processing step of the method for manufacturing a semiconductor wafer according to the second embodiment. FIG. 22 is a schematic plan view when FIG. 21 is viewed from the direction of an arrow 51. FIG. 22 is a schematic plan view when FIG. 21 is viewed from the direction of an arrow 52. FIG. 22 is a schematic plan view when FIG. 21 is viewed from the direction of an arrow 53. FIG. FIG. 22 is a schematic plan view when FIG. 21 is viewed from the direction of an arrow 54. It is a typical top view illustrating that a conductive wire vibrates and processing loss of a semiconductor crystal increases.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described. The embodiment of the present invention includes the following (1) to (7).

  (1) The embodiment of the present invention includes a step of attaching a semiconductor crystal on a support plate, a step of processing the semiconductor crystal, and a step of heating the support plate, and heat between the support plate and the semiconductor crystal. This is a method for manufacturing a semiconductor wafer having a difference in expansion coefficient of 40% or less. In this case, it is possible to reduce the occurrence of cracks in the semiconductor wafer when the semiconductor wafer after processing the semiconductor crystal is taken out by heating the support plate.

  (2) In the embodiment of the present invention, the semiconductor crystal preferably contains gallium nitride (GaN) or silicon carbide (SiC). Since the GaN crystal and the SiC crystal are very expensive, it is effective to apply the semiconductor wafer manufacturing method of the embodiment that can reduce the occurrence of cracks in the semiconductor wafer.

  (3) In the embodiment of the present invention, the surface diameter of the semiconductor crystal is preferably 40 mm or more. In this case, since the surface of the semiconductor wafer obtained by processing the semiconductor crystal becomes too large and easily breaks, manufacturing of the semiconductor wafer according to the embodiment can reduce the occurrence of cracking in the semiconductor wafer. Application of the method becomes more effective.

(4) In the embodiment of the present invention, the volume resistivity at 25 ° C. of the support plate is preferably 1 × 10 ⁻² Ω · cm or less. In this case, when the semiconductor crystal is cut by wire electric discharge machining in the machining process, it is possible to effectively suppress the processing of the semiconductor crystal from occurring at another location. Cutting is possible.

  (5) In the embodiment of the present invention, the support plate is made of a composite of aluminum oxide and titanium carbide (altic), tungsten (W), molybdenum (Mo), and cermet (carbonitride containing titanium and niobium). Preferably, at least one selected from the group consisting of: In this case, the thermal expansion coefficient difference between the support plate and the semiconductor crystal can be made 40% or less, and the support plate can be made conductive.

(6) In the embodiment of the present invention, the volume resistivity of the semiconductor crystal at 25 ° C. is preferably 3 × 10 ⁻² Ω · cm or less. In this case, when the semiconductor crystal is cut by wire electric discharge machining in the processing step, it is possible to effectively suppress the processing of the semiconductor crystal from occurring at another location. Accurate cutting is possible.

  (7) In the embodiment of the present invention, the step of processing the semiconductor crystal preferably includes at least one of a step of cutting the semiconductor crystal with a wire electric discharge machine and a step of polishing the semiconductor crystal. When the semiconductor crystal is cut by wire electric discharge machining, the kerf loss at the time of cutting the semiconductor crystal can be reduced as compared with the case of cutting the semiconductor crystal by a wire saw, and the semiconductor wafer obtained by cutting the semiconductor crystal Generation of warpage and variation in thickness can be reduced. In addition, when the surface of the semiconductor crystal is polished while being attached to the support plate, the support plate can be used as a gripping member when polishing the surface of the semiconductor crystal. In addition, since it is not necessary to remove the semiconductor crystal from the support plate, the surface of the semiconductor crystal can be efficiently polished.

  (8) In an embodiment of the present invention, the step of processing the semiconductor crystal is a step of processing the semiconductor crystal using a wire, and the length of the support plate in the longitudinal direction of the wire is the wire It is preferable that it is 102% or more and 125% or less of the length of the semiconductor crystal in the longitudinal direction. In this case, the processing loss of the semiconductor wafer can be reduced.

  (9) In an embodiment of the present invention, the diameter of the wire is preferably 70 μm or more and 100 μm or less. Also in this case, the processing loss of the semiconductor wafer can be reduced.

  (10) In an embodiment of the present invention, the wire preferably includes a core material and a plating layer on the core material. Also in this case, the processing loss of the semiconductor wafer can be reduced.

  (11) In an embodiment of the present invention, the core material preferably includes stainless steel. In this case, the strength of the wire tends to be kept high.

  (12) In an embodiment of the present invention, the plating layer preferably contains zinc. In this case, since the conductivity of the plating layer can be increased, when processing with a high-frequency current flowing through the conductive wire, the skin effect is used to efficiently flow the current through the plating layer. It becomes possible.

  (13) In an embodiment of the present invention, the plating layer preferably contains copper. Also in this case, since the conductivity of the plating layer can be increased, when processing is performed by supplying a high-frequency current to the conductive wire, the skin effect is used to efficiently supply the current to the plating layer. It becomes possible.

(14) In an embodiment of the present invention, the breaking strength of the wire is preferably 1800 N / mm ² or more. In this case, it is possible to suppress a decrease in the processing efficiency of the semiconductor crystal due to the breakage of the wire.

  (15) It is preferable that the embodiment of the present invention further includes a step of installing the semiconductor crystal so that a longitudinal direction of the wire and a thickness direction of the semiconductor crystal are perpendicular to each other. In this case, the semiconductor crystal can be processed more accurately in the direction perpendicular to the thickness direction of the semiconductor crystal.

  (16) It is preferable that the embodiment of the present invention further includes a step of placing the semiconductor crystal so that the longitudinal direction of the wire and the longitudinal direction of the support plate in the longitudinal direction of the wire are parallel to each other. In this case, the semiconductor crystal can be processed more accurately in the direction perpendicular to the thickness direction of the semiconductor crystal.

  (17) It is preferable that the embodiment of the present invention further includes a step of adjusting the position of the wire after the step of installing the semiconductor crystal. In this case, the processing position of the semiconductor crystal by the wire can be determined more accurately.

  (18) In an embodiment of the present invention, the step of processing the semiconductor crystal is preferably performed in water. In this case, the processing loss of the semiconductor wafer can be reduced.

  (19) In an embodiment of the present invention, the tension applied to the wire during processing of the semiconductor crystal is preferably 5N or more and 12N or less. In this case, the processing loss of the semiconductor wafer can be kept low, and the breakage of the wire can be suppressed.

  (20) In an embodiment of the present invention, the voltage applied to the wire during processing of the semiconductor crystal is preferably 30 V or more and 80 V or less. In this case, the semiconductor crystal can be stably processed while suppressing the breakage of the wire, and the kerf loss of the semiconductor crystal can be suppressed low.

  (21) In an embodiment of the present invention, it is preferable that a feeding speed of the wire at the time of processing the semiconductor crystal is 100 m / h or more and 1000 m / h or less. In this case, the frequency of wire breakage can be reduced, and the manufacturing cost of the semiconductor wafer can be kept low.

  (22) In an embodiment of the present invention, the step of processing the semiconductor crystal preferably includes a step of injecting a water flow onto the semiconductor crystal. In this case, it is possible to efficiently remove the semiconductor crystal processing waste and cool the wire.

  (23) In an embodiment of the present invention, the flow rate of the water flow is preferably 1 slm or more and 10 slm or less. In this case, efficient processing of the semiconductor crystal can be performed, kerf loss can be suppressed low, and breakage of the wire can also be suppressed.

  (24) An embodiment of the present invention includes a step of attaching a semiconductor crystal on a support plate and a step of processing the semiconductor crystal. The step of processing the semiconductor crystal uses the semiconductor crystal as a wire. The length of the support plate in the longitudinal direction of the wire is 102% to 125% of the length of the semiconductor crystal in the longitudinal direction of the wire. is there. In this case, the processing loss of the semiconductor wafer can be reduced.

  (25) In an embodiment of the present invention, the semiconductor crystal preferably contains gallium nitride or silicon carbide. Also in this case, the processing loss of the semiconductor wafer can be reduced. Since the GaN crystal and the SiC crystal are very expensive, it is effective to apply the semiconductor wafer manufacturing method of the embodiment that can reduce the occurrence of cracks in the semiconductor wafer.

  (26) In the embodiment of the present invention, the process of processing the semiconductor crystal is wire electric discharge machining, and the processing loss of the semiconductor wafer can be reduced.

  (27) In an embodiment of the present invention, the diameter of the wire is preferably 70 μm or more and 100 μm or less. Also in this case, the processing loss of the semiconductor wafer can be reduced.

  (28) In an embodiment of the present invention, the wire preferably includes a core material and a plating layer on the core material. Also in this case, the processing loss of the semiconductor wafer can be reduced.

  (29) In an embodiment of the present invention, the core material preferably includes stainless steel. Also in this case, the processing loss of the semiconductor wafer can be reduced. In this case, the strength of the wire tends to be kept high.

  (30) In an embodiment of the present invention, the plating layer preferably contains zinc. In this case, since the conductivity of the plating layer can be increased, when processing with a high-frequency current flowing through the conductive wire, the skin effect is used to efficiently flow the current through the plating layer. It becomes possible.

  (31) In an embodiment of the present invention, the plating layer preferably contains copper. Also in this case, since the conductivity of the plating layer can be increased, when processing is performed by supplying a high-frequency current to the conductive wire, the skin effect is used to efficiently supply the current to the plating layer. It becomes possible.

(32) In an embodiment of the present invention, the breaking strength of the wire is preferably 1800 N / mm ² or more. In this case, it is possible to suppress a decrease in the processing efficiency of the semiconductor crystal due to the breakage of the wire.

  (33) It is preferable that the embodiment of the present invention further includes a step of installing the semiconductor crystal so that a longitudinal direction of the wire and a thickness direction of the semiconductor crystal are perpendicular to each other. In this case, the semiconductor crystal can be processed more accurately in the direction perpendicular to the thickness direction of the semiconductor crystal.

  (34) It is preferable that the embodiment of the present invention further includes a step of placing the semiconductor crystal so that the longitudinal direction of the wire and the longitudinal direction of the support plate in the longitudinal direction of the wire are parallel to each other. In this case, the semiconductor crystal can be processed more accurately in the direction perpendicular to the thickness direction of the semiconductor crystal.

  (35) It is preferable that embodiment of this invention further includes the process of adjusting the position of the said wire after the process of installing the said semiconductor crystal. In this case, the processing position of the semiconductor crystal by the wire can be determined more accurately.

  (36) In an embodiment of the present invention, the step of processing the semiconductor crystal is preferably performed in water. In this case, the processing loss of the semiconductor wafer can be reduced.

  (37) In an embodiment of the present invention, the tension applied to the wire during the processing of the semiconductor crystal is preferably 5N or more and 12N or less. In this case, the processing loss of the semiconductor wafer can be kept low, and the breakage of the wire can be suppressed.

  (38) In an embodiment of the present invention, the voltage applied to the wire during processing of the semiconductor crystal is preferably 30 V or more and 80 V or less. In this case, the semiconductor crystal can be stably processed while suppressing the breakage of the wire, and the kerf loss of the semiconductor crystal can be suppressed low.

  (39) In an embodiment of the present invention, the wire feed rate during processing of the semiconductor crystal is preferably 100 m / h or more and 1000 m / h or less. In this case, the frequency of wire breakage can be reduced, and the manufacturing cost of the semiconductor wafer can be kept low.

  (40) In an embodiment of the present invention, it is preferable that the step of processing the semiconductor crystal includes a step of injecting a water flow onto the semiconductor crystal. In this case, it is possible to efficiently remove the semiconductor crystal processing waste and cool the wire.

  (41) In an embodiment of the present invention, the flow rate of the water flow is preferably 1 slm or more and 10 slm or less. In this case, efficient processing of the semiconductor crystal can be performed, kerf loss can be suppressed low, and breakage of the wire can also be suppressed.

  (42) In an embodiment of the present invention, it is preferable that the step of attaching the semiconductor crystal on the support plate includes a step of attaching the support plate and the semiconductor crystal with hot melt wax. In this case, it becomes easy to remove the processed semiconductor crystal and the support plate.

[Details of the embodiment of the present invention]
The details of an embodiment which is an example of the present invention will be described below. Note that in the drawings used to describe the embodiments, the same reference numerals represent the same or corresponding parts.

<Method for Manufacturing Semiconductor Wafer in First Embodiment>
FIG. 1 shows a flowchart of the semiconductor wafer manufacturing method of the first embodiment. As shown in FIG. 1, the semiconductor wafer manufacturing method of the first embodiment includes a semiconductor crystal preparation step (S10), an attaching step (S20), a processing step (S30), and a heating step (S40). In addition, a bonding step (S20) is performed after the semiconductor crystal preparation step (S10), a processing step (S30) is performed after the bonding step (S20), and a heating step (S30) is performed after the processing step (S30). S40) is performed. The semiconductor wafer manufacturing method of the embodiment may include steps other than the semiconductor crystal preparation step (S10), the attaching step (S20), the processing step (S30), and the heating step (S40). Needless to say. For example, heating or the like may be performed in the attaching step (S20).

<Semiconductor crystal preparation process>
The semiconductor crystal preparation step (S10) can be performed, for example, as follows. First, as shown in the schematic cross-sectional view of FIG. 2, the semiconductor crystal 13 is grown on the first base substrate 30. The growth method of the semiconductor crystal 13 is not particularly limited. For example, a vapor phase such as MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy), or sublimation. Or a liquid phase method such as a flux method or a high nitrogen pressure solution method can be used.

  Here, the diameter D of the semiconductor crystal 13 grown on the first base substrate 30 is preferably 40 mm or more. When the diameter D of the semiconductor crystal 13 is 40 mm or more, the semiconductor wafer obtained by cutting the semiconductor crystal 13 is easily cracked, so that an effect of reducing the occurrence of cracking in the semiconductor wafer is exhibited. The application of the semiconductor wafer manufacturing method of the embodiment becomes more effective.

  The first base substrate 30 can be used without any particular limitation as long as it can be used as a base for forming the semiconductor crystal 13. For example, the first base substrate 30 can be inexpensive and later such as a silicon (Si) substrate or gallium arsenide (GaAs). It is preferable to use a semiconductor substrate that can be easily removed in the process.

  The semiconductor crystal 13 grown on the first base substrate 30 is also not particularly limited, but is preferably a gallium nitride (GaN) crystal or a silicon carbide (SiC) crystal. Since the GaN crystal and the SiC crystal are very expensive, the application of the semiconductor wafer manufacturing method according to the embodiment that can reduce the occurrence of cracks in the semiconductor wafer becomes more effective.

The volume resistivity of the semiconductor crystal 13 at 25 ° C. is preferably 3 × 10 ⁻² Ω · cm or less. In this case, in the processing step (S30) described later, when the semiconductor crystal 13 is cut by wire electric discharge machining, it is possible to effectively suppress the processing of the semiconductor crystal 13 from occurring at another location. The semiconductor crystal 13 can be cut more accurately by electric discharge machining. The volume resistivity at 25 ° C. of the semiconductor crystal 13 can be obtained by, for example, a four-probe method, an eddy current method, or a Hall effect measurement.

  Next, as shown in the schematic cross-sectional view of FIG. 3, the first base substrate 30 is removed from the semiconductor crystal 13. The method for removing the first base substrate 30 is not particularly limited as long as the first base substrate 30 can be selectively removed. For example, when the first base substrate 30 is a Si substrate. For example, a method of dissolving the first base substrate 30 in a solution containing hydrofluoric acid or the like can be used. For example, when the first base substrate 30 is a GaAs substrate, a method of dissolving the first base substrate 30 in a solution containing aqua regia etc. can be used.

Next, as shown in the schematic cross-sectional view of FIG. 4, a first bonding layer 12 a is formed on the surface of the semiconductor crystal 13. As the first bonding layer 12a, for example, a single layer or a plurality of layers including at least one of silicon oxide (SiO ₂ ) and titanium oxide (TiO ₂ ) can be used. A method for forming the first bonding layer 12a is not particularly limited, and for example, a CVD (chemical vapor deposition) method or the like can be used. The thickness of the first bonding layer 12a is not particularly limited, but may be, for example, 0.2 μm or more and 2 μm or less.

Further, as shown in the schematic cross-sectional view of FIG. 5, the second bonding layer 12 b is formed on the second base substrate 11. As the second bonding layer 12b, for example, a single layer or a plurality of layers including at least one of SiO ₂ and TiO ₂ can be used. A method for forming the second bonding layer 12b is not particularly limited, and for example, a CVD method or the like can be used. The thickness of the second bonding layer 12b is not particularly limited, but may be, for example, 0.2 μm or more and 2 μm or less.

  The second base substrate 11 can be used without particular limitation as long as it can be used as a base for forming the second bonding layer 12b. For example, a mullite (a composite oxide of alumina and silicon oxide) substrate or the like can be used. Insulating substrates can be used.

  Next, as shown in the schematic cross-sectional view of FIG. 6, the first bonding layer 12a shown in FIG. 4 and the second bonding layer 12b shown in FIG. 2 joining layers 12b are joined. Thereby, as shown in the schematic cross-sectional view of FIG. 7, the bonding layer 12 in which the first bonding layer 12 a and the second bonding layer 12 b are integrated is formed, and the second base substrate 11 and the semiconductor crystal 13 are formed. And the preparation process of the semiconductor crystal 13 bonded to the second base substrate 11 by the bonding layer 12 is completed.

  The bonding method between the first bonding layer 12a and the second bonding layer 12b is not particularly limited, and for example, a direct bonding method or a surface activation method can be used. In the direct bonding method, for example, the bonding surface of the first bonding layer 12a and the bonding surface of the second bonding layer 12b are cleaned, and after these bonding surfaces are overlapped, the temperature is about 600 ° C. to about 1200 ° C. It can be performed by heating and joining. In addition, the surface activation method is performed, for example, after cleaning the bonding surface of the first bonding layer 12a and the bonding surface of the second bonding layer 12b and activating them with plasma or ions, and the like. It can be performed by heating to about 400 ° C. and joining.

  The semiconductor crystal preparation step (S10) is not particularly limited to the above step as long as the semiconductor crystal 13 that can be attached to the first support substrate can be prepared in the attachment step (S20) described later.

<Paste process>
The attaching step (S20) can be performed, for example, by attaching the semiconductor crystal 13 on the first support plate 7 as shown in the schematic cross-sectional view of FIG. Here, the semiconductor crystal 13 is affixed on the first support plate 7 by, for example, installing the conductive adhesive 6 on the first support plate 7 by coating or the like, and then on the conductive adhesive 6. The semiconductor crystal 13 is placed on the first support plate 7 and the semiconductor crystal 13 is attached to the first support plate 7 with the conductive adhesive 6.

In the method of manufacturing a semiconductor wafer according to the embodiment, the first support plate 7 is made of a material having a thermal expansion coefficient difference of 40% or less between the first support plate 7 and the semiconductor crystal 13. As a result of intensive studies by the present inventor, when a material having a thermal expansion coefficient difference of 40% or less with respect to the semiconductor crystal 13 is used for the first support plate 7, a heating step (S40 described later) is performed. ), When the conductive adhesive 6 is melted by heating the first support plate 7 and the semiconductor wafer obtained by the processing step (S30) described later is taken out, the semiconductor wafer is cracked. This is because it has been found that it can be reduced. In the present specification, the difference in thermal expansion coefficient between the support substrate (first support plate 7) and the semiconductor crystal (semiconductor crystal 13) is expressed by the following formula (I).
Thermal expansion coefficient difference [%] = 100 × | (thermal expansion coefficient of support plate) − (thermal expansion coefficient of semiconductor crystal) | / (thermal expansion coefficient of semiconductor crystal) (I)

  Further, in this specification, the thermal expansion coefficient of the support plate (first support plate 7) and the thermal expansion coefficient of the semiconductor crystal (semiconductor crystal 13) were raised from room temperature (25 ° C.) to 800 ° C., respectively. The value measured by TMA (thermomechanical analysis) is used as the average linear thermal expansion coefficient.

The average linear thermal expansion coefficient α is represented by the following formula (II).
Average linear thermal expansion coefficient α [1 / ° C.] = | (Length at 800 ° C. [mm]) − (length at 25 ° C. [mm]) | / {(length at 25 ° C. [mm]) × (800 -25)} (II)

  Further, when a semiconductor wafer is manufactured by cutting the semiconductor crystal 13 by wire electric discharge machining, it is preferable to use a conductive material as the first support plate 7. In this case, a contact for applying a voltage between the wire for cutting the semiconductor crystal 13 can be provided on the first support plate 7.

  For example, when the GaN crystal is used as the semiconductor crystal 13, the first support plate 7 includes a composite of aluminum oxide and titanium carbide (Altic), tungsten (W), molybdenum (Mo), and cermet (titanium and niobium). It is preferable to use a material including at least one selected from the group consisting of carbonitrides including In this case, the difference in thermal expansion coefficient between the first support plate 7 and the semiconductor crystal 13 can be made 40% or less, and the first support plate 7 can be made conductive.

  For example, when the SiC crystal is used as the semiconductor crystal 13, it is preferable to use a material containing at least one of tungsten and molybdenum as the first support plate 7. Also in this case, the difference in thermal expansion coefficient between the first support plate 7 and the semiconductor crystal 13 can be made 40% or less, and the first support plate 7 can be made conductive.

The volume resistivity at 25 ° C. of the first support plate 7 is preferably 1 × 10 ⁻² Ω · cm or less. In this case, when the semiconductor crystal 13 is cut by wire electric discharge machining in the later-described processing step (S30), it is possible to effectively prevent the semiconductor crystal 13 from being cut at another location. Therefore, the semiconductor crystal 13 can be more accurately cut by wire electric discharge machining. The volume resistivity at 25 ° C. of the first support plate 7 can be determined by, for example, the four-probe method, the eddy current method, or the Hall effect measurement.

  Moreover, it is preferable that the thickness of the 1st support plate 7 is 5 mm or more and 30 mm or less. When the thickness of the first support plate 7 is 5 mm or more, the first support plate 7 is not easily deformed, and the semiconductor crystal 13 can be processed without causing warpage. The manufacturing yield of the wafer can be improved. When the thickness of the first support plate 7 is 30 mm or less, the cost of the first support plate 7 can be reduced, so that the manufacturing cost of the semiconductor wafer can be kept low.

  Moreover, it is preferable that the 1st support plate 7 is cylindrical. When the first support plate 7 has a cylindrical shape, the first support plate 7 can easily function as a gripping member when the semiconductor crystal 13 is polished.

  Note that the conductive adhesive 6 is a conductive material capable of adhering the semiconductor crystal 13 on the first support plate 7 and is the first support in the heating step (S40) described later. The material is not particularly limited as long as it is a material that can be melted by heating the plate 7 and can take out a semiconductor wafer in which the semiconductor crystal 13 is processed. For example, a conventional material including a binder and a conductive filler in the binder is used. A known conductive adhesive or the like can be used. As the binder, for example, a thermoplastic resin can be used. As the conductive filler, for example, at least one selected from the group consisting of gold powder, silver powder, copper powder, nickel powder, aluminum powder, carbon powder and graphite powder can be used.

  Moreover, the melting temperature of the conductive adhesive 6 is not particularly limited, but is preferably 50 ° C. or higher and 200 ° C. or lower. When the melting temperature of the conductive adhesive 6 is 50 ° C. or higher, since the temperature at which the conductive adhesive 6 is melted is high, the first of the conductive adhesive 6 solidified after the conductive adhesive 6 is melted. The semiconductor crystal 13 can be fixed to the support plate 7 more reliably. Further, when the melting temperature of the conductive adhesive 6 is 200 ° C. or lower, in the heating step (S40) described later, the conductive adhesive 6 is not heated to a high temperature so that the semiconductor wafer is damaged by heat. Can be suppressed.

The surface of the second base substrate 11 opposite to the conductive adhesive 6 side can be bonded to the second support plate 1 by the adhesive 2. The adhesive 2 is not particularly limited as long as it can adhere the second base substrate 11 and the second support plate 1, and for example, a conventionally known hot melt wax can be used. The second support plate 1 is not particularly limited as long as it can adhere the second base substrate 11 with the adhesive ₂ , and for example, alumina (Al ₂ O ₃ ) or the like can be used.

  Note that the attaching step (S20) is performed as long as the semiconductor crystal 13 can be attached onto the first support plate 7 to the extent that the semiconductor crystal 13 can be processed in the processing step (S30) described later. The process is not limited.

<Processing process>
An example of the processing step (S30) can be performed by cutting the semiconductor crystal 13 by wire electric discharge machining using the conductive wire 8, for example, as shown in the schematic cross-sectional view of FIG. A semiconductor wafer can be obtained from the semiconductor crystal 13 by cutting the semiconductor crystal 13 using wire electric discharge machining. In the wire electric discharge machining, a discharge is generated by applying a voltage between the first support plate 7 and the conductive wire 8, and the semiconductor crystal 13 is partially heated by the local heat generated by the discharge. This can be done by non-contact removal. Further, as described above, when the semiconductor crystal 13 is cut by wire electric discharge machining, the kerf loss at the time of cutting the semiconductor crystal 13 can be reduced compared to the case where the semiconductor crystal 13 is cut by a wire saw, Generation of warpage and thickness variation of the semiconductor wafer obtained by cutting the semiconductor crystal 13 can be reduced.

  Further, another example of the processing step (S30) is performed by polishing the surface 13a of the semiconductor crystal 13 obtained by cutting by wire electric discharge processing, for example, as shown in the schematic cross-sectional view of FIG. it can. In this case, the first support plate 7 attached by the conductive adhesive 6 can be used as a gripping member when polishing the surface 13a of the semiconductor crystal 13, and every time the surface 13a of the semiconductor crystal 13 is polished. Since there is no need to remove the semiconductor crystal 13 from the first support plate 7, the surface 13a of the semiconductor crystal 13 can be efficiently polished.

  Note that the polishing step of the surface 13a of the semiconductor crystal 13 illustrated in FIG. 10 may be performed independently irrespective of the cutting step of the semiconductor crystal 13 by wire electric discharge machining illustrated in FIG. For example, after the semiconductor crystal 13 obtained by a method different from the cutting by wire electric discharge machining illustrated in FIG. 9 is attached to the first support plate 7 with the conductive adhesive 6, the surface 13a of the semiconductor crystal 13 is obtained. May be polished. In the case where the polishing step of the surface 13a of the semiconductor crystal 13 is performed regardless of the cutting step of the semiconductor crystal 13 by wire electric discharge machining, the adhesive for adhering the semiconductor crystal 13 to the first support plate 7 is as described above. In addition to the conductive adhesive 6, an insulating adhesive can also be used. As the insulating adhesive material, for example, a material that is melted by heating the first support plate 7 can be used as in the case of the conductive adhesive material 6.

  Further, the polishing step of the surface 13a of the semiconductor crystal 13 illustrated in FIG. 10 may be performed in combination with the cutting step of the semiconductor crystal 13 by wire electric discharge processing illustrated in FIG. For example, the surface 13 a of the semiconductor crystal 13 is attached to the first support plate 7 without removing the semiconductor crystal 13 after being cut by wire electric discharge machining exemplified in FIG. 9 from the first support plate 7. You may grind | polish.

<Heating process>
In the heating step (S40), for example, by heating the first support plate 7, the conductive adhesive 6 on the first support plate 7 is heated to a temperature equal to or higher than the melting temperature of the conductive adhesive 6. Can be done. Thereby, since the conductive adhesive 6 is melted to be in a liquid state, the semiconductor wafer after the processing step (S30) can be removed from the first support plate 7. In the semiconductor wafer manufacturing method of the embodiment, the difference in thermal expansion coefficient between the first support plate 7 and the semiconductor crystal 13 is 40% or less. Therefore, in the heating step (S40), when the first support plate 7 is heated, the conductive adhesive 6 is melted, and the semiconductor wafer obtained by the processing step (S30) described later is taken out. The occurrence of cracking can be reduced.

<Effect>
In the semiconductor wafer manufacturing method of the first embodiment, since the difference in thermal expansion coefficient between the first support plate 7 and the semiconductor crystal 13 is 40% or less, the first support plate 7 is heated. Thus, it is possible to reduce the occurrence of cracks in the semiconductor wafer when the semiconductor wafer is taken out.

<Method for Manufacturing Semiconductor Wafer in Second Embodiment>
FIG. 13 is a flowchart of the semiconductor wafer manufacturing method according to the second embodiment. As shown in FIG. 13, the semiconductor wafer manufacturing method of the second embodiment includes a wire preparation step (S11), a wire installation step (S21), a semiconductor crystal installation step (S31), and a wire position adjustment step (S41). ) And a semiconductor crystal processing step (S51), a wire installation step (S21) is performed after the wire preparation step (S11), and a semiconductor crystal installation step (S31) is performed after the wire installation step (S21). A wire position adjustment step (S41) is performed after the semiconductor crystal placement step (S31), and a semiconductor crystal processing step (S51) is performed after the wire position adjustment step (S41). The semiconductor wafer manufacturing method of the second embodiment includes a wire preparation step (S11), a wire placement step (S21), a semiconductor crystal placement step (S31), a wire position adjustment step (S41), and a semiconductor crystal processing step ( Needless to say, steps other than S51) may be included.

<Wire preparation process>
The wire preparation step (S11) can be performed, for example, by preparing a wire used for processing the semiconductor crystal 13. FIG. 14 shows a schematic perspective view of an example of a wire used in the wire preparation step (S11), and FIG. 15 shows a schematic cross-sectional view along XV-XV in FIG. As shown in FIG. 14, the conductive wire 8 extends linearly. As shown in FIG. 15, the conductive wire 8 includes a core material 8a and a plating layer 8b that covers the outer surface of the core material 8a.

  Although the material of the core material 8a of the conductive wire 8 is not particularly limited, it is preferable to use stainless steel. When stainless steel is used for the core material 8a of the conductive wire 8, the strength of the conductive wire 8 tends to be kept high.

  The material of the plating layer 8b of the conductive wire 8 is not particularly limited, but a material containing zinc (Zn) is preferably used, and an alloy of copper (Cu) and Zn or Zn is preferably used. When a material containing Zn is used for the plating layer 8b of the conductive wire 8, particularly when an alloy of Cu and Zn or Zn is used, the conductivity of the plating layer 8b can be increased. When performing a process of passing a high-frequency current through the conductive wire 8 such as electric discharge machining, it is possible to efficiently pass a current through the plating layer 8b by utilizing the skin effect. As an alloy of Cu and Zn, an alloy having a mass ratio of Cu and Zn of Cu: Zn = 6: 4 to Cu: Zn = 7: 3 is preferably used. In this case, a current can be more efficiently passed through the plating layer 8b due to the skin effect.

  The diameter d of the conductive wire 8 shown in FIG. 15 is not particularly limited, but is preferably 70 μm or more and 100 μm or less. When the diameter d of the conductive wire 8 is 70 μm or more, for example, when the semiconductor crystal 13 is cut by wire electric discharge machining to manufacture a semiconductor wafer having a surface of 4 inches in diameter, the conductive wire 8 does not break. In addition, since it is not necessary to lower the tension of the conductive wire 8, processing loss due to vibration of the conductive wire 8 can be kept low. When the diameter d of the conductive wire 8 is 100 μm or less, for example, when the semiconductor crystal 13 is cut by wire electric discharge machining to produce a semiconductor wafer having a diameter of 4 inches, the diameter of the conductive wire 8 is reduced. Processing loss due to d being too large can be kept low.

  The thickness t of the plating layer 8b shown in FIG. 15 is not particularly limited, but is preferably 5 μm or more and 20 μm or less. When the thickness t of the plating layer 8b is 5 μm or more, since the electric resistance of the plating layer 8b can be lowered, the electric resistance of the entire conductive wire 8 can be lowered. Further, when the thickness t of the plating layer 8b is 20 μm or less, the core material 8a does not have to be formed thin, so that the strength of the conductive wire 8 can be reduced.

The breaking strength of the conductive wire 8 is preferably 1800 N / mm ² or more. When the breaking strength of the conductive wire 8 is 1800 N / mm ² or more, a decrease in the processing efficiency of the semiconductor crystal 13 due to the breaking of the conductive wire 8 can be suppressed. The breaking strength of the conductive wire 8 is a value measured by performing a tensile strength test.

<Wire installation process>
The wire installation step (S21) can be performed, for example, by holding both ends of the conductive wire 8 prepared in the wire preparation step (S11) with dies. FIG. 16A and FIG. 17A are schematic plan perspective views illustrating an example of the wire installation step (S21). 16A is a plan perspective view along the traveling direction 21 of the conductive wire 8, and FIG. 17A is a plan perspective view of the conductive wire 8 in a direction 22 orthogonal to the traveling direction 21.

  As shown in FIGS. 16A and 17A, the conductive wire 8 has an upper die 41b inside the upper nozzle 41a and a lower die 42b inside the lower nozzle 42a so as to have a predetermined tension. Is gripped between. One end of the conductive wire 8 is held by the upper die 41b, and the other end of the conductive wire 8 is held by the lower die 42b.

  For example, as shown in FIG. 16 (b), the conductive wire 8 has a displacement in which the longitudinal direction 80 of the conductive wire 8 is 2 μm or less with respect to the vertical direction 20 in the traveling direction 21 of the conductive wire 8 (S 1). It is preferable to be installed so that In this case, variations occurring in the shape of the semiconductor wafer obtained by processing the semiconductor crystal 13 using the conductive wire 8 can be suppressed.

  For example, as shown in FIG. 17B, the conductive wire 8 has a longitudinal direction 80 of the conductive wire 8 of 2 μm or less with respect to the vertical direction 20 in the direction 22 orthogonal to the traveling direction 21 of the conductive wire 8. It is preferable to be installed so as to be the deviation (S2). In this case, the processing of the semiconductor crystal 13 in the direction perpendicular to the thickness direction of the semiconductor crystal 13 can be performed more accurately.

<Semiconductor crystal installation process>
In the semiconductor crystal installation step (S31), for example, the first support plate 7 and the second support plate can be processed by the conductive wire 8 installed in the wire installation step (S21). 1 can be performed by installing a semiconductor crystal 13 attached between the first and second semiconductor crystals 13. FIG. 18A shows a schematic plan perspective view illustrating an example of the semiconductor crystal installation step (S31). FIG. 18A is a plan perspective view in a direction 22 orthogonal to the traveling direction 21 of the conductive wire 8. Further, in FIGS. 18 to 22 and FIGS. 24 to 26, other members such as the conductive adhesive 6 may be provided between the first support plate 7 and the semiconductor crystal 13. Other members such as the adhesive 2, the second base substrate 11, and the bonding layer 12 may be provided between the support plate 1 and the semiconductor crystal 13, but these members are provided for convenience of explanation. The description about is omitted.

  The length L1 of the support plate in the longitudinal direction of the conductive wire 8 is 102% or more and 125% or less of the length L2 of the semiconductor crystal 13 in the longitudinal direction of the conductive wire 8. Note that the length of at least one of the first support plate 7 and the second support plate 1 in the longitudinal direction of the conductive wire 8 is 102% or more of the length L2 of the semiconductor crystal 13 in the longitudinal direction of the conductive wire 8. It may be 125% or less.

  The semiconductor crystal 13 is preferably installed so that the thickness direction 23 of the semiconductor crystal 13 is perpendicular to the longitudinal direction 80 of the conductive wire 8 as shown in FIG. In this case, the processing of the semiconductor crystal 13 in the direction perpendicular to the thickness direction of the semiconductor crystal 13 can be performed more accurately. In this specification, “the thickness direction 23 of the semiconductor crystal 13 is perpendicular to the longitudinal direction 80 of the conductive wire 8” means that the thickness direction 23 of the semiconductor crystal 13 and the longitudinal direction 80 of the conductive wire 8 are This means that the angle to be formed is an angle within the range of 90 ° ± 0.01 °.

  For example, as shown in FIG. 18C, the semiconductor crystal 13 is installed so that the longitudinal direction 80 of the conductive wire 8 and the longitudinal direction 24 of the support plate in the longitudinal direction 80 of the conductive wire 8 are parallel to each other. It is preferable. Also in this case, the processing of the semiconductor crystal 13 in the direction perpendicular to the thickness direction of the semiconductor crystal 13 can be performed more accurately. In this specification, “the longitudinal direction 80 of the conductive wire 8 and the longitudinal direction 24 of the support plate in the longitudinal direction 80 of the conductive wire 8 are parallel” means that the longitudinal direction 80 of the conductive wire 8 and the conductive direction are conductive. The angle formed by the length direction 24 of the support plate (the first support plate 7 and the second support plate 1) in the longitudinal direction 80 of the conductive wire 8 is an angle within the range of 0 ° ± 0.01 °. Means.

<Wire position adjustment process>
After installing the semiconductor crystal 13 in the semiconductor crystal installation step (S31), it is preferable to perform a wire position adjustment step (S41). By performing the wire position adjusting step (S41), the processing position of the semiconductor crystal 13 by the conductive wire 8 can be determined more accurately.

  FIGS. 19A to 19C are schematic plan views illustrating an example of the wire position adjustment process. In the present embodiment, the wire position adjusting step (S41) is performed in the order of FIG. 19 (a), FIG. 19 (b) and FIG. 19 (c).

  First, as shown in FIG. 19A, the conductive wire 8 is moved in the direction of the arrow 31 so that the conductive wire 8 is exposed to the first support plate 7 as shown in FIG. Touch the surface. At this time, a voltage is applied to the conductive wire 8 to cause a current to flow from the conductive wire 8 to the first support plate 7. Thereby, the coordinates of the exposed surface of the first support plate 7 are clarified. Then, as shown in FIG. 19C, the conductive wire 8 is placed in the direction of the arrow 32 (perpendicular to the exposed surface of the first support plate 7) on the basis of the position of the exposed surface of the first support plate 7. In a direction away from the exposed surface of the first support plate 7), the processing position of the conductive wire 8 is determined.

  Here, the movement amount 33 of the conductive wire 8 is, for example, when the semiconductor crystal 13 is cut by the conductive wire 8 to obtain a semiconductor wafer having a thickness T, the wire diameter is d, the kerf loss is Ts, and the polishing is performed. When the loss is Tk, it can be (T + Tk + (Ts / 2) − (d / 2)) (see FIG. 20).

<Semiconductor crystal processing process>
After adjusting the position of the conductive wire 8 by the wire position adjusting step (S41), the semiconductor crystal processing step (S51) is performed. In the present embodiment, the semiconductor crystal processing step (S51) is performed by cutting the semiconductor crystal 13 by wire electric discharge processing using the conductive wire 8.

  FIG. 21 is a schematic perspective view illustrating an example of the processing step (S51) of the semiconductor crystal 13. As shown in FIG. After the processing position of the conductive wire 8 is determined, the semiconductor crystal 13 is placed in water (not shown). Then, a voltage is applied between the first support plate 7 and the conductive wire 8 to generate a discharge, and the semiconductor crystal 13 is partially heated by the local heat generated by the discharge and removed without contact. To do. Then, the semiconductor crystal 13 is cut by moving the conductive wire 8 along the traveling direction 21 shown in FIG. 21 while removing the semiconductor crystal 13.

  The resistivity of water in which the semiconductor crystal 13 is disposed is preferably 10 MΩcm or more and 20 MΩcm or less. When the resistivity of water is 10 MΩcm or more, water insulation is high, and the occurrence of discharge at locations other than the semiconductor crystal 13 can be suppressed. Therefore, the semiconductor crystal 13 can be processed more efficiently. Can do. Moreover, when the resistivity of water is 20 MΩcm or less, it is possible to easily remove ions from the water, so that the manufacturing cost of the semiconductor wafer can be kept low.

  The tension applied to the conductive wire 8 when the semiconductor crystal 13 is processed is preferably 5N or more and 12N or less. When the tension of the conductive wire 8 at the time of processing the semiconductor crystal 13 is 5 N or more, the vibration of the conductive wire 8 due to the small tension of the conductive wire 8 can be suppressed, so that the processing loss is reduced. It can be kept low. Moreover, when the tension | tensile_strength of the conductive wire 8 at the time of the process of the semiconductor crystal 13 is 12 N or less, the fracture | rupture of the conductive wire 8 by the tension applied to the conductive wire 8 can be suppressed.

  The voltage applied to the conductive wire 8 when the semiconductor crystal 13 is processed is preferably 30 V or more and 80 V or less. When the voltage applied to the conductive wire 8 during processing of the semiconductor crystal 13 is 30 V or more, the semiconductor crystal 13 can be cut while maintaining a certain distance between the conductive wire 8 and the semiconductor crystal 13. Therefore, the semiconductor crystal 13 can be processed stably while suppressing breakage of the conductive wire 8. When the voltage applied to the conductive wire 8 when processing the semiconductor crystal 13 is 80 V or less, the semiconductor crystal 13 can be cut without excessively increasing the distance between the conductive wire 8 and the semiconductor crystal 13. Therefore, the kerf loss of the semiconductor crystal 13 can be kept low.

  When the pulse voltage is applied to the conductive wire 8 during the processing of the semiconductor crystal 13, the pulse width of the pulse voltage is preferably 0.1 microsecond or more and 500 microsecond or less, and is 0.2 microsecond or more and 200 microsecond. The following is more preferable. When the pulse width of the pulse voltage is not less than 0.1 microseconds and not more than 500 microseconds, especially when it is not less than 0.2 microseconds and not more than 200 microseconds, the heat generation of the conductive wire 8 is suppressed to a minimum. The breakage of the conductive wire 8 can be suppressed and efficient processing can be performed.

  At the time of processing the semiconductor crystal 13, the conductive wire 8 is sent from the upper side to the lower side in the vertical direction 20, and the semiconductor crystal 13 is processed. The feed rate of the conductive wire 8 is 100 m / h or more and 1000 m. / H or less is preferable. When the feeding speed of the conductive wire 8 is 100 m / h or more, since the consumption of the conductive wire 8 can be suppressed, the frequency of breakage of the conductive wire 8 can be reduced. In addition, when the feeding speed of the conductive wire 8 is 100 m / h or less, the usage amount of the conductive wire 8 can be kept low, so that the manufacturing cost of the semiconductor wafer can be kept low. “M / h” means the length [m] of the conductive wire 8 sent per hour.

  FIG. 22 shows a schematic plan view when FIG. 21 is viewed from the direction of arrow 51, and FIG. 23 shows a schematic plan view when FIG. 21 is viewed from the direction of arrow 52. 24 shows a schematic plan view when FIG. 21 is viewed from the direction of arrow 53, and FIG. 25 shows a schematic plan view when FIG. 21 is viewed from the direction of arrow 54. FIG.

  For example, as shown in FIG. 24, when the semiconductor crystal 13 is cut by wire electric discharge machining using the conductive wire 8, processing waste 13 b of the semiconductor crystal 13 is generated between the conductive wire 8 and the semiconductor crystal 13. In order to remove the processing waste 13b of the semiconductor crystal 13 and to cool the conductive wire 8 efficiently, a processed portion of the semiconductor crystal 13 by the conductive wire 8 is shown in FIGS. 22, 23 and 25, for example. It is preferable to inject the water stream 61 into the tank. In addition, the water flow 61 can be injected with respect to the semiconductor crystal 13 from at least one of the upper nozzle 41a and the lower nozzle 42a.

  The flow rate of the water stream 61 is preferably 1 slm or more and 10 slm or less. When the flow rate of the water stream 61 is 1 slm or more, since the processing waste 13b of the semiconductor crystal 13 can be efficiently removed, the semiconductor crystal 13 can be efficiently processed and the kerf loss can be suppressed low. Furthermore, breakage of the conductive wire 8 can be suppressed. In addition, when the flow rate of the water flow 61 is 10 slm or less, the conductive wire 8 and the semiconductor crystal 13 due to the water flow 61 being too strong can be suppressed, and the semiconductor crystal 13 can be efficiently processed and the kerf loss can be reduced. It can be suppressed low, and further, the breakage of the conductive wire 8 can be suppressed. “Slm” represents the flow rate per minute in the standard state (pressure: 1 atm, temperature: 0 ° C.) in units of liters.

  When the cross section in the direction orthogonal to the vertical direction 20 of the water flow 61 is circular, the diameter of the cross section of the water flow 61 is preferably 1 mm or more and 3 mm or less. When the diameter of the cross section of the water flow 61 is 1 mm or more, it is possible to generate the water flow 61 with less turbulence. Moreover, when the diameter of the cross section of the water flow 61 is 3 mm or less, the flow velocity of the water flow 61 can be kept high, and the conductive wire 8 can be efficiently cooled.

  The length of the water stream 61 is preferably 100 μm or more and 1000 μm or less. When the length of the water flow 61 is 100 μm or more, slight shaking generated in the first support plate 7 and the second support plate 1, and the first support plate 7 and / or the second support plate 1 There is a greater tendency to avoid machine damage due to collision with the upper nozzle 41a and / or the lower nozzle 42a. Further, when the length of the water flow 61 is 1000 μm or less, it is possible to efficiently discharge the processing waste 13 b and cool the conductive wire 8, so that the breakage of the conductive wire 8 can be suppressed. .

  Note that, after the semiconductor crystal processing step (S51) of the second embodiment, the heating step (S40) of the first embodiment can also be performed.

<Effect>
As described above, in the method of manufacturing the semiconductor wafer of the second embodiment, the length L1 of the support plate in the longitudinal direction of the conductive wire 8 is the length L2 of the semiconductor crystal 13 in the longitudinal direction of the conductive wire 8. It is set to 102% or more and 125% or less. This is because, as a result of intensive studies by the present inventors, it has been found that when L1 is 102% or more and 125% or less of L2, the processing loss of the semiconductor wafer can be reduced. That is, when L1 is less than 102% of L2, L2 becomes too large with respect to L1, and thus the case where the periphery of the semiconductor crystal 13 is chipped frequently occurs when the semiconductor crystal 13 is processed. When L1 exceeds 125% of L2, the length of the conductive wire 8 between the upper die 41b and the lower die 42b is longer than the length L2 of the semiconductor crystal 13 in the longitudinal direction of the conductive wire 8. For example, as shown in FIG. 26, the conductive wire 8 vibrates and the processing loss of the semiconductor crystal 13 increases. From the viewpoint of further reducing the processing loss of the semiconductor wafer, the length L1 of the support plate in the longitudinal direction of the conductive wire 8 is 102% or more and 110% of the length L2 of the semiconductor crystal 13 in the longitudinal direction of the conductive wire 8. More preferably, it is more preferably 105% or more and 110% or less.

Since the description other than the above in Embodiment 2 is the same as that in Embodiment 1, the description thereof will not be repeated.
[Experimental example]
Hereinafter, although the experimental example of the manufacturing method of the semiconductor wafer of embodiment is demonstrated, the manufacturing method of the semiconductor wafer of embodiment is not limited to the said experimental example.

<Experimental example 1>
First, a GaN single crystal having a thickness of 2 mm was grown by HVPE on a (111) surface polished to a mirror surface of a GaAs substrate having a diameter of 4 inches (100 mm) and a thickness of 0.5 mm. Here, HCl (hydrogen chloride) is sprayed on metal Ga as a raw material and supplied in the form of gallium chloride (GaCl), and ammonia (NH ₃ ) gas is further supplied. Hydrogen (H ₂ ) gas is used as a carrier gas. And nitrogen (N ₂ ) gas was used. The temperature of the GaAs substrate during the growth of the GaN single crystal was 1000 ° C., and the pressure was 1 atm (1.01325 × 10 ⁵ Pa). After the growth of the GaN single crystal, the GaAs substrate was dissolved and removed with aqua regia.

Next, a SiO ₂ film having a thickness of 2 μm was formed on the surface of the GaN single crystal by a CVD method. Then, the SiO ₂ film on the GaN single crystal was polished using a cerium oxide (CeO ₂ ) slurry, so that only the 0.2 μm thick SiO ₂ film was left.

Further, a 2 μm thick SiO ₂ film was formed on the surface of the mullite substrate by the CVD method. Then, the SiO ₂ film on the GaN single crystal was polished with CeO ₂ slurry, so that only the SiO ₂ film having a thickness of 0.2 μm was left.

After the surface of the SiO ₂ film on the GaN single crystal and the surface of the SiO ₂ film on the mullite substrate were cleaned and activated by argon (Ar) plasma, the surfaces of these SiO ₂ films were superposed and heated at 300 ° C. These SiO ₂ films were joined and integrated by heat treatment in a nitrogen atmosphere for 2 hours.

As a result, a composite substrate in which the SiO ₂ film and the GaN single crystal were laminated in this order on the mullite substrate was obtained.

  Next, the surface of the mullite substrate of the composite substrate obtained as described above is attached to the lower plate made of alumina with hot melt wax, and the surface of the GaN single crystal is attached to the upper plate made of Altic with a conductive adhesive. I attached. And the said upper plate and lower plate were fixed to the wire electric discharge machining apparatus, and the GaN single crystal was cut | disconnected with the wire of the wire electric discharge machining apparatus, and the GaN single crystal wafer was obtained.

  Then, an upper plate on which the GaN single crystal wafer obtained as described above is bonded with a conductive adhesive is placed on a hot plate, and the upper plate is heated to a temperature of 50 ° C. or higher by the hot plate. The conductive adhesive was melted into a liquid state, and the GaN single crystal wafer was removed from the upper plate.

  When the GaN single crystal wafer removed from the upper plate was visually confirmed, it was confirmed that no cracks occurred in the GaN single crystal wafer. The results are shown in the “crack” column of the evaluation in Table 1. In the “crack” column of the evaluation in Table 1, when the GaN single crystal wafer is visually confirmed, no crack is confirmed on the GaN single crystal wafer, and the evaluation is “A”. The evaluation when confirmed is “B”.

  In addition, the numerical value in the column of “thermal expansion coefficient (1 / ° C.)” of the semiconductor crystal in Table 1 is the value when the temperature is raised from room temperature (25 ° C.) to 800 ° C. for a GaN single crystal manufactured under the same conditions as above. The average linear thermal expansion coefficient was measured by TMA (thermomechanical analysis). Specifically, the average linear thermal expansion coefficient in the a-axis direction of the GaN single crystal was measured in a nitrogen gas flow atmosphere by a differential expansion method using TMA8310 manufactured by Rigaku Corporation.

  Further, the numerical value in the column of “volume resistivity (Ω · cm)” of the semiconductor crystal in Table 1 is a value measured by a four-probe method for a GaN single crystal manufactured under the same conditions as described above.

  The numerical value in the column of “thermal expansion coefficient (1 / ° C.)” of the upper plate in Table 1 is a value obtained by measuring the average linear thermal expansion coefficient when the temperature is raised from room temperature (25 ° C.) to 800 ° C. by TMA. is there. Specifically, the average linear thermal expansion coefficient of the upper plate was measured under a nitrogen gas flow atmosphere by a differential expansion method using TMA8310 manufactured by Rigaku Corporation.

  The numerical values in the column of “volume resistivity (Ω · cm)” of the upper plate in Table 1 are values measured by the four-probe method for the upper plate. The notation of “-” in the column of “volume resistivity (Ω · cm)” of the upper plate in Table 1 indicates that the volume resistivity (Ω · cm) of the upper plate is higher than 100 (Ω · cm). I mean.

Furthermore, in the “conductivity” column in the evaluation of Table 1, the evaluation when the numerical value in the volume resistivity (Ω · cm) column of the upper plate is 1 × 10 ⁻² (Ω · cm) or less is “ “A”, and the evaluation when it is higher than 1 × 10 ⁻² (Ω · cm) is “B”.

  As shown in Table 1, in Experimental Example 1, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 39.3%, the evaluation of conductivity was A, and the evaluation of crack was A. there were. FIG. 11 shows a schematic plan view of the GaN single crystal wafer 100 obtained in Experimental Example 1. FIG.

<Experimental example 2>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that Mo was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 2, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 8.9%, the conductivity evaluation was A, and the crack evaluation was A. there were.

<Experimental example 3>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that cermet (carbonitride containing titanium and niobium) was used for the upper plate, and the conductivity and The crack was evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 3, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 32.1%, the evaluation of conductivity was A, and the evaluation of cracking was A. there were.

<Experimental example 4>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that W was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 4, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 19.6%, the conductivity evaluation was A, and the crack evaluation was A. there were.

<Experimental example 5>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that iron (Fe) was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 5, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate is 96.4%, the evaluation of conductivity is A, and the evaluation of crack is B. there were. FIG. 12 shows a schematic plan view of the GaN single crystal wafer 101 obtained in Experimental Example 5. FIG.

<Experimental example 6>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that SiC was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 6, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 12.5%, the conductivity evaluation was B, and the crack evaluation was A. there were.

<Experimental example 7>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that copper (Cu) was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 7, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 167.9%, the evaluation of conductivity was A, and the evaluation of cracking was B. there were.

<Experimental Example 8>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that mullite was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 8, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 16.1%, the conductivity evaluation was B, and the crack evaluation was A. there were.

<Experimental Example 9>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that Al ₂ O ₃ was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 9, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 39.3%, the conductivity evaluation was B, and the crack evaluation was A. there were.

<Experimental example 10>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was the same as in Experimental Example 1 except that Inconel 600 (an alloy containing nickel (Ni), chromium (Cr), and Fe) was used for the upper plate. Was calculated, and conductivity and cracks were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 10, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate is 150.0%, the evaluation of conductivity is A, and the evaluation of crack is B. there were.

<Experimental example 11>
Except that SUS304 (stainless steel) was used for the upper plate, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 11, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate is 203.6%, the evaluation of conductivity is A, and the evaluation of crack is B. there were.

<Experimental example 12>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that quartz was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 12, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 91.1%, the evaluation of conductivity was B, and the evaluation of cracking was B. there were.

<Experimental example 13>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that aluminum nitride (AlN) was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 13, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate is 19.6%, the conductivity evaluation is B, and the crack evaluation is A. there were.

<Experimental Example 14>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that silicon nitride (SiN) was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 14, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 42.9%, the evaluation of conductivity was B, and the evaluation of crack was B. there were.

<Experimental Example 15>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that a composite of boron nitride and silicon carbide (BN-SiC) was used for the upper plate, and the conductivity was calculated. The properties and cracks were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 15, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 28.6%, the conductivity evaluation was B, and the crack evaluation was A. there were.

<Experimental Example 16>
The difference in thermal expansion coefficient between the GaN single crystal and the upper plate was calculated in the same manner as in Experimental Example 1 except that glassy carbon was used for the upper plate, and the conductivity and cracking were evaluated. The results are shown in Table 1.

  As shown in Table 1, in Experimental Example 16, the difference in thermal expansion coefficient between the GaN single crystal and the upper plate was 41.1%, the evaluation of conductivity was A, and the evaluation of cracking was B. there were.

<Evaluation>
As shown in Table 1, the GaN single crystal wafers of Experimental Examples 1-4, 6, 8, 9, 13, and 15 in which the difference in thermal expansion coefficient between the GaN single crystal and the upper plate is 40% or less are cracked. It was confirmed that no occurred.

<Experimental Example 17>
A wire electric discharge machine was used for electric discharge machining. As a conductive wire used for electric discharge machining, a wire having a diameter of 100 μm is prepared by coating a plating layer (Cu: Zn = 6: 4 by mass ratio) with a thickness of 5 μm or more and 20 μm or less on the outer surface of a core material made of SUS. did. The breaking strength of the conductive wire was 1800 N / mm ² or more.

  Next, the conductive wire was vertically pulled out using a jig. Here, the conductive wire was installed so as to have a deviation of 2 μm or less with respect to the vertical direction in both the traveling direction of the conductive wire and the direction orthogonal to the traveling direction of the conductive wire.

Next, the workpiece was set on a wire electric discharge machine via an adjustment jig. Here, as a workpiece, a GaN single crystal was produced in the same manner as in Experimental Example 1, and the surface of the mullite substrate of the composite substrate in which the SiO ₂ film and the GaN single crystal were laminated in this order on the mullite substrate was hot-melt waxed. Attached to the second support plate made of alumina, and the surface of the GaN single crystal attached to the first support plate made of Altic with a conductive adhesive was prepared.

  Next, (i) the longitudinal direction of the conductive wire and the longitudinal direction of the first support plate and the second support plate in the longitudinal direction of the conductive wire are parallel, and (ii) the conductive The inclination is measured using a dial gauge so that the traveling direction of the conductive wire is parallel to the length direction of the first support plate and the second support plate in the direction orthogonal to the longitudinal direction of the conductive wire. The position of the workpiece was adjusted using the adjustment mechanism of the adjustment jig. As a result, (i) the deviation from the parallel of the longitudinal direction of the conductive wire and the longitudinal direction of the first support plate and the second support plate in the longitudinal direction of the conductive wire is 5 μm, and (ii) the conductive The deviation from the parallel between the traveling direction of the conductive wire and the length direction of the first support plate and the second support plate in the direction orthogonal to the longitudinal direction of the conductive wire was 5 μm. When the deviation between the above (i) and (ii) is 10 μm, the processing loss can be significantly reduced.

  As described above, the thickness direction of the GaN single crystal is perpendicular to the longitudinal direction of the conductive wire, and the longitudinal direction of the first support plate and the second support plate in the longitudinal direction of the conductive wire is conductive. Parallel to the longitudinal direction of the wire.

  Furthermore, adjustment was performed using a gap gauge so that the gap between the lower nozzle and the lower surfaces of the first support plate and the second support plate was 0.2 mm. Moreover, it adjusted using the clearance gauge so that the clearance gap between an upper nozzle and the upper surface of a 1st support plate and a 2nd support plate might be set to 0.2 mm.

  Next, in order to determine the processing position of the conductive wire, the nozzle is moved so that the conductive wire comes into contact with the exposed surface from the GaN single crystal of the first support plate, and a voltage is applied to the conductive wire. An electric current was passed from the conductive wire to the first support plate to clarify the coordinates of the exposed surface of the first support plate. The nozzle is moved with reference to the coordinates of the exposed surface of the first support plate, and the direction is perpendicular to the exposed surface of the first support plate and away from the exposed surface of the first support plate 7. The conductive wire was moved to.

  Here, the moving amount of the conductive wire is (T + Tk + (Ts / 2) − (d / 2) where T is the thickness of the semiconductor wafer, d is the diameter of the wire, Ts is the kerf loss, and Tk is the polishing loss. )).

  Next, the processing tank was filled with water and the workpiece was placed in water. The resistivity of the water in which the work was placed was 10 MΩcm or more and 20 MΩcm or less.

  Next, a voltage of 60 V was applied to the conductive wire to start feeding the conductive wire. The direction of the conductive wire feed is from the top to the bottom in the vertical direction in order to efficiently discharge the work waste by matching the direction in which the work waste generated by processing falls by gravity and the direction of the conductive wire feed. The direction was headed. The feeding speed of the conductive wire was set to a predetermined speed within a range of 10 m / h to 1000 m / h. In addition, for the purpose of efficiently cooling the conductive wire from each of the upper nozzle and the lower nozzle and efficiently cooling the conductive wire, water is flown at a predetermined flow rate within a range of 1 slm to 10 slm with respect to the conductive wire and the semiconductor crystal. Sprayed.

  Thereafter, the nozzle was moved toward the workpiece, the conductive wire was advanced, and the GaN single crystal was cut. The tension | tensile_strength of the conductive wire at the time of the cutting | disconnection of a GaN single crystal was made into the predetermined tension | tensile_strength in the range of 5N or more and 12N or less. Here, when cutting the GaN single crystal, the moving speed of the conductive wire is adjusted so that the discharge voltage is constant, and the distance between the conductive wire and the GaN single crystal is controlled to be constant. It is preferable.

  After cutting the GaN single crystal, the first support plate on which the GaN single crystal wafer obtained as described above is bonded with a conductive adhesive is placed on the hot plate, and the first plate is formed by the hot plate. The support plate was heated to a temperature of 50 ° C. or higher to melt the conductive adhesive to a liquid state, and the GaN single crystal wafer was removed from the first support plate.

  In the manufacture of the GaN single crystal wafer as described above, the length L1 of the support plate in the longitudinal direction of the conductive wire is 100%, 102%, 110% of the length L2 of the GaN single crystal in the longitudinal direction of the conductive wire. , 125% and 130%, the machining loss is calculated, and when L1 is 102%, 110% and 125% of L2, the machining loss is reduced compared to 100% and 130%. can do.

  Although the embodiments and experimental examples of the present invention have been described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments and experimental examples.

  The embodiments and experimental examples disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be used in a method for manufacturing a semiconductor wafer, and in particular, a semiconductor wafer containing a GaN crystal or a SiC crystal can be manufactured.

DESCRIPTION OF SYMBOLS 1 2nd support plate 2 Adhesive material 6 Conductive adhesive material 7 1st support plate 8 Conductive wire 11 2nd base substrate 12 Bonding layer 12a 1st bonding layer 12b 2nd bonding layer 13 Semiconductor crystal 13a Surface 13b Processing scrap 20 Vertical direction 21 Wire traveling direction 22 Direction orthogonal to wire traveling direction 23 Semiconductor crystal thickness direction 24 Support plate length direction 30 First base substrate 31, 32, 51, 52, 53, 54 Arrow 33 Movement amount 41a Upper nozzle 41b Upper die 42a Lower nozzle 42b Lower die 61 Water flow 80 Wire longitudinal direction 100, 101 GaN single crystal wafer.

Claims (23)

Attaching a semiconductor crystal on a support plate;
Processing the semiconductor crystal;
Heating the support plate,
The manufacturing method of a semiconductor wafer whose thermal expansion coefficient difference between the said support plate and the said semiconductor crystal is 40% or less.   The method of manufacturing a semiconductor wafer according to claim 1, wherein the semiconductor crystal includes gallium nitride or silicon carbide.   The manufacturing method of the semiconductor wafer of Claim 1 or Claim 2 whose diameter of the surface of the said semiconductor crystal is 40 mm or more. 4. The method of manufacturing a semiconductor wafer according to claim 1, wherein the support plate has a volume resistivity at 25 ° C. of 1 × 10 ⁻² Ω · cm or less. 5.   The semiconductor according to any one of claims 1 to 4, wherein the support plate includes at least one selected from the group consisting of a composite of aluminum oxide and titanium carbide, tungsten, molybdenum, and cermet. Wafer manufacturing method. The method for producing a semiconductor wafer according to claim 1, wherein a volume resistivity of the semiconductor crystal at 25 ° C. is 3 × 10 ⁻² Ω · cm or less.   7. The process according to claim 1, wherein the step of processing the semiconductor crystal includes at least one of a step of cutting the semiconductor crystal with a wire electric discharge machine and a step of polishing the semiconductor crystal. Semiconductor wafer manufacturing method. The step of processing the semiconductor crystal is a step of processing the semiconductor crystal using a wire,
8. The length of the support plate in the longitudinal direction of the wire is 102% or more and 125% or less of the length of the semiconductor crystal in the longitudinal direction of the wire. Semiconductor wafer manufacturing method.   The method for manufacturing a semiconductor wafer according to claim 8, wherein a diameter of the wire is 70 μm or more and 100 μm or less.   The method of manufacturing a semiconductor wafer according to claim 8 or 9, wherein the wire includes a core material and a plating layer on the core material.   The method of manufacturing a semiconductor wafer according to claim 10, wherein the core material includes stainless steel.   The method for manufacturing a semiconductor wafer according to claim 10, wherein the plating layer contains zinc.   The method for manufacturing a semiconductor wafer according to claim 12, wherein the plating layer contains copper. The method for producing a semiconductor wafer according to claim 8, wherein the breaking strength of the wire is 1800 N / mm ² or more.   The semiconductor wafer manufacturing according to any one of claims 8 to 14, further comprising a step of placing the semiconductor crystal such that a longitudinal direction of the wire and a thickness direction of the semiconductor crystal are perpendicular to each other. Method.   The semiconductor crystal according to any one of claims 8 to 15, further comprising a step of placing the semiconductor crystal so that a longitudinal direction of the wire and a longitudinal direction of the support plate in the longitudinal direction of the wire are parallel to each other. The manufacturing method of the semiconductor wafer of description.   The method of manufacturing a semiconductor wafer according to claim 15, further comprising a step of adjusting a position of the wire after the step of installing the semiconductor crystal.   The method of manufacturing a semiconductor wafer according to claim 8, wherein the step of processing the semiconductor crystal is performed in water.   The method of manufacturing a semiconductor wafer according to any one of claims 8 to 18, wherein a tension applied to the wire during processing of the semiconductor crystal is 5N or more and 12N or less.   20. The method of manufacturing a semiconductor wafer according to claim 8, wherein a voltage applied to the wire during the processing of the semiconductor crystal is 30 V or more and 80 V or less.   The method for manufacturing a semiconductor wafer according to any one of claims 8 to 20, wherein a feed rate of the wire at the time of processing the semiconductor crystal is 100 m / h or more and 1000 m / h or less.   The method for manufacturing a semiconductor wafer according to any one of claims 8 to 21, wherein the step of processing the semiconductor crystal includes a step of injecting a water flow onto the semiconductor crystal.   23. The method of manufacturing a semiconductor wafer according to claim 22, wherein the flow rate of the water flow is 1 slm or more and 10 slm or less.

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