JP6447322B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor element and a method for manufacturing a semiconductor element.

  In recent years, there has been a demand for semiconductor elements capable of high-speed operation as communication equipment and the like increase in speed. As one of such semiconductor elements, for example, a heterojunction bipolar transistor (HBT) is known. For example, in the following Patent Document 1, an n-type GaAs collector layer, a p-type GaAs base layer, an emitter layer composed of an n-type InGaP layer and an n-type AlGaAs layer are sequentially arranged on a semi-insulating GaAs substrate. HBT provided in is disclosed.

JP-A-5-36713

  When a semiconductor element such as the above-described HBT operates at a high frequency at, for example, several tens of GHz to several hundreds of GHz, the influence of the parasitic capacitance of the semiconductor element cannot be ignored. For this reason, a technique for reducing the parasitic capacitance of the semiconductor element is desired.

  An object of the present invention is to provide a semiconductor element and a method for manufacturing the semiconductor element that can reduce parasitic capacitance.

  A semiconductor device according to one aspect of the present invention is a support substrate and a semiconductor stacked body provided on a main surface of the support substrate, and includes a collector layer, a base layer, and an emitter layer that are sequentially stacked from the support substrate side. A collector layer, and a collector layer formed inside the side surface of the collector layer and extending along a direction intersecting with a main surface of the support substrate; and The semiconductor device further includes a region having a second surface extending from the end on the base layer side toward the side surface of the collector layer, in contact with the first surface and the second surface, and having a relative dielectric constant smaller than that of the collector layer.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a semiconductor stacked body in which a collector layer, a base layer, and an emitter layer are sequentially stacked on a semiconductor substrate; Bonding the first support substrate onto the first main surface opposite to the side, removing the semiconductor substrate from the semiconductor stacked body, and from the second main surface facing the first main surface in the semiconductor stacked body Etching a part of the collector layer; filling a gap formed by etching the collector layer with a resin having a relative dielectric constant smaller than that of the collector layer; and a second support substrate on the second main surface. A step of bonding, a step of removing the first support substrate from the semiconductor stacked body, and a step of etching a part of the semiconductor stacked body.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor element which can reduce a parasitic capacitance, and a semiconductor element can be provided.

FIG. 1 is a plan view showing the semiconductor element according to the first embodiment. 2 is a cross-sectional view taken along line II-II in FIG. (A)-(c) of FIG. 3 is a figure explaining the manufacturing method of the semiconductor element which concerns on 1st Embodiment. FIGS. 4A to 4C are views for explaining a method of manufacturing a semiconductor device according to the first embodiment. FIGS. 5A to 5C are views for explaining a method of manufacturing a semiconductor device according to the first embodiment. 6A to 6C are views for explaining a method of manufacturing a semiconductor element according to the first embodiment. 7A to 7C are views for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 8A and 8B are views for explaining a method of manufacturing a semiconductor device according to the first embodiment. FIG. 9 is a plan view showing a semiconductor element of a first modification of the first embodiment. FIG. 10 is a cross-sectional view taken along line XX in FIG. FIG. 11 is a cross-sectional view showing a semiconductor element of a second modification of the first embodiment. FIG. 12 is a plan view showing a semiconductor element of a third modification of the first embodiment. 13 is a cross-sectional view taken along line XIII-XIII in FIG. FIG. 14 is a plan view showing a semiconductor element according to the second embodiment. 15 is a cross-sectional view taken along line XV-XV in FIG. FIG. 16 is a cross-sectional view showing a semiconductor element according to a first modification of the second embodiment.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described. One embodiment of the present invention is a semiconductor substrate having a support substrate and a semiconductor laminate provided on a main surface of the support substrate, the collector laminate having a collector layer, a base layer, and an emitter layer that are sequentially laminated from the support substrate side. The collector layer is formed on the inner side with respect to the side surface of the collector layer and extends along a direction intersecting the main surface of the support substrate, and the base layer side of the first surface The semiconductor device further includes a region having a second surface extending from the edge of the collector layer toward the side surface of the collector layer, in contact with the first surface and the second surface, and having a relative dielectric constant smaller than that of the collector layer. .

  The semiconductor element includes a region in contact with the first surface and the second surface and having a relative dielectric constant smaller than that of the collector layer. By providing such a region in the semiconductor element, parasitic capacitance of the semiconductor element can be reduced.

  The collector layer may include a first collector layer and a second collector layer stacked on the first collector layer, and the region may be provided only in the first collector layer. In this case, since heat can be radiated from the side surface of the second collector layer without passing through the region, the heat dissipation of the semiconductor element is improved.

  The collector layer includes a first collector layer and a second collector layer stacked on the first collector layer, and the second collector layer is provided on the first layer and the first layer. And a third surface located between the side surface and the first surface of the first layer and extending along a direction intersecting the main surface of the support substrate, and the region includes the third surface, You may touch. In this case, for example, when wet etching is performed on the base layer or the like on the second collector layer, the etchant can be prevented from entering the first collector layer along the surface of the region.

  The semiconductor element may further include a metal layer that is provided between the semiconductor stacked body and the support substrate and that joins the semiconductor stacked body and the support substrate to each other. In this case, the heat generated in the semiconductor stacked body is favorably released to the supporting substrate through the metal layer in contact with the supporting substrate and the semiconductor stacked body.

  The metal layer includes a first metal layer and a second metal layer that are stacked on each other. In the stacking direction of the semiconductor stacked body, the first metal layer that overlaps the region and the second metal layer are disposed between the first metal layer and the second metal layer. One gap may be provided. In this case, thermal stress generated when the semiconductor element is used can be relaxed.

  The region may be a resin. In this case, entry of impurities or the like into the region can be suppressed.

  Further, the resin may have a recess that is recessed from the support substrate side toward the base layer side in the stacking direction of the semiconductor stacked body, and the recess may form a second gap. When the resin thermally expands with the use of the semiconductor element, the resin can expand into the second gap formed by the recess. Thereby, damage to the semiconductor element can be suppressed.

  Another embodiment of the present invention includes a step of forming a semiconductor stacked body in which a collector layer, a base layer, and an emitter layer are sequentially stacked on a semiconductor substrate, and a first step of the semiconductor stacked body on the side opposite to the semiconductor substrate side. Bonding a first support substrate on one main surface, removing the semiconductor substrate from the semiconductor stack, and forming a part of the collector layer on the second main surface facing the first main surface in the semiconductor stack. Etching, filling the gap formed by etching the collector layer with a resin having a relative dielectric constant smaller than that of the collector layer, bonding the second support substrate on the second main surface, 1 is a method for manufacturing a semiconductor element, comprising: removing a supporting substrate from a semiconductor stacked body; and etching a part of the semiconductor stacked body.

  According to this manufacturing method, the void formed by removing a part of the collector layer is filled with a resin having a relative dielectric constant lower than that of the collector layer. Thereby, the parasitic capacitance of the semiconductor element manufactured by the manufacturing method can be reduced.

  In addition, the manufacturing method may further include a step of removing a part of the filled resin to form a recess before forming the second adhesive layer. When the resin is thermally expanded at the time of forming a semiconductor element or the like, the resin can be expanded into a gap formed by the recess. Thereby, damage to the semiconductor element can be suppressed.

[Details of the embodiment of the present invention]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description is omitted.

(First embodiment)
FIG. 1 is a plan view showing the semiconductor element according to the first embodiment. 2 is a cross-sectional view taken along line II-II in FIG. As shown in FIGS. 1 and 2, the semiconductor element 1 of the first embodiment is a heterojunction bipolar transistor (HBT) provided on a support substrate 2. The semiconductor element 1 includes a metal layer 3 provided on a main surface 2 a of a support substrate (second support substrate) 2, a semiconductor laminate 4 provided on the metal layer 3, and an electrode provided on the semiconductor laminate 4. 5-7, the insulating film 8 which embeds the semiconductor stacked body 4 and the electrodes 5-7, the wiring layers 9-11, and the region 12 provided by removing a part of the semiconductor stacked body 4.

  The support substrate 2 is a substrate having high thermal conductivity, such as an AlN substrate (aluminum nitride substrate), a Si substrate (silicon substrate), a SiC substrate (silicon carbide substrate), or a diamond substrate. The thickness of the support substrate 2 is, for example, 20 μm to 200 μm. The thermal conductivity of the support substrate 2 is preferably higher than that of, for example, an InP substrate (indium phosphorous substrate). The thermal conductivity of the support substrate 2 is, for example, 100 W / (m · K) or more and 2000 W / (m · K) or less. Moreover, the thermal expansion coefficient of the support substrate 2 is about 1-5 ppm / degrees C, for example.

  The metal layer 3 is provided between the support substrate 2 and the semiconductor stacked body 4 and is a layer for bonding the support substrate 2 and the semiconductor stacked body 4 to each other. The metal layer 3 is made of, for example, a metal or alloy containing at least one of tungsten, molybdenum, and tantalum. The thickness of the metal layer 3 is 10 nm to 60 nm. When the thickness of the metal layer 3 is 10 nm or more, it can suppress that the semiconductor laminated body 4 peels from the support substrate 2. FIG. When the thickness of the metal layer 3 is 60 nm or less, the heat generated in the semiconductor stacked body 4 is sufficiently transferred to the support substrate 2. The thickness of the metal layer 3 is preferably 50 nm or less, more preferably 45 nm or less, and further preferably 40 nm or less.

  The metal layer 3 includes a first metal layer 13 and a second metal layer 14 that are stacked on each other. The first metal layer 13 and the second metal layer 14 may be made of the same material, or may be made of different materials. A gap 15 is provided between the first metal layer 13 and the second metal layer 14 that overlap the region 12 in the stacking direction of the semiconductor stacked body 4 (hereinafter simply referred to as the stacking direction). The space 15 may be filled with air, or the space 15 may be in a vacuum state.

  The semiconductor stacked body 4 is made of, for example, a III-V group compound semiconductor. The semiconductor stacked body 4 includes a collector layer 21, a base layer 22, an emitter layer 23, and an emitter contact layer 24 that are sequentially stacked from the support substrate 2 side.

  The collector layer 21 is a layer having a sub-collector layer (first collector layer) 25 and a main collector layer (second collector layer) 26 stacked on the sub-collector layer 25. The side surface 26 a of the main collector layer 26 is formed inside the side surface 25 a of the subcollector layer 25. Hereinafter, a combination of the side surfaces 25 a and 26 a is referred to as a side surface 21 a of the collector layer 21.

The subcollector layer 25 is a layer in contact with the metal layer 3 and is, for example, an n-type InP layer. The thickness of the subcollector layer 25 is, for example, 300 nm. The concentration of Si (silicon) in the subcollector layer 25 is, for example, about 2 × 10 ¹⁹ atoms / cm ³ . The relative dielectric constant of InP forming the subcollector layer 25 is 12.4, and the thermal expansion coefficient of InP is 4.5 ppm / ° C.

The main collector layer 26 is in contact with a partial region of the sub-collector layer 25, and includes, for example, a first layer 31 and a second layer 32 that are sequentially stacked from the support substrate 2 side. The first layer 31 is, for example, an n-type InP layer. The second layer 32 is, for example, an n-type InAlGaAs layer. The thickness of the first layer 31 is, for example, 200 nm, and the thickness of the second layer 32 is, for example, 50 nm. The concentration of Si in the first layer 31 is, for example, about 3 × 10 ¹⁶ atoms / cm ³ . The concentration of Si in the second layer 32 is, for example, about 1 × 10 ¹⁷ atoms / cm ³ . In the main collector layer 26, the side surface 32 a of the second layer 32 is substantially flush with the side surface 22 a of the base layer 22, and the side surface 31 a of the first layer 31 is outside the side surface 32 a of the second layer 32. Is formed. Further, the side surface 31 a of the first layer 31 is formed inside the side surface 25 a of the subcollector layer 25.

  An opening 25b is formed in a part of the subcollector layer 25 so as to be substantially U-shaped when viewed from the stacking direction. The opening 25 b is provided inside the side surface 31 a of the first layer 31 of the main collector layer 26 and outside the emitter contact layer 24. The first layer 31 in the main collector layer 26 is provided with an opening 31b that overlaps the opening 25b in the stacking direction and exposes the surface of the second layer 32 on the support substrate 2 side. A part of the opening 31 b is provided outside the side surface 32 a of the second layer 32 and is exposed from the second layer 32. A void 41 is formed in the collector layer 21 by these openings 25b and 31b.

  Since the void 41 is formed in the collector layer 21, the collector layer 21 has a first surface 42, a second surface 43, and a third surface 44. The first surface 42 is formed on the inner side with respect to the side surface 21a of the collector layer 21 (particularly, the side surface 31a of the first layer 31) and extends along the direction intersecting the main surface 2a of the support substrate 2. It is. The second surface 43 is a surface extending from the end 42 a on the base layer 22 side of the first surface 42 toward the side surface 21 a of the collector layer 21. The third surface 44 is a surface that is located between the side surface 31 a and the first surface 42 of the first layer 31 and extends in a direction that intersects the main surface 2 a of the support substrate 2. The first surface 42 and the third surface 44 are provided on both the sub-collector layer 25 and the main collector layer 26, and the second surface 43 is provided only on the main collector layer 26. The end 43b of the second surface 43 opposite to the end 43a that contacts the end 42a of the first surface 42 is located on the side surface 32a of the second layer 32, and the end 44a of the third surface 44 on the base layer 22 side. It is located inside.

The base layer 22 is in contact with the collector layer 21 and is, for example, a p-type InGaAs layer. The thickness of the base layer 22 is 400 nm, for example. The concentration of C (carbon) in the base layer 22 is, for example, about 5 × 10 ¹⁹ atoms / cm ³ .

The emitter layer 23 is in contact with a part of the base layer 22 and is, for example, an n-type InP layer. The thickness of the emitter layer 23 is, for example, 150 nm. The concentration of Si in the emitter layer 23 is, for example, about 2 × 10 ¹⁸ atoms / cm ³ .

The emitter contact layer 24 is in contact with the emitter layer 23 and is, for example, an n-type InGaAs layer. The thickness of the emitter contact layer 24 is, for example, 250 nm. The concentration of Si in the emitter contact layer 24 is, for example, about 2 × 10 ¹⁹ atoms / cm ³ .

  The electrode 5 is a collector electrode in contact with the sub-collector layer 25 exposed from the main collector layer 26. The electrode 6 is a base electrode in contact with the base layer 22 exposed from the emitter layer 23. The electrode 7 is an emitter electrode in contact with the top surface of the emitter contact layer 24. Each of the electrodes 5 to 7 is configured, for example, by sequentially stacking a first Pt layer (platinum layer), a Ti layer (titanium layer), a second Pt layer, and an Au layer (gold layer). In each of the electrodes 5 to 7, the thickness of the first Pt layer is, for example, 10 nm, the thickness of the Ti layer is, for example, 30 nm, the thickness of the second Pt layer is, for example, 30 nm, and the thickness of the Au layer is, for example, 100 nm.

  The insulating film 8 is provided so as to cover the semiconductor stacked body 4 and to be in contact with the region 12, and is composed of, for example, a stacked body of a SiON film (silicon oxynitride film) and a SiN film (silicon nitride film). The insulating film 8 may include a SiOx film (silicon oxide film) or an organic resin layer (for example, a polyimide layer). The insulating film 8 is provided with openings 8a to 8c.

  The wiring layer 9 is connected to the electrode 6 through the opening 8 a of the insulating film 8. The wiring layer 10 is connected to the electrode 5 through the opening 8 b of the insulating film 8. The wiring layer 11 is connected to the electrode 7 through the opening 8 c of the insulating film 8. Each of the wiring layers 9 to 11 is configured by, for example, sequentially stacking a Ti layer, a Pt layer, and an Au layer. In each of the wiring layers 9 to 11, the thickness of the Ti layer is, for example, 30 nm, the thickness of the Pt layer is, for example, 50 nm, and the thickness of the Au layer is, for example, 500 nm. Note that “connection” in this specification includes not only direct connection but also electrical connection and functional connection.

  The region 12 is provided in the gap 41 of the collector layer 21 described above, and is in contact with the first surface 42, the second surface 43, and the third surface 44 of the collector layer 21. The region 12 is provided at least in a portion where the support substrate 2 and the electrode 6 serving as the base electrode overlap when viewed from the stacking direction, and the region 12 is substantially U-shaped when viewed from the stacking direction. Yes. Further, since a part of the opening 31 b constituting the gap 41 is exposed, a part of the region 12 is exposed from the second layer 32. In the present embodiment, the region 12 is an insulating resin. Therefore, in the semiconductor element 1, a current flows between the emitter and the collector through the semiconductor stacked body 4 in which the region 12 is not provided when viewed from the stacking direction.

  The relative dielectric constant of the resin that is the region 12 is smaller than the relative dielectric constant of the collector layer 21. As described above, since the relative dielectric constant of InP constituting the subcollector layer 25 and the first layer 31 is 12.4, the relative dielectric constant of this resin may be, for example, 2-6. In the present embodiment, for example, benzocyclobutene (BCB) having a relative dielectric constant of 2.6 is used as the resin. The relative permittivity of the benzocyclobutene is smaller than the relative permittivity of each layer of the semiconductor stacked body 4, and the thermal expansion coefficient is 52 ppm / ° C.

  The resin that is the region 12 has a recess 12a that is recessed from the support substrate 2 side toward the emitter layer 23 side in the stacking direction. The recess 12a forms a gap (second gap), and the gap 15 is formed by forming the gap.

  Next, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. 3 (a) to (c), FIG. 4 (a) to (c), FIG. 5 (a) to (c), FIG. 6 (a) to (c), FIG. 7 (a). (C) and (a), (b) of Drawing 8 are figures explaining a manufacturing method of a semiconductor device concerning a 1st embodiment.

  First, as shown in FIG. 3A, as a first step, a protective layer 52, a semiconductor stacked body 53, a protective layer 54, an adhesive layer 55, and a support substrate (first support substrate) 56 are sequentially stacked. A semiconductor substrate 51 is prepared. In the first step, first, the protective layer 52, the semiconductor stacked body 53, and the protective layer 54 are formed on the semiconductor substrate 51. Then, the metal layer provided on the protective layer 54 and the metal layer provided on the support substrate 56 are bonded to each other to form the adhesive layer 55. Accordingly, the support substrate 56 is bonded to the protective layer 54 on the first main surface 53 a opposite to the semiconductor substrate 51 in the semiconductor stacked body 53 via the adhesive layer 55. The adhesion between the metal layers is performed, for example, by atomic diffusion bonding.

  The semiconductor substrate 51 is made of, for example, a III-V group compound semiconductor. The semiconductor substrate 51 is, for example, an InP substrate. The protective layer 52 is a semiconductor layer having high etching selectivity with respect to a semiconductor layer 61 described later of the semiconductor stacked body 53. The protective layer 52 is an InGaAs layer of about 200 nm, for example. The protective layer 52 is formed by an epitaxial growth method.

  The semiconductor stacked body 53 includes semiconductor layers 61 to 65. The semiconductor layer 61 is a layer corresponding to the subcollector layer 25 shown in FIG. The semiconductor layer 62 is a layer corresponding to the main collector layer 26 shown in FIG. The semiconductor layer 62 includes a layer 62 a corresponding to the first layer 31 shown in FIG. 2 and a layer 62 b corresponding to the second layer 32. The semiconductor layer 63 is a layer corresponding to the base layer 22 shown in FIG. The semiconductor layer 64 is a layer corresponding to the emitter layer 23 shown in FIG. The semiconductor layer 65 is a layer corresponding to the emitter contact layer 24 shown in FIG. The semiconductor layers 61 to 65 are formed by, for example, an epitaxial growth method.

  The protective layer 54 is a semiconductor layer having high etching selectivity with respect to the semiconductor layer 65 of the semiconductor stacked body 53. The protective layer 54 is an InP layer of about 200 nm, for example. The protective layer 54 is formed by an epitaxial growth method. The adhesive layer 55 is a tungsten layer or the like, and is grown by sputtering, for example.

  Next, as shown in FIG. 3B, as a second step, the semiconductor substrate 51 is removed from the semiconductor stacked body 53. For example, the semiconductor substrate 51 is removed by dry etching or wet etching. Then, the protective layer 52 is removed from the semiconductor stacked body 53.

  Next, as shown in FIG. 3C, as a third step, a patterned etching mask 57 is formed on the second main surface 53 b facing the first main surface 53 a of the exposed semiconductor stacked body 53. Form. The etching mask 57 is made of, for example, a silicon compound (SiN layer or SiOx layer) and has an opening 57a. A part of the second main surface 53b is exposed through the opening 57a.

  Next, as shown in FIG. 4A, as a fourth step, a part of the semiconductor stacked body 53 is etched using the etching mask 57. Specifically, the gap 41 is formed in the semiconductor stacked body 53 by wet etching the semiconductor layers 61 and 62 of the semiconductor stacked body 53 corresponding to the collector layer 21. More specifically, the InP constituting the semiconductor layer 61 and the InP constituting the layer 62a included in the semiconductor layer 62 are wet-etched using hydrochloric acid whose concentration is adjusted, whereby the gap 41 is formed in the semiconductor stacked body 53. Form. By adjusting the wet etching time, the maximum width of the gap 41 is larger than the width of the opening 57 a provided in the etching mask 57. The wet etching time may be several minutes to several tens of minutes, for example.

  Next, as shown in FIG. 4B, as a fifth step, a resin layer 58 is formed on the etching mask 57 and the gap 41 is filled with resin. For example, the resin layer 58 is formed by a coating method, an inkjet method, or the like, and the gap 41 is filled with a resin.

  Next, as shown in FIG. 4C, as a sixth step, the resin layer 58 is removed. For example, the resin layer 58 is removed by CMP (Chemical Mechanical Polishing). As a result, at least the resin filled in the gap 41 remains and forms the region 12 of the present embodiment. Further, the surface of the etching mask 57 and the exposed surface of the resin that is the region 12 are substantially flush with each other. The exposed surface of the resin may be recessed by dishing.

Next, as shown in FIG. 5A, as a seventh step, a part of the resin that is the region 12 is removed to form a recess 12 a in the region 12. Specifically, the recess 12a is formed by dry etching a part of the region 12 using the etching mask 57. This dry etching is reactive ion etching using, for example, CF ₄ gas and O ₂ gas, and is performed until the recess of the recess 12a reaches at least the second main surface 53b toward the support substrate 56. For example, the reactive ion etching is performed under the conditions of a CF ₄ gas flow rate of 10 sccm, an O ₂ gas flow rate of 5 sccm, a pressure of 20 Pa, and 100 W.

  Next, as shown in FIG. 5B, as an eighth step, the etching mask 57 is removed. For example, the etching mask 57 is removed by various etchings.

  Next, as shown in FIG. 5C, as a ninth step, a support substrate (second support substrate) 2 in which a metal layer 59a corresponding to the first metal layer 13 is provided on the main surface 2a is provided. prepare. In addition, a metal layer 59 b corresponding to the second metal layer 14 is formed on the second main surface 53 b of the semiconductor stacked body 53 and on the exposed surface of the region 12. The metal layers 59a and 59b are, for example, tungsten layers. The thermal conductivity of the metal layers 59 a and 59 b is higher than that of the semiconductor stacked body 53. Further, the thermal conductivity of the support substrate 2 is higher than the thermal conductivity of the semiconductor substrate 51.

  Next, as shown in FIG. 6A, as a tenth step, the support substrate 2 is bonded onto the second main surface 53 b of the semiconductor stacked body 53. Specifically, the metal layer 59 is formed by bonding the metal layer 59 a and the metal layer 59 b to each other, and thereby the support substrate 2 is bonded onto the second main surface 53 b of the semiconductor stacked body 53. The adhesion of the metal layers 59a and 59b is performed by, for example, atomic diffusion bonding. Here, the metal layers 59a and 59b overlapping the concave portion 12a of the region 12 when viewed from the stacking direction do not adhere to each other and form the gap 15. Next, the support substrate 56 is removed from the semiconductor stacked body 53. For example, the support substrate 56 is removed by dry etching or wet etching. Then, the adhesive layer 55 and the protective layer 54 are removed. Thereby, the first main surface 53a of the semiconductor stacked body 53 is exposed.

  Next, as an eleventh step, a part of the semiconductor stacked body 53 is removed. In the eleventh step, first, the emitter contact layer 24 is formed by patterning the semiconductor layer 65 as shown in FIG. For example, the emitter contact layer 24 is formed by wet etching. Next, after forming an etching mask 71 covering at least the emitter contact layer 24, the semiconductor layers 63 and 64 and the layer 62b of the semiconductor layer 62 are wet-etched. Thereby, the second layer 32 in the emitter layer 23, the base layer 22, and the collector layer 21 is formed (see FIG. 2). Through the eleventh step, the region 12 formed outside the side surface 32a of the second layer 32 is exposed.

  Next, as a twelfth step, after removing the etching mask 71, as shown in FIG. 6C, at least the exposed region 12, the second layer 32 of the collector layer 21, the base layer 22, the emitter layer 23. And an etching mask 72 that covers the emitter contact layer 24 is formed. Then, the first layer 31 is formed by wet etching the layer 62a of the semiconductor layer 62 (see FIG. 2). Thereby, the main collector layer 26 having the first layer 31 and the second layer 32 is formed.

  Next, as a thirteenth step, after removing the etching mask 72, as shown in FIG. 7A, at least the exposed region 12, the main collector layer 26, the base layer 22, the emitter layer 23, and the emitter contact An etching mask 73 covering the layer 24 is formed. Then, the subcollector layer 25 is formed by wet etching the semiconductor layer 61 (see FIG. 2). Thus, the mesa structure semiconductor stacked body 4 having the collector layer 21 having the sub-collector layer 25 and the main collector layer 26, the base layer 22, the emitter layer 23, and the emitter contact layer 24 is formed.

  Next, as a 14th step, as shown in FIG. 7B, the metal layer 59 is removed by reactive ion etching using the etching mask 73, and the first metal layer 13 and the second metal layer 14 are removed. The metal layer 3 is formed.

  Next, as a fifteenth step, the etching mask 73 is removed as shown in FIG. The etching mask 73 is removed by various etchings.

  Next, as shown in FIG. 8A, as a sixteenth step, the electrode 7 is formed on a partial region of the emitter contact layer 24 (on the first main surface 53a shown in FIG. 3A). Form. Further, the electrode 5 is formed on a partial region of the subcollector layer 25, and the electrode 6 is formed on a partial region of the base layer 22. The electrode 6 formed on a partial region of the base layer 22 is connected to the base layer 22 by, for example, platinum sintering by heat treatment at 400 ° C. for 1 minute.

  Next, as shown in FIG. 8B, as a seventeenth step, the insulating film 8 is formed so as to embed the semiconductor stacked body 4 and the electrodes 5 to 7. By selectively etching the insulating film 8, an opening 8a exposing the electrode 5, an opening 8b exposing the electrode 6, and an opening 8c exposing the electrode 7 are formed (see also FIG. 1). ). Then, the wiring layers 9 to 11 are formed by patterning, thereby completing the semiconductor element 1 that is an HBT (see FIG. 2).

  The semiconductor element 1 formed by the manufacturing method according to the first embodiment described above is in contact with the first surface 42 and the second surface 43 of the collector layer 21 and has a relative dielectric constant smaller than that of the collector layer 21. A region 12 is provided. By providing such a region 12 in the semiconductor element 1, a part of the semiconductor stacked body 4 included in the semiconductor element 1 is replaced with the region 12 having a smaller relative dielectric constant. Parasitic capacitance can be reduced.

  The main collector layer 26 is located between the first layer 31, the second layer 32 provided on the first layer 31, and the side surface 31 a of the first layer 31 and the second surface 43 of the collector layer 21. The third surface 44 may extend along the direction intersecting the main surface 2 a of the support substrate 2, and the region 12 may be in contact with the third surface 44. In this case, for example, when the layer 62 a corresponding to the first layer 31 of the main collector layer 26 provided on the semiconductor layer 61 is wet etched, the etchant travels along the surface of the region 12 and corresponds to the subcollector layer 25. Intrusion into the semiconductor layer 61 can be suppressed.

  The semiconductor element 1 may further include a metal layer 3 that is provided between the semiconductor stacked body 4 and the support substrate 2 and that joins the semiconductor stacked body 4 and the support substrate 2 to each other. In this case, the heat generated in the semiconductor stacked body 4 is favorably released to the support substrate 2 through the metal layer 3 in contact with the support substrate 2 and the semiconductor stacked body 4.

  The metal layer 3 includes a first metal layer 13 and a second metal layer 14 that are stacked on each other, and the first metal layer 13 and the second metal layer 14 that overlap the region 12 in the stacking direction of the semiconductor stacked body 4. A gap 15 may be provided between the two. In this case, the thermal stress generated when the semiconductor element 1 is used can be relaxed. Although not shown, by providing a gap in one of the support substrate 2 and the semiconductor laminate 4, a gap 15 is provided between the first metal layer 13 and the second metal layer 14 that overlap the region 12. Also good.

  Further, the region 12 may be a resin. By filling the void 41 of the collector layer 21 with the resin and forming the region 12, it is possible to suppress the entry of impurities or the like into the region 12.

  The region 12 made of resin has a recess 12a that is recessed from the support substrate 2 side toward the base layer 22 side in the stacking direction of the semiconductor stacked body 4, and the recess 12a forms a void. Also good. When the resin thermally expands with the use of the semiconductor element 1, the resin can expand into the gap formed by the recess 12a. Thereby, damage to the semiconductor element 1 can be suppressed.

  The semiconductor element 1 may further include an insulating film 8 that covers the semiconductor stacked body 4, and the insulating film 8 may be in contact with the region 12. Even when the region 12 is exposed from the collector layer 21, the region 12 exposed by the insulating film 8 can be covered.

  The semiconductor element 1 further includes an electrode 6 connected to the base layer 22 exposed from the collector layer 21, and the region 12 is a portion where the support substrate 2 and the electrode 6 overlap along the stacking direction of the semiconductor stacked body 4. May be provided at least. By providing the region 12 in this manner, the parasitic capacitance generated due to the electrode 6 serving as the base electrode can be suitably reduced.

  FIG. 9 is a plan view showing a semiconductor element of a first modification of the first embodiment. FIG. 10 is a cross-sectional view taken along line XX in FIG. As shown in FIG. 10, the semiconductor element 1A may have a plurality of emitter contact layers 24A and 24B. In this case, the emitter contact layers 24A and 24B are provided on different regions of the emitter layer 23 that are separated from each other. An electrode 7A is provided on the emitter contact layer 24A, and an electrode 7B is provided on the emitter contact layer 24B. Even in this case, the same effects as those of the first embodiment can be obtained. In addition, the amount of current flowing in the semiconductor stacked body 4 can be increased.

  FIG. 11 is a cross-sectional view showing a semiconductor element of a second modification of the first embodiment. As shown in FIG. 11, the gap 41 of the semiconductor element 1 </ b> B is formed only in the subcollector layer 25. That is, the region 12 that is the resin filled in the gap 41 is provided only in the subcollector layer 25. In this case, the surface on the support substrate 2 side of the first layer 31 in the main collector layer 26 is in contact with the region 12. The first surface 42 and the third surface 44 are formed only on the subcollector layer 25. Even in this case, the parasitic capacitance of the semiconductor element 1B can be reduced as in the first embodiment. In addition, since heat can be radiated from the entire side surface 31a of the first layer 31 of the main collector layer 26 without going through the region 12, the heat dissipation of the semiconductor element 1B is improved.

  FIG. 12 is a plan view showing a semiconductor element of a third modification of the first embodiment. 13 is a cross-sectional view taken along line XIII-XIII in FIG. As shown in FIG. 12, the region 12 of the semiconductor element 1 </ b> C is formed so as to surround the emitter contact layer 24 when viewed from the stacking direction. In this case, since the ratio of the region 12 in the semiconductor element 1C is increased, the parasitic capacitance of the semiconductor element 1C can be favorably reduced. As shown in FIG. 13, the electrode 5 is provided directly on the metal layer 3. Thereby, even when the region 12 is formed so as to surround the emitter contact layer 24, a current flows favorably in the semiconductor element 1.

(Second Embodiment)
Hereinafter, the semiconductor element according to the second embodiment will be described. In the description of the second embodiment, descriptions overlapping with the first embodiment are omitted, and only the parts different from the first embodiment are described. In other words, the description of the first embodiment may be used as appropriate for the second embodiment within the technically possible range.

  FIG. 14 is a plan view showing a semiconductor element according to the second embodiment. 15 is a cross-sectional view taken along line XV-XV in FIG. As shown in FIGS. 14 and 15, the region 12 of the semiconductor element 1 </ b> D is not exposed from the collector layer 21. In other words, the region 12 of the semiconductor element 1D is provided so as to be embedded in the collector layer 21 of the semiconductor stacked body 4. Thereby, in the collector layer 21, the end 43 b of the second surface 43 is in contact with the end 44 a of the third surface 44.

  Even the semiconductor element 1D according to the second embodiment described above can achieve the same effects as those of the first embodiment. In addition, for example, when the insulating film 8 is formed, the resin that is the region 12 is not irradiated with plasma, so that an increase in the relative dielectric constant of the resin can be prevented.

  FIG. 16 is a cross-sectional view showing a semiconductor element according to a first modification of the second embodiment. As shown in FIG. 16, the gap 41 formed in the collector layer 21 of the semiconductor element 1E is not filled with resin or the like, and is in a vacuum state or a state filled with air. The relative permittivity of vacuum is 1, and the relative permittivity of air is about 1, which is smaller than the relative permittivity of the resin shown in the first embodiment. Therefore, in this modification, the parasitic capacitance of the semiconductor element 1E can be reduced satisfactorily.

  The semiconductor element and the method for manufacturing the semiconductor element according to the present invention are not limited to the above-described embodiments and modifications, and various other modifications are possible. For example, the emitter contact layer 24 of the semiconductor device 1D according to the second embodiment may be provided in a plurality of regions separated from each other on the emitter layer 23 as in the first modification of the first embodiment.

  Moreover, in the said embodiment and modification, although the main collector layer 26 has the 1st layer 31 and the 2nd layer 32, this main collector layer 26 may have a 3rd layer etc. For example, a third layer may be provided between the first layer 31 and the second layer 32, and the third layer may be in contact with the region 12. In this case, the impurity concentration of the third layer is lower than the impurity concentration of the second layer 32. By providing such a third layer, it is possible to reduce the leakage current flowing through the interface where the region 12 and the main collector layer 26 are in contact with each other.

  Moreover, in the said embodiment and modification, you may combine mutually in the possible range. For example, the aspect of the second modification of the first embodiment may be combined with the second embodiment. In this case, the region 12 embedded in the semiconductor stacked body 4 is provided only in the subcollector layer 25. In addition, the space 41 may be formed in the subcollector layer 25 without filling the region with resin or the like.

  In the embodiment and the modification, the semiconductor stacked body 53 may include an etch stop layer. For example, the etch stop layer is included between the semiconductor layer 61 and the semiconductor layer 62 in the semiconductor stacked body 53, and the etching selectivity with respect to the semiconductor layer 62 is very low. In this case, the etch stop layer can suppress excessive etching of the semiconductor layer 62, and can suppress a change in characteristics of the semiconductor element. For example, InGaAs is used as the etch stop layer. This etch stop layer is etched using, for example, a liquid obtained by diluting a mixed solution of phosphoric acid and hydrogen peroxide with water as an etchant.

  DESCRIPTION OF SYMBOLS 1,1A-1E ... Semiconductor element, 2 ... Support substrate, 2a ... Main surface, 3 ... Metal layer, 4 ... Semiconductor laminated body, 5-7, 7A, 7B ... Electrode, 8 ... Insulating film, 9-11 ... Wiring Layer, 12 region, 13 first metal layer, 14 second metal layer, 15 void, 21 collector layer, 21a side surface, 22 base layer, 22a side surface, 23 emitter layer, 24A 24B ... emitter contact layer, 25 ... sub-collector layer, 25a ... side face, 25b, 31b ... opening, 26 ... main collector layer, 26a ... side face, 31 ... first layer, 32 ... second layer, 41 ... air gap, 42 ... 1st surface, 42a ... End, 43 ... 2nd surface, 43a, 43b ... End, 44 ... 3rd surface, 44a ... End, 51 ... Semiconductor substrate, 53 ... Semiconductor laminated body, 53a ... 1st main surface, 53b ... second main surface, 56 ... support substrate, 57 ... etching mask, 58 Resin layer, 59a, 59b ... metal layer, 61 to 65 ... semiconductor layer.

Claims (7)

A support substrate;
A semiconductor laminate provided on a main surface of the support substrate, the semiconductor laminate having a collector layer, a base layer, and an emitter layer, which are sequentially laminated from the support substrate side;
A semiconductor device comprising:
The collector layer is formed on the inner side with respect to the side surface of the collector layer, and extends along a direction intersecting the main surface of the support substrate, and the base layer of the first surface A second surface extending from a side end toward the side surface of the collector layer;
Together with contact with the first surface and the second surface, further example Bei regions having a smaller dielectric constant than said collector layer,
The collector layer has a first collector layer and a second collector layer stacked on the first collector layer;
The second collector layer is located between the first layer, the second layer provided on the first layer, a side surface of the first layer, and the first surface, and the main surface of the support substrate. And a third surface extending along the direction intersecting with
The semiconductor element is in contact with the third surface . A support substrate;
A semiconductor laminate provided on a main surface of the support substrate, the semiconductor laminate having a collector layer, a base layer, and an emitter layer, which are sequentially laminated from the support substrate side;
A semiconductor device comprising:
The collector layer is formed on the inner side with respect to the side surface of the collector layer, and extends along a direction intersecting the main surface of the support substrate, and the base layer of the first surface A second surface extending from a side end toward the side surface of the collector layer;
A region in contact with the first surface and the second surface and having a relative dielectric constant smaller than that of the collector layer;
The semiconductor laminated body and with provided between the supporting substrate, further comprising a metal layer for bonding the semiconductor laminate and said supporting substrate to each other, a semi conductor elements. The metal layer has a first metal layer and a second metal layer stacked on each other,
3. The semiconductor device according to claim 2 , wherein a first gap is provided between the first metal layer and the second metal layer overlapping with the region in a stacking direction of the semiconductor stacked body. The region is a resin, the semiconductor device according to any one of claims 1-3. The resin has a recess that is recessed from the support substrate side toward the base layer side in the stacking direction of the semiconductor stack,
The semiconductor element according to claim 4 , wherein the concave portion forms a second gap. Forming a semiconductor stacked body in which a collector layer, a base layer, and an emitter layer are sequentially stacked on a semiconductor substrate;
Bonding a first support substrate on a first main surface opposite to the semiconductor substrate in the semiconductor laminate;
Removing the semiconductor substrate from the semiconductor stack;
Etching a part of the collector layer from a second main surface facing the first main surface in the semiconductor laminate;
Filling a void formed by etching the collector layer with a resin having a relative dielectric constant smaller than that of the collector layer;
Adhering a second support substrate on the second main surface;
Removing the first support substrate from the semiconductor stack;
Etching a portion of the semiconductor stack;
A method for manufacturing a semiconductor device comprising: The method for manufacturing a semiconductor element according to claim 6 , further comprising a step of removing a part of the filled resin to form a recess before bonding the second support substrate on the second main surface. .

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