JP2853761B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high-speed bipolar transistor for reducing a base parasitic resistance and a collector-base parasitic capacitance and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the demand for high-speed bipolar transistors has been increased in accordance with the trend toward higher functionality of applied equipment. Higher speeds have been realized by miniaturization, shallow junctions, and reduction of parasitic resistance and parasitic capacitance. I've been. However, it is not easy to reduce the parasitic resistance and the parasitic capacitance at the same time, and it is not easy to simultaneously reduce the base parasitic resistance and the collector-base parasitic capacitance, which have a great influence on the speeding up. For example, if an attempt is made to reduce the base parasitic resistance without lowering the current amplification factor h _FE , the impurity concentration of the base lead portion (graft base) will increase, but this will increase the junction capacitance per area. In addition, since the graft base largely diffuses into the collector region, the parasitic capacitance between the collector and the base increases as a result.

As a method of reducing the base parasitic resistance and the parasitic resistance between the collector and the base, there is a method in which the collector and the graft base are separated by an insulating film as shown in FIG. In this structure, even if the impurity concentration of the graft base portion is increased, the diffusion to the collector region is suppressed by the insulating film, and the parasitic capacitance between the collector and the base is reduced because of the separation by the insulating film. Can be.

[0004] This semiconductor device is manufactured as follows. First, as shown in FIG. 3A, an n-type diffusion layer 2 serving as a collector burying layer is formed on a p-type silicon substrate 1. Next, a silicon oxide film 3 is formed by selectively oxidizing the surface of the n-type diffusion layer 2 in a region other than a region where a transistor active portion is formed and a region where a collector lead-out region is formed in a later step. Next, as shown in FIG.
Epitaxial growth of silicon on the main surface of the substrate,
An epitaxial silicon layer 15 is formed on type diffusion layer 2 and a polycrystalline silicon layer 14 is formed on silicon oxide film 3. Next, as shown in FIG. 3C, a silicon oxide film 6 is formed by oxidizing so as to reach the silicon oxide film 3 except for a portion serving as a graft base after the polycrystalline silicon layer 14. U-groove insulating film 5 for separating transistors
To form

Next, a p-type impurity is diffused in the polycrystalline silicon layer 14 to form a graft base 16, and a p-type impurity is further diffused in a transistor active portion forming region to form a base diffusion layer 11. The emitter diffusion layer 9 is formed by selectively diffusing an n-type impurity into the surface region of the diffusion layer 11. The portion of the epitaxial silicon layer 15 below the base diffusion layer 11 becomes a collector region 12, and the n-type diffusion layer 2 functions as a collector buried layer 2a. Further, an n-type impurity is diffused in the collector electrode forming portion to form a collector lead region 8. Thereafter, a silicon oxide film 7 is formed on the surface, an opening is selectively formed in the silicon oxide film, and then a collector electrode, an emitter electrode, and a base electrode (all not shown) are formed.

[0006]

In the above prior art, since the graft base region is made of polycrystalline silicon, the specific resistance is higher than that of single crystal silicon, and the sheet resistance is higher than 100 Ω / □. In addition, the silicon oxide film 3
Since the polycrystalline silicon layer 14 grows thereon, the region A secured as a region where the active region of the transistor is formed
Must secure a margin for the emitter region B, and cannot be made as small as the emitter region. Therefore, the base region is opposed to the collector buried layer 2a having a high impurity concentration over a wide area, and the collector buried layer 2a having a high impurity concentration is in contact with the graft base 16 having a high impurity concentration. -A considerable capacitance is parasitic between the bases. Also, when the epitaxial silicon layer 15 is formed, the impurity concentration of the n-type diffusion layer 2 serving as the collector lead-out region 2a is high, so that the concentration of the epitaxial silicon layer 15 immediately above the n-type diffusion layer 2 becomes high due to out diffusion during epitaxial growth. It is difficult to secure a sufficient junction breakdown voltage. If the impurity concentration of the n-type diffusion layer 2 is reduced in order to secure the junction withstand voltage, the resistance of the collector buried layer increases and a transistor having desired characteristics cannot be obtained. Therefore, an object of the present invention is to provide a high-quality transistor having a low base parasitic resistance and a low collector-base parasitic resistance and a high collector breakdown voltage.

[0007]

An object of the present invention is to provide a first semiconductor substrate having an n-type diffusion layer serving as a collector burying layer on the surface thereof, and an n-type second semiconductor having an oxide film selectively formed on the surface. This can be solved by forming a base diffusion layer and an emitter diffusion layer on the side of the second semiconductor substrate.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention comprises a first impurity of a first conductivity type having a high impurity concentration formed on a semiconductor substrate.
A first insulating film formed on the first semiconductor layer and provided with a first opening in a portion corresponding to a region where an active region of a transistor is formed; It formed on the insulating film, a second insulating film a second opening at a region formed in the active region and a graft base of the transistor, embedded within the first and second openings, the single A second conductivity type second semiconductor layer made of a crystalline semiconductor , wherein a second conductivity type base diffusion layer is formed in the second semiconductor layer so as to cover and cover the first opening. A first conductivity type emitter diffusion layer is formed in a surface region of the base diffusion layer, and a side surface of the base diffusion layer and the second diffusion layer are formed in the second semiconductor layer outside the base diffusion layer. The second conductive type having a high impurity concentration so as to be in contact with the upper surface of the first insulating film. It is characterized in that over the scan out region is formed.

Further, according to the method of manufacturing a semiconductor device of the present invention, there are provided (1) a main surface of a first semiconductor substrate of a second conductivity type having a semiconductor layer of the first conductivity type formed on the main surface side; First on the side
A step of bonding a main surface of a second semiconductor substrate of the first conductivity type in which a first insulating film having an opening is formed and whose main surface is flattened; (2) the second semiconductor substrate And (3) a step of selectively oxidizing the second semiconductor substrate to form a base diffusion layer and a base lead region on the first opening. Forming a second insulating film having a second opening having a shape larger than that of the first opening so as to be in contact with the first insulating film; and (4) forming a second conductive type in the second semiconductor substrate. An impurity is selectively introduced, and a base diffusion layer is formed so as to cover the first opening, and a base is formed outside the base diffusion layer so as to be in contact with a side surface of the base diffusion layer and an upper surface of the first insulating film. Forming a lead region; and (5) in the surface region of the base diffusion layer. And a, and forming an emitter diffusion layer by selectively introducing first conductivity type impurity.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 (c) is a sectional view showing a first embodiment of the present invention, and FIGS. 1 (a) and 1 (b) are sectional views showing a manufacturing process in the order of steps. is there. First, as shown in FIG. 1 (a), on the p-type silicon 1 having an impurity concentration of 1 to 5E15 cm ⁻³ , 1 to ³ μm, preferably 1.5 to 2.5 μm
N-type impurity (for example, phosphorus) with a thickness of 1 to 5E19 cm
^The n-type diffusion layer 2 is formed by diffusing to a concentration of ^-3 . This n-type diffusion layer becomes a collector buried layer of the transistor. Separately, an n-type silicon substrate 4a having an impurity concentration of 0.7 to 2E16 cm ^-3 is prepared, and its surface is selectively oxidized to form a silicon oxide film 3 having a thickness of 0.5 μm to 1.5 μm. CMP (Chemical Mechanical)
(Polishing) technology or the like to smooth its surface. Here, the size of the opening of the portion of the silicon oxide film 3 corresponding to the active region of the transistor (length of one side A)
Is approximately equal to 0.8 μm to 1.0 μm, preferably 0.4 μm to 0.7 μm, as the emitter diffusion layer formed in the subsequent step.
μm.

After bonding the two substrates by a method similar to the method of forming an SOI substrate by the bonding method and performing a heat treatment, the n-type silicon substrate 4a is ground and CM
0.3 μm to 1.0 μm, preferably 0.1 μm using P technology.
Polishing to a thickness of 4 μm to 0.7 μm forms an n-type silicon layer 4 on the n-type diffusion layer 2 [FIG.
(B)]. This n-type silicon layer 4 will form the collector region 1 in the future.
It becomes 2.

Next, a silicon oxide film 6 having an opening in a region where a transistor active region, a graft base is formed, and a region for forming a collector lead-out region is formed. The trench insulating film 5 is formed so as to penetrate the n-type diffusion layer 2, and the collector buried layer 2a is separated for each transistor. Next, a p-type impurity (for example, boron) is selectively introduced into the n-type silicon layer 4 so that the sheet resistance becomes 5 to 50.
A Ω / □ graft base 10 is formed, and a p-type impurity is selectively introduced to form a base diffusion layer 11 having an impurity concentration of 1 to 5E18 cm ⁻³ . Base diffusion layer 11 may be formed so as to have a junction depth reaching silicon oxide film 3. Next, an emitter diffusion layer 9 is formed by selectively diffusing an n-type impurity (for example, arsenic) into the surface region of the base diffusion layer 11 to a concentration of 1 to 2E20 cm ^-3 . Further, an n-type impurity is selectively diffused to form a collector lead region 8 having an impurity concentration of 1 to 5E20 cm ^-3 . Next, a silicon oxide film 7 is formed on the entire surface to a thickness of 0.5 μm to 1 μm.
The film is deposited to a thickness of μm, and an opening is selectively formed so that the base electrode, the emitter electrode, and the collector electrode can be connected to each diffusion layer (FIG. 1C).

In the transistor thus formed, the resistivity of the graft base, which is the base lead-out portion, can be reduced to about 1/3 or less of the conventional one, and the base parasitic resistance can be reduced by about 10%. become. Also,
The size of the opening of the silicon oxide film 3 formed under the transistor active layer can be made substantially the same as that of the emitter diffusion layer, and the semiconductor layer between the base diffusion layer 11 and the silicon oxide film 3 can be depleted. Therefore, the collector buried layer 2a having a higher impurity concentration and the graft base 10 can be completely separated from each other, so that the collector-base parasitic capacitance can be reduced by about 20% as compared with the conventional case. Furthermore, since the region for forming the transistor active region is formed by using a bonding technique instead of the conventional epitaxial growth, the distance from the collector buried layer 2a to the base diffusion layer can be increased. From 20 to 30 Ω / □ to 10 Ω / □ or less, and a high junction breakdown voltage can be maintained.

[Second Embodiment] FIG. 2C is a sectional view showing a second embodiment of the present invention, and FIGS. 2A and 2B.
4A to 4C are sectional views in the order of steps showing the manufacturing process. In FIG. 2, the same parts as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals. In this embodiment, p
After the n-type diffusion layer 2 is formed on the silicon substrate 1 of FIG.
As shown in (a), by the LPCVD (low pressure CVD) method, 0.05 μm to 0.5 μm, preferably 0.1 μm to
A polycrystalline silicon layer 13 having a thickness of 0.3 μm is deposited.

Thereafter, this substrate and an n-type silicon substrate 4 having a silicon oxide film 3 are bonded. At this time, since the polycrystalline silicon layer 13 serves as a buffer film, a good bonded substrate without voids can be obtained. The polycrystalline silicon layer 13 may be a non-doped film because the polycrystalline silicon layer 13 is made n-type by impurity diffusion from the n-type diffusion layer 2 at the time of heat treatment after bonding the substrates, but may be doped with an n-type impurity in advance. More preferred. The polycrystalline silicon film is n
It may be formed on the mold silicon substrate 4a side, or may be formed on both substrates. Further, amorphous silicon can be used instead of polycrystalline silicon. The process after bonding the two substrates is the same as that of the first embodiment, and the description is omitted.

[0016]

As described above, the semiconductor device of the present invention can be manufactured by using a bonding type SOI substrate manufacturing technique.
Since the active layer of the transistor is formed in the OI layer, according to the present invention, the base parasitic resistance and the parasitic capacitance between the collector and the base can be reduced at the same time, and a high-speed transistor can be provided. become. Further, according to the present invention, it is possible to simultaneously reduce the resistance of the collector buried layer and improve the collector breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a sectional view in the order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view in the order of steps for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view of a conventional example in the order of steps.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type silicon substrate 2 n-type diffusion layer 2 a collector buried layer 3, 6, 7 silicon oxide film 4 n-type silicon layer 4 a n-type silicon substrate 5 U-groove insulating film 8 collector drawing region 9 emitter diffusion layer 10, 16 graft base Reference Signs List 11 base diffusion layer 12 collector region 13, 14 polycrystalline silicon layer 15 epitaxial silicon layer

Claims (9)

(57) [Claims] A first conductive type first semiconductor layer having a high impurity concentration formed on a semiconductor substrate; and a first active region of a transistor formed on the first semiconductor layer. A first insulating film provided with a first opening in a corresponding portion; and a second opening provided in a region where an active region of a transistor and a graft base are formed over the first insulating film. A second insulating film, and a second semiconductor layer of a first conductivity type embedded in the first and second openings. A second conductive type base diffusion layer is formed in a shape covering the opening, and a first conductive type emitter diffusion layer is formed in a surface region of the base diffusion layer. In the second semiconductor layer, a side surface of the base diffusion layer and the first insulating layer are provided. In a semiconductor device in which a second conductive type base extraction region having a high impurity concentration is formed so as to be in contact with an upper surface of a film, all of the second semiconductor layers are formed by a single connection.
A semiconductor device comprising a crystalline semiconductor . 2. A third and a fourth opening for exposing a surface of a first semiconductor layer are respectively formed continuously in the first and second insulating films. 2. The semiconductor device according to claim 1, wherein a third semiconductor layer of a first conductivity type forming a collector lead-out region is formed in said opening. 3. The semiconductor device according to claim 1, wherein said first opening is formed below said emitter diffusion layer with a size substantially equal to said emitter diffusion layer. 4. The semiconductor device according to claim 1, wherein in the second semiconductor layer, the thickness of the base diffusion layer is smaller than the thickness of the second insulating film. 5. The semiconductor device according to claim 1, wherein the first to third semiconductor layers are surrounded by a U-groove insulating film, so that elements inside and outside the U-groove insulating film are electrically separated from each other. Item 2. The semiconductor device according to item 1. 6. The semiconductor device according to claim 1, wherein said first semiconductor layer is located between said second semiconductor layer and said first insulating film, or said first semiconductor layer is located between said second and third semiconductor layers and said first insulating layer. 2. A polycrystalline silicon layer or an amorphous silicon layer is formed between the first and second insulating films.
Or the semiconductor device according to 2. 7. (1) A first surface of a first semiconductor substrate of a second conductivity type having a semiconductor layer of a first conductivity type formed on a main surface side, and a first opening having a first opening on the main surface side. A step of laminating a main surface of a second semiconductor substrate of the first conductivity type, the main surface of which is formed and the main surface of which is flattened; and (2) forming a desired film on the back surface of the second semiconductor substrate. Grinding to a thickness; and (3) a shape larger than the first opening for selectively oxidizing the second semiconductor substrate to form a base diffusion layer and a base extension region on the first opening. Forming a second insulating film having a second opening so as to be in contact with the first insulating film; and (4) selectively introducing a second conductivity type impurity into the second semiconductor substrate. Then, a base diffusion layer is provided outside the base diffusion layer so as to cover the first opening. Forming a base extraction region so as to be in contact with the upper surface of the first insulating film; and (5) selectively introducing a first conductivity type impurity into a surface region of the base diffusion layer to form an emitter diffusion layer. Forming a semiconductor device. 8. The method according to claim 1, wherein in the step (1), an amorphous silicon film or a polycrystalline silicon film is formed on a bonding surface of the first semiconductor substrate and / or the second semiconductor substrate, and thereafter, bonding is performed. The method for manufacturing a semiconductor device according to claim 7, wherein: 9. When forming the first and second insulating films, third and fourth openings for forming a collector lead-out region are formed on the semiconductor layer of the first conductivity type. 8. The method for manufacturing a semiconductor device according to claim 7, wherein: