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JP6466252B2 - Semiconductor package and manufacturing method thereof - Google Patents
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JP6466252B2 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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JP6466252B2
JP6466252B2 JP2015106230A JP2015106230A JP6466252B2 JP 6466252 B2 JP6466252 B2 JP 6466252B2 JP 2015106230 A JP2015106230 A JP 2015106230A JP 2015106230 A JP2015106230 A JP 2015106230A JP 6466252 B2 JP6466252 B2 JP 6466252B2
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stress relaxation
relaxation layer
semiconductor package
semiconductor device
sealing body
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JP2016178272A (en
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聖昭 橋本
聖昭 橋本
靖之 竹原
靖之 竹原
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株式会社ジェイデバイス
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Priority to KR1020150081878A priority Critical patent/KR102487894B1/en
Priority to CN201510320188.2A priority patent/CN105280567B/en
Priority to TW104119150A priority patent/TWI660477B/en
Priority to US14/739,829 priority patent/US9418944B2/en
Priority to US15/235,439 priority patent/US9786611B2/en
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Publication of JP6466252B2 publication Critical patent/JP6466252B2/en
Priority to KR1020230000304A priority patent/KR102673994B1/en
Priority to KR1020240072402A priority patent/KR102938134B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/01—Manufacture or treatment
    • H10W40/03—Manufacture or treatment of arrangements for cooling
    • H10W40/037—Assembling together parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

本発明は、半導体パッケージの実装技術に関する。特に、半導体パッケージの製造工程において発生する応力を緩和するための技術に関する。   The present invention relates to a semiconductor package mounting technology. In particular, the present invention relates to a technique for relieving stress generated in a semiconductor package manufacturing process.

従来、支持基板上に、ＩＣチップ等の半導体デバイスを搭載する半導体パッケージ構造が知られている。このような半導体パッケージは、一般的には、支持基板上に、ダイアタッチ材と呼ばれる接着材を介してＩＣチップ等の半導体デバイスを接着し、その半導体デバイスを封止体（封止用樹脂）で覆って保護する構造を採用している。   Conventionally, a semiconductor package structure in which a semiconductor device such as an IC chip is mounted on a support substrate is known. In general, such a semiconductor package is obtained by bonding a semiconductor device such as an IC chip on a support substrate via an adhesive called a die attach material, and sealing the semiconductor device (sealing resin). The structure that covers and protects with is adopted.

半導体パッケージに用いる支持基板としては、プリント基板、セラミックス基板等の様々な基板が用いられている。特に、近年では、金属基板を用いた半導体パッケージの開発が進められている。金属基板を用いた半導体パッケージは、電磁シールド性や熱特性に優れるといった利点を有し、信頼性の高い半導体パッケージとして注目されている。   Various substrates, such as a printed circuit board and a ceramic substrate, are used as a support substrate used for a semiconductor package. In particular, in recent years, development of semiconductor packages using metal substrates has been promoted. A semiconductor package using a metal substrate has an advantage such as excellent electromagnetic shielding properties and thermal characteristics, and has attracted attention as a highly reliable semiconductor package.

しかし、金属と樹脂とでは熱膨張係数（coefficient of thermal expansion ：CTE）に大きな差があるため、金属基板を用いた半導体パッケージの製造工程においては、金属基板と封止体（半導体デバイスを保護するための樹脂）との間における熱膨張係数の差に起因して内部応力が発生し、封止体に反りが発生するという問題が指摘されていた（特許文献１）。   However, since there is a large difference in the coefficient of thermal expansion (CTE) between metal and resin, in the manufacturing process of a semiconductor package using a metal substrate, the metal substrate and the sealing body (protect the semiconductor device). For this reason, a problem has been pointed out that internal stress occurs due to a difference in thermal expansion coefficient between the sealing body and the sealing body (Patent Document 1).

特開２０１０−４０９１１号公報JP 2010-40911 A

本発明は、上述した問題に鑑みてなされたものであり、支持基板と封止体との間に発生する内部応力を低減し、信頼性の高い半導体パッケージを提供することを課題とするものである。   The present invention has been made in view of the above-described problems, and it is an object of the present invention to reduce internal stress generated between a support substrate and a sealing body and to provide a highly reliable semiconductor package. is there.

本発明の一実施形態による半導体パッケージは、支持基板と、前記支持基板の主面に設けられた応力緩和層と、前記応力緩和層の上に配置された半導体デバイスと、前記半導体デバイスを覆い、前記応力緩和層とは異なる絶縁材料からなる封止体と、前記封止体を貫通して前記半導体デバイスと電気的に接続された配線と、前記配線と電気的に接続された外部端子と、を備えることを特徴とする。   A semiconductor package according to an embodiment of the present invention covers a support substrate, a stress relaxation layer provided on a main surface of the support substrate, a semiconductor device disposed on the stress relaxation layer, and the semiconductor device. A sealing body made of an insulating material different from the stress relaxation layer, a wiring that penetrates the sealing body and is electrically connected to the semiconductor device, and an external terminal that is electrically connected to the wiring; It is characterized by providing.

本発明の一実施形態による半導体パッケージは、支持基板と、前記支持基板の主面に設けられた応力緩和層と、前記応力緩和層の上に設けられた導電層と、前記導電層の上に配置された半導体デバイスと、前記半導体デバイスを覆い、前記応力緩和層とは異なる絶縁材料からなる封止体と、前記封止体を貫通して前記半導体デバイスと電気的に接続された配線と、前記配線と電気的に接続された外部端子と、を備えることを特徴とする。   A semiconductor package according to an embodiment of the present invention includes a support substrate, a stress relaxation layer provided on a main surface of the support substrate, a conductive layer provided on the stress relaxation layer, and the conductive layer. A semiconductor device disposed; a sealing body that covers the semiconductor device and is made of an insulating material different from the stress relaxation layer; and a wiring that penetrates the sealing body and is electrically connected to the semiconductor device; And an external terminal electrically connected to the wiring.

本発明の一実施形態による半導体パッケージは、支持基板と、前記支持基板の主面に設けられた応力緩和層と、前記応力緩和層の上に設けられた導電層と、前記導電層に囲まれ、かつ、前記応力緩和層の上に配置された半導体デバイスと、前記半導体デバイスを覆い、前記応力緩和層とは異なる絶縁材料からなる封止体と、前記封止体を貫通して前記半導体デバイスと電気的に接続された配線と、前記配線と電気的に接続された外部端子と、を備えることを特徴とする。   A semiconductor package according to an embodiment of the present invention is surrounded by a support substrate, a stress relaxation layer provided on a main surface of the support substrate, a conductive layer provided on the stress relaxation layer, and the conductive layer. And a semiconductor device disposed on the stress relaxation layer, a sealing body covering the semiconductor device and made of an insulating material different from the stress relaxation layer, and penetrating through the sealing body, the semiconductor device A wiring electrically connected to the wiring, and an external terminal electrically connected to the wiring.

また、本発明の一実施形態による半導体パッケージの製造方法は、支持基板の主面に応力緩和層を形成する工程と、前記応力緩和層の上に、少なくとも１つの半導体デバイスを配置する工程と、前記半導体デバイスを、前記応力緩和層とは異なる材料からなる封止体で覆う工程と、前記封止体を貫通して前記半導体デバイスと電気的に接続された配線を形成する工程と、前記配線と電気的に接続された外部端子を形成する工程と、を備えることを特徴とする。   According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor package, the step of forming a stress relaxation layer on a main surface of a support substrate, the step of disposing at least one semiconductor device on the stress relaxation layer, A step of covering the semiconductor device with a sealing body made of a material different from that of the stress relaxation layer, a step of forming a wiring penetrating the sealing body and electrically connected to the semiconductor device, and the wiring And a step of forming an external terminal electrically connected.

本発明の一実施形態による半導体パッケージの製造方法は、支持基板の主面に応力緩和層を形成する工程と、前記応力緩和層の上に、導電層を形成する工程と、前記導電層の上に、少なくとも１つの半導体デバイスを配置する工程と、前記半導体デバイスを、前記応力緩和層とは異なる材料からなる封止体で覆う工程と、前記封止体を貫通して前記半導体デバイスと電気的に接続された配線を形成する工程と、前記配線と電気的に接続された外部端子を形成する工程と、を備えることを特徴とする。   A method of manufacturing a semiconductor package according to an embodiment of the present invention includes a step of forming a stress relaxation layer on a main surface of a support substrate, a step of forming a conductive layer on the stress relaxation layer, A step of disposing at least one semiconductor device, a step of covering the semiconductor device with a sealing body made of a material different from the stress relieving layer, and an electrical connection with the semiconductor device through the sealing body Forming a wiring connected to the wiring, and forming an external terminal electrically connected to the wiring.

本発明の一実施形態による半導体パッケージの製造方法は、支持基板の主面に応力緩和層を形成する工程と、前記応力緩和層の上に導電層を形成する工程と、前記導電層をエッチングして前記応力緩和層を露出させる工程と、前記応力緩和層を露出させた領域に、少なくとも１つの半導体デバイスを配置する工程と、前記半導体デバイスを、前記応力緩和層とは異なる材料からなる封止体で覆う工程と、前記封止体を貫通して前記半導体デバイスと電気的に接続された配線を形成する工程と、前記配線と電気的に接続された外部端子を形成する工程と、を備えることを特徴とする。   A method of manufacturing a semiconductor package according to an embodiment of the present invention includes a step of forming a stress relaxation layer on a main surface of a support substrate, a step of forming a conductive layer on the stress relaxation layer, and etching the conductive layer. The step of exposing the stress relaxation layer, the step of disposing at least one semiconductor device in the region where the stress relaxation layer is exposed, and the sealing of the semiconductor device from a material different from the stress relaxation layer A step of covering with a body, a step of forming a wiring passing through the sealing body and electrically connected to the semiconductor device, and a step of forming an external terminal electrically connected to the wiring It is characterized by that.

本発明によれば、支持基板と封止体との間に発生する内部応力を低減し、信頼性の高い半導体パッケージを実現することができる。   According to the present invention, the internal stress generated between the support substrate and the sealing body can be reduced, and a highly reliable semiconductor package can be realized.

本発明の第１実施形態に係る半導体パッケージの外観図である。1 is an external view of a semiconductor package according to a first embodiment of the present invention. 本発明の第１実施形態に係る半導体パッケージの断面図である。1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention. 本発明の第１実施形態に係る半導体パッケージの製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor package which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体パッケージの製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor package which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体パッケージの製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor package which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体パッケージの製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor package which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る半導体パッケージの断面図である。It is sectional drawing of the semiconductor package which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る半導体パッケージの断面図である。It is sectional drawing of the semiconductor package which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る半導体パッケージの上面図である。It is a top view of the semiconductor package which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る半導体パッケージの上面図である。It is a top view of the semiconductor package which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る半導体パッケージの断面図である。It is sectional drawing of the semiconductor package which concerns on 3rd Embodiment of this invention. 本発明の第３実施形態に係る半導体パッケージの断面図である。It is sectional drawing of the semiconductor package which concerns on 3rd Embodiment of this invention. 本発明の第３実施形態に係る半導体パッケージの断面図である。It is sectional drawing of the semiconductor package which concerns on 3rd Embodiment of this invention. 本発明の第３実施形態に係る半導体パッケージの上面図である。It is a top view of the semiconductor package which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係る半導体パッケージの断面図である。It is sectional drawing of the semiconductor package which concerns on 4th Embodiment of this invention. 本発明の第４実施形態に係る半導体パッケージの上面図である。It is a top view of the semiconductor package which concerns on 4th Embodiment of this invention. 本発明の第５実施形態に係る半導体パッケージの断面図である。It is sectional drawing of the semiconductor package which concerns on 5th Embodiment of this invention. 本発明の第６実施形態に係る半導体パッケージの上面図である。It is a top view of the semiconductor package which concerns on 6th Embodiment of this invention. 本発明の第６実施形態において、一辺が４００μｍのサイズの開口部を形成した場合における信頼性評価結果である。In 6th Embodiment of this invention, it is a reliability evaluation result in the case of forming the opening part whose size is 400 micrometers on one side. 本発明の第６実施形態において、一辺が５００μｍのサイズの開口部を形成した場合における信頼性評価結果である。In 6th Embodiment of this invention, it is a reliability evaluation result in case an opening part with a side of 500 micrometers is formed. 本発明の第６実施形態において、一辺が６００μｍのサイズの開口部を形成した場合における信頼性評価結果である。In 6th Embodiment of this invention, it is a reliability evaluation result in the case where the opening part of a size whose side is 600 micrometers is formed. 本発明の第６実施形態において、一辺が４００μｍのサイズの開口部を形成した場合における信頼性評価結果である。In 6th Embodiment of this invention, it is a reliability evaluation result in the case of forming the opening part whose size is 400 micrometers on one side.

以下、本発明の一実施形態に係る半導体パッケージについて、図面を参照しながら詳細に説明する。以下に示す実施形態は本発明の実施形態の一例であって、本発明はこれらの実施形態に限定されるものではない。   Hereinafter, a semiconductor package according to an embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are examples of the embodiments of the present invention, and the present invention is not limited to these embodiments.

なお、本実施形態で参照する図面において、同一部分または同様な機能を有する部分には同一の符号または類似の符号（数字の後にＡ、Ｂなどを付しただけの符号）を付し、その繰り返しの説明は省略する場合がある。また、図面の寸法比率は説明の都合上実際の比率とは異なったり、構成の一部が図面から省略されたりする場合がある。   Note that in the drawings referred to in this embodiment, the same portion or a portion having a similar function is denoted by the same reference symbol or a similar reference symbol (a reference symbol simply including A, B, etc. after a number) and repeated. The description of may be omitted. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

また、本明細書中における断面図において「上」とは、支持基板の主面（半導体デバイスを配置する面）を基準とした相対的な位置を指し、支持基板の主面から離れる方向が「上」である。図２以降においては、紙面に向かって上方が「上」となる。また、「上」には、物体の上に接する場合（つまり「ｏｎ」の場合）と、物体の上方に位置する場合（つまり「ｏｖｅｒ」の場合）とが含まれる。   In the cross-sectional views in this specification, “up” refers to a relative position with respect to the main surface of the support substrate (surface on which the semiconductor device is arranged), and the direction away from the main surface of the support substrate is “ "Up". In FIG. 2 and subsequent figures, the upper side is “up” toward the page. In addition, “upper” includes a case where it is in contact with an object (that is, “on”) and a case where it is located above the object (that is, “over”).

（第１実施形態）
＜パッケージの外観＞
図１は、本発明の第１実施形態に係る半導体パッケージ１００の外観図である。なお、図１の手前部分は、内部構成の外観を示すために切断面を図示している。 (First embodiment)
<Appearance of the package>
FIG. 1 is an external view of a semiconductor package 100 according to the first embodiment of the present invention. Note that the front portion of FIG. 1 shows a cut surface in order to show the external appearance of the internal configuration.

図１において、１１は、支持基板であり、１２は支持基板の主面に設けられた応力緩和層である。１３は、ＩＣチップやＬＳＩチップ等の半導体デバイスであり、１４及び１５は、半導体デバイスを保護する封止体（封止用樹脂）である。ここでは図示されないが、封止体１４、１５内には配線が形成され、半導体デバイスの出力端子と、外部端子としてのはんだボール１６とを電気的に接続している。   In FIG. 1, 11 is a support substrate, and 12 is a stress relaxation layer provided on the main surface of the support substrate. Reference numeral 13 denotes a semiconductor device such as an IC chip or an LSI chip, and reference numerals 14 and 15 denote sealing bodies (sealing resins) that protect the semiconductor device. Although not shown here, wiring is formed in the sealing bodies 14 and 15, and the output terminal of the semiconductor device and the solder ball 16 as an external terminal are electrically connected.

このように、本実施形態に係る半導体パッケージ１００は、支持基板１１をそのまま基体として用い、積層された樹脂層（封止体１４、１５）で半導体デバイス１３を外気から保護する構造となっている。   As described above, the semiconductor package 100 according to the present embodiment has a structure in which the support substrate 11 is used as it is as a base and the semiconductor device 13 is protected from the outside air by the laminated resin layers (sealing bodies 14 and 15). .

＜パッケージ構造＞
図２は、図１を用いて説明した半導体パッケージ１００の構造を詳細に説明するための断面図である。１０１は、支持基板であり、ここでは金属基板を用いる。金属基板としては、ステンレス等の鉄合金基板や銅合金基板などの金属基板を用いればよい。勿論、金属基板に限定する必要はなく、用途やコストに応じて、シリコン基板、ガラス基板、セラミックス基板、有機基板などを用いることも可能である。 <Package structure>
FIG. 2 is a cross-sectional view for explaining in detail the structure of the semiconductor package 100 described with reference to FIG. Reference numeral 101 denotes a support substrate, and a metal substrate is used here. As the metal substrate, a metal substrate such as an iron alloy substrate such as stainless steel or a copper alloy substrate may be used. Of course, it is not necessary to limit to a metal substrate, A silicon substrate, a glass substrate, a ceramic substrate, an organic substrate etc. can also be used according to a use and cost.

支持基板１０１上には、応力緩和層１０２が設けられている。応力緩和層１０２は、支持基板１０１と後述する第１封止体１０５との間に生じる応力を緩和するために設けられる絶縁層である。応力緩和層１０２の詳細については後述する。本実施形態に係る半導体パッケージ１００では、膜厚が１０〜２００μｍの熱硬化性樹脂若しくは熱可塑性樹脂（例えばエポキシ系樹脂）を用いる。また、熱伝導率を高めた無機材料や金属フィラーを含有した材料であってもよい。   A stress relaxation layer 102 is provided on the support substrate 101. The stress relaxation layer 102 is an insulating layer provided for relaxing stress generated between the support substrate 101 and a first sealing body 105 described later. Details of the stress relaxation layer 102 will be described later. In the semiconductor package 100 according to the present embodiment, a thermosetting resin or a thermoplastic resin (for example, epoxy resin) having a film thickness of 10 to 200 μm is used. Moreover, the material containing the inorganic material and metal filler which improved thermal conductivity may be sufficient.

応力緩和層１０２の上には、接着材（ダイアタッチ材）１０３を介して半導体デバイス１０４が設けられている。接着材１０３は、支持基板と半導体デバイスとを接着する公知の接着材（ここでは、応力緩和層１０２と半導体デバイス１０４とを接着する接着材）であり、本実施形態では、ダイアタッチフィルムを用いる。   A semiconductor device 104 is provided on the stress relaxation layer 102 via an adhesive (die attach material) 103. The adhesive material 103 is a known adhesive material (here, an adhesive material that bonds the stress relaxation layer 102 and the semiconductor device 104) to bond the support substrate and the semiconductor device. In this embodiment, a die attach film is used. .

なお、本実施形態では、接着材１０３を用いて半導体デバイス１０４を接着しているが、接着材１０３を省略し、応力緩和層１０２上に直接半導体デバイス１０４を設けてもよい。   In the present embodiment, the semiconductor device 104 is bonded using the adhesive 103, but the adhesive 103 may be omitted and the semiconductor device 104 may be provided directly on the stress relaxation layer 102.

半導体デバイス１０４は、ＩＣチップやＬＳＩチップ等の半導体素子である。公知のダイシング工程、ダイボンディング工程を経て、応力緩和層１０２上に配置される。なお、図１では、支持基板１０１上に２つの半導体デバイスを配置する例を示しているが、実際には、支持基板１０１上にさらに多くの半導体デバイスを配置することが可能である。これにより量産性を向上させることができる。例えば、５００ｍｍ×４００ｍｍといった大型基板上に５００個以上の半導体デバイス１０４を配置してもよい。   The semiconductor device 104 is a semiconductor element such as an IC chip or an LSI chip. It arrange | positions on the stress relaxation layer 102 through a known dicing process and a die-bonding process. Note that FIG. 1 shows an example in which two semiconductor devices are arranged on the support substrate 101, but in reality, more semiconductor devices can be arranged on the support substrate 101. Thereby, mass productivity can be improved. For example, 500 or more semiconductor devices 104 may be arranged on a large substrate of 500 mm × 400 mm.

半導体デバイス１０４は、第１封止体１０５によってその上面及び側面を覆われ、外部環境から保護される。第１封止体１０５としては、エポキシ系樹脂を用いることができるが、その他の公知の封止用樹脂を用いてもよい。   The upper surface and side surfaces of the semiconductor device 104 are covered with the first sealing body 105 and are protected from the external environment. As the first sealing body 105, an epoxy resin can be used, but other known sealing resins may be used.

第１封止体１０５の上には第１配線層１０６が形成されている。ここでは、第１配線層１０６は、銅シード層１０６ａと銅配線１０６ｂとで構成されている。勿論、銅に限らず、アルミニウムや銀など、半導体デバイスとの良好な電気的接続が確保できる材料であれば公知の如何なる材料を用いてもよい。   A first wiring layer 106 is formed on the first sealing body 105. Here, the first wiring layer 106 includes a copper seed layer 106a and a copper wiring 106b. Needless to say, not only copper but also any known material such as aluminum or silver may be used as long as it can secure a good electrical connection with a semiconductor device.

第１配線層１０６上には、さらに第２封止体１０７、第２配線層１０８が設けられている。第２封止体１０７は、第１封止体１０５と同じものを用いればよく、ここでの説明は省略する。第２配線層１０８は、第１配線層１０６と同様に、銅シード層１０８ａと銅配線１０８ｂとで構成される。本実施形態では、配線層を第１配線層１０６と第２配線層１０８の二層構造としているが、配線層の数は増減可能であり、必要に応じて適宜決定すればよい。   A second sealing body 107 and a second wiring layer 108 are further provided on the first wiring layer 106. The same thing as the 1st sealing body 105 should just be used for the 2nd sealing body 107, and description here is abbreviate | omitted. Similar to the first wiring layer 106, the second wiring layer 108 includes a copper seed layer 108a and a copper wiring 108b. In the present embodiment, the wiring layer has a two-layer structure of the first wiring layer 106 and the second wiring layer 108. However, the number of wiring layers can be increased or decreased, and may be determined as needed.

第２配線層１０８上には、第３封止体（公知のソルダレジスト）１０９が設けられ、その上には、開口部を介して外部端子１１０としてはんだボールが設けられる。ここでは第３封止体１０９としてソルダレジストを用いるが、第１封止体１０５や第２封止体１０７と同じものを用いてもよいし、外気に直接触れるため、より保護膜としての機能性に優れた材料を用いてもよい。また、はんだボールで構成される外部端子１１０は、２６０℃前後のリフロー処理により形成すればよい。   A third sealing body (known solder resist) 109 is provided on the second wiring layer 108, and solder balls are provided thereon as external terminals 110 via openings. Here, a solder resist is used as the third sealing body 109. However, the same material as the first sealing body 105 and the second sealing body 107 may be used, and since it directly touches the outside air, it functions more as a protective film. A material having excellent properties may be used. Further, the external terminals 110 formed of solder balls may be formed by a reflow process at around 260 ° C.

以上説明した本発明の第１実施形態に係る半導体パッケージ１００は、支持基板１０１の主面に応力緩和層１０２を設けたことにより、支持基板１０１と第１封止体１０５との間の物性値（特に、弾性率や線膨張係数）の差に起因する応力の発生を低減する構造となっている。以下、応力緩和層１０２の物性について詳細に説明する。   In the semiconductor package 100 according to the first embodiment of the present invention described above, the physical property value between the support substrate 101 and the first sealing body 105 is obtained by providing the stress relaxation layer 102 on the main surface of the support substrate 101. In particular, it has a structure that reduces the generation of stress due to the difference in elastic modulus and linear expansion coefficient. Hereinafter, the physical properties of the stress relaxation layer 102 will be described in detail.

本発明の第１実施形態に係る半導体パッケージ１００において、応力緩和層１０２の役割は、支持基板１０１の物性値と第１封止体１０５の物性値との差に起因する内部応力（支持基板１０１と第１封止体１０５の境界面に生じる応力）を低減することである。そのため、応力緩和層１０２としては、支持基板１０１及び第１封止体１０５の弾性率より小さい弾性率を有する絶縁層を用いることが望ましい。   In the semiconductor package 100 according to the first embodiment of the present invention, the role of the stress relaxation layer 102 is the internal stress (support substrate 101) caused by the difference between the physical property value of the support substrate 101 and the physical property value of the first sealing body 105. And stress generated on the boundary surface between the first sealing body 105 and the first sealing body 105. Therefore, as the stress relaxation layer 102, it is desirable to use an insulating layer having an elastic modulus smaller than that of the support substrate 101 and the first sealing body 105.

具体的には、同一温度条件下で、支持基板１０１の弾性率をＡ、応力緩和層１０２の弾性率をＢ、第１封止体１０５の弾性率をＣとした場合、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂが成り立つように、支持基板１０１、応力緩和層１０２及び第１封止体１０５の組み合わせを決定すればよい。   Specifically, when the elastic modulus of the support substrate 101 is A, the elastic modulus of the stress relaxation layer 102 is B, and the elastic modulus of the first sealing body 105 is C under the same temperature condition, A> C> B Alternatively, the combination of the support substrate 101, the stress relaxation layer 102, and the first sealing body 105 may be determined so that C> A> B is satisfied.

このように応力緩和層１０２は、低弾性であることが望ましい。例えば、約２５℃（室温）の温度領域で２Ｇｐａ以下、かつ、１００℃を超える温度領域で１００ＭＰａ以下の弾性率を有することが望ましい。それぞれの温度領域において弾性率に上限を設けた理由は、それら上限値を超えると応力緩和層１０２が硬すぎて応力緩和層としての機能が落ちてしまうからである。   Thus, it is desirable that the stress relaxation layer 102 has low elasticity. For example, it is desirable to have an elastic modulus of 2 Gpa or less in a temperature region of about 25 ° C. (room temperature) and 100 MPa or less in a temperature region exceeding 100 ° C. The reason why the upper limit is provided for the elastic modulus in each temperature region is that when the upper limit value is exceeded, the stress relaxation layer 102 is too hard and the function as the stress relaxation layer is reduced.

すなわち、室温においては、ある程度の硬さがあっても（弾性率が高くても）応力緩和層として十分機能するため、応力緩和層１０２の弾性率は、少なくとも２ＧＰａ以下であればよい。一方、熱硬化性樹脂の硬化温度（１７０℃前後）付近など、１００℃を超える温度領域（例えば１５０℃を超える温度領域）においては、応力緩和層１０２の弾性率を１００ＭＰａ以下とする。そのような高温域で１００ＭＰａを上回ると、応力緩和層としての機能を果たせなくなる虞があるからである。   That is, at room temperature, even if there is a certain degree of hardness (even if the elastic modulus is high), it functions sufficiently as a stress relaxation layer, so the elastic modulus of the stress relaxation layer 102 may be at least 2 GPa or less. On the other hand, in a temperature region exceeding 100 ° C. (for example, a temperature region exceeding 150 ° C.) such as near the curing temperature (around 170 ° C.) of the thermosetting resin, the elastic modulus of the stress relaxation layer 102 is set to 100 MPa or less. This is because if it exceeds 100 MPa in such a high temperature range, the function as a stress relaxation layer may not be achieved.

なお、弾性率が低ければ低いほど応力緩和層としての機能は高くなるが、あまりにも弾性率が低すぎると流動性が極端に高くなり、もはや層としての形状を維持できなくなる虞がある。したがって、本実施形態では、特に弾性率に下限を設けていないが、室温から２６０℃（後述するリフロー温度）の範囲内において形状を維持できる範囲の弾性率であることが条件となる。   The lower the elastic modulus is, the higher the function as a stress relaxation layer is. However, if the elastic modulus is too low, the fluidity becomes extremely high, and the layer shape may no longer be maintained. Therefore, in the present embodiment, there is no particular lower limit on the elastic modulus, but the condition is that the elastic modulus is in a range in which the shape can be maintained within the range of room temperature to 260 ° C. (reflow temperature described later).

また、応力緩和層１０２として、上述した弾性率の関係を満たす絶縁層を用いた場合、結果的に、同一温度条件下で、支持基板１０１の線膨張係数をａ、応力緩和層１０２の線膨張係数をｂ、第１封止体１０５の線膨張係数をｃとすると、ａ≦ｃ＜ｂ（又は、ａ≒ｃ＜ｂ）が成り立つ。   Further, when an insulating layer satisfying the above-described elastic modulus relationship is used as the stress relaxation layer 102, as a result, the linear expansion coefficient of the support substrate 101 is a and the linear expansion of the stress relaxation layer 102 under the same temperature condition. When a coefficient is b and a linear expansion coefficient of the first sealing body 105 is c, a ≦ c <b (or a≈c <b) is established.

一般的に、金属基板の線膨張係数は、２０ｐｐｍ／℃程度であり、封止体の線膨張係数は、数十ｐｐｍ／℃程度である。そのため、本実施形態に係る半導体パッケージ１００では、２００℃以下の温度領域において、線膨張係数が１００〜２００ｐｐｍ／℃、望ましくは１００〜１５０ｐｐｍ／℃である絶縁層を用いる。なお、２００℃以下の温度領域という条件は、半導体パッケージの製造工程における上限温度が２００℃前後であることに因る。少なくとも半導体パッケージの製造工程中において、線膨張係数が前述の範囲に収まることが望ましいという趣旨である。   In general, the linear expansion coefficient of the metal substrate is about 20 ppm / ° C., and the linear expansion coefficient of the sealing body is about several tens of ppm / ° C. Therefore, in the semiconductor package 100 according to the present embodiment, an insulating layer having a linear expansion coefficient of 100 to 200 ppm / ° C., preferably 100 to 150 ppm / ° C. is used in a temperature range of 200 ° C. or lower. The condition of the temperature range of 200 ° C. or lower is due to the upper limit temperature in the semiconductor package manufacturing process being around 200 ° C. This means that it is desirable that the linear expansion coefficient be within the aforementioned range at least during the manufacturing process of the semiconductor package.

さらに、本発明の第１実施形態に係る半導体パッケージ１００では、応力緩和層１０２として、５％重量減少温度が３００℃以上である接着材を用いることが望ましい。この条件は、一般的なリフロー温度が２６０℃前後であるため、リフロー処理を経ても重量減少の少ない絶縁層（すなわち、リフロー耐性のある絶縁層）を用いることにより、半導体パッケージの信頼性の低下を防ぐためである。   Furthermore, in the semiconductor package 100 according to the first embodiment of the present invention, it is desirable to use an adhesive having a 5% weight reduction temperature of 300 ° C. or more as the stress relaxation layer 102. Under this condition, since the general reflow temperature is around 260 ° C., the reliability of the semiconductor package is lowered by using an insulating layer with a small weight loss even after the reflow process (that is, an insulating layer having reflow resistance). Is to prevent.

なお、「重量減少温度」とは、物質の耐熱性を示すために用いられる指標の一つであり、窒素ガスや空気を流しながら、室温から徐々に微量の物質を加熱していき、一定の重量減少が起きる温度で示す。ここでは、５％の重量減少が起きる温度を示している。   “Weight loss temperature” is one of the indicators used to indicate the heat resistance of a substance. While flowing nitrogen gas or air, a slight amount of substance is gradually heated from room temperature to a certain level. Indicated at the temperature at which weight loss occurs. Here, the temperature at which a 5% weight loss occurs is shown.

さらに、応力緩和層１０２として、支持基板（鉄合金や銅合金等の代表的な金属材料で構成される基板）１０１と第１封止体（エポキシ系、フェノール系、またはポリイミド系などの樹脂）１０５の双方に対して、ＪＩＳの碁盤目テープ試験（旧ＪＩＳ Ｋ５４００）において「分類０」に分類される密着力を有する樹脂を用いることが望ましい。これにより、支持基板１０１と第１封止体１０５との間の密着性を高め、さらに第１封止体１０５の膜剥がれを抑制することができる。   Further, as the stress relaxation layer 102, a support substrate (a substrate made of a typical metal material such as an iron alloy or a copper alloy) 101 and a first sealing body (an epoxy resin, a phenol resin, a polyimide resin, or the like) are used. For both of 105, it is desirable to use a resin having an adhesive force classified as “Class 0” in the JIS grid tape test (formerly JIS K5400). Thereby, the adhesiveness between the support substrate 101 and the 1st sealing body 105 can be improved, and also film | membrane peeling of the 1st sealing body 105 can be suppressed.

以上のように、本発明の第１実施形態に係る半導体パッケージ１００では、応力緩和層１０２として、（１）同一温度条件下で、支持基板１０１の弾性率をＡ、応力緩和層１０２の弾性率をＢ、第１封止体１０５の弾性率をＣとした場合、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂが成り立つこと、（２）同一温度条件下で、支持基板１０１の線膨張係数をａ、応力緩和層１０２の線膨張係数をｂ、第１封止体１０５の線膨張係数をｃとした場合、ａ≦ｃ＜ｂ（又は、ａ≒ｃ＜ｂ）が成り立つこと、の少なくともいずれか１つ（望ましくは全て）を満たす絶縁層を用いる点に特徴がある。   As described above, in the semiconductor package 100 according to the first embodiment of the present invention, as the stress relaxation layer 102, (1) the elastic modulus of the support substrate 101 is A and the elastic modulus of the stress relaxation layer 102 under the same temperature condition. Where B> and the elastic modulus of the first sealing body 105 is C, A> C> B or C> A> B is established, and (2) the linear expansion coefficient of the support substrate 101 is set under the same temperature condition. When a is the linear expansion coefficient of the stress relaxation layer 102 and b is the linear expansion coefficient of the first sealing body 105, a ≦ c <b (or a≈c <b) is satisfied. One feature is that an insulating layer satisfying one (preferably all) is used.

これにより、支持基板１０１と第１封止体１０５との間の物性値の差に起因する内部応力の発生を低減し、支持基板１０１や第１封止体１０５に極力反りを発生させないようにすることができ、半導体パッケージとしての信頼性を向上させることができる。   As a result, the generation of internal stress due to the difference in physical property values between the support substrate 101 and the first sealing body 105 is reduced, and the support substrate 101 and the first sealing body 105 are prevented from warping as much as possible. Thus, reliability as a semiconductor package can be improved.

＜製造工程＞
図３〜図６は、本発明の第１実施形態に係る半導体パッケージ１００の製造工程を示す図である。図３（Ａ）において、支持基板１０１上に、応力緩和層１０２を形成する。ここでは、支持基板１０１として鉄合金のステンレス基板（ＳＵＳ基板）を用いるが、ある程度の剛性を備えた基板であれば他の材料で構成される基板であってもよい。例えば、ガラス基板、シリコン基板、セラミックス基板、有機基板であってもよい。 <Manufacturing process>
3 to 6 are views showing manufacturing steps of the semiconductor package 100 according to the first embodiment of the present invention. In FIG. 3A, the stress relaxation layer 102 is formed over the support substrate 101. Here, an iron alloy stainless steel substrate (SUS substrate) is used as the support substrate 101, but a substrate made of other materials may be used as long as the substrate has a certain degree of rigidity. For example, a glass substrate, a silicon substrate, a ceramic substrate, or an organic substrate may be used.

応力緩和層１０２としては、膜厚が１０〜２００μｍの熱硬化性樹脂を用いる。前述のとおり、応力緩和層１０２の物性値は、（１）同一温度条件下で、支持基板１０１の弾性率をＡ、応力緩和層１０２の弾性率をＢ、第１封止体１０５の弾性率をＣとした場合、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂが成り立つこと、（２）同一温度条件下で、支持基板１０１の線膨張係数をａ、応力緩和層１０２の線膨張係数をｂ、第１封止体１０５の線膨張係数をｃとした場合、ａ≦ｃ＜ｂ（又は、ａ≒ｃ＜ｂ）が成り立つこと、の少なくともいずれか１つ（望ましくは全て）を満たす。   As the stress relaxation layer 102, a thermosetting resin having a thickness of 10 to 200 μm is used. As described above, the physical properties of the stress relaxation layer 102 are as follows: (1) Under the same temperature condition, the elastic modulus of the support substrate 101 is A, the elastic modulus of the stress relaxation layer 102 is B, and the elastic modulus of the first sealing body 105. Where C> A> B or C> A> B, and (2) the linear expansion coefficient of the support substrate 101 is a and the linear expansion coefficient of the stress relaxation layer 102 is b under the same temperature condition. When the linear expansion coefficient of the first sealing body 105 is c, at least one (preferably all) of a ≦ c <b (or a≈c <b) is satisfied.

また、応力緩和層１０２として、支持基板１０１と第１封止体１０５の双方に対して、ＪＩＳの碁盤目テープ試験（旧ＪＩＳ Ｋ５４００）において「分類０」に分類される密着力を有する樹脂を用いることが望ましい。   In addition, as the stress relaxation layer 102, a resin having an adhesive force classified as “Class 0” in the JIS grid tape test (former JIS K5400) is applied to both the support substrate 101 and the first sealing body 105. It is desirable to use it.

応力緩和層１０２を形成したら、次に、図３（Ｂ）に示すように、接着材１０３を用いて半導体デバイス１０４を応力緩和層１０２上に接着する。ここでは、接着材１０３として、公知のダイアタッチフィルムを用いる。   After the stress relaxation layer 102 is formed, next, as illustrated in FIG. 3B, the semiconductor device 104 is bonded onto the stress relaxation layer 102 using the adhesive material 103. Here, a known die attach film is used as the adhesive material 103.

具体的には、まずウェハ上に公知の半導体プロセスによって複数の半導体デバイス（半導体素子）を作り込み、ダイアタッチフィルムを半導体デバイスに貼り付けた状態でバックグラインド工程（ウェハの薄厚化）を行う。その後、ダイシング工程により複数の半導体デバイスを個片化し、接着材１０３ごと切り離した複数の半導体デバイス１０４を、応力緩和層１０２上に接着する。このように、支持基板１０１上に複数の半導体デバイス１０４を配置し、パッケージ化した後に個々に切り離すことにより、量産性が大幅に向上する。   Specifically, first, a plurality of semiconductor devices (semiconductor elements) are formed on a wafer by a known semiconductor process, and a back grinding process (thinning of the wafer) is performed in a state where a die attach film is attached to the semiconductor device. Thereafter, a plurality of semiconductor devices are separated into pieces by a dicing process, and the plurality of semiconductor devices 104 separated together with the adhesive material 103 are bonded onto the stress relaxation layer 102. As described above, by arranging a plurality of semiconductor devices 104 on the support substrate 101, packaging them, and separating them individually, mass productivity is greatly improved.

次に、図３（Ｃ）に示すように、半導体デバイス１０４を覆うように第１封止体１０５を形成する。第１封止体１０５としては、エポキシ系樹脂、フェノール系樹脂、およびポリイミド系樹脂のいずれかを用いることができる。熱硬化性樹脂であっても、光硬化性樹脂であってもよい。また、第１封止体１０５は、スクリーン印刷法、スピンコーティング法等、公知の如何なる塗布方法を用いてもよい。   Next, as illustrated in FIG. 3C, the first sealing body 105 is formed so as to cover the semiconductor device 104. As the first sealing body 105, any of an epoxy resin, a phenol resin, and a polyimide resin can be used. It may be a thermosetting resin or a photocurable resin. The first sealing body 105 may use any known coating method such as a screen printing method or a spin coating method.

第１封止体１０５を形成したら、次は、第１封止体１０５に対して公知のフォトリソグラフィ技術または公知のレーザー加工技術によりパターニングを行い、複数の開口部１０５ａを形成する（図４（Ａ））。これら開口部１０５ａは、後に形成する第１配線層１０６と半導体デバイス１０４との電気的接続を確保するためのものである。   After the first sealing body 105 is formed, next, the first sealing body 105 is patterned by a known photolithography technique or a known laser processing technique to form a plurality of openings 105a (FIG. 4 ( A)). These openings 105 a are for ensuring electrical connection between the first wiring layer 106 to be formed later and the semiconductor device 104.

次に、図４（Ｂ）に示すように、第１封止体１０５及び開口部１０５ａを覆うように銅シード層１０６ａを形成する。銅シード層１０６ａは、銅めっき（銅プレーティング）の下地となる銅、ニッケル、ニッケル−クロム（ＮｉＣｒ）、チタンまたはチタン−タングステン（ＴｉＷ）などを主成分とする薄膜であり、例えばスパッタリング法で形成される。   Next, as shown in FIG. 4B, a copper seed layer 106a is formed so as to cover the first sealing body 105 and the opening 105a. The copper seed layer 106a is a thin film mainly composed of copper, nickel, nickel-chromium (NiCr), titanium, titanium-tungsten (TiW), or the like, which is a base for copper plating (copper plating). It is formed.

次に、図４（Ｃ）に示すように、銅シード層１０６ａを形成した後、銅シード層１０６ａを覆うレジストマスク２１を形成する。レジストマスク２１の形成は、公知の方法（例えばスピンコーティング法）を用いてレジスト材料を塗布した後、フォトリソグラフィ技術または公知のレーザー加工技術により開口部２１ａを形成すればよい。この開口部２１ａが、後述する銅配線１０６ｂの形成領域として機能する。   Next, as shown in FIG. 4C, after forming the copper seed layer 106a, a resist mask 21 covering the copper seed layer 106a is formed. The resist mask 21 may be formed by applying a resist material using a known method (for example, spin coating method) and then forming the opening 21a by a photolithography technique or a known laser processing technique. The opening 21a functions as a formation region of a copper wiring 106b described later.

レジストマスク２１に対して開口部２１ａを形成した後、銅プレーティングにより銅シード層１０６ａ上に銅配線１０６ｂを形成する（図５（Ａ））。銅プレーティングは電気めっきを用いても無電解めっきを用いてもよい。また、本実施形態では、銅プレーティングにより銅配線１０６ｂを形成したが、これに限らず、他の方法で銅配線１０６ｂを形成してもよい。例えば、スパッタリング法や蒸着法などを用いてもよい。   After the opening 21a is formed in the resist mask 21, a copper wiring 106b is formed on the copper seed layer 106a by copper plating (FIG. 5A). The copper plating may use electroplating or electroless plating. In this embodiment, the copper wiring 106b is formed by copper plating. However, the present invention is not limited to this, and the copper wiring 106b may be formed by other methods. For example, a sputtering method or a vapor deposition method may be used.

次に、図５（Ｂ）に示すように、レジストマスク２１を除去し、続いて図５（Ｃ）に示すように、銅配線１０６ｂをマスクとして銅シード層１０６ａをエッチング除去する。銅シード層１０６ａのエッチング除去により銅配線１０６ｂが電気的にアイソレートされ、第１配線層１０６として機能する。   Next, as shown in FIG. 5B, the resist mask 21 is removed, and then, as shown in FIG. 5C, the copper seed layer 106a is etched away using the copper wiring 106b as a mask. By removing the copper seed layer 106 a by etching, the copper wiring 106 b is electrically isolated and functions as the first wiring layer 106.

銅配線１０６ｂを形成した後、次に、第２封止体１０７を形成し、フォトリソグラフィ技術または公知のレーザー加工技術により開口部１０７ａを形成する（図６（Ａ））。第２封止体１０７の形成に関しては、第１封止体１０５と同様であるので説明を省略する。開口部１０７ａは、後述する外部端子１１０と第１配線層１０６とを電気的に接続するためのものである。   After forming the copper wiring 106b, next, the second sealing body 107 is formed, and the opening 107a is formed by a photolithography technique or a known laser processing technique (FIG. 6A). Since the formation of the second sealing body 107 is the same as that of the first sealing body 105, the description thereof is omitted. The opening 107a is for electrically connecting an external terminal 110, which will be described later, and the first wiring layer 106.

次に、図６（Ｂ）に示すように、第２封止体１０７に設けられた開口部１０７ａを埋めるように外部端子（ここでは、はんだボール）１１０を形成する。外部端子１１０の形成は、公知の如何なる方法を用いてもよい。ここでは、２６０℃のリフロー処理により行う。また、はんだボールの代わりに、ピン形状の金属導体を形成してもよい。   Next, as illustrated in FIG. 6B, external terminals (in this case, solder balls) 110 are formed so as to fill the openings 107 a provided in the second sealing body 107. Any known method may be used to form the external terminal 110. Here, the reflow process is performed at 260 ° C. Further, a pin-shaped metal conductor may be formed instead of the solder ball.

最後に、図６（Ｃ）に示すように、支持基板１０１ごと公知のダイシング工程により切断して個々の半導体デバイス１０４を切り離す。以上のようにして、複数の半導体パッケージ１００ａ、１００ｂが形成される。   Finally, as shown in FIG. 6C, the individual semiconductor devices 104 are separated by cutting the supporting substrate 101 together with a known dicing process. As described above, a plurality of semiconductor packages 100a and 100b are formed.

なお、図３〜図６に示した製造工程では、第１配線層１０６に外部端子１１０を設けた構成としたが、図２に示したように、外部端子１１０を形成する前に、さらに第２配線層１０８を形成してもよい。   In the manufacturing process shown in FIGS. 3 to 6, the first wiring layer 106 is provided with the external terminal 110. However, as shown in FIG. 2, before the external terminal 110 is formed, the first step is further performed. Two wiring layers 108 may be formed.

以上のような製造工程を経て、図１に示す本発明の半導体パッケージ１００が完成する。本発明によれば、前述した所定の条件を満たす応力緩和層１０２を支持基板１０１上に設けた構成とするため、その後の加熱工程（熱硬化性樹脂の硬化処理やはんだボールのリフロー処理）において、支持基板１０１と第１封止体１０５との間の物性値の差に起因する内部応力の発生を低減し、全体を通じて反りを極力抑えた半導体パッケージの製造工程が実現される。   Through the manufacturing steps as described above, the semiconductor package 100 of the present invention shown in FIG. 1 is completed. According to the present invention, since the stress relaxation layer 102 satisfying the above-mentioned predetermined condition is provided on the support substrate 101, in the subsequent heating process (thermosetting resin curing process or solder ball reflow process). Thus, a semiconductor package manufacturing process in which the generation of internal stress due to the difference in physical property values between the support substrate 101 and the first sealing body 105 is reduced and the warpage is suppressed as much as possible is realized.

（第２実施形態）
図７Ａに、本発明の第２実施形態に係る半導体パッケージ２００の断面図を示す。第２実施形態に係る半導体パッケージ２００は、応力緩和層１０２上に導電層３１を設けた点で、第１実施形態の半導体パッケージ１００と異なる。その他の点は、第１実施形態に係る半導体パッケージ１００と同様である。 (Second Embodiment)
FIG. 7A shows a cross-sectional view of a semiconductor package 200 according to the second embodiment of the present invention. The semiconductor package 200 according to the second embodiment differs from the semiconductor package 100 according to the first embodiment in that the conductive layer 31 is provided on the stress relaxation layer 102. Other points are the same as those of the semiconductor package 100 according to the first embodiment.

図７Ａにおいて、導電層３１は、銅に限らず、アルミニウムや銀といった如何なる材料を用いてもよいが、半導体デバイス１０４からの放熱を効率良く行うためにも熱伝導率の良い金属材料を用いることが望ましい。   In FIG. 7A, the conductive layer 31 is not limited to copper, and any material such as aluminum or silver may be used. However, in order to efficiently dissipate heat from the semiconductor device 104, a metal material having good thermal conductivity is used. Is desirable.

なお、図７Ａに示す半導体パッケージ２００では、半導体デバイス１０４の下方全体からの放熱効果を高めるために、図８Ａに示すように、半導体デバイス１０４の下方に矩形（本実施形態では正方形）の導電層３１を設けている。勿論、導電層３１の形状は矩形に限らず、如何なる形状であってもよい。図８Ａにおいて、点線は半導体デバイス１０４の輪郭を示しており、導電層３１より内側に半導体デバイス１０４を配置している。   In the semiconductor package 200 shown in FIG. 7A, a rectangular (square in this embodiment) conductive layer is formed below the semiconductor device 104 as shown in FIG. 8A in order to enhance the heat dissipation effect from the entire lower portion of the semiconductor device 104. 31 is provided. Of course, the shape of the conductive layer 31 is not limited to a rectangle, and may be any shape. In FIG. 8A, the dotted line indicates the outline of the semiconductor device 104, and the semiconductor device 104 is arranged inside the conductive layer 31.

また、導電層３１は、図７Ａに示すように、上層の銅配線３２、３３と電気的に接続させることができる。ここでは、第２封止体１０７上に形成された第２配線層１０８と電気的に接続させる例を示したが、第１封止体１０５上に形成された第１配線層１０６と電気的に接続させることも可能である。そのため、導電層３１を配線として機能させたり、電気容量（キャパシタ）、抵抗、インダクタ等の負荷素子として機能させたりすることが可能である。   Further, as shown in FIG. 7A, the conductive layer 31 can be electrically connected to the upper copper wirings 32 and 33. Here, an example is shown in which the second wiring layer 108 formed on the second sealing body 107 is electrically connected, but the first wiring layer 106 formed on the first sealing body 105 is electrically connected. It is also possible to connect to. Therefore, the conductive layer 31 can function as a wiring, or can function as a load element such as an electric capacity (capacitor), a resistor, and an inductor.

また、図７Ｂに、本発明の第２実施形態に係る半導体パッケージ２００ａの断面図を示す。図７Ｂに示すように、導電層３１ａを半導体デバイス１０４の輪郭の内側に設けることも可能である。さらに、本実施形態では、導電層３１ａによる段差を接着材１０３ａによって埋め込む構造とし、接着材１０３ａを平坦化層として用いる。この場合、接着材１０３ａとしては、半導体デバイス１０４の接着時に十分な流動性を有する材料を用いることが望ましい。なお、半導体パッケージ２００ａについては、図８Ｂに示すように、導電層３１ａの輪郭は、半導体デバイス１０４の輪郭の内側に位置する。   FIG. 7B shows a cross-sectional view of a semiconductor package 200a according to the second embodiment of the present invention. As shown in FIG. 7B, the conductive layer 31 a can be provided inside the outline of the semiconductor device 104. Further, in the present embodiment, the step due to the conductive layer 31a is embedded with the adhesive 103a, and the adhesive 103a is used as the planarization layer. In this case, it is desirable to use a material having sufficient fluidity when the semiconductor device 104 is bonded as the bonding material 103a. As for the semiconductor package 200a, the outline of the conductive layer 31a is located inside the outline of the semiconductor device 104 as shown in FIG. 8B.

以上のように、第２実施形態の半導体パッケージ２００及び２００ａにおいては、第１実施形態の半導体パッケージ１００が奏する効果に加えて、導電層３１を用いて各半導体デバイス間を接続する配線や各種機能回路を構成する負荷素子を形成できるため、回路設計の自由度が向上とするという効果を奏する。   As described above, in the semiconductor packages 200 and 200a of the second embodiment, in addition to the effects exhibited by the semiconductor package 100 of the first embodiment, wirings and various functions for connecting the semiconductor devices using the conductive layer 31. Since the load element which comprises a circuit can be formed, there exists an effect that the freedom degree of circuit design improves.

さらに、半導体デバイス１０４の下方に熱伝導率のよい金属で構成される導電層を設けることにより、半導体デバイス１０４からの放熱効果を高めることができ、放熱性に優れた信頼性の高い半導体パッケージを実現することができる。   Furthermore, by providing a conductive layer made of a metal with good thermal conductivity below the semiconductor device 104, the heat dissipation effect from the semiconductor device 104 can be enhanced, and a highly reliable semiconductor package with excellent heat dissipation can be obtained. Can be realized.

（第３実施形態）
図９Ａに、本発明の第３実施形態に係る半導体パッケージ３００の断面図を示す。第３実施形態に係る半導体パッケージ３００Ａは、応力緩和層１０２上に設ける導電層にパターニングを施して積極的に配線として用いる点で、第２実施形態の半導体パッケージ２００と異なる。その他の点は、第２実施形態に係る半導体パッケージ２００と同様である。 (Third embodiment)
FIG. 9A shows a cross-sectional view of a semiconductor package 300 according to the third embodiment of the present invention. The semiconductor package 300A according to the third embodiment is different from the semiconductor package 200 according to the second embodiment in that the conductive layer provided on the stress relaxation layer 102 is patterned and actively used as wiring. Other points are the same as those of the semiconductor package 200 according to the second embodiment.

図９Ａにおいて、導電層４１は、銅に限らず、アルミニウムや銀といった如何なる材料を用いてもよい。図中では、複数の導電層４１に分離しているように見えるが、実際には、図１０に示すように相互に電気的に接続され、半導体デバイスに形成された素子間を接続する配線として機能したり、様々な負荷素子として機能したりしている。   In FIG. 9A, the conductive layer 41 is not limited to copper, and any material such as aluminum or silver may be used. In the drawing, it appears that the conductive layers 41 are separated, but in actuality, as shown in FIG. 10, they are electrically connected to each other, and as wirings connecting elements formed in the semiconductor device. It functions or functions as various load elements.

導電層４１で形成可能な負荷素子としては、電気容量（キャパシタ）、抵抗、インダクタなどを挙げることができる。勿論、これ以外にも導電層をパターニングして形成することができる素子であれば如何なる素子を形成してもよい。   Examples of the load element that can be formed by the conductive layer 41 include a capacitance (capacitor), a resistor, and an inductor. Of course, any other element can be formed as long as the element can be formed by patterning the conductive layer.

また、導電層４１は、図９Ａに示すように、上層の銅配線４２、４３と電気的に接続させることができる。ここでは、第２封止体１０７上に形成された第２配線層１０８と電気的に接続させる例を示したが、第１封止体１０５上に形成された第１配線層１０６と電気的に接続させることも可能である。   Further, as shown in FIG. 9A, the conductive layer 41 can be electrically connected to the upper copper wirings 42 and 43. Here, an example is shown in which the second wiring layer 108 formed on the second sealing body 107 is electrically connected, but the first wiring layer 106 formed on the first sealing body 105 is electrically connected. It is also possible to connect to.

また、図９Ｂに、本発明の第３実施形態に係る半導体パッケージ３００ｂの断面図を示す。図９Ｂに示すように、本実施形態では、導電層４１のパターンによる段差を接着材１０３ｂによって埋め込む構造とし、接着材１０３ｂを平坦化層として用いる。この場合、接着材１０３ｂとしては、半導体デバイス１０４の接着時に十分な流動性を有する材料を用いることが望ましい。さらに、図９Ｃに、本発明の第３実施形態に係る半導体パッケージ３００ｃの断面図を示す。図９Ｃに示すように、本実施形態では、導電層４１のパターンによる段差を平坦化層１１１によって埋め込む構造とし、平坦化層１１１の上に接着材１０３を介して半導体デバイス１０４を設ける構造としてもよい。このとき、平坦化層１１１としては、公知の樹脂材料を用いることができる。例えば、応力緩和層１０２と同じ材料を用いてもよいし、第１封止体１０５と同じ材料を用いてもよい。   FIG. 9B shows a cross-sectional view of a semiconductor package 300b according to the third embodiment of the present invention. As shown in FIG. 9B, in the present embodiment, a step due to the pattern of the conductive layer 41 is embedded with an adhesive 103b, and the adhesive 103b is used as a planarizing layer. In this case, it is desirable to use a material having sufficient fluidity when the semiconductor device 104 is bonded as the bonding material 103b. Further, FIG. 9C shows a sectional view of a semiconductor package 300c according to the third embodiment of the present invention. As shown in FIG. 9C, in this embodiment, a step due to the pattern of the conductive layer 41 is embedded in the planarizing layer 111, and the semiconductor device 104 is provided on the planarizing layer 111 with an adhesive 103 interposed therebetween. Good. At this time, a known resin material can be used for the planarization layer 111. For example, the same material as the stress relaxation layer 102 may be used, or the same material as the first sealing body 105 may be used.

以上のように、第３実施形態の半導体パッケージ３００、３００ｂ及び３００ｃにおいては、第２実施形態の半導体パッケージ２００が奏する効果に加えて、導電層４１を用いて各半導体デバイス間を接続する配線や各種機能回路を構成する負荷素子を形成できるため、回路設計の自由度が向上とするという効果を奏する。   As described above, in the semiconductor packages 300, 300b, and 300c of the third embodiment, in addition to the effects exhibited by the semiconductor package 200 of the second embodiment, wirings that connect the respective semiconductor devices using the conductive layer 41, and Since load elements constituting various functional circuits can be formed, there is an effect that the degree of freedom in circuit design is improved.

（第４実施形態）
図１１に、本発明の第４実施形態に係る半導体パッケージ４００の断面図を示す。第４実施形態に係る半導体パッケージ４００は、導電層５１を半導体デバイス１０４の下には設けない点で、第２実施形態の半導体パッケージ２００と異なる。その他の点は、第２実施形態に係る半導体パッケージ２００と同様である。 (Fourth embodiment)
FIG. 11 is a cross-sectional view of a semiconductor package 400 according to the fourth embodiment of the present invention. The semiconductor package 400 according to the fourth embodiment is different from the semiconductor package 200 of the second embodiment in that the conductive layer 51 is not provided under the semiconductor device 104. Other points are the same as those of the semiconductor package 200 according to the second embodiment.

図１１に示した半導体パッケージ４００では、半導体デバイス１０４の下に導電層５１を設けないため、導電層５１の厚さの分だけ半導体デバイス１０４と支持基板１０１との間の距離が縮まることになる。本実施形態の構造とした場合、図１２に示すように、導電層５１は、半導体デバイス１０４より若干大きい面積で一部がくり抜かれた形となっている。このような構造は、例えば、導電層５１を形成した後、導電層５１をエッチングして応力緩和層１０２を露出させ、応力緩和層１０２の露出した部分に半導体デバイス１０４を設ければよい。   In the semiconductor package 400 shown in FIG. 11, since the conductive layer 51 is not provided under the semiconductor device 104, the distance between the semiconductor device 104 and the support substrate 101 is reduced by the thickness of the conductive layer 51. . In the case of the structure of the present embodiment, as shown in FIG. 12, the conductive layer 51 has a shape that is partly cut out with a slightly larger area than the semiconductor device 104. In such a structure, for example, after the conductive layer 51 is formed, the conductive layer 51 is etched to expose the stress relaxation layer 102, and the semiconductor device 104 may be provided in the exposed portion of the stress relaxation layer 102.

この場合においても、導電層５１は、図１１に示すように、上層の銅配線５２、５３と電気的に接続させることができる。また、第２封止体１０７上に形成された第２配線層１０８と電気的に接続させる例を示したが、第１封止体１０５上に形成された第１配線層１０６と電気的に接続させることも可能である。   Also in this case, the conductive layer 51 can be electrically connected to the upper copper wirings 52 and 53 as shown in FIG. Further, although an example in which the second wiring layer 108 formed on the second sealing body 107 is electrically connected is shown, the first wiring layer 106 formed on the first sealing body 105 is electrically connected. It is also possible to connect them.

以上のように、第４実施形態の半導体パッケージ４００においては、第１実施形態及び第２実施形態に係る半導体パッケージが奏する効果に加えて、半導体パッケージ全体の厚さを薄くすることができるという効果を奏する。   As described above, in the semiconductor package 400 of the fourth embodiment, in addition to the effect exhibited by the semiconductor package according to the first embodiment and the second embodiment, the effect that the thickness of the entire semiconductor package can be reduced. Play.

（第５実施形態）
図１３に、本発明の第５実施形態に係る半導体パッケージ５００の断面図を示す。第５実施形態に係る半導体パッケージ５００は、半導体デバイス１０４の下に接着材１０３を設けない点で、第１実施形態の半導体パッケージ１００と異なる。その他の点は、第１実施形態に係る半導体パッケージ１００と同様である。 (Fifth embodiment)
FIG. 13 shows a cross-sectional view of a semiconductor package 500 according to the fifth embodiment of the present invention. A semiconductor package 500 according to the fifth embodiment is different from the semiconductor package 100 according to the first embodiment in that the adhesive 103 is not provided under the semiconductor device 104. Other points are the same as those of the semiconductor package 100 according to the first embodiment.

本発明の第５実施形態に係る半導体パッケージ５００では、応力緩和層１０２上に半導体デバイス１０４を配置するに当たり、接着材１０３を用いずに、直接応力緩和層１０２上に半導体デバイス１０４を接着することができる。具体的には、応力緩和層１０２を構成する樹脂を設けた後、キュア（焼成）工程を行う前に半導体デバイス１０４を搭載し、その状態でキュア工程を行えばよい。   In the semiconductor package 500 according to the fifth embodiment of the present invention, when the semiconductor device 104 is disposed on the stress relaxation layer 102, the semiconductor device 104 is directly bonded on the stress relaxation layer 102 without using the adhesive material 103. Can do. Specifically, the semiconductor device 104 is mounted after the resin constituting the stress relaxation layer 102 is provided and before the curing (firing) step, and the curing step is performed in that state.

これにより、ダイアタッチフィルム等の接着材を用いる必要がないため、第１実施形態に係る半導体パッケージより応力が発生する可能性を低減でき、さらに接着材の分だけ厚みが減るため、半導体パッケージの小型化を図ることができる。   Thereby, since it is not necessary to use an adhesive such as a die attach film, it is possible to reduce the possibility that stress is generated from the semiconductor package according to the first embodiment, and further, the thickness is reduced by the amount of the adhesive. Miniaturization can be achieved.

（第６実施形態）
上述した第１実施形態から第５実施形態に係る半導体パッケージでは、応力緩和層１０２の上に半導体デバイス１０４を設ける構成となるが、その際、半導体デバイス１０４を正確な位置に配置する必要がある。しかし、支持基板１０１上に応力緩和層１０２を設けた場合、支持基板１０１上にアライメントマークを設けたとしても応力緩和層１０２の存在により位置確認が困難となることが予想される。 (Sixth embodiment)
In the semiconductor package according to the first to fifth embodiments described above, the semiconductor device 104 is provided on the stress relaxation layer 102. At this time, the semiconductor device 104 needs to be arranged at an accurate position. . However, when the stress relaxation layer 102 is provided on the support substrate 101, it is expected that the position confirmation becomes difficult due to the presence of the stress relaxation layer 102 even if an alignment mark is provided on the support substrate 101.

そこで、第６実施形態に係る半導体パッケージ６００では、半導体デバイス１０４を応力緩和層１０２上に配置する際に正確なアライメントを可能とするアライメントマークを設けることを特徴としている。   Therefore, the semiconductor package 600 according to the sixth embodiment is characterized by providing an alignment mark that enables accurate alignment when the semiconductor device 104 is disposed on the stress relaxation layer 102.

図１４（Ａ）は、本発明の第６実施形態に係る半導体パッケージ６００の一部を示す上面図であり、図１４（Ｂ）は、図１４（Ａ）に示される点線６２で囲まれた領域の拡大図である。   FIG. 14A is a top view showing a part of a semiconductor package 600 according to the sixth embodiment of the present invention, and FIG. 14B is surrounded by a dotted line 62 shown in FIG. It is an enlarged view of an area.

図１４（Ａ）において、支持基板１０１上には、ほぼ全面に応力緩和層１０２が設けられており、その上に複数の半導体デバイス１０４が配置される。第６実施形態に係る半導体パッケージ６００では、応力緩和層１０２の一部に開口部６３を設け、半導体デバイス１０４を配置する際の基準となるアライメントマークとして用いる点に特徴がある。   In FIG. 14A, a stress relaxation layer 102 is provided on almost the entire surface of a supporting substrate 101, and a plurality of semiconductor devices 104 are disposed thereon. The semiconductor package 600 according to the sixth embodiment is characterized in that an opening 63 is provided in a part of the stress relaxation layer 102 and used as an alignment mark serving as a reference when the semiconductor device 104 is arranged.

開口部６３は、応力緩和層１０２に対してエッチングを施して形成すればよく、レーザーエッチングなど公知のエッチング技術を用いることができる。開口部６３そのものをアライメントマークとして用いることもできるが、開口部６３によって露出する支持基板１０１の表面にハーフエッチング等を用いて溝や穴等を設けてあってもよい。この場合、応力緩和層１０２の形成前に予め支持基板１０１をエッチングして溝や穴を形成してもよいし、開口部６３を形成した後にレーザーエッチング等により支持基板１０１上に溝や穴を形成してもよい。   The opening 63 may be formed by etching the stress relaxation layer 102, and a known etching technique such as laser etching can be used. Although the opening 63 itself can be used as an alignment mark, a groove, a hole, or the like may be provided on the surface of the support substrate 101 exposed by the opening 63 by using half etching or the like. In this case, the support substrate 101 may be etched in advance before the stress relaxation layer 102 is formed, or grooves or holes may be formed on the support substrate 101 by laser etching or the like after the opening 63 is formed. It may be formed.

ただし、開口部６３のサイズを必要以上に大きくしてしまうと、その開口部６３から応力緩和層１０２が剥がれてしまう虞があるため、開口部６３のサイズには一定の制限を設けることが好ましい。   However, if the size of the opening 63 is increased more than necessary, the stress relaxation layer 102 may be peeled off from the opening 63. Therefore, it is preferable to provide a certain restriction on the size of the opening 63. .

本発明者らの実験結果では、開口部６３の一辺が４８０μｍ（または直径４８０μｍ）を超えると応力緩和層１０２の信頼性に影響が出ることが確認された。そのため、開口部６３は、一辺が少なくとも４８０μｍ以下の多角形、又は、直径４８０μｍ以下の円形であることが望ましい。なお、開口部６３のサイズの下限値は、支持基板の材質、開口加工精度やダイアタッチ装置のアライメント性能に応じて多少変動する可能性があるため、適宜決定すればよい。   The experimental results of the present inventors confirmed that the reliability of the stress relaxation layer 102 is affected when one side of the opening 63 exceeds 480 μm (or diameter 480 μm). Therefore, the opening 63 is desirably a polygon having a side of at least 480 μm or a circle having a diameter of 480 μm or less. Note that the lower limit value of the size of the opening 63 may be appropriately determined because it may slightly vary depending on the material of the support substrate, the opening processing accuracy, and the alignment performance of the die attach device.

ここで、本発明者らが行った実験結果について説明する。本発明者らは、図３〜図６を用いて説明したプロセスにより半導体パッケージを作製し、作製した半導体パッケージに対して、ＪＥＤＥＣ規格のレベル２に準拠した湿度信頼性テスト（Ｍｏｉｓｔｕｒｅ Ｒｅｌｉａｂｉｌｉｔｙ Ｔｅｓｔ）を行った。なお、半導体パッケージを作製する際、図１４を用いて説明したように、応力緩和層に形成された開口部をアライメントマークとして利用した。   Here, the experimental results conducted by the present inventors will be described. The present inventors manufactured a semiconductor package by the process described with reference to FIGS. 3 to 6, and performed a humidity reliability test (Moisture Reliability Test) based on the JEDEC standard level 2 on the manufactured semiconductor package. went. When manufacturing the semiconductor package, as described with reference to FIG. 14, the opening formed in the stress relaxation layer was used as an alignment mark.

湿度信頼性テストは、半導体パッケージを温度８５℃、湿度６０％の雰囲気中に１６８時間置いて十分に水分を含ませた後、最高温度２６０℃の標準的なリフロー条件に４回通すことにより行った。テスト後の評価は、超音波映像装置（Ｓｃａｎｎｉｎｇ Ａｃｏｕｓｔｉｃ Ｔｏｍｏｇｒａｐｈ：ＳＡＴ）を用いて行った。   The humidity reliability test is performed by placing the semiconductor package in an atmosphere of 85 ° C. and 60% humidity for 168 hours to sufficiently contain moisture, and then passing it through standard reflow conditions at a maximum temperature of 260 ° C. four times. It was. The evaluation after the test was performed using an ultrasonic imaging device (Scanning Acoustic Tomography: SAT).

図１５は、一辺が４００μｍのサイズの開口部を形成した場合における信頼性評価結果である。図１６は、一辺が５００μｍのサイズの開口部を形成した場合における信頼性評価結果である。図１７は、一辺が６００μｍのサイズの開口部を形成した場合における信頼性評価結果である。   FIG. 15 shows a reliability evaluation result when an opening having a size of 400 μm on one side is formed. FIG. 16 shows a reliability evaluation result when an opening having a size of 500 μm on one side is formed. FIG. 17 shows a reliability evaluation result when an opening having a size of 600 μm on one side is formed.

図１５〜図１７に示されるように、開口部の一辺が５００μｍ及び６００μｍの場合には、半導体パッケージの面内に不具合が発生したが、開口部の一辺が４００μｍの場合には、不具合は発生しなかった。さらに、本発明者らは、より過酷な条件（ＪＥＤＥＣ規格のレベル１に準拠した湿度信頼性テスト）を開口部の一辺が４００μｍである半導体パッケージに対して行い、さらなる実験結果の検証を行った。   As shown in FIGS. 15 to 17, when one side of the opening is 500 μm and 600 μm, a defect occurs in the surface of the semiconductor package, but when one side of the opening is 400 μm, the defect occurs. I did not. Furthermore, the present inventors performed more severe conditions (humidity reliability test in accordance with JEDEC standard level 1) on a semiconductor package having an opening side of 400 μm, and further verified the experimental results. .

図１８は、一辺が４００μｍのサイズの開口部における信頼性評価結果である。この信頼性評価では、半導体パッケージを温度８５℃、湿度８５％の雰囲気中に１６８時間置いて十分に水分を含ませた後、最高温度２６０℃の標準的なリフロー条件に３回通すことにより行った。テスト後の評価は、前述の超音波映像装置を用いて行った。その結果、図１８に示されるように、ＪＥＤＥＣ規格のレベル１に準拠した湿度信頼性テストの前後において半導体パッケージの外観に何ら変化はなく、高い信頼性を確保できていることが確認された。   FIG. 18 shows a reliability evaluation result in an opening having a size of 400 μm on a side. In this reliability evaluation, the semiconductor package was placed in an atmosphere of 85 ° C. and 85% humidity for 168 hours to sufficiently contain moisture, and then passed through standard reflow conditions at a maximum temperature of 260 ° C. three times. It was. Evaluation after the test was performed using the above-described ultrasonic imaging apparatus. As a result, as shown in FIG. 18, it was confirmed that there was no change in the appearance of the semiconductor package before and after the humidity reliability test in conformity with the JEDEC standard level 1 and high reliability was ensured.

これらの結果と、アライメントマークを形成する際の加工精度（σ＝６μｍ）とを考慮すると、５００μｍ±３σの範囲は、不具合が生じる恐れがあると考えられる。つまり、開口部の一辺が４８０μｍ（または直径４８０μｍ）を超えると応力緩和層の信頼性に影響が出ることが確認されたと言える。   Considering these results and the processing accuracy (σ = 6 μm) when forming the alignment mark, it is considered that the range of 500 μm ± 3σ may cause problems. In other words, it can be said that it has been confirmed that if one side of the opening exceeds 480 μm (or diameter 480 μm), the reliability of the stress relaxation layer is affected.

以上のように、第６実施形態に係る半導体パッケージ６００は、半導体デバイス１０４の近傍（例えば、半導体デバイス１０４の角部）に、応力緩和層１０２のエッチングにより形成された開口部６３を有し、その開口部６３を、半導体デバイス１０４を応力緩和層１０２の上に配置する際のアライメントマークとして使用することにより、正確なアライメント作業が可能となり、半導体パッケージの製造工程の歩留りや信頼性の向上を図ることができる。   As described above, the semiconductor package 600 according to the sixth embodiment has the opening 63 formed by etching the stress relaxation layer 102 in the vicinity of the semiconductor device 104 (for example, the corner of the semiconductor device 104). By using the opening 63 as an alignment mark when the semiconductor device 104 is disposed on the stress relaxation layer 102, an accurate alignment operation can be performed, and the yield and reliability of the manufacturing process of the semiconductor package can be improved. Can be planned.

さらに、開口部６３を、一辺が少なくとも４８０μｍ以下の多角形、又は、直径４８０μｍ以下の円形（さらに好ましくは、一辺が少なくとも４００μｍ以下の多角形、又は、直径４００μｍ以下の円形）とすることにより、応力緩和層１０２の膜剥がれを防ぐことができる。これにより、第１実施形態からｓ第５実施形態までの半導体パッケージが備える利点を損なうことなく、半導体パッケージの製造工程の歩留り向上や信頼性向上を図ることができる。   Furthermore, by making the opening 63 a polygon having a side of at least 480 μm or less, or a circle having a diameter of 480 μm or less (more preferably, a polygon having a side of at least 400 μm or less, or a circle having a diameter of 400 μm or less), The peeling of the stress relaxation layer 102 can be prevented. Thereby, it is possible to improve the yield and reliability of the manufacturing process of the semiconductor package without impairing the advantages of the semiconductor package from the first embodiment to the s5th embodiment.

本発明者らは、次の条件でサンプルを作製して信頼性試験を行い、封止体の剥がれ等が発生しないことを確認した。
（実施例１）
支持基板：金属基板（弾性率：１９３ＧＰａ＠２５℃、１００℃）
応力緩和層：変性エポキシ系樹脂（弾性率：５８０ＭＰａ＠２５℃、４ＭＰａ＠１００℃）
封止体：エポキシ系樹脂（弾性率：１６ＧＰａ＠２５℃、１４．７ＧＰａ＠１００℃） The inventors of the present invention produced a sample under the following conditions and conducted a reliability test, and confirmed that peeling of the sealing body did not occur.
Example 1
Support substrate: Metal substrate (elastic modulus: 193 GPa @ 25 ° C, 100 ° C)
Stress relaxation layer: Modified epoxy resin (elastic modulus: 580 MPa @ 25 ° C., 4 MPa @ 100 ° C.)
Sealing body: epoxy resin (elastic modulus: 16 GPa @ 25 ° C., 14.7 GPa @ 100 ° C.)

（実施例２）
支持基板：金属基板（弾性率：１９３ＧＰａ＠２５℃、１００℃）
応力緩和層：変性エポキシ系樹脂（弾性率：１０ＭＰａ＠２５℃、０．６ＭＰａ＠１００℃）
封止体：エポキシ系樹脂（弾性率：１．８ＧＰａ＠２５℃、１ＧＰａ＠１００℃） (Example 2)
Support substrate: Metal substrate (elastic modulus: 193 GPa @ 25 ° C, 100 ° C)
Stress relaxation layer: Modified epoxy resin (elastic modulus: 10 MPa @ 25 ° C., 0.6 MPa @ 100 ° C.)
Sealing body: epoxy resin (elastic modulus: 1.8 GPa @ 25 ° C., 1 GPa @ 100 ° C.)

以上のように、同一温度条件下で、支持基板の弾性率をＡ、応力緩和層の弾性率をＢ、封止体の弾性率をＣとした場合、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂが成り立つように各弾性率の関係を調整することにより、支持基板と封止体との間に発生する内部応力を低減し、信頼性の高い半導体パッケージを実現することができる。   As described above, when the elastic modulus of the support substrate is A, the elastic modulus of the stress relaxation layer is B, and the elastic modulus of the sealing body is C under the same temperature condition, A> C> B or C> A> By adjusting the relationship between the elastic moduli so that B is satisfied, the internal stress generated between the support substrate and the sealing body can be reduced, and a highly reliable semiconductor package can be realized.

１００：半導体パッケージ
１０１：支持基板
１０２：応力緩和層
１０３：接着材
１０４：半導体デバイス
１０５：第１封止体
１０６：第１配線層
１０７：第２封止体
１０８：第２配線層
１０９：第３封止体
１１０：外部端子
１１１：平坦化層 100: semiconductor package 101: support substrate 102: stress relaxation layer 103: adhesive material 104: semiconductor device 105: first sealing body 106: first wiring layer 107: second sealing body 108: second wiring layer 109: first 3 Sealing body 110: External terminal 111: Flattening layer

Claims (18)

支持基板と、
前記支持基板の主面に設けられた応力緩和層と、
前記応力緩和層の上に配置された半導体デバイスと、
前記半導体デバイスを覆い、前記応力緩和層とは異なる絶縁材料からなる封止体と、
前記封止体を貫通して前記半導体デバイスと電気的に接続された配線と、
前記配線と電気的に接続された外部端子と、
を備えることを特徴とする半導体パッケージ。 A support substrate;
A stress relaxation layer provided on the main surface of the support substrate;
A semiconductor device disposed on the stress relaxation layer;
A sealing body covering the semiconductor device and made of an insulating material different from the stress relaxation layer;
A wiring penetrating the sealing body and electrically connected to the semiconductor device;
An external terminal electrically connected to the wiring;
A semiconductor package comprising: 支持基板と、
前記支持基板の主面に設けられた応力緩和層と、
前記応力緩和層の上に設けられた導電層と、
前記導電層の上に配置された半導体デバイスと、
前記半導体デバイスを覆い、前記応力緩和層とは異なる絶縁材料からなる封止体と、
前記封止体を貫通して前記半導体デバイスと電気的に接続された配線と、
前記配線と電気的に接続された外部端子と、
を備えることを特徴とする半導体パッケージ。 A support substrate;
A stress relaxation layer provided on the main surface of the support substrate;
A conductive layer provided on the stress relaxation layer;
A semiconductor device disposed on the conductive layer;
A sealing body covering the semiconductor device and made of an insulating material different from the stress relaxation layer;
A wiring penetrating the sealing body and electrically connected to the semiconductor device;
An external terminal electrically connected to the wiring;
A semiconductor package comprising: 支持基板と、
前記支持基板の主面に設けられた応力緩和層と、
前記応力緩和層の上に設けられた導電層と、
前記導電層に囲まれ、かつ、前記応力緩和層の上に配置された半導体デバイスと、
前記半導体デバイスを覆い、前記応力緩和層とは異なる絶縁材料からなる封止体と、
前記封止体を貫通して前記半導体デバイスと電気的に接続された配線と、
前記配線と電気的に接続された外部端子と、
を備えることを特徴とする半導体パッケージ。 A support substrate;
A stress relaxation layer provided on the main surface of the support substrate;
A conductive layer provided on the stress relaxation layer;
A semiconductor device surrounded by the conductive layer and disposed on the stress relaxation layer;
A sealing body covering the semiconductor device and made of an insulating material different from the stress relaxation layer;
A wiring penetrating the sealing body and electrically connected to the semiconductor device;
An external terminal electrically connected to the wiring;
A semiconductor package comprising: 前記導電層が、少なくともキャパシタ、抵抗及びインダクタのいずれか１つを構成することを特徴とする請求項２又は３に記載の半導体パッケージ。   The semiconductor package according to claim 2, wherein the conductive layer constitutes at least one of a capacitor, a resistor, and an inductor. 同一温度条件下で、前記支持基板の弾性率をＡ、前記応力緩和層の弾性率をＢ、前記封止体の弾性率をＣとするとき、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂの関係が成り立つことを特徴とする請求項１〜４のいずれか１項に記載の半導体パッケージ。   When the elastic modulus of the support substrate is A, the elastic modulus of the stress relaxation layer is B, and the elastic modulus of the sealing body is C under the same temperature condition, A> C> B or C> A> B. The semiconductor package according to claim 1, wherein the relationship is established. 前記応力緩和層の弾性率は、室温で２ＧＰａ以下、かつ、１００℃を超える温度で１００ＭＰａ以下であることを特徴とする請求項５に記載の半導体パッケージ。   6. The semiconductor package according to claim 5, wherein the stress relaxation layer has an elastic modulus of 2 GPa or less at room temperature and 100 MPa or less at a temperature exceeding 100 ° C. 6. 同一温度条件下で、前記支持基板の線膨張係数をａ、前記応力緩和層の線膨張係数をｂ、前記封止体の線膨張係数をｃとするとき、ａ≦ｃ＜ｂ、又は、ａ≒ｃ＜ｂの関係が成り立つことを特徴とする請求項１〜６のいずれか１項に記載の半導体パッケージ。   When the linear expansion coefficient of the support substrate is a, the linear expansion coefficient of the stress relaxation layer is b, and the linear expansion coefficient of the sealing body is c under the same temperature condition, a ≦ c <b or a The semiconductor package according to claim 1, wherein a relationship of ≈c <b is established. 前記半導体デバイスの周囲に、前記応力緩和層に設けられた開口部を有することを特徴とする請求項１〜７のいずれか１項に記載の半導体パッケージ。   The semiconductor package according to claim 1, further comprising an opening provided in the stress relaxation layer around the semiconductor device. 前記開口部は、アライメントマークであり、少なくとも一辺が４８０μｍ以下の多角形、又は、直径４８０μｍ以下の円形であることを特徴とする請求項８に記載の半導体パッケージ。   The semiconductor package according to claim 8, wherein the opening is an alignment mark, and at least one side is a polygon having a diameter of 480 μm or less or a circle having a diameter of 480 μm or less. 支持基板の主面に応力緩和層を形成する工程と、
前記応力緩和層の上に、少なくとも１つの半導体デバイスを配置する工程と、
前記半導体デバイスを、前記応力緩和層とは異なる材料からなる封止体で覆う工程と、
前記封止体を貫通して前記半導体デバイスと電気的に接続された配線を形成する工程と、
前記配線と電気的に接続された外部端子を形成する工程と、
を備えることを特徴とする半導体パッケージの製造方法。 Forming a stress relaxation layer on the main surface of the support substrate;
Disposing at least one semiconductor device on the stress relieving layer;
Covering the semiconductor device with a sealing body made of a material different from the stress relaxation layer;
Forming a wiring penetrating the sealing body and electrically connected to the semiconductor device;
Forming an external terminal electrically connected to the wiring;
A method for manufacturing a semiconductor package, comprising: 支持基板の主面に応力緩和層を形成する工程と、
前記応力緩和層の上に、導電層を形成する工程と、
前記導電層の上に、少なくとも１つの半導体デバイスを配置する工程と、
前記半導体デバイスを、前記応力緩和層とは異なる材料からなる封止体で覆う工程と、
前記封止体を貫通して前記半導体デバイスと電気的に接続された配線を形成する工程と、
前記配線と電気的に接続された外部端子を形成する工程と、
を備えることを特徴とする半導体パッケージの製造方法。 Forming a stress relaxation layer on the main surface of the support substrate;
Forming a conductive layer on the stress relaxation layer;
Disposing at least one semiconductor device on the conductive layer;
Covering the semiconductor device with a sealing body made of a material different from the stress relaxation layer;
Forming a wiring penetrating the sealing body and electrically connected to the semiconductor device;
Forming an external terminal electrically connected to the wiring;
A method for manufacturing a semiconductor package, comprising: 支持基板の主面に応力緩和層を形成する工程と、
前記応力緩和層の上に導電層を形成する工程と、
前記導電層をエッチングして前記応力緩和層を露出させる工程と、
前記応力緩和層を露出させた領域に、少なくとも１つの半導体デバイスを配置する工程と、
前記半導体デバイスを、前記応力緩和層とは異なる材料からなる封止体で覆う工程と、
前記封止体を貫通して前記半導体デバイスと電気的に接続された配線を形成する工程と、
前記配線と電気的に接続された外部端子を形成する工程と、
を備えることを特徴とする半導体パッケージの製造方法。 Forming a stress relaxation layer on the main surface of the support substrate;
Forming a conductive layer on the stress relaxation layer;
Etching the conductive layer to expose the stress relaxation layer;
Disposing at least one semiconductor device in a region where the stress relaxation layer is exposed;
Covering the semiconductor device with a sealing body made of a material different from the stress relaxation layer;
Forming a wiring penetrating the sealing body and electrically connected to the semiconductor device;
Forming an external terminal electrically connected to the wiring;
A method for manufacturing a semiconductor package, comprising: 前記導電層をパターニングして、少なくともキャパシタ、抵抗及びインダクタのいずれか１つを形成することを特徴とする請求項１１又は１２に記載の半導体パッケージの製造方法。   13. The method of manufacturing a semiconductor package according to claim 11, wherein the conductive layer is patterned to form at least one of a capacitor, a resistor, and an inductor. 同一温度条件下で、前記支持基板の弾性率をＡ、前記応力緩和層の弾性率をＢ、前記封止体の弾性率をＣとするとき、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂの関係が成り立つことを特徴とする請求項１０〜１３のいずれか１項に記載の半導体パッケージの製造方法。   When the elastic modulus of the support substrate is A, the elastic modulus of the stress relaxation layer is B, and the elastic modulus of the sealing body is C under the same temperature condition, A> C> B or C> A> B. 14. The method of manufacturing a semiconductor package according to claim 10, wherein the relationship is established. 前記応力緩和層の弾性率は、室温で２ＧＰａ以下、かつ、１００℃を超える温度で１００ＭＰａ以下であることを特徴とする請求項１４に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 14, wherein the elastic modulus of the stress relaxation layer is 2 GPa or less at room temperature and 100 MPa or less at a temperature exceeding 100 ° C. 同一温度条件下で、前記支持基板の線膨張係数をａ、前記応力緩和層の線膨張係数をｂ、前記封止体の線膨張係数をｃとするとき、ａ≦ｃ＜ｂ、又は、ａ≒ｃ＜ｂの関係が成り立つことを特徴とする請求項１０〜１５のいずれか１項に記載の半導体パッケージの製造方法。   When the linear expansion coefficient of the support substrate is a, the linear expansion coefficient of the stress relaxation layer is b, and the linear expansion coefficient of the sealing body is c under the same temperature condition, a ≦ c <b or a The method of manufacturing a semiconductor package according to claim 10, wherein a relationship of ≈c <b is established. 前記半導体デバイスの周囲に、前記応力緩和層をエッチングして開口部を形成することを特徴とする請求項１０〜１６のいずれか１項に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 10, wherein an opening is formed by etching the stress relaxation layer around the semiconductor device. 前記開口部は、アライメントマークであり、少なくとも一辺が４８０μｍ以下の多角形、又は、直径４８０μｍ以下の円形であることを特徴とする請求項１７に記載の半導体パッケージの製造方法。   18. The method of manufacturing a semiconductor package according to claim 17, wherein the opening is an alignment mark and is a polygon having at least one side of 480 μm or less or a circle having a diameter of 480 μm or less.
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