JP6466722B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board used for mounting a semiconductor element such as a semiconductor integrated circuit element.

  A conventional example of a wiring board for mounting a semiconductor element is shown in FIG. The conventional wiring substrate 40 is formed by stacking build-up portions 22 on the upper and lower surfaces of the core substrate 21.

  The core substrate 21 includes a core insulating layer 23, a core conductor layer 24, and a core via conductor 25. The core insulating layers 23 and the core conductor layers 24 are alternately stacked. The core conductor layer 24 is embedded in the surface of the core insulating layer 23. A core via hole 23 a is formed in each core insulating layer 23. The core via conductor 25 fills the inside of the core via hole 23 a of each core insulating layer 23. The core via conductor 25 is in contact with the core conductor layer 24 at its upper and lower ends. Thereby, the core conductor layers 24 positioned above and below the core insulating layer 23 are electrically connected via the core via conductor 25.

  The build-up part 22 includes a build-up insulating layer 26, a build-up conductor layer 27, and a solder resist layer 28. Build-up insulating layers 26 and build-up conductor layers 27 are alternately stacked. Further, a solder resist layer 28 is deposited on the outermost surfaces of the buildup insulating layer 26 and the buildup conductor layer 27. Each build-up insulating layer 26 has a number of build-up via holes 26a. The buildup conductor layer 27 is deposited on the surface of each buildup insulating layer 26 so as to fill the buildup via hole 26a. The buildup conductor layer 27 filled in the buildup via hole 26 a forms a buildup via conductor 29. The buildup via conductors 29 electrically connect the buildup conductor layers 27 positioned above and below the buildup insulating layer 26 or the buildup conductor layer 26 and the core conductor layer 24. The solder resist layer 28 on the upper surface side has an opening 28 a that exposes a part of the buildup conductor layer 27 as the semiconductor element connection pad 30. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 30. The solder resist layer 28 on the lower surface side has an opening 28 b that exposes a part of the buildup conductor layer 27 as the external connection pad 31. The external connection pad 31 is connected to the wiring conductor of the external electric circuit board.

  The semiconductor element connection pads 30 are two-dimensionally arranged in the center of the upper surface of the outermost buildup insulating layer 26 on the upper surface side. The array of the semiconductor element connection pads 30 has a plurality of outer peripheral rows located on the outer peripheral side and a plurality of inner peripheral rows located on the inner side. In addition, the outer peripheral side row | line | column here and the inner peripheral side row | line | column represent the relative positional relationship of both, and do not prescribe | regulate absolute number of rows | lines. For example, when there are five rows including the outer circumferential side row and the inner circumferential side row, two rows on the outer circumferential side may be designated as the outer circumferential side row, and the inner three rows may be designated as the inner circumferential side row. These three rows may be the outer circumferential side row, and the inner two rows may be the inner circumferential side row. In the case of this conventional wiring board 40, two rows on the outer peripheral side are outer peripheral side rows, and an inner row is an inner peripheral side row.

  The external connection pads 31 are two-dimensionally arranged in a region extending from the lower surface center portion and the lower surface outer peripheral portion of the outermost buildup insulating layer 26 on the lower surface side. Note that the central portion and the outer peripheral portion described here represent a relative positional relationship between them, and do not define an absolute position. In the case of this conventional wiring board 40, a region on the outer peripheral side with respect to the inner peripheral side row of the array of the semiconductor element connection pads 30 in the lower surface of the buildup insulating layer 26 on the outermost surface on the lower surface side is defined as a lower peripheral portion. To do.

  The semiconductor element connection pad 30 includes a signal semiconductor element connection pad 30S connected to the signal electrode T of the semiconductor element S and a ground semiconductor element connection connected to the ground electrode T of the semiconductor element S. There are a pad 30G and a power supply semiconductor element connection pad 30P connected to the power supply electrode T of the semiconductor element S. In general, the number of signal semiconductor element connection pads 30S is large in the outer peripheral row in the arrangement of the semiconductor element connection pads 30, and is less in the inner peripheral row. On the contrary, the semiconductor element connection pads 30G for grounding and the semiconductor element connection pads 30P for power supply are arranged in the inner peripheral side row in the array of the semiconductor element connection pads 30 and less in the outer peripheral side row.

  The external connection pad 31 includes a signal external connection pad 31S electrically connected to the signal semiconductor element connection pad 30S and a ground connection electrically connected to the ground semiconductor element connection pad 30G. External connection pads 31G and power supply external connection pads 31P electrically connected to the power supply semiconductor element connection pads 30P. In general, a large number of signal external connection pads 31S are arranged on the outer periphery of the lower surface of the outermost buildup insulating layer 26 on the lower surface side. Conversely, the ground external connection pads 31G and the power supply external connection pads 31P are arranged in the center of the lower surface of the outermost buildup insulating layer 26 on the lower surface side.

  The signal semiconductor element connection pad 30S and the signal external connection pad 31S include a strip-shaped lead wiring 32a formed of a buildup conductor layer 27 provided on the surface of the buildup insulating layer 26 on the upper surface side, The core insulating layer 23 is connected via a strip-shaped lead wiring 32b formed of a core conductor layer 24 provided on the surface. The grounding semiconductor element connection pad 30G and the power supply semiconductor element connection pad 30P and the grounding external connection pad 31G and the power supply external connection pad 31P are formed on the surface of the buildup insulating layer 26 on the upper surface side and the lower surface side. The connection is made via the solid wiring 33 a made of the built-up conductor layer 27 provided and the solid wiring 33 b made of the core conductor 24 provided on the surface of the core insulating layer 23.

  However, according to this conventional wiring board 40, when the power supply or ground solid wiring 33b is provided on the core conductor layer 24 provided with the lead wiring 32b, the current path in the solid wiring 33b is the lead wiring. It may be divided by 32b, or it may be difficult to provide a solid wiring 33b having a sufficient area. For this reason, the semiconductor element S cannot be operated satisfactorily because the semiconductor element S cannot be supplied with sufficient power.

JP2013-30516A

  The problem to be solved by the present invention is to provide a wiring board capable of supplying sufficient power to a semiconductor element to be mounted, and thereby allowing the semiconductor element to be mounted to operate satisfactorily.

In the wiring board according to the present invention, a plurality of core insulating layers each having a core conductor layer embedded on the surface thereof are stacked on the upper and lower sides, and the upper and lower core conductor layers are electrically connected to each other by a core via conductor penetrating each core insulating layer. a core substrate formed by connecting in, the upper and lower surfaces of the core substrate, the buildup conductor layer to the surface through the respective build-up insulating layer with the build-up insulating layer is deposited is a plurality of layers stacked A buildup portion formed by electrically connecting upper and lower buildup conductor layers or the buildup conductor layer and the core conductor layer by a buildup via conductor; A plurality of semiconductor element connection pads made of the build-up conductor layer are arranged at the center of the upper surface. A plurality of external connection pads made up of the buildup wiring conductors in the lowermost layer are arranged in a two-dimensional array having side rows and at the center and outer periphery of the lower surface of the lowermost buildup insulating layer A wiring board that is arranged in a two-dimensional array including a plurality of external connection pads for a plurality of numbers on the outer peripheral portion, wherein the signal semiconductor element connection pads in the outer peripheral row are arranged on the upper surface of the core substrate. The build-up conductor layer extending from the position directly below the signal semiconductor element connection pad of the outer peripheral side row to the position directly above the signal external connection pad of the outer peripheral portion Are connected to the signal external connection pads via the strip-shaped lead wires, and the signal semiconductor element connection pads in the inner circumferential row are formed on the surface of the build-up insulating layer on the lower surface side of the core substrate. Through a strip-shaped lead wire composed of the build-up conductor layer extending from a position immediately below the signal semiconductor element connection pad in the inner peripheral side row to a position directly above the signal external connection pad in the outer peripheral portion. And connected to the signal external connection pad.

  According to the wiring board of the present invention, the signal semiconductor element connection pads in the outer peripheral side row in the arrangement of the semiconductor element connection pads are arranged so that the surface of the buildup insulating layer on the upper surface side than the core substrate Connected to the signal external connection pad through a strip-shaped lead wiring composed of a build-up conductor layer extending from a position immediately below the semiconductor element connection pad to a position directly above the signal external connection pad on the outer periphery. In the array of semiconductor element connection pads, the signal semiconductor element connection pads on the inner peripheral side column are formed on the surface of the buildup insulating layer on the lower surface side of the core substrate by the signal semiconductor element connection pads for signals on the inner peripheral side column. It is connected to the signal external connection pad through a strip-shaped lead wiring composed of a build-up conductor layer extending from a position immediately below to a position directly above the signal external connection pad on the outer periphery. From, in the core conductor layer, the strip of lead wiring for signal is never to divide the current path of a solid-like wiring for ground and power supply. Further, more solid wiring for grounding and power supply can be arranged on the side closer to the semiconductor element. Therefore, it is possible to provide a wiring board that can supply sufficient power to the semiconductor element to be mounted and can thereby operate the mounted semiconductor element satisfactorily.

FIG. 1 is a schematic sectional view showing an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic cross-sectional view of a conventional wiring board.

  Next, an embodiment of the wiring board of the present invention will be described with reference to FIG. As shown in FIG. 1, the wiring substrate 20 of this example is formed by stacking build-up portions 2 on the upper and lower surfaces of the core substrate 1.

  The core substrate 1 includes a core insulating layer 3, a core conductor layer 4, and a core via conductor 5. The core insulating layers 3 and the core conductor layers 4 are alternately stacked. The core conductor layer 4 is embedded in the surface of the core insulating layer 3. Each core insulating layer 3 is provided with a core via hole 3a. The core via conductor 5 fills the inside of the core via hole 3 a of each core insulating layer 3. The core via conductor 5 is in contact with the core conductor layer 4 at its upper and lower ends. Thereby, the core conductor layers 4 positioned above and below the core insulating layer 3 are electrically connected via the core via conductor 5.

  The core insulating layer 3 is formed by impregnating a heat-resistant fiber base material such as glass cloth with a thermosetting resin such as allyl-modified polyphenylene ether resin. The thickness of the core insulating layer 3 is about 100 to 200 μm. As will be described later, the core insulating layer 3 is formed by impregnating an insulating sheet obtained by impregnating a heat-resistant fiber base material with an uncured thermosetting resin composition, forming a core via hole 3a, filling a metal paste, After processing such as transfer, a plurality of such insulating sheets are laminated and thermally integrated to be integrated with each other.

  The core conductor layer 4 is made of a copper foil. The thickness of the core conductor layer 4 is about 5 to 25 μm. The core conductor layer 4 is embedded in the surface of the core insulating layer 3 by a transfer method. The transfer method is an etching process using a subtractive method by etching a copper foil, which is detachably attached to a transfer film made of a heat resistant resin such as polyethylene terephthalate, through an adhesive into a pattern corresponding to the core conductor layer 4. The patterned copper foil is embedded in the surface of the insulating sheet for the core insulating layer 3 by thermocompression bonding using a hot press, and then the transfer film is removed to remove the transfer film from the core conductor on the surface of the core insulating layer 3. This is a method of forming the layer 4.

  The core via conductor 4 is made of, for example, a silver-coated copper powder, a solder powder made of a tin-silver-bismuth-copper alloy, and a conductive material containing a thermosetting resin. The core through conductor 3 is formed by drilling a core via hole 3a having a diameter of about 50 to 200 μm by laser processing in an insulating sheet for the core insulating layer 3 before the core conductor layer 4 is embedded, and the core via hole 3a includes the core via hole 3a. It is formed by filling a metal paste of a conductive material and thermally curing the metal paste together with the insulating sheet for the core insulating layer 3.

  The build-up part 2 includes a build-up insulating layer 6, a build-up conductor layer 7, and a solder resist layer 8. Build-up insulating layers 6 and build-up conductor layers 7 are alternately stacked. Further, a solder resist layer 8 is deposited on the outermost surfaces of the buildup insulating layer 6 and the buildup conductor layer 7. Each buildup insulating layer 6 has a number of buildup via holes 6a. The buildup conductor layer 7 is deposited on the surface of each buildup insulating layer 6 so as to fill the buildup via hole 6a. The buildup conductor layer 7 filled in the buildup via hole 6 a forms a buildup via conductor 9. The buildup via conductors 9 electrically connect the buildup conductor layers 7 positioned above and below the buildup insulating layer 6 or the buildup conductor layer 7 and the core conductor layer 4. The solder resist layer 8 on the upper surface side has an opening 8 a that exposes a part of the buildup conductor layer 7 as the semiconductor element connection pad 10. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 10. The solder resist layer 8 on the lower surface side has an opening 8 b that exposes a part of the buildup conductor layer 7 as the external connection pad 11. The external connection pad 11 is connected to the wiring conductor of the external electric circuit board.

The build-up insulating layer 6 is made of an insulating resin material in which an inorganic insulating filler such as silica is dispersed in a thermosetting resin such as an epoxy resin. The build-up insulating layer 6 has a thickness of about 10 to 50 μm. This build-up insulating layer 6 is made of a resin sheet in which an inorganic insulating filler having an average particle size of 0.1 to 2 μm is dispersed in an uncured thermosetting resin, on the surface of the core substrate 1 or on the underlying build-up insulating layer 6. The thermosetting resin in the resin sheet is then thermoset at 150 to 200 ° C., and finally the build-up via hole 6a is drilled by laser processing.

  The buildup conductor layer 7 is composed of an electroless copper plating layer as a base conductor layer and an electrolytic copper plating layer as a main conductor layer thereon. The thickness of the electroless copper plating layer is 0.1 to 1 μm. The thickness of the electrolytic copper plating layer is about 5 to 25 μm. The buildup conductor layer 7 is formed by a well-known semi-additive method. The buildup via conductor 9 is simultaneously formed as a part of the buildup conductor layer 7 in the buildup via hole 6a.

  The solder resist layer 8 is made of a photosensitive thermosetting resin such as an acrylic-modified epoxy resin. The solder resist layer 8 has a thickness of about 5 to 25 μm on the outermost buildup conductor layer 7. The solder resist layer 8 is formed by applying a photosensitive resin paste on the build-up insulating layer 6 on which the outermost build-up conductor layer 7 is formed, and exposing and developing it to a predetermined pattern, followed by ultraviolet curing and heat. It is formed by curing.

  The semiconductor element connection pads 10 are two-dimensionally arranged in the center of the upper surface of the outermost buildup insulating layer 6 on the upper surface side. The array of the semiconductor element connection pads 10 has a plurality of outer peripheral rows arranged on the outer peripheral side and a plurality of inner peripheral rows arranged on the inner side. In addition, the outer peripheral side row | line | column here and the inner peripheral side row | line | column represent the relative positional relationship of both, and do not prescribe | regulate absolute number of rows | lines. For example, when there are five rows including the outer circumferential side row and the inner circumferential side row, two rows on the outer circumferential side may be designated as the outer circumferential side row, and the inner three rows may be designated as the inner circumferential side row. These three rows may be the outer circumferential side row, and the inner two rows may be the inner circumferential side row. In the case of the wiring board 20 of this example, two rows on the outer peripheral side are outer peripheral side rows, and an inner row is an inner peripheral side row. The semiconductor element connection pad 10 has a circular shape with a diameter of about 50 to 100 μm. The arrangement pitch of the semiconductor element connection pads 10 is about 100 to 200 μm.

  The external connection pads 11 are arranged two-dimensionally in a region extending from the lower surface center portion and the lower surface outer peripheral portion of the outermost buildup insulating layer 16 on the lower surface side. Note that the central portion and the outer peripheral portion described here represent a relative positional relationship between them, and do not define an absolute position. In the case of the wiring board 20 of the present example, a region on the outer peripheral side with respect to the inner peripheral side row in the array of the semiconductor element connection pads 10 in the lower surface of the uppermost buildup insulating layer 6 on the lower surface side is the lower outer periphery. Part. The external connection pad 11 has a circular shape with a diameter of about 300 to 1000 μm. The arrangement pitch of the external connection pads 11 is about 1000 to 2000 μm.

  The semiconductor element connection pad 10 includes a signal semiconductor element connection pad 10S connected to the signal electrode T of the semiconductor element S and a ground semiconductor element connection connected to the ground electrode T of the semiconductor element S. There are a pad 10G and a power supply semiconductor element connection pad 10P connected to a power supply electrode T of the semiconductor element S. In general, the signal semiconductor element connection pads 10S are arranged more in the outer peripheral side row in the arrangement of the semiconductor element connection pads 10 and fewer in the inner peripheral side row. On the contrary, the semiconductor element connection pads 10G for grounding and the semiconductor element connection pads 10P for power supply are arranged in the inner peripheral side row in the array of the semiconductor element connection pads 10 and in the outer peripheral side row fewer.

  The external connection pad 11 includes a signal external connection pad 11S electrically connected to the signal semiconductor element connection pad 10S, and a ground connection electrically connected to the ground semiconductor element connection pad 10G. External connection pads 11G and power supply external connection pads 11P electrically connected to the power supply semiconductor element connection pads 10P. Generally, a large number of signal external connection pads 11S are arranged on the outer peripheral portion of the lower surface of the outermost buildup insulating layer 6 on the lower surface side. On the contrary, the ground external connection pads 11G and the power supply external connection pads 11P are arranged in the center of the lower surface of the outermost buildup insulating layer 6 on the lower surface side.

  The signal semiconductor element connection pad 10 </ b> S and the signal external connection pad 11 </ b> S are a strip-like lead wiring 12 a made up of the buildup conductor layer 7 provided on the surface of the buildup insulating layer 6 on the upper surface side of the core substrate 1. Alternatively, they are connected via a strip-like lead wiring 12 b made of a build-up conductor layer 7 provided on the surface of the build-up insulating layer 6 on the lower surface side of the core substrate 1. The width of the lead wires 12a and 12b is about 10 to 25 μm. The semiconductor element connection pad 10G for grounding or the semiconductor element connection pad 10P for power supply and the external connection pad 11G for grounding or the external connection pad 11P for power supply are built-up insulation on the upper surface side and the lower surface side from the core substrate 1. They are connected via a solid wiring 13 a made up of the build-up conductor layer 7 provided on the surface of the layer 6 and a solid wiring 13 b made up of the core conductor 4 provided on the surface of the core insulating layer 3 of the core substrate 1. .

  In the wiring board 20 of the present example, the signal semiconductor element connection pads 10S in the outer peripheral row in the arrangement of the semiconductor element connection pads 10 are formed on the surface of the buildup insulating layer 6 on the upper surface side of the core substrate 1. The signal external connection pad 11S through a strip-shaped lead wiring 12b extending from a position immediately below the signal semiconductor element connection pad 10S in the outer peripheral side row to a position directly above the signal external connection pad 11S in the outer peripheral portion. The signal semiconductor element connection pads 10S in the inner circumferential side row in the arrangement of the semiconductor element connection pads 10 are arranged on the inner circumferential side row of the surface of the buildup insulating layer 6 on the lower surface side of the core substrate 1. The signal outside is provided via a strip-like lead wiring 12b extending from a position immediately below the signal semiconductor element connection pad 10S to a position immediately above the signal external connection pad 11S in the outer peripheral portion. It is connected to the connection pad 11S. Therefore, in the core conductor layer 4, the strip-shaped lead wires 12a and 12b for signals do not divide the current path of the solid wire 13b for grounding or power supply. Further, the solid wiring 13b for grounding and power supply in the core substrate 1 can be arranged more on the side closer to the semiconductor element S. Therefore, it is possible to provide the wiring board 20 that can supply sufficient power to the semiconductor element S to be mounted, and can thereby operate the mounted semiconductor element S satisfactorily.

1 ... Core substrate 2 ... Build-up part 3 ... Core insulation layer 4 ... Core conductor layer 5 ... · Core via conductor 6 ··········· Build-up insulating layer 7 ······· Build-up conductor layer 9 ············ Build-up via conductor 10 ······· Semiconductor element connection Pad 10S... Signal semiconductor element connection pad 11... External connection pad 11S... Signal external connection pads 12a, 12b.

Claims (1)

A core formed by stacking a plurality of core insulating layers with a core conductor layer embedded on the surface and electrically connecting the upper and lower core conductor layers with core via conductors penetrating each core insulating layer A plurality of buildup insulating layers each having a buildup conductor layer deposited on the surface thereof are laminated on the upper and lower surfaces of the substrate and the upper and lower surfaces of the core substrate by buildup via conductors penetrating each buildup insulating layer. A build-up portion formed by electrically connecting the build-up conductor layers to each other or the build-up conductor layer and the core conductor layer; A two-dimensional structure in which a plurality of semiconductor element connection pads made of an up conductor layer each have a plurality of outer peripheral rows and a plurality of inner peripheral rows each including a signal semiconductor element connection pad A plurality of external connection pads made up of the buildup wiring conductor in the lowermost layer at the center and outer peripheral portion of the lowermost layer of the buildup insulating layer at the lowermost layer, and a plurality of signals on the outer peripheral portion. A wiring board that is arranged in a two-dimensional array including external connection pads for use, wherein the signal semiconductor element connection pads in the outer peripheral side row are formed on the build-up insulating layer on the upper surface side of the core substrate. A strip-like lead wiring comprising the build-up conductor layer extending from a position immediately below the signal semiconductor element connection pad in the outer peripheral side row to a position immediately above the signal external connection pad in the outer peripheral portion Connected to the signal external connection pads, and the signal semiconductor element connection pads in the inner circumferential side row are formed on the surface of the buildup insulating layer on the lower surface side of the core substrate. Via a strip-shaped lead wiring composed of the build-up conductor layer extending from a position immediately below the signal semiconductor element connection pad in the inner peripheral side row to a position immediately above the signal external connection pad in the outer peripheral portion. A wiring board connected to an external connection pad for signals.

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