JP6492607B2 - Semiconductor integrated circuit and electronic equipment - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, an electronic device, and the like.

Some circuits are known to generate significant noise at specific times. For example,
In a motor driver circuit or the like that drives an H bridge circuit, large noise is generated at the timing of switching the operation mode of the H bridge circuit. This noise can cause malfunction of other circuits.

On the other hand, Patent Document 1 discloses a noise removal device that removes short-period noise using a delay circuit.

JP 2011-66547 A

In the case of removing noise using a delay circuit, it is necessary to design a longer delay time with a margin. However, since it becomes a dead time during which the correct signal cannot be obtained during the delay time, it is not preferable that the delay time is too long.

The present invention has been made in view of the above problems, and according to some aspects of the present invention, it is possible to suppress the influence of noise generated at a specific timing, a semiconductor integrated circuit, an electronic device, and the like Can be provided.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following aspects or application examples.

[Application Example 1]
The semiconductor integrated circuit according to this application example is
Based on a timing signal based on the timing of mode switching, a detection unit that detects the pulse width of the signal under test and outputs pulse width information that is information of the pulse width;
A storage unit for storing the pulse width information;
A signal generator for generating a test enable signal based on the timing signal and the pulse width information;
A semiconductor integrated circuit.

According to this application example, since the test enable signal is generated based on the detected pulse width, it is possible to remove the signal based on noise generated at a specific timing while optimizing the dead time. Therefore, a semiconductor integrated circuit that can suppress the influence of noise generated at a specific timing can be realized.

[Application Example 2]
In the above-described semiconductor integrated circuit,
The detection unit may output the pulse width information based on the first timing signal.

The pulse width of noise generated at a specific timing often does not change significantly between the first timing and the second and subsequent timings. Therefore, according to this application example, by using the pulse width information based on the first timing signal even after the second time, it is possible to realize a semiconductor integrated circuit capable of suppressing the influence of noise generated at a specific timing while reducing processing. it can.

[Application Example 3]
In the above-described semiconductor integrated circuit,
The detector is
Including a plurality of delay circuits connected in series;
The pulse width may be detected based on the output signal of each delay circuit.

  According to this application example, the pulse width can be detected with a simple configuration.

[Application Example 4]
In the above-described semiconductor integrated circuit,
A noise cancellation unit that removes noise from the signal under test and outputs the signal based on the pulse width information may be further included.

According to this application example, since the pulse width of the noise generated at a specific timing is known, the noise generated at the specific timing can be easily removed.

[Application Example 5]
In the above-described semiconductor integrated circuit,
The mode may be an operation mode of the H-bridge circuit.

Noise is likely to occur at the switching timing of the operation mode of the H-bridge circuit. According to this application example, it is possible to realize a semiconductor integrated circuit capable of suppressing the influence of noise generated at the switching timing of the operation mode of the H-bridge circuit.

[Application Example 6]
The electronic device according to this application example is
An electronic apparatus including the semiconductor integrated circuit described above.

According to this application example, since the semiconductor integrated circuit capable of suppressing the influence of noise generated at a specific timing is included, an electronic apparatus capable of suppressing the influence of noise generated at the specific timing can be realized.

1 is a circuit diagram showing a circuit configuration example of a semiconductor integrated circuit 1 according to the present embodiment. 1 is a circuit diagram illustrating a specific circuit configuration example of a main part of a semiconductor integrated circuit 1 according to the present embodiment. 3 is a flowchart showing an operation example of the semiconductor integrated circuit 1 according to the present embodiment. 6 is a table showing operation modes of the H-bridge circuit 80. 4 is a table showing a correspondence relationship between a value of a register 21, a pulse width (relative value), and an output signal of a selector 41. It is a functional block diagram which shows the structural example of the electronic device 300 with which the semiconductor integrated circuit 1 of this embodiment was applied.

DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The drawings used are for convenience of explanation. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Circuit Configuration Example FIG. 1 is a circuit diagram showing a circuit configuration example of a semiconductor integrated circuit 1 according to the present embodiment. FIG. 2 is a circuit diagram showing a specific circuit configuration example of a main part of the semiconductor integrated circuit 1 according to the present embodiment.
In the example shown in FIG. 1, the semiconductor integrated circuit 1 is configured as a motor drive circuit that drives a motor 100.

As will be described later, the semiconductor integrated circuit 1 according to the present embodiment detects the pulse width of the signal under test based on the timing signal based on the mode switching timing, and the pulse width information which is information of the pulse width. Are included, a storage unit 20 that stores pulse width information, and a signal generation unit 30 that generates a test enable signal DE based on the timing signal and the pulse width information. Further, the semiconductor integrated circuit 1 may further include a noise canceling unit 40 that removes noise from the test signal and outputs the signal based on the pulse width information.

In the example shown in FIG. 1, the semiconductor integrated circuit 1 includes a test signal generation unit 50, a control unit 60, a pre-driver 70, an H bridge circuit 80, and a DAC (digital to analog converter) 91.
And a comparator 92.

The H bridge circuit 80 drives an external motor 100 (DC motor) based on a PWM (pulse width modulation) signal from the control unit 60. Specifically, the H bridge circuit 80 includes transistors Q1 to Q4 (switch elements) configured as an H bridge and diodes D1 to D4. For example, the transistors Q1 and Q2 are P-type, and the transistors Q3 and Q4 are N-type. Alternatively, the transistors Q1 to Q4 may all be N-type.

The transistor Q1 and the diode D1 are connected to the node of the power supply voltage VCC, the motor 1
00 is provided between the terminal OUT1 to which one end of 00 is connected. The transistor Q2 and the diode D2 have a terminal O to which the node of the power supply voltage VCC and the other end of the motor 100 are connected.
It is provided between UT2. Transistor Q3 and diode D3 are connected to terminal OUT1.
And a terminal RNF connected to the other end of the sense resistor R to which one end is supplied with a ground voltage. Transistor Q4 and diode D4 are connected to terminal OUT2 and terminal RNF.
Connected between.

The DAC 91 generates a reference voltage VR for detecting the chopping current. DAC9
1 generates a reference voltage VR based on the input data from the terminal IN, and the comparator 92
Output to.

The comparator 92 detects whether or not the current for driving the motor 100 has reached the chopping current (threshold value). Specifically, the comparator 92 compares the voltage VS at one end of the sense resistor R input via the terminal RNF with the reference voltage VR. And the voltage VS
Detects that the reference voltage VR has been reached, the controller 6 uses the detected signal as the output signal CO.
Output to 0.

The control unit 60 controls the chopping operation of the H bridge circuit 80. The chopping operation is an operation of controlling the charge / decay of the current that drives the motor 100 by the on / off control of the transistors Q1 to Q4. Specifically, the control unit 60 controls the pulse width of the PWM signal based on the output signal CO from the comparator 92 so that the current for driving the motor 100 is constant. Then, from the PWM signal, transistor Q1
~ Q4 on / off control signal is generated, and the generated on / off control signal is pre-driver 7
Output to 0. Further, the control unit 60 outputs a timing signal based on the operation mode switching timing of the H-bridge circuit 80 to the detection unit 10 and the signal generation unit 30. In addition, the control unit 60 outputs a reset signal to the storage unit 20.

The pre-driver 70 includes buffer amplifiers 71 to 74. Buffer amplifier 71-
74 buffers the on / off control signal from the controller 60, and drives the drive signal G
1 to G4 are output to the gates of the transistors Q1 to Q4.

The test signal generator 50 generates a test signal. In the present embodiment, the test signal generator 50 monitors the power supply voltage VCC, and outputs a high-level signal as the test signal when the power supply voltage VCC is equal to or lower than a reference value. If the reference value is exceeded, a low level signal is output.

The detection unit 10 detects the pulse width of the signal under test based on the timing signal output by the control unit 60, and outputs pulse width information that is information on the pulse width. In this embodiment,
As illustrated in FIG. 2, the detection unit 10 includes delay circuits 11 to 14 and NAND gates 15 to 18.
And a decoder 19.

As shown in FIG. 2, the delay circuits 11 to 14 are connected in series. Delay circuit 11
Is input with a test signal. The NAND gate 15 outputs the NAND of the signal under test and the output signal of the delay circuit 11 to the decoder 19. The NAND gate 16 outputs a NAND of the signal under test and the output signal of the delay circuit 12 to the decoder 19. NAND gate 17
Outputs the NAND of the signal under test and the output signal of the delay circuit 13 to the decoder 19. N
The AND gate 18 converts the NAND of the signal under test and the output signal of the delay circuit 14 into the decoder 1.
Output to 9.

The decoder 19 detects the pulse width of the signal under test based on the output signals of the NAND gates 15-18. The decoder 19 outputs pulse width information, which is information on the detected pulse width, to the storage unit 20. A specific example of the operation of the decoder 19 will be described in detail in the section “2. Operation Example”.

The storage unit 20 stores pulse width information output from the decoder 19 of the detection unit 10. FIG.
In the example shown in FIG. 2, the storage unit 20 includes a register 21.

The signal generation unit 30 generates the test enable signal DE based on the timing signal output from the control unit 60 and the pulse width information stored in the storage unit 20. The signal generation unit 30 outputs a low level signal during the dead time as the test enable signal DE, and generates a high level signal during normal times. The signal generator 30 sends the test enable signal DE to the controller 60.
Output to.

The noise canceling unit 40 removes noise from the test signal based on the pulse width information stored in the storage unit 20 and outputs the result. In the example shown in FIG. 2, the noise canceling unit 4
0 includes a selector 41. The selector 41 includes a NAND gate 15
Output signal S1, NAND gate 16 output signal S2, and NAND gate 17 output signal S.
3 and one of the output signals S4 of the NAND gate 18 are selected and output to the control unit 60 as a reset signal. A specific example of the operation of the selector 41 will be described in detail in “2. Operation example”.

2. Operation Example FIG. 3 is a flowchart showing an operation example of the semiconductor integrated circuit 1 according to the present embodiment.

First, the control unit 60 performs predetermined mode switching (step S100). The mode in the present embodiment is an operation mode of the H bridge circuit 80. The control unit 60 outputs the timing signal to the decoder 19 and the signal generation unit 30 of the detection unit 10.

FIG. 4 is a table showing operation modes of the H bridge circuit 80. FIG. 4 shows the on / off states of the transistors Q1 to Q4 in each operation mode. As shown in FIG. 4, in the present embodiment, the H bridge circuit 80 has a charge mode, an operation mode,
There are three modes, a fast decay mode and a slow decay mode. In the present embodiment, the control unit 60 switches the operation mode of the H bridge circuit 80 in the order of the charge mode, the first decay mode, and the slow decay mode.

In the charge mode, the transistor Q1 and the transistor Q4 are on, and the transistor Q2 and the transistor Q3 are off. In the first decay mode, the transistor Q1 and the transistor Q4 are in the off state, and the transistor Q2 and the transistor Q3 are in the on state. In the slow decay mode, the transistors Q1 and Q2 are off, and the transistors Q3 and Q4 are on.

In ideal operation, no through current through transistor Q1 and transistor Q3 or through current through transistor Q2 and transistor Q4 should flow. However, in an actual circuit, a through current may flow due to a shift in the switching timing of the on / off operations of the transistors Q1 to Q4. In particular, a large through current may flow at the timing of switching to the charge mode and the timing of switching to the fast decay mode. When a through current flows, a large current temporarily flows through the sense resistor R, and thus erroneous control may be performed. For this reason, in this embodiment, the possibility of erroneous control is reduced by lowering the test enable signal DE and providing a dead time by the process described later.

Also, if a large through current flows, the power supply potential and ground potential will fluctuate.
There is a possibility that a large amount of noise enters the signal under test and an erroneous pulse due to the noise occurs. Therefore, in the present embodiment, the possibility of erroneous verification is reduced by removing erroneous pulses by a process described later.

In the present embodiment, the predetermined mode switching is switching to the charge mode and switching to the first decay mode in which a large through current may flow. Further, since the first mode switching is switching to the charge mode, the predetermined mode switching in step S100 is switching to the charge mode.

Returning to FIG. 3, after step S100, the control unit 60 resets the register 21 (step S102).

FIG. 5 is a table showing a correspondence relationship between the value of the register 21, the pulse width (relative value), and the output signal of the selector 41. When the register 21 is reset, the value becomes 00 and becomes pulse width information indicating 4 as the pulse width. In the present embodiment, a pulse width of 4 indicates the longest pulse width. Therefore, the signal generation unit 30 outputs the test enable signal DE having the longest dead time to the control unit 60.

After step S102, the detection unit 10 detects the pulse width of the test signal (step S104). After step S104, the detection unit 10 sets a value in the register 21 (
Step S106).

As shown in FIG. 2, the NAND of the signal under test and the output signals of the delay circuits 11 to 14 is output to the decoder 19. The decoder 19 outputs 00 as a value to the register 21 when a pulse is not output from the NAND gate 18 and a pulse is output from the NAND gates 15 to 17. When no pulse is output from the NAND gates 17 to 18 and a pulse is output from the NAND gates 15 to 16, the decoder 19 registers 21.
01 is output as the value. When no pulse is output from the NAND gates 16 to 18 and a pulse is output from the NAND gate 15, the decoder 19 outputs 10 as a value to the register 21. When no pulse is output from the NAND gates 15 to 18, the decoder 19 outputs 11 as a value to the register 21.

A pulse width of 4 in FIG. 5 corresponds to the delay time of the delay circuits 11 to 14. The pulse width 3 in FIG. 5 corresponds to the delay time of the delay circuits 11 to 13. A pulse width of 2 in FIG. 5 corresponds to the delay time of the delay circuits 11 to 12. The pulse width 1 in FIG. 5 corresponds to the delay time of the delay circuit 11. Accordingly, the decoder 19 selects the shortest delay time that can remove the pulse of the signal under test from the four delay times.

After step S106, the signal generation unit 30 reads the value of the register 21 based on the timing signal output from the control unit 60 (step S108). After step S108, the signal generation unit 30 causes the test enable signal DE to fall for a predetermined time based on the value of the register 21 (pulse width information) (step S110). The control unit 60 performs control while ignoring the output signal CO of the comparator 92 during a period in which the test enable signal DE is at a low level.

According to the present embodiment, the test enable signal DE is generated based on the detected pulse width, so that the dead time is optimized and a specific timing (in this embodiment, the operation mode of the H bridge circuit 80 is switched). Signals based on noise generated at (timing) can be removed. Therefore, the semiconductor integrated circuit 1 that can suppress the influence of noise generated at a specific timing can be realized.

After step S110, the control unit 60 performs predetermined mode switching (step S11).
2). After step S112, step S108 and subsequent steps are repeated.

As shown in FIG. 3, in the present embodiment, the detection unit 10 outputs pulse width information based on the first timing signal, and does not output pulse width information for the second and subsequent timing signals. The signal generator 30 generates the test enable signal DE based on the value already written in the register 21.

The pulse width of noise generated at a specific timing often does not change significantly between the first timing and the second and subsequent timings. Therefore, according to this embodiment, the first
By using the pulse width information based on this timing signal even after the second time, it is possible to realize the semiconductor integrated circuit 1 capable of suppressing the influence of noise generated at a specific timing while reducing the processing.

In the present embodiment, as shown in FIG. 2, the detection unit 10 includes a plurality of delay circuits 11 to 14 connected in series, and the pulse width is based on the output signals of the respective delay circuits 11 to 14. Is detected. Therefore, according to the present embodiment, the pulse width can be detected with a simple configuration.

As shown in FIGS. 2 and 5, the selector 41 of the noise cancellation unit 40 selects one of the output signals S <b> 1 to S <b> 4 based on the value (pulse width information) stored in the register 21. To the control unit 60. In the present embodiment, the output signals S1 to S4 are signals that do not include an erroneous pulse that occurs at a specific timing (mode switching timing).
One of them is selected and output to the control unit 60.

According to this embodiment, since the pulse width of noise generated at a specific timing is known, noise generated at a specific timing can be easily removed.

FIG. 6 is a functional block diagram illustrating a configuration example of an electronic device 300 to which the semiconductor integrated circuit 1 of the present embodiment is applied. The electronic apparatus 300 according to the present embodiment includes a semiconductor integrated circuit 1 that functions as a motor driving device, a processing unit 310, a storage unit 320, an operation unit 330, an input / output unit 340,
A bus 350 that connects these components and the motor 100 are included. Hereinafter, the electronic device 300 will be described by taking a printer that controls the head and paper feed by motor drive as an example, but the present invention is not limited to this and can be applied to various electronic devices.

The input / output unit 340 is, for example, a USB (Universal Serial Bus) connector or a wireless LAN (Lo
cal Area Network), and image data and document data are input. The input data is stored in the storage unit 320 which is an internal storage device such as a DRAM (Dynamic Random Access Memory). When the printing instruction is received by the operation unit 330, the processing unit 310 starts a printing operation of data stored in the storage unit 320. Processing unit 31
0 sends an instruction to the semiconductor integrated circuit 1 in accordance with the print layout of the data, and the semiconductor integrated circuit 1 rotates the motor 100 based on the instruction to move the head and feed the paper.

According to this embodiment, since the semiconductor integrated circuit 1 that can suppress the influence of noise generated at a specific timing is included, the electronic apparatus 300 that can suppress the influence of noise generated at a specific timing can be realized.

As mentioned above, although this embodiment or the modification was demonstrated, this invention is not limited to these this embodiment or a modification, It is possible to implement in a various aspect in the range which does not deviate from the summary.

The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. In addition, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 10 ... Detection part, 11-14 ... Delay circuit, 15-18 ... NAND gate, 19 ... Decoder, 20 ... Memory | storage part, 21 ... Register, 30 ... Signal generation part, 40 ... Noise cancellation part, 41 ... selector, 50 ... tested signal generation unit, 60 ... control unit, 70 ...
Pre-driver, 71-74 ... Buffer amplifier, 80 ... H bridge circuit, 91 ... DAC
, 92: Comparator, 100 ... Motor, 300 ... Electronic device, 310 ... Processing unit, 32
DESCRIPTION OF SYMBOLS 0 ... Memory | storage part, 330 ... Operation part, 340 ... Input / output part, D1-D4 ... Diode, Q1-Q4
... Transistor, R ... Sense resistor, IN, OUT1, OUT2, RNF ... Terminal

Claims (6)

A test signal generator for generating a test signal;
Based on the timing signal based on the switching timing of the mode, and the detected pulse width of the test signal, detecting unit for outputting a pulse width information that is information of the pulse width,
A storage unit for storing the pulse width information;
A signal generator for generating a test enable signal based on the timing signal and the pulse width information;
Said test enable signal is input, Outputs the timing signal to the detection unit and the signal generating unit controller,
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
The detection unit is a semiconductor integrated circuit that outputs the pulse width information based on the first timing signal. The semiconductor integrated circuit according to claim 1 or 2,
The detector is
Including a plurality of delay circuits connected in series;
A semiconductor integrated circuit that detects the pulse width based on an output signal of each delay circuit. The semiconductor integrated circuit according to any one of claims 1 to 3,
A semiconductor integrated circuit, further comprising: a noise cancellation unit that removes noise from the signal under test based on the pulse width information and outputs the noise. The semiconductor integrated circuit according to any one of claims 1 to 4,
The mode is a semiconductor integrated circuit which is an operation mode of the H-bridge circuit.   An electronic apparatus comprising the semiconductor integrated circuit according to claim 1.

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