JP6515901B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus provided with an inrush current prevention circuit.

  A power supply device of an image processing apparatus such as a printer may be provided with an inrush current prevention circuit. For example, an inrush current preventing circuit using a switching element or a field effect transistor as an inrush current preventing element is known (see, for example, Patent Documents 1 and 2).

JP, 2000-224845, A Unexamined-Japanese-Patent No. 2004-129419

  By the way, in the field effect transistor, a current flows between the source and the drain when the gate voltage is larger than the gate threshold voltage. In the field effect transistor, the smaller the difference between the gate voltage and the gate threshold voltage, the larger the channel resistance between the source and the drain.

  On the other hand, in the rush current prevention circuit using a field effect transistor, the gate voltage of the field effect transistor may be reduced when an input / output abnormality of a mounted part or the like occurs. Therefore, in the rush current prevention circuit, when the gate voltage is reduced, the field effect transistor generates heat, and problems such as open defects and burnout may occur in the field effect transistor and the mounted components therearound.

  An object of the present invention is to provide an image processing apparatus capable of suppressing the occurrence of a failure in an inrush current prevention circuit caused by heat generation of a field effect transistor.

  An image processing apparatus according to one aspect of the present invention includes a power supply unit having a rush current prevention circuit, and a control unit that controls the power supply unit. The inrush current prevention circuit includes a field effect transistor and a switching element. The switching element selects the drive state and the drive stop state of the field effect transistor by switching between the on state and the off state. The control unit includes a gate voltage detection unit, an abnormality determination unit, and a switching control unit. The gate voltage detection unit detects a gate voltage of the field effect transistor. The abnormality determination unit determines whether the gate voltage of the field effect transistor detected by the gate voltage detection unit is a predetermined abnormal low voltage. The switching control unit switches the ON state and the OFF state of the switching element when the abnormality determining unit determines that the gate voltage of the field effect transistor is the abnormal low voltage, and the field effect transistor is turned on. Drive stop state.

  According to the present invention, there is provided an image processing apparatus capable of suppressing the occurrence of a defect in the inrush current prevention circuit caused by the heat generation of a field effect transistor.

FIG. 1 is a cross-sectional view schematically showing an image forming apparatus according to the first embodiment of the present invention. FIG. 2 is a block diagram showing the system configuration of the image forming apparatus shown in FIG. FIG. 3 is a circuit diagram showing a power supply unit of the image forming apparatus together with a control unit. FIG. 4 is a flowchart showing an example of the FET monitoring process executed by the control unit of the image forming apparatus. FIG. 5 is a flow chart showing an example of the temperature monitoring process in the FET monitoring process shown in FIG. FIG. 6 is a flow chart showing an example of the normal temperature process in the temperature monitoring process shown in FIG. FIG. 7 is a flowchart showing an example of the warning process in the temperature monitoring process shown in FIG. FIG. 8 is a flowchart showing an example of the image processing stop processing in the temperature monitoring processing shown in FIG. FIG. 9 is a flowchart showing an example of the voltage monitoring process in the FET monitoring process shown in FIG. FIG. 10 is a flow chart showing an example of normal voltage processing in the voltage monitoring processing shown in FIG. FIG. 11 is a flowchart showing an example of the warning process in the voltage monitoring process shown in FIG. FIG. 12 is a circuit diagram showing a power supply unit and a control unit in the second embodiment of the present invention. FIG. 13 is a flowchart showing an example of FET monitoring processing by the control unit shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings for understanding of the present invention. The following embodiments are merely specific examples of the present invention, and do not limit the technical scope of the present invention.

First Embodiment
First, the configuration of an image forming apparatus 10 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3.

  As shown in FIGS. 1 and 2, the image forming apparatus 10 includes an ADF 1, an image reading unit 2, an image forming unit 3, a sheet feeding unit 4, a control unit 5, an operation display unit 6, and a power supply unit 7. The image forming apparatus 10 is a multifunction peripheral having a scan function for reading image data from a document, a print function for forming an image based on image data, and a plurality of functions such as a facsimile function and a copy function. Here, the image forming apparatus 10 is an example of the image processing apparatus in the present invention. The present invention is also applicable to an image processing apparatus such as a scanner apparatus, a printer apparatus, a facsimile apparatus, and a copier.

  The ADF 1 is an automatic document conveying device that includes a document setting unit, a plurality of conveyance rollers, a document pressing unit, and a discharge unit, and conveys a document read by the image reading unit 2. The image reading unit 2 includes a document table, a light source, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device), and can read image data from a document.

  The image forming unit 3 can execute an image forming process for forming an image by electrophotography based on image data read by the image reading unit 2 or image data input from an information processing apparatus such as an external personal computer. It is. Specifically, as shown in FIG. 1, the image forming unit 3 includes the photosensitive drum 31, the charger 32, the light scanning unit 33, the developing unit 34, the transfer roller 35, the cleaning device 36, the fixing unit 37, and the discharge unit. A paper tray 38 is provided.

  The sheet feeding unit 4 includes a sheet feeding cassette and a plurality of conveyance rollers, and supplies the sheet stored in the sheet feeding cassette to the image forming unit 3. The sheet is a paper, a coated paper, a postcard, an envelope, an OHP sheet, or the like.

  In the image forming unit 3, an image is formed on the sheet supplied from the sheet feeding unit 4 in the following procedure, and the sheet after the image formation is discharged to the sheet discharge tray 38.

  First, the surface of the photosensitive drum 31 is uniformly charged to a predetermined potential by the charger 32. Next, the light scanning unit 33 irradiates the surface of the photosensitive drum 31 with light based on the image data. Thereby, an electrostatic latent image corresponding to the image data is formed on the surface of the photosensitive drum 31. Then, the electrostatic latent image on the photosensitive drum 31 is developed by the developing unit 34 as a toner image. Note that toner is replenished to the developing device 34 from a toner container 34A that is attachable to and detachable from the image forming unit 3.

  Subsequently, the toner image formed on the photosensitive drum 31 is transferred onto the sheet by the transfer roller 35. Thereafter, when the sheet passes between the fixing roller and the pressure roller of the fixing section 37, the toner image transferred to the sheet is heated and fused and fixed by the fixing roller. The toner remaining on the surface of the photosensitive drum 31 is removed by the cleaning device 36.

  The control unit 5 includes control devices such as a CPU, a ROM, a RAM, and an EEPROM (registered trademark) (not shown). The CPU is a processor that executes various arithmetic processing. The ROM is a non-volatile storage unit in which information such as a control program for causing the CPU to execute various processes is stored in advance. The RAM is a volatile storage unit, and the EEPROM is a non-volatile storage unit. The RAM and the EEPROM are used as temporary storage memories of various processes executed by the CPU. In the control unit 5, the CPU executes various control programs stored in advance in the ROM. As a result, the image forming apparatus 10 is integrally controlled by the control unit 5. The control unit 5 may be configured by an electronic circuit such as an integrated circuit, or may be an engine control unit provided separately from the main control unit that generally controls the image forming apparatus 10. Good. The details of the control unit 5 will be described later.

  The operation display unit 6 is a display unit such as a liquid crystal display that displays various types of information in response to a control instruction from the control unit 5, and operation keys or a touch panel that inputs various types of information to the control unit 5 in accordance with user operations. Etc. has an operation unit.

  The display unit of the operation display unit 6 notifies that a field effect transistor 81 (see FIG. 3) described later is in the alert state, that it is in an abnormal state, that image processing can not be performed, and the like. The display unit of the operation display unit 6 is an example of the notification unit of the present invention. A speaker (not shown) is mentioned as another example of the alerting | reporting part of this invention. When the notification unit is a speaker, for example, by outputting a warning sound or message determined in advance corresponding to the notification content, the field effect transistor 81 can be in a warning temperature state, an abnormal state, and image processing can be performed. It is informed that there is nothing.

  As shown in FIG. 3, the power supply unit 7 includes a first power supply 71, a second power supply 72, a third power supply 73, an interlock switch 74, and an inrush current prevention circuit 8. The power supply unit 7 is removable independently of the image forming apparatus 10, for example.

  The first power supply 71 is an AC-DC converter that converts an AC voltage (for example, 100 V) supplied from the external power supply 91 into a DC voltage of a predetermined first voltage V1 (for example, 24 V) and outputs it. The first power supply 71 supplies a first voltage V1 to the load 92, the third power supply 73, and an inrush current prevention circuit 8 described later. The load 92 is, for example, an ADF 1, an image reading unit 2, an image forming unit 3, a sheet feeding unit 4, a control unit 5, and an operation display unit 6.

  The second power supply 72 is a DC power supply that supplies a second voltage V2 to the inrush current prevention circuit 8 described later. The second power source 72 is connected to the inrush current prevention circuit 8 and the load 93.

  The third power supply 73 is a DC-DC converter that converts the DC voltage supplied from the first power supply 71 into a predetermined third voltage V3 and outputs the voltage. The third power supply 73 supplies the third voltage V3 to the gate of the field effect transistor 81 of the rush current prevention circuit 8 described later. Further, the third power supply 73 can change and output the third voltage V3 within a specific range (for example, 0 V to 5 V) according to a voltage designation signal from a third power control unit 52 of the control unit 5 described later.

  The interlock switch 74 selects the on state and the off state by the selection processing unit 51 of the control unit 5 described later, and brings the power supply unit 7 into the driving state or the stop state according to the on state and the off state. On the other hand, the inrush current prevention circuit 8 is selected from the drive state or the stop state according to the drive state or the stop state of the power supply unit 7. The interlock switch 74 is turned on when a field effect transistor 81 described later is in a normal state or an alert state, and causes the power supply unit 7 and the rush current prevention circuit 8 to be in a driving state. The interlock switch 74 is an example of the circuit drive selection unit of the present invention. In addition, the circuit drive selection unit of the present invention may be a switching unit provided separately from the interlock switch 74.

  The inrush current prevention circuit 8 includes a field effect transistor 81, a thermistor 82 and a switching element 83. The inrush current prevention circuit 8 prevents the current exceeding the rated current from being supplied to the first power supply 71 and the interlock switch 74.

  The field effect transistor 81 is a P-channel MOSFET (metal oxide semiconductor field effect transistor). The field effect transistor 81 may be an N channel MOSFET.

The field effect transistor 81 has a gate connected to the output line 731 of the third power supply 73, a source connected to the output line 711 of the first power supply 71, and a drain connected to the output line 721 of the second power supply 72. When the gate voltage _VGS is equal to or higher than the gate threshold voltage, the field effect transistor 81 conducts between the source and the drain, and is driven. On the other hand, the field effect transistor 81 is cut off between the source and the drain because the gate voltage V _GS is less than the gate threshold voltage, and is brought to a stop state.

  Then, in the rush current prevention circuit 8, the output current of the first power supply 71 can be shunted to the load 93 when the field effect transistor 81 is driven. Thereby, the field effect transistor 81 prevents the rush current from flowing into the first power supply 71 and the interlock switch 74, and a current exceeding the rated current is supplied to the first power supply 71 and the interlock switch 74. To prevent.

  The thermistor 82 is disposed in the vicinity of the field effect transistor 81, and measures the temperature T of the field effect transistor 81. The thermistor 82 is connected to the output line 711 of the first power supply 71 and the ground (GND). Therefore, the first voltage V1 is applied to the thermistor 82. The thermistor 82 is connected to the temperature detection unit 53 of the control unit 5, and outputs a voltage according to the temperature T of the field effect transistor 81 to the temperature detection unit 53. Note that, instead of the thermistor 82, a temperature sensor such as a thermocouple may be used.

  The switching element 83 selects the state in which the third voltage V3 is applied to the gate of the field effect transistor 81 and the state in which the third voltage V3 is not applied by switching between the on state and the off state. That is, the switching element 83 selects the drive state and the drive stop state of the field effect transistor 81 by switching between the on state and the off state. The switching element 83 is turned on when the field effect transistor 81 is in the normal state or the alert state, and the field effect transistor 81 is driven. On the other hand, the switching element 83 is turned off when the field effect transistor 81 is in an abnormal state, and the driving of the field effect transistor 81 is stopped.

In the present embodiment, the switching element 83 is an N-channel MOSFET. The switching element 83 in this case has a gate connected to the switching control unit 54, a source connected to the output line 731 of the third power supply 73, and a drain connected to the gate of the field effect transistor 81. When the gate voltage V _GS is equal to or higher than the gate threshold voltage, the switching element 83 is in an on state in which the source and the drain are in conduction. Thereby, the third voltage V3 is applied to the gate of the field effect transistor 81. On the other hand, when the gate voltage V _GS is less than the gate threshold voltage, the source and the drain are cut off to be in the off state. Thus, the third voltage V3 is not applied to the gate of the field effect transistor 81.

  The switching element 83 includes other types of transistors generally used as switching elements such as P-channel MOSFET, PNP transistor, and NPN transistor.

The control unit 5 also controls the power supply unit 7. Specifically, the control unit 5 monitors the temperature T and the gate voltage V _GS of the field effect transistor 81, and controls the third power supply 73, the interlock switch 74, and the switching element 83. The control unit 5 includes a selection processing unit 51, a third power control unit 52, a temperature detection unit 53, a switching control unit 54, a gate voltage detection unit 55, an abnormality determination unit 56, and a notification control unit 57.

  The selection processing unit 51 controls switching of the interlock switch 74 between the on state and the off state, and selects the state where the first voltage V1 is input to the inrush current prevention circuit 8 and the state where the first voltage V1 is not input. Specifically, the selection processing unit 51 turns on the interlock switch 74 to input the first voltage V1 to the inrush current prevention circuit 8 and causes the inrush current prevention circuit 8 to be in a drive state. On the other hand, the selection processing unit 51 turns off the interlock switch 74 so that the first voltage V1 is not input to the inrush current prevention circuit 8, and the inrush current prevention circuit 8 is in the stop state.

The third power supply control unit 52 adjusts the third voltage V3 output from the third power supply 73 according to the temperature T and / or the gate voltage V _GS of the switching element 83. The third power-supply control unit 52, by adjusting the third voltage V3 output from the third power source 73, to adjust the gate voltage V _GS of the switching element 83. For example, if the abnormality determination unit 56 determines that the temperature T or the gate voltage V _GS of the field effect transistor 81 is a warning temperature or a warning voltage, the third power control unit 52 normalizes the temperature T of the field effect transistor 81 The third voltage V3 is adjusted to maintain the temperature. That is, since the gate voltage V _GS is increased by decreasing the third voltage V 3 in the field effect transistor 81, the channel resistance is reduced. Thereby, the temperature rise in the field effect transistor 81 is suppressed.

The adjustment of the third voltage V3 by the third power supply control unit 52 is performed, for example, by the difference between the temperature T detected by the temperature detection unit 53 or the gate voltage V _GS detected by the gate voltage detection unit 55 and the reference temperature or reference voltage. It is done based on the value. The reference temperature or reference voltage is, for example, a first threshold temperature Tth1 or a first threshold voltage Vth1. Then, the third power supply control unit 52 generates a voltage designation signal corresponding to the control amount determined according to the difference value, for example, and transmits the voltage specification signal to the third power supply 73.

The voltage designation signal is also generated when the power supply unit 7 is started. The voltage designation signal at the time of activation of the power supply unit 7 is the same every time of activation. Therefore, the third voltage V3 at the start of the power supply unit 7 is the same at each start. In the following, it referred to a third voltage V3 during startup and initial set value V3 _0.

The third power supply control unit 52 is also output from the third power supply 73 even when the abnormality determination unit 56 determines that the temperature T or the gate voltage V _GS of the field effect transistor 81 is the normal temperature or the normal voltage. Third voltage V3 may be adjusted. Thereby, the temperature T or the gate voltage V _GS of the field effect transistor 81 is controlled to the optimum range.

  The temperature detection unit 53 detects the temperature T of the field effect transistor 81 based on the voltage output from the thermistor 82.

The switching control unit 54 controls switching of the switching element 83 between the on state and the off state. The switching control unit 54 adjusts the voltage applied to the gate of the switching element 83, and brings the switching element 83 into the ON state by setting the gate voltage V _GS to the gate threshold voltage or more. As a result, the third voltage V3 is applied to the gate of the field effect transistor 81, and the field effect transistor 81 is turned on with conduction between the source and the drain. On the other hand, the switching control unit 54 does not apply a voltage to the gate of the switching element 83, thereby making the gate voltage V _GS less than the gate threshold voltage and turning on the switching element 83. As a result, the third voltage V3 is not applied to the gate of the field effect transistor 81, and the field effect transistor 81 is turned off with the source and drain cut off.

The gate voltage detection unit 55 detects the gate voltage V _GS of the field effect transistor 81. Here, the gate voltage V _GS conducts between the source and the drain as having a value exceeding the gate threshold voltage. On the other hand, the smaller the difference between the gate voltage V _GS and the gate threshold voltage, the larger the channel resistance between the source and the drain of the field effect transistor 81, and the larger the difference tends to increase as it approaches zero. Therefore, if the difference is small, the temperature T of the field effect transistor 81 is increased, which may cause the inrush current prevention circuit 8 to be unrecoverable. Therefore, the gate voltage detection unit 55 detects the gate voltage V _GS of the field effect transistor 81 to grasp the temperature rise of the field effect transistor 81 and the possibility thereof.

Here, in the P-channel MOSFET, the channel resistance value is reduced by applying a voltage smaller than the source by a predetermined value or more to the gate, and a current flows from the source to the drain. Therefore, when a P-channel MOSFET is used as the field effect transistor 81, the gate voltage V _GS is a value obtained by subtracting the third voltage V3 applied to the gate from the first voltage V1 applied to the source. Therefore, the gate voltage detection unit 55 detects the gate voltage V _GS as the difference (V1−V3) between the first voltage V1 and the third voltage V3.

  The abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is a normal temperature, a warning temperature, or an abnormal overheat temperature. Specifically, whether the abnormality determination unit 56 is the normal temperature by comparing the temperature T of the field effect transistor 81 detected by the temperature detection unit 53 with the first threshold temperature Tth1 and the second threshold temperature Tth2. It is determined whether or not it is a warning temperature, and whether it is an abnormal overheat temperature.

  Here, the abnormal overheat temperature is determined in advance as a temperature that can cause the inrush current prevention circuit 8 to have a serious abnormality. The serious abnormality means, for example, that a defect such as an open defect or burnout occurs in the field effect transistor 81 and the mounting components in the periphery thereof. The normal temperature is determined in advance as a temperature at which the field effect transistor 81 and the components mounted therearound can be driven without any problem. The normal temperature is determined, for example, by the specification of the field effect transistor 81. The warning temperature is defined as the temperature between the normal temperature and the abnormal overheat temperature.

  Then, the first threshold temperature Tth1 is set as a boundary temperature between the normal temperature and the warning temperature, and the second threshold temperature Tth2 is set as a boundary temperature between the warning temperature and the abnormal overheat temperature. Therefore, when the temperature detected by the temperature detection unit 53 is less than the first threshold temperature Tth1, the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is a normal temperature. When the temperature detected by the temperature detection unit 53 is equal to or higher than the first threshold temperature Tth1 and lower than the second threshold temperature Tth2, the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is the alert temperature. When the temperature detected by the temperature detection unit 53 is equal to or higher than the second threshold temperature Tth2, the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is an abnormal overheat temperature.

Further, the abnormality determination unit 56 determines which of the normal voltage, the warning voltage, and the abnormal low voltage the gate voltage V _GS of the field effect transistor 81 is. Specifically, the abnormality determination unit 56 compares the gate voltage V _GS of the field effect transistor 81 detected by the gate voltage detection unit 55 with the first threshold voltage Vth1 and the second threshold voltage Vth2 to obtain a normal voltage. It is determined whether or not it is a warning voltage, and whether it is an abnormal low voltage.

  Here, the abnormal low voltage has a large channel resistance between the source and the drain, and is determined in advance as a voltage at which the temperature T of the field effect transistor 81 can become an abnormal overheat temperature. The normal voltage is predetermined as a voltage with which the channel resistance between the source and the drain is small and which can drive the field effect transistor 81 without any problem. The warning voltage is defined as the temperature between the normal voltage and the abnormal low voltage.

The first threshold voltage Vth1 is set as a boundary voltage between the normal voltage and the warning voltage, and the second threshold voltage Vth2 is set as a boundary voltage between the warning voltage and the abnormal low voltage. Therefore, the abnormality determination section 56 determines the gate voltage V _GS of the field effect transistor 81 can exceed the first threshold voltage Vth1, the gate voltage V _GS of the field effect transistor 81 is normal voltage. Abnormality determination unit 56 determines, when the gate voltage V _GS of the field effect transistor 81 is not higher than the first threshold voltage Vth1 exceeds the second threshold voltage Vth2, the gate voltage V _GS of the FET 81 is warning voltage . Abnormality determination unit 56 determines the gate voltage V _GS of the FET 81 if the following second threshold voltage Vth2, the gate voltage V _GS of the field effect transistor 81 is abnormal low voltage.

The abnormality determination unit 56 repeatedly determines the abnormality of the temperature T of the field effect transistor 81 and the gate voltage _VGS at predetermined time intervals. The predetermined time is not particularly limited, and may be determined in consideration of the frequency of occurrence of abnormality in the temperature T or the gate voltage _VGS of the field effect transistor 81, the temperature rise characteristic of the field effect transistor 81, and the like.

The notification control unit 57 causes the notification unit such as the display unit of the operation display unit 6 to issue a warning. For example, the notification control unit 57 displays a message that the temperature T of the field effect transistor 81 is a warning temperature, that the gate voltage V _GS of the field effect transistor 81 is a warning voltage, and that the image processing can not be performed. Display on the display unit 6. Further, the notification control unit 57 may cause a notification unit such as a speaker (not shown) to output a warning sound or a message notifying that the warning temperature or the warning voltage is obtained.

Further, the notification control unit 57 determines the number of times that the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is a warning temperature, and / or determines that the gate voltage V _GS of the field effect transistor 81 is a warning voltage. Count the number of times done. Hereinafter, the number of times of determining that the alarm temperature is the warning temperature is referred to as a first count value N1, and the number of times of determining that the alarm temperature is the alarm voltage is referred to as a second count value N2. The first count value N1 is reset when the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is a normal temperature after a predetermined time has elapsed from a predetermined start point. The second count value N2 is reset when the abnormality determination unit 56 determines that the gate voltage V _GS is a normal voltage after a predetermined time has elapsed from a predetermined start point. For example, the notification control unit 57 uses the time when it is determined that the warning temperature or the warning voltage is first after the first count value N1 or the second count value N2 is reset, until the predetermined time elapses. Within a specific period, count the number of times determined to be a warning temperature or a warning voltage.

  The notification control unit 57 determines that the first count value N1 or the second count value N2 within the specific period exceeds a predetermined number of times determined in advance when the abnormality determination unit 56 determines that the warning temperature or the warning voltage is applied. On the condition that the notification unit such as the display unit of the operation display unit 6 is notified of the alert state.

[FET monitoring process]
Hereinafter, an example of the procedure of the monitoring process (FET monitoring process) of the field effect transistor 81 performed by the control unit 5 in the image forming apparatus 10 will be described with reference to FIGS. Here, FET monitoring process monitors the temperature T and gate voltage V _GS of the field effect transistor 81 is a process for controlling the inrush current preventing circuit 8. In addition, notations such as step S11 and step S12 indicate numbers of processing procedures (steps) executed by the control unit 5.

<Step S11>
First, in step S11 shown in FIG. 4, the control unit 5 determines whether or not the input of the first voltage V1 to the inrush current prevention circuit 8 is started. That is, the control unit 5 determines whether or not the drive of the inrush current prevention circuit 8 has been started. Specifically, the control unit 5 performs the determination in step S11 based on whether the selection processing unit 51 switches the interlock switch 74 from the off state to the on state.

  The drive start of the rush current prevention circuit 8 is performed when the main power supply (not shown) of the image forming apparatus 10 is turned on or when the power supply unit 7 is restarted.

  Here, when the control unit 5 determines that the input of the first voltage V1 to the inrush current prevention circuit 8 is started (step S11: Yes), the control unit 5 shifts the process to step S12. On the other hand, when the control unit 5 determines that the input of the first voltage V1 to the inrush current prevention circuit 8 is not started (step S11: No), the FET monitoring process ends.

<Step S12>
In step S12, the control unit 5 applies the third voltage V3 to the gate of the field effect transistor 81. Here, the process of step S12 is executed by turning on the switching element 83 by the switching control unit 54 of the control unit 5. Specifically, the switching control unit 54 applies a gate voltage V _GS higher than the gate threshold voltage to the switching element 83.

<Step S13>
In step S13, the control unit 5 adjusts the third voltage V3 output from the third power source 73 to the initial set value V3 _0. Here, when the temperature detected by the temperature detection unit 53 of the control unit 5 is the alert temperature, the third voltage V3 output from the third power supply control unit 52 is initialized at step S1551 (see FIG. 7) described later. It is adjusted to be lower than the value V3 _0. Therefore, when the recovery from the abnormality of the field effect transistor 81, the third voltage V3 output from the third power supply control unit 52 may be lower than the initial set value V3 _0. Therefore, by executing the processing in step S13, it is possible to a third voltage V3 at the start of driving of the rush current prevention circuit 8 always default value V3 _0. Thus, it is possible to prevent the occurrence of a situation where the third voltage V3 is too low at the start of driving of the inrush current prevention circuit 8 due to the recovery from the abnormality of the field effect transistor 81.

<Step S14>
In step S14, the control unit 5 determines whether or not a predetermined time has elapsed since the process of step S14 was started. The starting point of whether the predetermined time in step S14 has passed is the start time or end time of the temperature monitoring process of step S15 described later, or the start time or end time of the voltage monitoring process of step S16. Good.

  Here, when the control unit 5 determines that the predetermined time has elapsed since the process of step S14 is started (step S14: Yes), the process proceeds to step S15. On the other hand, when control unit 5 determines that the predetermined time has not elapsed since the start of the process of step S14 (step S14: No), it determines that the predetermined time has elapsed since the process of step S14 has started. Until (step S14: Yes), the determination in step S14 is repeated.

<Step S15>
In step S15, the control unit 5 executes a temperature monitoring process. Here, the process of step S15 is performed by the temperature detection unit 53 and the abnormality determination unit 56 of the control unit 5. The details of the temperature monitoring process will be described later.

<Step S16>
In step S16, the control unit 5 executes a voltage monitoring process. Here, the process of step S16 is executed by the gate voltage detection unit 55 and the abnormality determination unit 56 of the control unit 5. The details of the voltage monitoring process will be described later. Further, the voltage monitoring process may be performed prior to the temperature monitoring process of step S15.

<Step S17>
In step S17, control unit 5 determines whether or not the input of first voltage V1 to inrush current prevention circuit 8 is stopped. That is, the control unit 5 determines whether or not the drive of the inrush current prevention circuit 8 is stopped.

  The drive stop of rush current prevention circuit 8 is performed when the main power supply (not shown) of image forming apparatus 10 is turned off or when an abnormality occurs in rush current prevention circuit 8 (step 1562 in FIG. 8). To be done.

  Here, when the control unit 5 determines that the input of the first voltage V1 to the inrush current prevention circuit 8 is stopped (step S17: Yes), the FET monitoring process ends. On the other hand, when the controller 5 determines that the input of the first voltage V1 to the rush current prevention circuit 8 is not stopped (step S17: No), the process proceeds to step S14 and a predetermined time has elapsed. Under the conditions (step S14: Yes), the temperature monitoring process of step S15 and the voltage monitoring process of step S16 are continuously executed.

[Temperature monitoring process]
Next, the details of the temperature monitoring process executed in step S15 of the FET monitoring process shown in FIG. 4 will be described with reference to FIGS.

<Step S151>
First, in step S151 shown in FIG. 5, the temperature detection unit 53 of the control unit 5 detects the temperature T of the field effect transistor 81 based on the voltage output from the thermistor. The detection of the temperature T of the field effect transistor 81 is repeatedly performed at predetermined time intervals during the execution of the FET monitoring process.

<Step S152>
In step S152, the abnormality determination unit 56 of the control unit 5 determines whether the temperature detected by the temperature detection unit 53 is equal to or higher than the first threshold temperature Tth1. That is, the abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is the normal temperature or the warning temperature or more.

  Here, when the control unit 5 determines that the temperature detected by the temperature detection unit 53 is equal to or higher than the first threshold temperature Tth1 (step S152: Yes), the control unit 5 shifts the process to step S154. On the other hand, when determining that the temperature detected by the temperature detection unit 53 is less than the first threshold temperature Tth1 (step S152: No), the control unit 5 shifts the processing to step S153.

<Step S153>
The control unit 5 can determine that the temperature T of the field effect transistor 81 is normal when the temperature detected by the temperature detection unit 53 by the abnormality determination unit 56 is not the first threshold temperature Tth1 or more (step S152: No). Therefore, in step S153, the control unit 5 executes the normal temperature process. The details of the normal temperature process will be described later.

<Step S154>
In step S154, the abnormality determination unit 56 of the control unit 5 determines whether the temperature detected by the temperature detection unit 53 is equal to or higher than the second threshold temperature Tth2. That is, the abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is an abnormal overheat temperature or a warning temperature.

  Here, when it is determined that the temperature detected by the temperature detection unit 53 is equal to or higher than the second threshold temperature Tth2 (step S154: Yes), the control unit 5 shifts the process to step S156. On the other hand, when the controller 5 determines that the temperature detected by the temperature detector 53 is less than the second threshold temperature Tth2 (step S154: No), the controller 5 shifts the process to step S155.

<Step S155>
If the temperature detected by the temperature detection unit 53 is equal to or higher than the first threshold temperature Tth1 (step S152: Yes) and not equal to or higher than the second threshold temperature Tth2 (step S154: No), the controller 5 controls the temperature of the field effect transistor 81 It can be determined that T is the alert temperature. Therefore, in step S155, the control unit 5 executes a warning process. The details of the warning process will be described later.

<Step S156>
When the temperature detected by the temperature detection unit 53 is equal to or higher than the second threshold temperature Tth2 (step S154: Yes), the control unit 5 determines that the temperature T of the field effect transistor 81 is an abnormal overheat temperature. it can. Therefore, in step S156, the control unit 5 executes stop processing of image processing. The details of the image processing stop processing will be described later.

(Normal temperature process)
Next, with reference to FIG. 6, the details of the normal temperature process executed in step 153 of FIG. 5 will be described.

<Step S1530>
First, in step S1530 shown in FIG. 6, the abnormality determination unit 56 of the control unit 5 determines whether or not a predetermined time has elapsed since the first count value was reset last time. That is, the abnormality determination unit 56 determines whether or not the specific period for counting the number of times that the temperature is determined to be the warning temperature has elapsed.

  Here, when the control unit 5 determines that the predetermined time has elapsed since the first count value was reset last time (step S1530: Yes), the control unit 5 shifts the process to step S1531. On the other hand, when determining that the predetermined time has not elapsed since the first count value was reset last time (step S1530: No), the control unit 5 shifts the process to step S1532.

<Step S1531>
In step S1531, the abnormality determination unit 56 of the control unit 5 resets the first count value N1. The first count value N1 is determined by the abnormality determination unit 56 in a specific period from when the temperature T of the field effect transistor 81 is determined to be the normal temperature last time to when it is determined to be the alarm temperature this time. This corresponds to the number of times that the temperature T is determined to be a warning temperature. The first count value N1 is added in step 1553 of the warning processing described later (see FIG. 7).

<Step S1532>
In step S1532, the control unit 5, the third voltage V3 to determine whether the initial set value V3 _0. This determination is performed the third voltage V3 which is calculated by subtracting the gate voltage V _GS detected in the gate voltage detection unit 55 from the first voltage V1 by the control unit 5 by comparing the initial set value V3 ₀ Ru.

Here, the control unit 5, when the third voltage V3 is determined to be the initial set value V3 ₀ (Step S1532: Yes), then the process proceeds to step S1534. On the other hand, the control unit 5, when the third voltage V3 is determined not initial set value V3 ₀ (Step S1532: No), then the process proceeds to step S1533.

<Step S1533>
In step S1533, the control unit 5 adjusts the third voltage V3 to the initial set value V3 _0. Adjustment of the third voltage V3 in step S1533 is performed in the same procedure as step S13 (see FIG. 4) described above.

<Step S1534>
In step S1534, abnormality determination unit 56 of control unit 5 determines whether a warning is in progress. Specifically, abnormality determination unit 56 determines whether or not the warning is in progress based on whether or not the warning flag is set in step S1556 (see FIG. 7) or step S1666 (see FIG. 11) described later. .

  Here, if the control unit 5 determines that the warning is in progress (step S1534: YES), the control unit 5 shifts the process to step S1535. On the other hand, when determining that the warning is not being issued (step S1534: No), the control unit 5 ends the temperature normal state processing and shifts the processing to step S16 (see FIG. 4).

<Steps S1535 and S1536>
In steps S1535 and S1536, abnormality determination unit 56 of control unit 5 instructs cancellation of the warning and clears the warning flag. When the process of step S1536 ends, the control unit 5 ends the temperature normal time process and shifts the process to step S16 (see FIG. 4).

(Warning process)
Next, with reference to FIG. 7, the details of the warning process executed in step 155 of FIG. 5 will be described.

<Step S1551>
First, in step S1551 shown in FIG. 7, the third power control unit 52 of the control unit 5 adjusts the third voltage V3. Specifically, the third power control unit 52 first determines the control amount in accordance with the difference value between the temperature detected by the temperature detection unit 53 and a reference value such as the first threshold temperature Tth1. Next, the third power supply control unit 52 generates a voltage designation signal corresponding to the control amount based on the difference value. Then, the third power control unit 52 adjusts the third voltage V3 output from the third power supply 73 by transmitting the voltage designation signal to the third power supply 73. The third voltage V3 is adjusted in the range between ₀ V and the initial set value V30, and is decreased as the difference value is increased. That is, when the temperature T of the field effect transistor 81 is a warning temperature, the third voltage V3 is adjusted to a voltage value at which the channel resistance of the field effect transistor 81 decreases as the temperature T increases.

<Step S1552>
In step S1552, the abnormality determination unit 56 of the control unit 5 determines whether a warning is in progress. This determination is performed according to the same procedure as step S1534 (see FIG. 6) of the normal temperature process.

  Here, if the control unit 5 determines that a warning is in progress (step S1552: YES), the control unit 5 ends the warning processing and shifts the processing to step S16 (see FIG. 4). On the other hand, when determining that the warning is not being issued (step S 1552: No), the control unit 5 shifts the processing to step S 1553.

<Step S1553>
In step S1553, the abnormality determination unit 56 of the control unit 5 adds 1 to the first count value N1. That is, in step S1553, the abnormality temperature is determined to be the alarm temperature during the specific period from when the temperature T of the field effect transistor 81 is determined to be the normal temperature last time to when it is determined to be the alarm temperature this time. Count the number of times.

<Step S1554>
In step S1554, the abnormality determination unit 56 determines whether the first count value N1 is a predetermined reference number N1α. That is, the abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is a warning temperature or not.

  Here, when the control unit 5 determines that the first count value N1 is the reference number N1α (step S1554: Yes), the control unit 5 shifts the processing to step S1555. On the other hand, when determining that the first count value N1 is not the reference number N1α (step S1554: No), the control unit 5 ends the warning processing and shifts the processing to step S16 (see FIG. 4).

<Step S1555>
In step S1555, the notification control unit 57 of the control unit 5 causes the notification unit such as the operation display unit 6 and the speaker (not shown) to issue a warning that the temperature T of the field effect transistor 81 is the alert temperature. As a result, the user can be made aware of the alert state, and the user can be made to take measures such that the temperature T of the field effect transistor 81 does not become higher than the alert temperature.

<Step S1556>
In step S1556, abnormality determination unit 56 sets a warning flag indicating that warning is in progress. This warning flag enables the abnormality determination unit 56 to grasp that a warning is being made. The warning flag is set in a register (not shown) of the control unit 5 or the like.

(Stop processing of image processing)
Next, the details of the image processing stop process executed in step 156 of FIG. 5 will be described with reference to FIG.

<Step S1561>
First, in step S1561 shown in FIG. 8, the switching control unit 54 of the control unit 5 stops the application of the third voltage V3 to the gate of the field effect transistor 81. That is, the switching control unit 54 stops the application of the third voltage V3 to the gate of the field effect transistor 81 by stopping the application of the voltage to the gate of the switching element 83. As a result, the gate voltage V _GS of the field effect transistor 81 becomes smaller than the gate threshold voltage, and the driving of the field effect transistor 81 is stopped. As a result, the temperature rise of the field effect transistor 81 is suppressed.

<Step S1562>
In step S1562, the selection processing unit 51 of the control unit 5 stops the input of the first voltage V1 to the inrush current prevention circuit 8. That is, the switching control unit 54 stops the driving of the power supply unit 7 by turning off the interlock switch 74, and stops the input of the first voltage V1 to the inrush current prevention circuit 8. This also stops the drive of the inrush current prevention circuit 8. As a result, the driving of the field effect transistor 81 can be more reliably stopped, and the temperature rise of the field effect transistor 81 can be more reliably suppressed.

<Step S1563>
In step S1563, the notification control unit 57 of the control unit 5 instructs the notification unit such as the display unit of the operation display unit 6 to display a message notifying that the image processing can not be performed. On the other hand, the notification unit such as the display unit of the operation display unit 6 that has received the instruction displays the message. Thus, the image forming apparatus 10 notifies the user that the image processing can not be performed. Further, the user who has confirmed the message can understand that the image processing can not be performed, and can take measures such as maintenance of the image forming apparatus 10. In addition to displaying the message on the display unit of the operation display unit 6, the control unit 5 displays a message indicating that the image forming apparatus 10 should be restarted and / or the image forming apparatus 10 should be maintained. May be

[Voltage monitoring process]
Next, the details of the voltage monitoring process executed in step 16 of FIG. 4 will be described with reference to FIGS. 9 to 11.

<Step S161>
First, in step S161 shown in FIG. 9, the control unit 5 determines whether the first voltage V1 is input to the inrush current prevention circuit 8 or not. Specifically, the control unit 5 causes the switching control unit 54 to determine whether the interlock switch 74 is in the on state.

  Here, when the control unit 5 determines that the first voltage V1 is input to the rush current prevention circuit 8 (step S161: Yes), the control unit 5 shifts the process to step S162. On the other hand, when the controller 5 determines that the first voltage V1 is not input to the rush current prevention circuit 8 (step S161: No), the voltage monitoring process is ended, and the process proceeds to step S17 (see FIG. 4). Let That is, since the control unit 5 can determine that the drive of the inrush current prevention circuit 8 is stopped, the control unit 5 ends the voltage monitoring process.

<Step S162>
In step S162, the gate voltage detection unit 55 of the control unit 5 detects the gate voltage V _GS . Specifically, the gate voltage detection unit 55 detects the gate voltage V _GS as the difference between the first voltage V1 and the third voltage V3 as described above. The detection of the gate voltage V _GS of the field effect transistor 81 is repeatedly performed at predetermined time intervals during the execution of the FET monitoring process.

<Step S163>
In step S163, the abnormality determination unit 56 of the control unit 5 determines whether the gate voltage V _GS detected by the gate voltage detection unit 55 is equal to or less than the first threshold voltage Vth1. That is, the abnormality determination unit 56 determines whether the gate voltage V _GS is the normal voltage or the warning voltage or more.

Here, when the control unit 5 determines that the gate voltage V _GS is lower than or equal to the first threshold voltage Vth1 (step S163: Yes), the control unit 5 shifts the process to step S165. On the other hand, when the controller 5 determines that the gate voltage V _GS is not less than or equal to the first threshold voltage Vth1 (step S163: No), the process proceeds to step S164.

<Step S164>
If the gate voltage V _GS is not less than or equal to the first threshold voltage Vth1 (step S163: Yes), the control unit can determine that the gate voltage V _GS is normal. Therefore, in step S164, control unit 5 executes normal voltage processing. The details of the normal voltage process will be described later.

<Step S165>
In step S165, abnormality determination unit 56 determines whether gate voltage V _GS is equal to or lower than second threshold voltage Vth2. That is, the gate voltage detection unit 55 determines whether the gate voltage V _GS is an abnormal low voltage or a warning voltage.

Here, when the control unit 5 determines that the gate voltage V _GS is lower than or equal to the second threshold voltage Vth2 (step S165: Yes), the control unit 5 shifts the process to step S167. On the other hand, when control unit 5 determines that gate voltage V _GS is not less than or equal to second threshold voltage Vth 2 (step S 165: No), the process proceeds to step S 166.

<Step S166>
Gate voltage V _GS is equal to or less than the first threshold voltage Vth1 (step S163: Yes), if not below the second threshold voltage Vth2 (step S165: No), the control unit 5 is the gate voltage V _GS of the FET 81 vigilance It can be judged that it is a voltage. Therefore, in step S166, the control unit 5 executes a warning process. The details of the warning process will be described later.

<Step S167>
When the gate voltage V _GS is equal to or less than the second threshold voltage Vth2 (step S165: Yes), the control unit 5 can determine that the gate voltage V _GS of the field effect transistor 81 is abnormal low voltage. Therefore, in step S167, the control unit 5 executes an image processing stop process. The image processing stop processing in step S167 is the same as the image processing stop processing (see FIG. 8) of the temperature monitoring processing described above, and therefore the description thereof is omitted.

(Processing when gate voltage is normal)
Next, the details of the gate voltage normal time process executed in step 164 of FIG. 9 will be described with reference to FIG.

<Step S1640>
First, in step S1640 shown in FIG. 10, the third power supply control unit 52 of the control unit 5 adjusts the third voltage V3 to the initial set value V3 _0. Step S1641 is performed according to the same procedure as step S13 (see FIG. 4) of the FET monitoring process.

<Step S1641>
In step S1641, the abnormality determination unit 56 of the control unit 5 determines whether a predetermined time has elapsed since the second count value was reset last time. That is, the abnormality determination unit 56 determines whether or not the specific period for counting the number of times of determination as the warning voltage has elapsed.

  Here, when the control unit 5 determines that the predetermined time has elapsed since the second count value was reset last time (step S1641: Yes), the control unit 5 shifts the process to step S1642. On the other hand, when determining that the predetermined time has not elapsed since the first count value was previously reset (step S1641: No), the control unit 5 shifts the process to step S1643.

<Step S1642>
In step S1642, the abnormality determination unit 56 of the control unit 5 resets the second count value N2. Second count value N2 is a certain period until the gate voltage V _GS is determined to be a time alert voltage from a decision of the previous normal voltage, the gate voltage V _GS is in alarm voltage by the abnormality determination unit 56 It corresponds to the number of times determined to be present.

<Step S1643>
In step S1643, the abnormality determination unit 56 of the control unit 5 determines whether a warning is in progress. This determination is performed according to the same procedure as step S1534 (see FIG. 6) of the above-described normal temperature process.

  Here, if the control unit 5 determines that a warning is in progress (step S1643: YES), the control unit 5 shifts the process to step S1644. On the other hand, when determining that the warning is not being issued (step S1643: No), the control unit 5 ends the gate voltage normal process and shifts the process to step S17 (see FIG. 4).

<Steps S1644 and S1645>
In steps S1644 and S1645, abnormality determination unit 56 of control unit 5 instructs cancellation of the warning and clears the warning flag. When the process of step S1645 ends, the control unit 5 ends the gate voltage normal time process and shifts the process to step S17 (see FIG. 4).

(Warning process)
Next, with reference to FIG. 11, the details of the warning process executed in step 166 of FIG. 9 will be described.

<Step S1661>
First, in step S1661 shown in FIG. 11, the third power control unit 52 of the control unit 5 adjusts the third voltage V3. Specifically, first, the third power supply control unit 52 determines the control amount in accordance with the difference value between the gate voltage V _GS detected by the gate voltage detection unit 55 and a reference value such as the first threshold voltage Vth1. . Next, the third power supply control unit 52 generates a voltage designation signal corresponding to the control amount based on the difference value. Then, the third power control unit 52 adjusts the third voltage V3 output from the third power supply 73 by transmitting the voltage designation signal to the third power supply 73. The third voltage V3 is adjusted in the range between ₀ V and the initial setting value V30, and is decreased as the absolute value of the difference value is increased. That is, the third voltage V3, when the gate voltage V _GS of the FET 81 is warning voltage, the voltage value such that the channel resistance decreases the gate voltage V _GS smaller the field effect transistor 81 is adjusted Ru.

<Step S1662>
In step S1662, the abnormality determination unit 56 of the control unit 5 determines whether a warning is in progress. This determination is performed according to the same procedure as step S1534 (see FIG. 6).

  Here, if the control unit 5 determines that a warning is being issued (step S1662: YES), the control unit 5 ends the warning processing and shifts the processing to step S17 (see FIG. 4). On the other hand, when determining that the warning is not being issued (step S1662: No), the control unit 5 shifts the processing to step S1663.

<Step S1663>
In step S1663, the abnormality determination unit 56 of the control unit 5 adds 1 to the second count value N2. That is, in step S1663, the number of times of determination as the warning voltage is counted in the specific period from when the gate voltage V _GS is determined to be the normal voltage last time to the current determination voltage.

<Step S1664>
In step S1664, abnormality determination unit 56 determines whether second count value N2 is equal to predetermined reference number N2α. That is, in step S1664, it is determined whether the gate voltage V _GS is a warning voltage or not.

  Here, when the control unit 5 determines that the second count value N2 is the reference number of times N2α (step S1664: Yes), the control unit 5 shifts the process to step S1665. On the other hand, when determining that the second count value N2 is not the reference number N2α (step S1664: No), the control unit 5 ends the warning processing and shifts the processing to step S17 (see FIG. 4).

<Step S1665>
In step S1665, the notification control unit 57 of the control unit 5 warns that the gate voltage V _GS of the field effect transistor 81 is the alert voltage to the notification unit such as the display unit of the operation display unit 6 or the speaker (not shown). Let it go. Thus, the user can be made aware of the alarm state, and the user can be made to take measures such that the gate voltage V _GS is not lower than the alarm voltage.

<Step S1666>
In step S1666, the abnormality determination unit 56 sets a warning flag indicating that a warning is in progress. This warning flag enables the abnormality determination unit 56 to grasp that a warning is being made. The warning flag is set in a register (not shown) of the control unit 5 or the like.

As described above, in the image forming apparatus 10, the temperature T and the gate voltage V _GS of the field effect transistor 81 of the rush current prevention circuit 8 are controlled by the gate voltage detection unit 55 and the temperature detection unit 53 of the control unit 5 during execution of the FET monitoring process. Are repeatedly detected at predetermined time intervals. Thereby, the state of the field effect transistor 81 can be monitored in real time. For the field effect transistor 81, the abnormality determination unit 56 of the control unit 5 determines abnormality of the temperature T and the gate voltage _VGS of the field effect transistor 81 under monitoring in real time. As a result, the abnormality in the temperature T or the gate voltage V _GS of the field effect transistor 81 in the inrush current prevention circuit 8 can be immediately detected from the time of the abnormality occurrence.

Then, in rush current prevention circuit 8, switching element 83 is turned off by switching control unit 54 of control unit 5 when field effect transistor 81 reaches an abnormal overheat temperature or an abnormal low voltage. On the other hand, in the field effect transistor 81, when the switching element 83 is turned off, the gate voltage V _GS becomes lower than the gate threshold voltage, and the field effect transistor 81 is put in the stop state. As a result, the temperature rise of the field effect transistor 81 is suppressed, and the occurrence of defects such as open defects and burnout in the field effect transistor 81 and the components mounted therearound is suppressed.

  In addition, in the inrush current prevention circuit 8, the interlock switch 74 is turned off by the selection processing unit 51 of the control unit 5 when the field effect transistor 81 reaches an abnormal overheat temperature or an abnormal low voltage. As a result, the input of the first voltage V1 to the inrush current prevention circuit 8 is stopped, and the drive of the inrush current prevention circuit 8 is stopped. Therefore, in rush current prevention circuit 8, the conduction between the source and the drain of field effect transistor 81 is reliably cut off, and the occurrence of a defect in field effect transistor 81 and the components mounted therearound is more reliably suppressed. Ru.

Further, in the image forming apparatus 10, while the state of the field effect transistor 81 in the rush current prevention circuit 8 is monitored in real time, the temperature T or the gate voltage V _GS of the field effect transistor 81 is alert by the abnormality determination unit 56 of the control unit 5. It is determined whether it is a voltage or a warning temperature. This makes it possible to prevent the field effect transistor 81 from becoming an abnormally overheated temperature and an abnormally low voltage.

On the other hand, in the power supply unit 7, a voltage is applied to the gate of the field effect transistor 81 in the rush current prevention circuit 8 by the third power supply 73 which is a variable voltage power supply. Therefore, the gate voltage V _GS of the field effect transistor 81 can be adjusted by the output of the third power supply 73. Then, in the power supply unit 7, when the field effect transistor 81 is at the alert voltage or the alert temperature, the voltage applied to the gate of the field effect transistor 81 is reduced. As a result, the channel resistance of the field effect transistor 81 can be reduced, and the abnormal low voltage and abnormal overheating temperature of the field effect transistor 81 can be prevented in advance.

Second Embodiment
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 12 and 13. However, in the following description, the configuration common to the first embodiment of the second embodiment is denoted by the same reference numeral as the configuration of the first embodiment, and the detailed description thereof is omitted.

  As shown in FIG. 12, the image forming apparatus according to the second embodiment includes an inrush current prevention circuit 8A and a control unit 5A.

  Inrush current prevention circuit 8A includes field effect transistor 81 and switching element 88A.

  The field effect transistor 81 is a P-channel MOSFET. The gate of the field effect transistor 81 is connected to the ground via the switching element 88 A, the source is connected to the output line 711 of the first power supply 71, and the drain is connected to the output line 721 of the second power supply 72.

  The switching element 88A switches between the on state and the off state to select the state in which the first voltage V1 is applied to the gate of the field effect transistor 81 and the state in which the first voltage V1 is not applied. That is, the switching element 88A selects the drive state and the drive stop state of the field effect transistor 81 by switching between the on state and the off state. In the present embodiment, when the temperature T of the field effect transistor 81 is normal, the switching element 84A is turned on, and the gate of the field effect transistor 81 is grounded. On the other hand, switching element 84A is turned off when temperature T of field effect transistor 81 is an abnormal overheat temperature, and a first voltage V1 is applied to the gate of field effect transistor 81. Here, the switching element 88A is an N-channel MOSFET. In the switching element 88A, the gate is connected to the switching control unit 54, the source is connected to the ground, and the drain is connected to the gate of the field effect transistor 81. The switching control unit 54A switches the switching element 88A between the on state and the off state.

  As another example of the switching element 88A, there may be mentioned other types of transistors generally used as switching elements such as N-channel MOSFETs, PNP transistors, and NPN transistors.

  The control unit 5A includes a selection processing unit 51, a switching control unit 54A, a gate voltage detection unit 55, an abnormality determination unit 56A, and a notification control unit 57.

The gate voltage detection unit 55 monitors the gate voltage V _GS of the field effect transistor 81. Since the field effect transistor 81 is a P-channel MOSFET, the gate voltage detection unit 55 monitors the gate voltage V _GS as the difference (V1) between the V1 voltage and the ground (0 V).

  The selection processing unit 51 controls switching of the interlock switch 74 between the on state and the off state. When the temperature T of the field effect transistor 81 is normal, the selection processing unit 51 turns on the interlock switch 74. On the other hand, when the temperature T of the field effect transistor 81 is an abnormal overheat temperature, the selection processing unit 51 turns off the interlock switch 74 and stops the input of the first voltage V1 to the inrush current prevention circuit 8A.

  The switching control unit 54A selects the on state and the off state of the switching element 88A. Specifically, the switching control unit 54A turns on the switching element 88A by applying a voltage exceeding the gate threshold voltage to the gate of the switching element 88A. On the other hand, the switching control unit 54A turns off the switching element 88A by not applying a voltage to the gate of the switching element 88A.

The gate voltage detection unit 55 detects the gate voltage V _GS of the field effect transistor 81.

The abnormality determination unit 56A compares the gate voltage V _GS detected by the gate voltage detection unit 55 with the first threshold voltage Vth1 or the second threshold voltage Vth2 to determine abnormality of the gate voltage V _GS of the field effect transistor 81. Do.

Further, abnormality determination unit 56A counts the number of times that gate voltage V _GS of field effect transistor 81 is determined to be a warning voltage. Furthermore, the abnormality determination unit 56A instructs the user that the gate voltage V _GS of the field effect transistor 81 is a warning voltage, and the gate voltage V _GS of the field effect transistor 81 is an image due to an abnormal low voltage. For example, an instruction for notifying that the formation processing can not be performed is given to a notification unit such as the operation display unit 6 or a speaker (not shown).

The notification control unit 57 causes the display unit of the operation display unit 6 and a notification unit such as a speaker (not shown) to issue a warning. For example, the notification control unit 57 causes the display unit of the operation display unit 6 to display a message that the gate voltage V _GS of the field effect transistor 81 is a warning voltage and that image processing can not be performed. In addition, the notification control unit 57 may cause a speaker (not shown) to notify that the warning temperature is reached and that image processing can not be performed.

[FET monitoring process]
Hereinafter, an example of the procedure of the FET monitoring process performed by the control unit 5A will be described with reference to FIG. Here, the FET monitoring process is a process of monitoring an abnormality of the gate voltage V _GS of the field effect transistor 81. In the following, detailed description of steps similar to those of the FET monitoring process of the first embodiment described above will be omitted.

<Step S21>
First, in step S21 shown in FIG. 13, the control unit 5A determines whether or not the input of the first voltage V1 to the inrush current prevention circuit 8A is started.

  Here, when the control unit 5A determines that the input of the first voltage V1 to the inrush current prevention circuit 8A is started (step S21: Yes), the control unit 5A shifts the process to step S22. On the other hand, when controller 5A determines that input of first voltage V1 to inrush current prevention circuit 8A is not started (step S21: No), it can be determined that inrush current prevention circuit 8A is in the drive stop state. End the FET monitoring process.

<Step S22>
When the input of the first voltage V1 to the inrush current prevention circuit 8A is started (step S21: Yes), the control unit 5A can determine that the inrush current prevention circuit 8A is in the driving state. Therefore, in step S22, control unit 5A determines whether or not a predetermined time has elapsed since the process of step S22 was started. That is, the voltage monitoring process of step S23 mentioned later is repeatedly performed for every predetermined time. The starting point of whether the predetermined time has elapsed in step S22 may be the start time point or the end time point of the voltage monitoring process of step S23 described later.

  Here, when the control unit 5A determines that the predetermined time has elapsed since the process of step S22 is started (step S22: Yes), the process proceeds to step S23. On the other hand, when controller 5A determines that the predetermined time has not elapsed since the start of the process of step S22 (step S22: No), it determines that the predetermined time has elapsed since the process of step S22 has started. Until (step S22: Yes), the determination of step S22 is repeated.

<Step S23>
In step S23, the control unit 5A executes a voltage monitoring process. Here, the process of step S23 is performed by the gate voltage detection unit 55 and the abnormality determination unit 56 of the control unit 5A in accordance with basically the same procedure as the voltage monitoring process (see FIG. 9) of the first embodiment described above. Ru.

<Step S24>
In step S24, control unit 5A determines whether or not the input of first voltage V1 to rush current prevention circuit 8A is stopped. The determination in step S24 is performed according to the same procedure as step S17 of the FET monitoring process shown in FIG.

  Here, when the control unit 5A determines that the input of the first voltage V1 to the inrush current prevention circuit 8A is stopped (step S24: Yes), the FET monitoring process ends. On the other hand, when controller 5A determines that input of first voltage V1 to rush current prevention circuit 8A is not stopped (step S24: No), the process proceeds to step S22, and a predetermined time has elapsed. Under the condition (step S22: Yes), the voltage monitoring process of step S23 is continuously executed.

As described above, in the rush current prevention circuit 8A of the image forming apparatus 10, the gate voltage detection unit 55 detects the gate voltage V _GS of the field effect transistor 81 at predetermined time intervals. When the gate voltage V _GS of the field effect transistor 81 is an abnormal low voltage, the switching element 88A is turned off. As a result, when the field effect transistor 81 is at the abnormal overheat temperature, the drive of the field effect transistor 81 is stopped. Therefore, in rush current prevention circuit 8A, it is possible to suppress the occurrence of defects such as open defects and burnout in field effect transistor 81 and the components mounted therearound due to the heat generation of field effect transistor 81. In addition, in the inrush current prevention circuit 8A, the interlock switch 74 is turned off when the field effect transistor 81 reaches an abnormal overheat temperature. As a result, the input of the first voltage V1 to the inrush current prevention circuit 8A is stopped, and the occurrence of defects such as open defects and burnout in the field effect transistor 81 and the components mounted therearound is more reliably suppressed.

  Although the case where the field effect transistor 81 is used as an inrush current prevention element has been described in the present embodiment, the present invention can also be applied to the case where the field effect transistor 81 is used as a switching element.

10 image forming apparatus 5 control unit 51 selection processing unit 54 switching control unit 55 gate voltage detection unit 56 abnormality determination unit 57 notification control unit 6 operation display unit 7 power supply unit 74 interlock switch 8 rush current prevention circuit 81 field effect transistor 83 switching element

Claims (4)

An image processing apparatus comprising: a power supply unit having a rush current prevention circuit; and a control unit that controls the power supply unit,
The inrush current prevention circuit includes a field effect transistor, and a switching element that selects a drive state and a drive stop state of the field effect transistor by switching on and off states,
The control unit determines whether a gate voltage detection unit that detects a gate voltage of the field effect transistor, and whether a gate voltage of the field effect transistor detected by the gate voltage detection unit is a predetermined low voltage. When the abnormality determination unit to determine and the abnormality determination unit determine that the gate voltage of the field effect transistor is the abnormal low voltage, the field effect transistor is switched between the on state and the off state of the switching element have a, a switching control unit for the drive stop state,
The abnormality determining unit determines whether the gate voltage of the field effect transistor is any one of the abnormal low voltage, a predetermined normal voltage, and a warning voltage between the normal voltage and the abnormal low voltage. ,
The information processing apparatus further comprises a notification unit that notifies that the gate voltage of the field effect transistor is the warning voltage,
The control unit is configured to notify that the gate voltage of the field effect transistor is the warning voltage when the abnormality determination unit determines that the gate voltage of the field effect transistor is the warning voltage. An image processing apparatus having a notification control unit to be performed by the control unit . The power supply unit includes a circuit drive selection unit that selects a drive state and a drive stop state of the rush current prevention circuit,
The control unit is configured to cause the circuit drive selection unit to select the drive stop state of the rush current prevention circuit when the abnormality determination unit determines that the gate voltage of the field effect transistor is the abnormal low voltage. The image processing apparatus according to claim 1, further comprising a processing unit. The notification control unit counts the number of times that the gate voltage of the field effect transistor is determined to be the warning voltage, and determines that the gate voltage of the field effect transistor is the warning voltage within a predetermined specific period. If more than a specified number of times which number is predetermined, the image processing apparatus according to the notification that the gate voltage of the field effect transistor is the guard voltage to claim 1 or 2 causes the notification unit. The notification control unit causes the notification unit to notify that the image processing can not be performed when the abnormality determination unit determines that the gate voltage of the field effect transistor is the abnormal low voltage. The image processing apparatus according to any one of claims 1 to 3 .

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