JP6537576B2 - Data acquisition device - Google Patents

Description

  The present invention relates to a data acquisition device.

  There is known a data recording device which converts a sensor signal which is an analog signal output from a sensor into a digital value and records the digital value in a memory. For example, Patent Document 1 describes a data recording apparatus that records a signal input by a signal input unit in a storage unit when a trigger signal supplied from the outside is detected.

  In addition, there is known an integrated circuit in which an analog circuit block, an analog / digital converter, a memory, a CPU, a communication interface, etc. are integrated into one chip and an internal circuit is configured to be changeable (for example, non-patent document 1; Patent Document 2).

JP 2005-274223 A

Smart Analog MCU (RL78 / G1E), [online], [search September 2, 2015], Internet <URL: http://japan.renesas.com/products/smart_analog/smart_analog_mcu/index.jsp> PSoC 5LP: CY8C58LP Family Datasheet, [online], July 15, 2015, [Search on September 2, 2015], Internet <URL: http://japan.cypress.com/file/45906/download>

  By integrating a plurality of circuit blocks into one chip as in the integrated circuits disclosed in Non-Patent Documents 1 and 2, it is possible to miniaturize the device. However, since many functional elements are included in one chip, the number and capacity of individual elements are small, and thus individual functional elements only hold general processing functions, and data as a data acquisition device It is difficult to configure various functions of recording and to increase the number of channels. In addition, when all functions are accommodated in one chip, it is difficult to flexibly cope with expansion of data recording capacity, that is, expansion of memory capacity and expansion of memory elements. Furthermore, it is difficult to flexibly cope with changes in communication specifications such as speeding up of communication and power saving. Further, in an integrated circuit having a variable circuit configuration as described in Non-Patent Document 2, redundancy is provided to detailed elements inside the integrated circuit by programmable switch elements and the like, and as a result, circuit area and consumption Power increases.

  The present invention has been made in view of the above points, and provides a data recording apparatus capable of achieving both the downsizing of the apparatus and the flexibility and expandability of the apparatus configuration meeting various data recording needs. The purpose is

  A data recording apparatus according to the present invention includes an amplifier for amplifying a sensor signal output from a sensor, an analog-to-digital converter for converting the sensor signal amplified by the amplifier into a digital value, and recording of the digital value. A recording control logic circuit for controlling, a communication control logic circuit for controlling communication with an external device, a memory in which the digital value is recorded under the control of the recording control logic circuit, and the communication control logic circuit The communication control module includes a communication module for communicating with the external device under control, and a central processing unit for giving an instruction to the recording control logic circuit, wherein the recording control logic circuit responds to an externally supplied trigger signal. Start or stop the recording of the digital value in the memory.

  The trigger signal may include additional information, and when the recording control logic circuit records the digital value in the memory in response to the trigger signal, the additional information corresponding to each of the digital values And may be recorded in the memory.

  The recording control logic circuit may record, in the memory, status information indicating continuation, interruption, and end of recording of the digital value in the memory.

  The recording control logic circuit may control the recording order of the plurality of digital values sequentially supplied from the analog to digital converter to the memory.

  According to the data recording apparatus of the present invention, it is possible to achieve both the downsizing of the apparatus and the flexibility and expandability of the apparatus configuration to meet various data recording needs.

FIG. 1 is a perspective view showing a schematic configuration of a data recording device according to an embodiment of the present invention. FIG. 1 is a circuit block diagram showing an example of a circuit configuration of a data recording device according to an embodiment of the present invention. It is a circuit block diagram showing the power supply composition of an instrumentation amplifier, a low pass filter, a multiplexer, and an AD converter concerning an embodiment of the present invention. It is a circuit block diagram showing composition for realizing setting change about a characteristic of an instrumentation amplifier, a low pass filter, a multiplexer, and an AD converter concerning an embodiment of the present invention, function, or operation. FIG. 1 is a circuit block diagram showing an example of a circuit configuration of a data recording device according to an embodiment of the present invention. FIG. 1 is a circuit block diagram showing an example of a circuit configuration of a data recording device according to an embodiment of the present invention. It is a perspective view which shows the general | schematic structure of the data recording device which concerns on other embodiment of this invention. It is a perspective view which shows the general | schematic structure of the data recording device which concerns on other embodiment of this invention. It is a perspective view which shows the general | schematic structure of the data recording device which concerns on other embodiment of this invention. It is a perspective view which shows the general | schematic structure of the data recording device which concerns on other embodiment of this invention. FIG. 7 is a circuit block diagram showing an example of a circuit configuration of a data recording device according to another embodiment of the present invention. It is a perspective view which shows the general | schematic structure of the data recording device which concerns on other embodiment of this invention. FIG. 7 is a circuit block diagram showing an example of a circuit configuration of a data recording device according to another embodiment of the present invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and portions are denoted by the same reference numerals.

  FIG. 1 is a perspective view showing a schematic configuration of a data recording apparatus 100 according to a first embodiment of the present invention. The data recording apparatus 100 includes an LSI (Large Scale Integration) 10 mounted on the wiring substrate 1, an RF (Radio Frequency) communication module 41, a Universal Asynchronous Receiver Transmitter (UART) 42, a CPU (Central Processing Unit) 50, and a memory 60. Is composed including.

  Among the above components, the LSI 10, the CPU 50 and the memory 60 are mounted on the wiring substrate 1 in a bare chip state which is constituted by separate semiconductor chips and which is not covered with the mold resin. The LSI 10, the CPU 50 and the memory 60 may be covered with a protective film made of a resin or the like for protecting them from mechanical stress and thermal stress, respectively. The RF communication module 41 and the UART 42 are configured as package components separate from the semiconductor chip that configures the LSI 10, the CPU 50, and the memory 60, and are mounted on the wiring board 1. The RF communication module 41 and the UART 42 may be in a bare chip state. In the present embodiment, the LSI 10, the RF communication module 41, the UART 42, and the CPU 50 are mounted on the first substrate surface S1 of the wiring substrate 1, and the memory 60 having a larger area than these is the first substrate surface of the wiring substrate 1. It is mounted on the second substrate surface S2 opposite to S1.

  The LSI 10, the RF communication module 41, the UART 42, the CPU 50, and the memory 60 are each connected to the wiring substrate 1 via bumps formed on the bonding surface with the wiring substrate 1. The wiring board 1 has a single layer or a multilayer wiring layer, and the respective components mounted on the wiring board 1 are electrically connected to each other via the wiring formed on the wiring board 1. The components mounted on the wiring board 1 may be connected by wires. Alternatively, the wires of the wiring substrate 1 may be directly connected to the respective bare chip terminal portions.

  FIG. 2 is a circuit block diagram showing an example of a circuit configuration of the data recording device 100. As shown in FIG. In FIG. 2, a plurality of sensors 12 connected to the data acquisition device 100 are shown together with the data acquisition device 100.

  The data recording device 100 converts the sensor signal output from the sensor 12 into a digital value and records the digital value in the memory 60, and the data recording device 100 receives a request from an external device (for example, a personal computer communicably connected to the data recording device 100). Accordingly, it has a function of transmitting the sensor signal value recorded in the memory 60 to an external device as a main function. As the sensor 12 connected to the data acquisition device 100, any sensor such as a pressure sensor, an acceleration sensor, a displacement sensor, or a voltage sensor can be used.

  The LSI 10 integrates an instrumentation amplifier 21, a low pass filter 22, a multiplexer 23, an analog / digital converter (hereinafter referred to as an AD converter) 24, a recording control logic circuit 30, and a communication control logic circuit 40 in a single semiconductor chip. Integrated circuit. The LSI 10 has, for example, 16 sensor signal input channels, and can connect 16 sensors 12. The sensor signal output from each of the plurality of sensors 12 is input to the LSI 10 through the port 91 for sensor signal input.

  The instrumentation amplifier 21 and the low pass filter 22 are provided corresponding to each of the 16 sensors 12 respectively. Each of the instrumentation amplifiers 21 amplifies the sensor signal output from the corresponding sensor 12. The low pass filter 22 removes high frequency components (noise) from the corresponding sensor signal amplified by the instrumentation amplifier 21. In addition, when a high frequency component does not become a problem from a sensor signal, the low pass filter 22 may be omitted.

  The multiplexer 23 and the AD converter 24 are provided one for every four input channels. Each of the multiplexers 23 sequentially selects the sensor signals output from the corresponding four low pass filters 22, and supplies the selected sensor signal to the AD converter 24.

  The AD converter 24 converts a sensor signal which is an analog signal sequentially supplied from the multiplexer 23 into a digital value. The sensor signal value converted into the digital value by the AD converter 24 is supplied to the recording control logic circuit 30. Here, instead of sharing the AD converter 24 with a plurality of input channels, the AD converter 24 is provided for each input channel, and the sensor signals respectively output from the low pass filter 22 are directly received by the corresponding AD converter 24. It is good also as composition. In this case, the multiplexer 23 becomes unnecessary.

  The recording control logic circuit 30 performs various operations based on the command supplied from the CPU 50. When a command to perform data acquisition is issued from the CPU 50, the recording control logic circuit 30 operates these by supplying control signals to the multiplexer 23 and the AD converter 24, and sequentially supplies them from the AD converter 24. The sensor signal value to be recorded is recorded in the memory 60. On the other hand, when an instruction to read data is issued from the CPU 50, the recording control logic circuit 30 reads the sensor signal value recorded in the memory 60, and the communication control logic circuit 40 and the RF communication module 41 or the UART 42 are The sensor signal value read out is transmitted to an external device.

  The communication control logic circuit 40 is a circuit block that controls communication with an external device. The communication control logic circuit 40 transmits, for example, a sensor signal value read from the memory 60 supplied from the recording control logic circuit 30 to an external device via the RF communication module 41 or the UART 42 in accordance with a predetermined communication protocol. The communication control logic circuit 40 transmits a sensor signal value to an external device through one or both of the RF communication module 41 and the UART 42 based on an instruction from the CPU 50. The communication control logic circuit 40 also supplies the CPU 50 with commands and information supplied from an external device via the RF communication module 41 or the UART 42.

  The memory 60 is a recording medium for recording a sensor signal value output from the sensor 12 and converted into a digital value. The memory 60 is a non-volatile recording medium capable of writing, erasing and rewriting data. The memory 60 may be, for example, a NAND flash memory. The memory 60 is configured as a semiconductor chip separate from the semiconductor chip constituting the LSI 10, and is connected to the recording control logic circuit 30 via the data input / output port 93 of the LSI 10.

  The RF communication module 41 is a communication module for performing wireless communication with an external device under the control of the communication control logic circuit 40. The RF communication module 41 can be configured as a package component separate from the semiconductor chip that configures the LSI 10. The RF communication module 41 is connected to the communication control logic circuit 40 via the communication port 95 of the LSI 10.

  The UART 42 is a communication module for performing wired communication with an external device under the control of the communication control logic circuit 40. The UART 42 has a function of mutually converting data of the serial transfer scheme and data of the parallel transfer scheme. The UART 42 can be configured as a package component separate from the semiconductor chip that configures the LSI 10. The UART 42 is connected to the communication control logic circuit 40 via the communication port 96 of the LSI 10. In the present embodiment, a configuration including both the RF communication module 41 and the UART 42 is illustrated as a communication module for communicating with an external device, but a configuration including only one of the RF communication module 41 and the UART 42 It may be

  The CPU 50 is a central processing unit that centrally controls the operation of the data acquisition device 100. The CPU 50 controls data recording and data reading by sending an instruction to the recording control logic circuit 30. Further, the CPU 50 controls communication with an external device by sending an instruction to the communication control logic circuit 40. The CPU 50 is configured as a semiconductor chip that is separate from the semiconductor chip that configures the LSI 10. The CPU 50 is connected to the communication control logic circuit 40 through the communication port 97 of the LSI 10, and is connected to the recording control logic circuit 30 through the communication port 98 of the LSI 10.

  Hereinafter, various functions provided to the data recording device 100 will be described.

  The data recording apparatus 100 can perform synchronization processing to match data held with an external device (for example, another data recording apparatus) connected via the port 92 for communication. .

  Further, the data recording apparatus 100 can externally control the timing of start and stop of data recording by externally supplying the trigger signal St. The LSI 10 has a port 94 for trigger signal input that receives an input of a trigger signal St supplied from an external device. The trigger signal St input to the LSI 10 through the port 94 is received by the recording control logic circuit 30. The recording control logic circuit 30 starts or stops the recording of the sensor signal value according to the received trigger signal St.

  The trigger signal St can include additional information, which can be recorded in the memory 60 together with the sensor signal value. Examples of the additional information include time information, environment information such as temperature, humidity, and pressure of an object (hereinafter referred to as a sensing object) sensed by the sensor 12, and information on the state of the sensing object. For example, in the case where the sensing target is a mobile that moves on a predetermined moving path, position information indicating the position of the sensing target on the moving path can be included as additional information in the trigger signal. The additional information may be a digital signal integrated with the trigger signal, and may be supplied to the data acquisition device 100 in the form of, for example, an optical signal or a wireless signal.

  When recording the sensor signal value in the memory 60 according to the trigger signal St including the additional information, the recording control logic circuit 30 adds the corresponding additional information to each of the sensor signal values sequentially supplied from the AD converter 24. The data is added and recorded in the memory 60. Thus, by including additional information in each of the sensor signal values recorded in the memory 60, it is possible to record additional information at the time of acquisition of the sensor signals sequentially output from the sensor 12 together with the sensor signal values. Become. Note that one common additional information may be added to a plurality of sensor signal values supplied from the AD converter 24 within a predetermined period, and may be recorded in the memory 60 as one data set. According to this aspect, it is possible to reduce the amount of data to be recorded in the memory 60 as compared to the case where the additional information is included in each of the sensor signal values.

  Further, the recording control logic circuit 30 records, in the memory 60, status information indicating continuation, interruption, and end of recording of the sensor signal value supplied from the AD converter 24 in the memory 60 together with the sensor signal value. The command regarding continuation, interruption, and termination of the recording of the sensor signal value in the memory 60 is supplied from the CPU 50 to the recording control logic circuit 30.

  While the CPU 50 issues a command to continue data acquisition, the recording control logic circuit 30 appends status information indicating "continuation" of data acquisition to the sensor signal value supplied from the AD converter 24. The sensor signal value is recorded in the memory 60. When the CPU 50 issues a command to interrupt data acquisition, the recording control logic circuit 30 adds status information indicating “interruption” of data acquisition to the sensor signal value supplied from the AD converter 24, After the sensor signal value is recorded in the memory 60, data acquisition is interrupted. That is, status information indicating “discontinue” of data acquisition is added to the sensor signal value recorded in the memory 60 immediately before interrupting data acquisition. When the CPU 50 issues a command to end data acquisition, the recording control logic circuit 30 adds status information indicating “end” of data acquisition to the sensor signal value supplied from the AD converter 24, After the sensor signal value is recorded in the memory 60, data acquisition is ended. That is, status information indicating “end” of data acquisition is added to the sensor signal value recorded in the memory 60 immediately before the end of data acquisition.

  By including the status information in each of the sensor signal values recorded in the memory 60 as described above, it is possible to record the data acquisition process together with the sensor signal values. When the recording control logic circuit 30 records a sensor signal value in the memory 60 in response to the trigger signal St including the above-mentioned additional information, a data set including one or more sensor signal values, additional information, and status information is stored. The data is recorded in the memory 60. In this case, the CPU 50 determines continuation, interruption, and termination of data recording by cooperating with an external device that outputs the trigger signal St.

  Further, the recording control logic circuit 30 controls the recording order of the plurality of sensor signal values sequentially supplied from each of the AD converters 24 to the memory 60 based on an instruction from the CPU 50. That is, the recording control logic circuit 30 can record a plurality of sensor signal values in the memory 60 in an order different from the order supplied from each of the AD converters 24.

  FIG. 3 is a circuit block diagram showing a power supply configuration of the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23 and the AD converter 24 built in the LSI 10. The LSI 10 includes power supply circuits 21P, 22P, 23P, and 24P that supply power to the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23, and the AD converter 24, respectively. The recording control logic circuit 30 has power supply control registers 31a, 31b, 31c and 31d corresponding to the power supply circuits 21P, 22P, 23P and 24P, respectively. The power supply circuits 21P, 22P, 23P and 24P are turned on / off according to the set values written in the registers 31a, 31b, 31c and 31d corresponding to themselves. The write control logic circuit 30 itself carries out the writing of the setting values to the registers 31a, 31b, 31c and 31d based on the command from the CPU 50. The CPU 50 may directly write the setting values to the registers 31a, 31b, 31c and 31d.

  The recording control logic circuit 30 writes setting values for turning on the power supply circuits 21P, 22P, 23P, and 24P in the registers 31a, 31b, 31c, and 31d during the data recording period based on an instruction from the CPU 50. As a result, power is supplied to the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23, and the AD converter 24 during the data recording period, and these components become operable. On the other hand, the recording control logic circuit 30 sets the setting values for turning off the power supply circuits 21P, 22P, 23P and 24P during the period other than the data recording period based on the command from the CPU 50, the registers 31a, 31b, 31c and Write to 31d. As a result, during the period other than the data recording period, the power supply to the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23, and the AD converter 24 is lost, and these components are stopped. Thus, power consumption can be suppressed by turning off the power supply circuits 21P, 22P, 23P, and 24P during a period other than the data recording period.

  Although the registers 31a, 31b, 31c and 31d are disposed in the recording control logic circuit 30 in this embodiment, the present invention is not limited to this aspect. For example, the registers 31a, 31b, 31c and 31d may be disposed in the vicinity of the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23, and the AD converter 24, respectively. Moreover, although the case where an individual power supply circuit was provided in each of the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23, and the AD converter 24 was illustrated in this embodiment, it is not limited to this aspect. That is, one power supply circuit and one register commonly used for the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23, and the AD converter 24 may be provided.

  The instrumentation amplifier 21, the low pass filter 22, the multiplexer 23, and the AD converter 24 built in the LSI 10 can be changed in setting regarding their characteristics, functions or operations. FIG. 4 is a circuit block diagram showing a configuration for realizing setting change regarding the characteristic, function or operation of the instrumentation amplifier 21, the low pass filter 22, the multiplexer 23 and the AD converter 24.

  The recording control logic circuit 30 has setting change registers 32 a, 32 b, 33 c and 33 d corresponding to the in-amp 21, the low pass filter 22, the multiplexer 23 and the AD converter 24 respectively.

  The instrumentation amplifier 21 amplifies the sensor signal with an amplification degree corresponding to the set value written to the register 32 a. That is, it is possible to change the amplification degree of the instrumentation amplifier 21 by the set value written to the register 32a.

  The low pass filter 22 filters the signal with a frequency characteristic according to the frequency of the pulse signal supplied from the frequency divider 25. The divider 25 has a plurality of divider circuits (not shown) that divide the input basic clock by different division ratios. The divider 25 supplies the low pass filter 22 with a pulse signal output from one divider circuit selected according to the setting value written to the register 32 b. That is, it is possible to change the frequency characteristic of the low pass filter 22 by the set value written to the register 32 b.

  The multiplexer 23 supplies the four sensor signals input thereto to the AD converter in the order according to the set values written to the register 32 c. That is, it is possible to change the selection order of the sensor signals in the multiplexer 23, that is, the supply order of the sensor signals to the AD converter 24 by the setting value written to the register 32c.

  The AD converter 24 converts the sensor signal to a digital value at a cycle corresponding to the frequency of the pulse signal supplied from the frequency divider 26. The frequency divider 26 has a plurality of frequency divider circuits (not shown) that divide the input basic clock by different division ratios. The divider 26 supplies, to the AD converter 24, a pulse signal output from one divider circuit selected according to the set value written to the register 32d. That is, it is possible to change the AD conversion cycle in the AD converter 24 by the set value written to the register 32 d.

  The write control logic circuit 30 itself carries out the writing of the setting values to the registers 32a, 33b, 33c and 33d based on the command from the CPU 50. The CPU 50 may directly write the set values to the registers 32a, 32b, 32c and 32d. Further, although the configuration in which the registers 32a, 32b, 32c and 32d are arranged in the recording control logic circuit 30 is illustrated in the present embodiment, the present invention is not limited to this aspect. For example, the resistors 32 a, 32 b, 32 c and 32 d may be disposed in the vicinity of the in-amp 21, the low pass filter 22, the multiplexer 23 and the AD converter 24, respectively.

  In the data recording apparatus 100 according to the present embodiment, the memory 60 is configured separately from the LSI 10, so the data recording capacity is expanded and the memory 60 is accommodated inside the LSI 10, as compared with the case where the memory 60 is accommodated. It is possible to flexibly cope with the reduction. Further, since the RF communication module 41 and the UART 42 are configured separately from the LSI 10, the communication speed can be increased and the communication method can be changed as compared with the case where the communication module is accommodated inside the LSI 10. Etc. can be flexibly dealt with. On the other hand, components that are basically not supposed to be changed or expanded in function (instrument amplifier 21, low pass filter 22, multiplexer 23, AD converter 24, recording control logic circuit 30, and communication control logic circuit) As for 40), by integrating in LSI 10, it is possible to miniaturize the device without losing flexibility. In addition, by mounting the LSI 10, the CPU 50, and the memory 60 on the wiring substrate 1 in a bare chip state, the device can be miniaturized as compared to the case where these portions are configured as package components covered with a mold resin. Is possible.

  Further, according to the data recording device 100 according to the present embodiment, the amplification degree of the instrumentation amplifier 21, the frequency characteristic of the low pass filter 22, the selection order of sensor signals in the multiplexer 23, and the AD conversion cycle in the AD converter are variable. Therefore, it is possible to flexibly respond to various sensors and various events.

  Moreover, since amplification of the sensor signal output from the sensor 12 is performed using the instrumentation amplifier 21 which is not specialized to a specific sensor, it is possible to respond to various sensors. Further, for example, when amplification of a signal is insufficient only with the instrumentation amplifier 21 and a sensor signal having a sufficient signal level can not be obtained, the instrumentation amplifier 21 outside the LSI 10 as shown in FIG. This can be coped with by providing the pre-amplifier 13 in the previous stage of.

  Further, as shown in FIG. 6, a sensor drive circuit 14 for supplying a drive signal to the sensor 12 can be provided outside the LSI 10 as to a sensor that requires supply of a drive signal from the outside. In addition, an eddy current type displacement sensor is mentioned as an example of a sensor which needs supply of a drive signal. The eddy current displacement sensor generates high frequency magnetic field by flowing high frequency current through the sensor coil to generate eddy current on the surface of the sensing object, and the impedance of the sensor coil changes according to the distance between the sensor coil and the sensing object To detect changes in In the eddy current displacement sensor, it is necessary to externally supply a high frequency current flowing through the sensor coil as the drive signal.

  As described above, according to the data recording apparatus 100 according to the embodiment of the present invention, it is possible to achieve both the downsizing of the apparatus and the flexibility of data recording.

  FIG. 7A is a perspective view showing a schematic configuration of a data recording device 100A according to a second embodiment of the present invention. The data recording device 100A according to the second embodiment is different from the data recording device 100 according to the first embodiment in that the semiconductor chip forming the memory 60 is stacked on the semiconductor chip forming the LSI 10. . According to the data storage device 100A of the second embodiment, it is not necessary to form the wiring on both sides of the wiring substrate 1, so the configuration of the wiring substrate 1 can be simplified.

  FIG. 7B is a perspective view showing a configuration of a data recording device 100B according to a third embodiment of the present invention. The data recording device 100B according to the third embodiment includes a semiconductor chip that configures the LSI 10, a semiconductor chip that configures the CPU 50, a semiconductor chip that configures the memory 60, and the RF communication module 41 and the UART 42, respectively. It differs from the data recording device according to the first embodiment in that it is juxtaposed to different regions on the surface S1. According to the data storage device 100B in the third embodiment, the configuration of the wiring board 1 can be simplified, and the mounting of each semiconductor chip can be easily performed.

  FIG. 7C is a perspective view showing a configuration of a data recording device 100C according to a fourth embodiment of the present invention. The data recording device 100C according to the fourth embodiment includes the semiconductor chips constituting the LSI 10, the semiconductor chips constituting the CPU 50, and the semiconductor chips constituting the memory 60 respectively different substrate surfaces S1, S2 and S3 of different wiring boards. Is different from the data recording device according to the first embodiment in that it is mounted in the second embodiment. More specifically, the semiconductor chip constituting the CPU 50, the RF communication module 41 and the UART 42 are mounted on the substrate surface S1 of the wiring substrate 1A, and the semiconductor chip constituting the LSI 10 is opposite to the substrate surface S1 of the wiring substrate 1A. It is mounted on the substrate surface S2 on the side. The semiconductor chip constituting the memory 60 is mounted on the substrate surface S3 of the wiring substrate 1B different from the wiring substrate 1A. The data recording device 100C is configured by laminating the wiring boards 1A and 1B. According to the data storage device 100C of the fourth embodiment, the size of the data storage device can be further miniaturized.

  FIG. 7D is a perspective view showing a configuration of a data recording device 100D according to a fifth embodiment of the present invention. The data recording device 100D according to the fifth embodiment includes two memories 60A and 60B. More specifically, the semiconductor chip constituting the CPU 50, the semiconductor chip constituting the LSI 10, the RF communication module 41 and the UART 42 are mounted on the substrate surface S1 of the wiring substrate 1A. The semiconductor chip constituting the memory 60A is mounted on the substrate surface S3 of the wiring substrate 1B different from the wiring substrate 1A. The semiconductor chip constituting the memory 60B is mounted on the substrate surface S4 of the wiring substrate 1C different from the wiring substrates 1A and 1B. The data recording device 100D is configured by laminating the wiring boards 1A, 1B and 1C. According to the data storage device 100D of the fifth embodiment, it is possible to increase the memory capacity while suppressing the expansion of the size of the data storage device.

  FIG. 8 is a circuit block diagram showing an example of a circuit configuration of a data recording device 100D according to the fifth embodiment. The recording control logic circuit 30 controls recording and reading of data to the memories 60A and 60B based on an instruction from the CPU 50. Although the number of mounted memory chips is two in this embodiment, three or more memory chips may be mounted.

  FIG. 9 is a perspective view showing a schematic configuration of a data recording device 100E according to a sixth embodiment of the present invention. FIG. 10 is a circuit block diagram showing an example of a circuit configuration of a data recording device 100E according to the sixth embodiment. In FIG. 10, a plurality of sensors 12 connected to the data acquisition device 100E are shown together with the data acquisition device 100E. The data storage device 100E according to the sixth embodiment differs from the data storage device 100 according to the first embodiment in that the CPU 50 is accommodated in a semiconductor chip constituting the LSI 10. In the example shown in FIG. 9, the semiconductor chip including the CPU 50 and the LSI 10 is mounted on the substrate surface S1 of the wiring substrate 1, and the semiconductor chip forming the memory 60 is the surface S2 opposite to the substrate surface S1 of the wiring substrate 1. Mounted on the. According to the data recording device 100E of the sixth embodiment, the number of parts can be reduced as compared with the data recording device 100 of the first embodiment. Therefore, the number of steps can be reduced and the device can be further miniaturized. It is possible to Note that, according to the example shown in FIG. 7A, the semiconductor chip constituting the memory 60 may be stacked on the semiconductor chip including the CPU 50 and the LSI 10. Further, according to the example shown in FIG. 7B, the semiconductor chip including the CPU 50 and the LSI 10 and the semiconductor chip forming the memory 60 may be juxtaposed on the same substrate surface 1A of the wiring substrate 1. 7C, the semiconductor chip including the CPU 50 and the LSI 10 is mounted on the substrate surface S1 of the wiring substrate 1A, and the semiconductor chip constituting the memory 60 is a substrate of the wiring substrate 1B different from the wiring substrate 1A. It may be mounted on the surface S3. Further, according to the example shown in FIG. 7D, a wiring board on which a semiconductor chip including the CPU 50 and the LSI 10 is mounted, a wiring board 1B on which the memory 60A is mounted, and a wiring board 1C on which the memory 60B is mounted may be stacked.

1 Wiring board 10 LSI
12 sensor 21 instrumentation amplifier 22 low pass filter 23 multiplexer 24 AD converter 30 recording control logic 31 a to 31 d, 32 a to 32 d register 41 RF communication module 42 UART
50 CPU
60 Memory 100, 100A, 100B, 100C, 100D, 100E Data Recording Device

Claims (3)

An amplifier for amplifying a sensor signal output from the sensor;
An analog-to-digital converter that converts the sensor signal amplified by the amplifier into a digital value;
A recording control logic circuit for controlling the recording of the digital value;
A communication control logic circuit that controls communication with an external device;
A memory configured separately from the recording control logic circuit and the communication control logic circuit, and in which the digital value is recorded under control of the recording control logic circuit;
A communication module that is configured separately from the recording control logic circuit and the communication control logic circuit, and that communicates with the external device under the control of the communication control logic circuit;
A central processing unit that is configured separately from the recording control logic circuit and the communication control logic circuit and that gives instructions to the recording control logic circuit;
Including
The recording control logic circuit starts or stops recording of the digital value in the memory in response to a trigger signal supplied from the outside, and the digital value in the memory in response to a command to continue data recording. Status information indicating continuation of recording is recorded in the memory together with the digital value, and status information indicating interruption of recording of the digital value in the memory according to a command to interrupt data recording is also indicated together with the digital value Recording the digital value in the memory and interrupting the recording of the digital value in the memory according to a command to end the data recording, together with the digital value, the status information indicating the end of the recording of the digital value. A data recording device for terminating the recording of the digital value in the memory after the recording of the digital value . The trigger signal includes additional information,
The recording control logic circuit, when recording the digital values in the memory in response to the trigger signal, adds the additional information corresponding to each of the digital values and records the additional information in the memory. Data storage device. The recording control logic circuitry, data acquisition device according to claim 1 or claim 2 for controlling the recording order to the memory of the plurality of the digital values sequentially supplied from the analog-digital converter.