JP6958266B2 - Data recording device - Google Patents

Description

The present invention relates to a data recording device.

A data recording device that converts a sensor signal, which is an analog signal output from a sensor, into a digital value and records it in a memory is known. For example, Patent Document 1 describes a data recording device that records a signal input by a signal input means in a storage means when a trigger signal supplied from the outside is detected.

Further, there are known integrated circuits in which an analog circuit block, an analog-to-digital converter, a memory, a CPU, a communication interface, etc. are integrated into one chip and the internal circuit can be changed (for example, Non-Patent Document 1, Non-Patent Document 1, Non-Patent Document 1). Patent Document 2).

Japanese Unexamined Patent Publication No. 2005-274223

Smart Analog MCU (RL78 / G1E), [online], [Search on September 2, 2015], Internet <URL: http://japan.renesas.com/products/smart_analog/smart_analog_mcu/index.jsp> PSoC 5LP: CY8C58LP Family Database, [online], July 15, 2015, [Search September 2, 2015], Internet <URL: http://japan.cypress.com/file/45906/download>

The data recording device may include an AFE (Analog Front End) that handles analog signals such as sensor signals, a logic circuit that handles digital signals, a CPU (Central Processing Unit), and a memory. By stacking these components, it is possible to reduce the size of the data recording device. However, if the stacking order of these components is randomly determined, the analog signal wiring for incorporating the analog signal into the AFE becomes long, and the analog signal wiring and the digital signal wiring are in an intersecting state or a parallel state. This makes it easier for noise to be superimposed on the analog signal. In order to avoid this, if the analog signal wiring is arranged apart from the digital signal wiring, the area of the data recording device increases.

The present invention has been made in view of the above points, and an object of the present invention is to suppress the superposition of noise on an analog signal due to the proximity of the analog signal wiring and the digital signal wiring in the data recording device. ..

The data recording device according to the present invention is a first integrated circuit in which an amplifier that amplifies a sensor signal output from a sensor and an analog / digital converter that converts the sensor signal amplified by the amplifier into a digital value are integrated. A second integrated circuit is formed by integrating a first semiconductor chip in which the above is formed, a recording control logic circuit for controlling the recording of the digital value, and a communication control logic circuit for controlling communication with an external device. A second semiconductor chip, a third semiconductor chip in which a memory for recording the digital value is formed under the control of the recording control logic circuit, and a central arithmetic processing device that gives a command to the recording control logic circuit. The first semiconductor chip includes the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the first substrate on which the central arithmetic processing apparatus is mounted, and the first semiconductor chip is the first. The sensor signal input terminal is mounted on the first surface of the substrate or the inner layer of the first substrate adjacent to the first surface, and the input terminal of the sensor signal is provided on the first surface or the side surface of the first substrate. It is provided. An analog signal wiring provided between the input terminal of the sensor signal and the first semiconductor chip and into which the sensor signal is input is provided between the first to third semiconductor chips and the central arithmetic processing apparatus. It is configured to avoid crossing or paralleling with the digital signal wiring through which the digital signal transmitted / received in the above is passed.

The other data recording device according to the present invention is a first integrated device that integrates an amplifier that amplifies the sensor signal output from the sensor and an analog-digital converter that converts the sensor signal amplified by the amplifier into a digital value. A second integrated circuit that integrates a first semiconductor chip on which an integrated circuit is formed, a recording control logic circuit that controls recording of the digital value, and a communication control logic circuit that controls communication between an external device is provided. A central calculation that gives a command to the formed second semiconductor chip, the third semiconductor chip in which the memory in which the digital value is recorded under the control of the recording control logic circuit is formed, and the recording control logic circuit. On a processing apparatus, a first substrate on which the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the central arithmetic processing apparatus are mounted, and a first surface of the first substrate. The first semiconductor chip including the bonded second substrate is mounted on the inner layer of the first surface or the first substrate adjacent to the first surface, and the sensor signal is input. The terminals are provided on the second substrate. An analog signal wiring provided between the input terminal of the sensor signal and the first semiconductor chip and into which the sensor signal is input is provided between the first to third semiconductor chips and the central arithmetic processing apparatus. It is configured to avoid crossing or paralleling with the digital signal wiring through which the digital signal transmitted / received in the above is passed.

The first semiconductor chip may have a port into which the sensor signal is input, and the first substrate has a land pattern including a land connected to the port on the first surface. You may be doing it. The second substrate may have a corresponding land pattern corresponding to the land pattern on the joint surface with the first substrate, including the land connected to the input terminal.

The data recording device according to the present invention may further include a first circuit element provided on the second substrate and constituting a preprocessing circuit for preprocessing the sensor signal.

The data recording device according to the present invention is provided on the first substrate and is associated with at least one of the first integrated circuit, the second integrated circuit, and the central processing unit. May further be included.

The second substrate may be joined to the first surface so as to partially expose the first surface, and the second circuit element is attached to the exposed portion of the first surface. It may be installed. Further, the first semiconductor chip may be mounted on the exposed portion of the first surface.

The data recording device according to the present invention may further include a communication module that communicates with the external device under the control of the communication control logic circuit.

The data recording device according to the present invention is a third substrate on which the communication module is mounted and joined to the first surface of the first substrate or a second surface opposite to the first surface. May further be included. The first circuit element and the communication module may be provided on the surface of the second substrate opposite to the bonding surface with the first substrate.

The data recording device according to the present invention may further include a fourth semiconductor chip mounted on the inner layer of the first substrate and on which the central processing unit is formed.

According to the present invention, in the data recording device, it is possible to suppress the superposition of noise on the analog signal due to the proximity of the analog signal wiring and the digital signal wiring.

It is a circuit block diagram which shows an example of the circuit structure of the data recording apparatus which concerns on 1st Embodiment of this invention. It is a perspective view which shows the structure of the data recording apparatus which concerns on 1st Embodiment of this invention. It is a figure which shows the variation of the laminated structure of the AFE, the memory, the CPU and the logic circuit which concerns on embodiment of this invention. It is a figure which shows the variation of the laminated structure of the AFE, the memory, the CPU and the logic circuit which concerns on embodiment of this invention. It is a figure which shows the variation of the laminated structure of the AFE, the memory, the CPU and the logic circuit which concerns on embodiment of this invention. It is a figure which shows the variation of the laminated structure of the AFE, the memory, the CPU and the logic circuit which concerns on embodiment of this invention. It is a figure which shows the variation of the laminated structure of the AFE, the memory, the CPU and the logic circuit which concerns on embodiment of this invention. It is a figure which shows the variation of the laminated structure of the AFE, the memory, the CPU and the logic circuit which concerns on embodiment of this invention. It is a figure which shows the laminated structure which concerns on a comparative example. It is a figure which shows the laminated structure which concerns on a comparative example. It is a figure which shows the laminated structure which concerns on a comparative example. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a circuit block diagram which shows an example of the circuit structure of the data recording apparatus which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows an example of the structure of the pretreatment circuit which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows another example of the structure of the pretreatment circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows an example of the circuit element which concerns on 2nd Embodiment of this invention. It is a figure which shows an example of the circuit element which concerns on 2nd Embodiment of this invention. It is a perspective view which shows the structure of the data recording apparatus which concerns on 2nd Embodiment of this invention. It is a perspective view which showed the two wiring boards which concerns on 2nd Embodiment of this invention separately. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification. It is a perspective view which shows the structure of the data recording apparatus which concerns on a modification.

Hereinafter, an example of the embodiment of the present invention will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are designated by the same reference numerals, and duplicate description will be omitted as appropriate.

[First Embodiment]
FIG. 1 is a circuit block diagram showing an example of the circuit configuration of the data recording device 100 according to the first embodiment of the present invention. FIG. 2 is a perspective view showing the configuration of the data recording device 100. In FIG. 1, a plurality of sensors 12 connected to the data recording device 100 are shown together with the data recording device 100.

The data recording device 100 includes an AFE (Analog Front End) 10, a logic circuit 300, an RF (Radio Frequency) communication module 41, a UART (Universal Asynchronous Receiver Transmitter) 42, and a CPU (Central Processing Unit) 50 mounted on the wiring board 1. And the memory 60 are included in the configuration.

The data recording device 100 converts the sensor signal output from the sensor 12 into a digital value and records it in the memory 60 to meet a request from an external device (for example, a personal computer communicably connected to the data recording device 100). The main function is to transmit the sensor signal value recorded in the memory 60 to the external device accordingly. As the sensor 12 connected to the data recording device 100, any sensor such as a pressure sensor, an acceleration sensor, a displacement sensor, a voltage sensor, a temperature sensor, and a strain sensor can be assumed.

The AFE 10 is an integrated circuit in which an instrumentation amplifier 21, a low-pass filter 22, a multiplexer 23, and an analog-to-digital converter (hereinafter referred to as an AD converter) 24 are integrated on a single semiconductor chip. As an example, the AFE 10 has 16 sensor signal input channels, and 16 sensors 12 can be connected to the AFE 10. The sensor signals output from each of the plurality of sensors 12 are supplied to the AFE 10 via the input terminal 90 provided on the wiring board 1 and the sensor signal input port 91 provided on the semiconductor chip constituting the AFE 10. ..

The instrumentation amplifier 21 and the low-pass filter 22 are provided corresponding to each of the 16 sensors 12. Each of the instrumentation amplifiers 21 amplifies the sensor signal output from the corresponding sensor 12. The low-pass filter 22 removes high frequency components (noise) from the corresponding sensor signal amplified by the instrumentation amplifier 21. If the high frequency component does not matter from the sensor signal, the low-pass filter 22 may be omitted.

One multiplexer 23 and one AD converter 24 are provided for each of the four input channels. Each of the multiplexers 23 sequentially selects the sensor signals output from the four corresponding low-pass filters 22, and supplies the selected sensor signals to the AD converter 24.

The AD converter 24 converts a sensor signal, which is an analog signal sequentially supplied from the multiplexer 23, into a digital value. The sensor signal value converted into a digital value by the AD converter 24 is supplied to the recording control logic circuit 30 described later. Instead of sharing the AD converter 24 with a plurality of input channels, an AD converter 24 is provided for each input channel, and the sensor signals output from the low-pass filter 22 are directly received by the corresponding AD converter 24. It may be configured. In this case, the multiplexer 23 becomes unnecessary.

The logic circuit 300 is an integrated circuit in which the recording control logic circuit 30 and the communication control logic circuit 40 are integrated on a single semiconductor chip separate from the AEF 10. The logic circuit 300 is a programmable logic device such as a CPLD (Complex Programmable Logic Device) or an FPGA (Field Programmable Gate Array), and the logic configuration of the recording control logic circuit 30 and the communication control logic circuit 40 can be programmed by an external designation. Is. Therefore, the logic configurations of the recording control logic circuit 30 and the communication control logic circuit 40 can be changed ex post facto by programming.

The recording control logic circuit 30 performs various operations based on the commands supplied from the CPU 50. When a command to record data is issued from the CPU 50, the recording control logic circuit 30 operates the multiplexer 23 and the AD converter 24 by supplying control signals, and sequentially supplies the data from the AD converter 24. The process of recording the sensor signal value to be recorded in the memory 60 is performed. On the other hand, when a command to read data is issued from the CPU 50, the recording control logic circuit 30 reads the sensor signal value recorded in the memory 60, and causes the communication control logic circuit 40 and the RF communication module 41 or UART 42. The sensor signal value read out via the device is transmitted to an external device. Further, the recording control logic circuit 30 adds to the sensor signal value sequentially supplied from the AD converter 24 or the sensor signal value when a command to transmit data is issued from the CPU 50 to the external device. The data to which the information is added is transmitted to the external device via the communication control logic circuit 40 without going through the memory 60. The recording control logic circuit 30 can perform recording control of the digital value supplied from the AD converter 24 for the memory 60 and transmission control for the external device in parallel based on a command from the CPU 50. Further, the recording control logic circuit 30 can set a priority for recording data in the memory 60 and transmitting data to an external device. For example, when the priority set for recording data to the memory 60 is lower than the priority set for transmitting data to the external device, the digital value supplied from the AD converter 24 is thinned out and recorded in the memory 60. You may.

The communication control logic circuit 40 is a circuit block that controls communication with an external device. The communication control logic circuit 40 uses, for example, a sensor signal value read from the memory 60 supplied from the recording control logic circuit 30, a sensor signal value directly supplied from the AD converter 24, or additional information. The added data is transmitted to an external device via the RF communication module 41 or UART 42 according to a predetermined communication protocol. Based on the command from the CPU 50, the communication control logic circuit 40 transmits the sensor signal value or data to which additional information is added to the external device via either or both of the RF communication module 41 and the UART 42. Further, the communication control logic circuit 40 supplies commands and information supplied from an external device via the RF communication module 41 or UART 42 to the CPU 50.

The memory 60 is a recording medium for recording the sensor signal value output from the sensor 12 and converted into a digital value. The memory 60 is a non-volatile recording medium capable of writing, erasing, and rewriting data. The memory 60 may be, for example, a NAND flash memory. The memory 60 is configured as a semiconductor chip separate from the semiconductor chip constituting the AFE 10 and the semiconductor chip constituting the logic circuit 300, and is connected to the recording control logic circuit 30 via the data input / output port 93 of the logic circuit 300. It is connected.

The RF communication module 41 is a communication module for performing wireless communication with an external device under the control of the communication control logic circuit 40. The RF communication module 41 may be configured as a package component separate from the semiconductor chip constituting the AFE 10 and the semiconductor chip constituting the logic circuit 300. The RF communication module 41 is connected to the communication control logic circuit 40 via the communication port 95 of the logic circuit 300.

The UART 42 is a communication module for performing wired communication with an external device under the control of the communication control logic circuit 40. The UART 42 has a function of converting data of the serial transfer method and data of the parallel transfer method to each other. The UART 42 may be configured as a package component separate from the semiconductor chip constituting the AFE 10 and the semiconductor chip constituting the logic circuit 300. The UART 42 is connected to the communication control logic circuit 40 via the communication port 96 of the logic circuit 300. In the present embodiment, as a communication module for communicating with an external device, a configuration including both the RF communication module 41 and the UART 42 is illustrated, but a configuration including only one of the RF communication module 41 and the UART 42 is provided. May be. Further, when the functions corresponding to the RF communication module 41 and the UART 42 are provided in the external device linked with the data recording device 100, these can be reduced from the data recording device 100.

The CPU 50 is a central processing unit that comprehensively controls the operation of the data recording device 100. The CPU 50 controls data recording and data reading by sending a command to the recording control logic circuit 30. Further, the CPU 50 controls communication with the external device by sending a command to the communication control logic circuit 40. The CPU 50 is configured as a semiconductor chip separate from the semiconductor chip constituting the AFE 10, the semiconductor chip constituting the logic circuit 300, and the semiconductor chip constituting the memory 60. The CPU 50 is connected to the communication control logic circuit 40 via the communication port 97 of the logic circuit 300, and is connected to the recording control logic circuit 30 via the communication port 98 of the logic circuit 300.

The data recording device 100 can perform synchronization processing for matching the held data with an external device (for example, another data recording device) connected to the communication port 92.

Further, the data recording device 100 can control the start and stop timings of data recording from the outside by supplying the trigger signal St from the outside. The logic circuit 300 has a port 94 for inputting a trigger signal that receives an input of a trigger signal St supplied from an external device. The trigger signal St input to the logic circuit 300 via the port 94 is received by the recording control logic circuit 30. The recording control logic circuit 30 starts or stops recording of the sensor signal value according to the received trigger signal St.

The trigger signal St can include additional information, and this additional information can be recorded in the memory 60 together with the sensor signal value. Examples of the additional information include time information, environmental information such as temperature, humidity, and atmospheric pressure of the object (hereinafter referred to as the sensing object) sensed by the sensor 12, and information on the state of the sensing object. For example, when the sensing object is a moving body that moves on a predetermined movement path, it is possible to include the position information indicating the position of the sensing object on the movement path in the trigger signal as additional information. The additional information may be a digital signal integrated with the trigger signal and may be supplied to the data recording device 100 in the form of, for example, an optical signal or a radio signal.

When the recording control logic circuit 30 records the sensor signal value in the memory 60 in response to the trigger signal St including the additional information, the recording control logic circuit 30 adds the corresponding additional information to each of the sensor signal values sequentially supplied from the AD converter 24. It is added and recorded in the memory 60. In this way, by including the additional information in each of the sensor signal values recorded in the memory 60, it is possible to record the additional information at the time of acquisition of the sensor signals sequentially output from the sensor 12 together with the sensor signal values. Become. It should be noted that a plurality of sensor signal values supplied from the AD converter 24 within a predetermined period to which one common additional information is added may be recorded in the memory 60 as one data set. According to this aspect, the amount of data recorded in the memory 60 can be reduced as compared with the case where additional information is included in each of the sensor signal values. Further, the recording control logic circuit 30 is added to the trigger signal St when the sensor signal values sequentially supplied from the AD converter 24 are transmitted to the external device via the communication control logic circuit 40 without going through the memory 60. It is also possible to transmit the additional information to an external device in addition to the sensor signal value.

Further, the recording control logic circuit 30 records the status information indicating the continuation, interruption and termination of the recording of the sensor signal value supplied from the AD converter 24 in the memory 60 in the memory 60 together with the sensor signal value. Commands regarding continuation, interruption, and termination of recording of the sensor signal value in the memory 60 are supplied from the CPU 50 to the recording control logic circuit 30.

The recording control logic circuit 30 adds status information indicating “ongoing” of data recording to the sensor signal value supplied from the AD converter 24 while the CPU 50 issues a command to continue data recording. The sensor signal value is recorded in the memory 60. When the CPU 50 issues a command to interrupt data recording, the recording control logic circuit 30 adds status information indicating "interruption" of data recording to the sensor signal value supplied from the AD converter 24. After recording the sensor signal value in the memory 60, data recording is interrupted. That is, status information indicating "interruption" of data recording is added to the sensor signal value recorded in the memory 60 immediately before the data recording is interrupted. When the CPU 50 issues a command to end data recording, the recording control logic circuit 30 adds status information indicating "end" of data recording to the sensor signal value supplied from the AD converter 24. After recording the sensor signal value in the memory 60, data recording is terminated. That is, status information indicating "end" of data recording is added to the sensor signal value recorded in the memory 60 immediately before the end of data recording.

By including the status information in each of the sensor signal values recorded in the memory 60 in this way, it is possible to record the data recording process together with the sensor signal values. When the recording control logic circuit 30 records the sensor signal value in the memory 60 in response to the trigger signal St including the above-mentioned additional information, the recording control logic circuit 30 stores a data set including one or more sensor signal values, additional information, and status information. Record in memory 60. In this case, the CPU 50 determines the continuation, interruption, and end of data recording by cooperating with an external device that outputs the trigger signal St.

Further, the recording control logic circuit 30 controls the recording order of the plurality of sensor signal values sequentially supplied from each of the AD converters 24 in the memory 60 based on the command from the CPU 50. That is, the recording control logic circuit 30 can record a plurality of sensor signal values in the memory 60 in an order different from the order supplied from each of the AD converters 24.

Among the components of the data recording device 100, the AFE 10, the logic circuit 300, the CPU 50, and the memory 60 are each composed of separate semiconductor chips, and are mounted on the wiring board 1 in a chip state not covered with the mold resin. .. The AFE 10, the logic circuit 300, the CPU 50, and the memory 60 may be covered with a protective film made of a resin or the like for protecting them from mechanical stress and thermal stress, respectively. The RF communication module 41 and the UART 42 are configured as package components separate from the semiconductor chips constituting the AFE 10, the logic circuit 300, the CPU 50, and the memory 60. The RF communication module 41 and the UART 42 may be in a chip state not covered with the mold resin.

As shown in FIG. 2, the logic circuit 300, the RF communication module 41, and the UART 42 are mounted on the upper surface S1 of the wiring board 1, respectively. The AFE 10, the memory 60, and the CPU 50 are each provided in the inner layer of the wiring board 1. The wiring board 1 has a multi-layer structure, and the AFE 10, the memory 60, and the CPU 50 are mounted in a laminated state inside the wiring board 1. The AFE 10 is mounted on the lowest layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The memory 60 is mounted on a layer one layer above the layer on which the AFE 10 is mounted. The CPU 50 is mounted on a layer one layer above the layer on which the memory 60 is mounted. Each component mounted on the wiring board 1 passes through the wiring provided on the upper surface S1 and the lower surface S2 of the wiring board 1, the wiring provided on the inner layer of the wiring board 1, and vias (none of which are shown). It is electrically connected to other components. An input terminal 90 into which a sensor signal output from the sensor 12 is input is provided on the lower surface S2 of the wiring board 1. The input terminal 90 is connected to the port 91 of the AFE 10 via a wiring (not shown) provided on the lower surface S2 of the wiring board 1 and a via (not shown) provided inside the wiring board 1.

As described above, in the data recording apparatus 100, the AFE 10, the memory 60, the CPU 50, and the logic circuit 300 are mounted on the wiring board 1 in a state in which these components are laminated. Among these components, the AFE 10 is mounted on the lower layer of the plurality of inner layers included in the wiring board 1, and the sensor signal input terminal 90 is mounted on the lower surface S2 of the wiring board 1 adjacent to the lower layer on which the AFE 10 is mounted. It is provided in. The analog signal wiring through which the sensor signal, which is an analog signal, passes is provided between the input terminal 90 and the port 91 of the AFE 10.

In the data recording device 100 configured by stacking a plurality of components in this way, the AFE 10 is arranged at the end of the components in the stacking direction, and the input terminal 90 into which the sensor signal is input is the AFE 10. By providing it on the nearest board surface, it is possible to prevent the analog signal wiring from being close to the digital signal wiring. Further, it is possible to prevent the analog signal wiring and the digital signal wiring from being in an intersecting state or a parallel state. Therefore, it is possible to suppress the superposition of noise on the sensor signal which is an analog signal.

3A to 3F are diagrams showing variations in the laminated configuration of the AFE 10, the memory 60, the CPU 50, and the logic circuit 300 according to the embodiment of the present invention. In FIGS. 3A to 3F, among the signal wirings connected to each component, the analog signal wiring through which the analog signal passes is shown by a solid line, and the digital signal wiring through which the digital signal passes is shown by a dotted line. Note that FIG. 3A corresponds to the configuration of the data recording device 100 shown in FIG.

4A to 4C are diagrams showing a laminated structure according to a comparative example. As shown in FIGS. 4A to 4C, when the AFE 10 is arranged in the intermediate layer of the wiring board 1 and is arranged between other components, the length of the analog signal wiring from the input terminal 90 to the AFE 10 is increased. It cannot be the shortest, and the digital signal wiring penetrating the layers of the wiring board 1 and the analog signal wiring are close to each other and are in an intersecting state or a parallel state. This makes it easier for noise to be superimposed on the sensor signal, which is an analog signal. Further, when the analog signal wiring is arranged apart from the digital signal wiring in order to suppress the superposition of noise on the sensor signal, the size of the data recording device becomes large. Further, when the shield layer 200 is provided between the AFE 10 and other components in order to suppress the superposition of noise on the sensor signal, it is necessary to provide the shield layer 200 on both the upper layer side and the lower layer side of the AFE 10. , The thickness of the wiring board 1 becomes thicker.

On the other hand, according to the laminated configuration according to the embodiment of the present invention shown in FIGS. 3A to 3F, the AFE 10 is arranged at the end of the component in the laminated direction, and the input terminal 90 is placed on the surface of the substrate closest to the AFE 10. Since it is provided, the length of the analog signal wiring from the input terminal 90 to the AFE 10 can be minimized, and the digital signal wiring penetrating the layers of the wiring board 1 and the analog signal wiring are close to each other. It is possible to avoid being in a crossed state or a parallel state. As a result, it is possible to suppress the superposition of noise on the sensor signal. Further, when the shield layer 200 is provided between the AFE 10 and other components, it is sufficient to provide the shield layer 200 only on one side of the AFE 10, so that wiring is performed as compared with the case where the laminated configuration according to the comparative example is adopted. The thickness of the substrate 1 can be reduced.

FIG. 5 is a perspective view showing the configuration of the data recording device 100A according to the modified example. The data recording device 100A is different from the data recording device 100 (see FIG. 2) in that the input terminal 90 into which the sensor signal is input is provided on the side surface S10 of the wiring board 1.

FIG. 6 is a perspective view showing the configuration of the data recording device 100B according to the modified example. The data recording device 100B includes a wiring board 2 joined to the lower surface S2 of the wiring board 1. The upper surface S3 of the wiring board 2 is provided with an RF communication module 41, a UART 42, and an input terminal 90 into which a sensor signal is input. A land pattern including a land (not shown) connected to a port 91 for inputting a sensor signal is provided on the lower surface S2 of the wiring board 1, and a land of the wiring board 1 is provided on the upper surface S3 of the wiring board 2. Corresponding land patterns corresponding to the patterns, and wiring (not shown) for connecting the lands included in the corresponding land patterns and the input terminal 90 are provided.

FIG. 7 is a perspective view showing the configuration of the data recording device 100C according to the modified example. The data recording device 100C includes a wiring board 8 connected to the wiring board 1 via a connection board 9. The RF communication module 41 and the UART 42 are mounted on the upper surface S11 of the wiring board 8. The connection substrate 9 may be, for example, a flexible substrate made of a plastic film and having flexibility.

FIG. 8 is a perspective view showing the configuration of the data recording device 100D according to the modified example. The data recording device 100D is different from the data recording device 100 (see FIG. 2) in that it includes two memories 60A and 60B in the inner layer of the wiring board 1 and the laminated configuration of each component. That is, in the data recording device 100D, the AFE 10 is mounted on the lowest layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The CPU 50 is mounted on a layer one layer above the layer on which the AFE 10 is mounted. The memory 60A is mounted on a layer one layer above the layer on which the CPU 50 is mounted. The memory 60B is mounted on a layer immediately above the layer on which the memory 60A is mounted. The logic circuit 300, the RF communication module 41, and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminal 90 is provided on the lower surface S2 of the wiring board 1.

FIG. 9 is a perspective view showing the configuration of the data recording device 100E according to the modified example. The data recording device 100E is different from the data recording device 100 (see FIG. 2) in that it includes two memories 60A and 60B in the inner layer of the wiring board 1 and the laminated configuration of each component. That is, in the data recording device 100E, the AFE 10 is mounted on the lowest layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The CPU 50 is mounted on a layer one layer above the layer on which the AFE 10 is mounted. The logic circuit 300 is mounted on a layer one layer above the layer on which the CPU 50 is mounted. The memory 60A is mounted on a layer one layer above the layer on which the logic circuit 300 is mounted. The memory 60B is mounted on a layer immediately above the layer on which the memory 60A is mounted. The RF communication module 41 and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminal 90 is provided on the lower surface S2 of the wiring board 1.

FIG. 10 is a perspective view showing the configuration of the data recording device 100F according to the modified example. The data recording device 100F differs from the data recording device 100 (see FIG. 2) in the laminated configuration of each component. That is, in the data recording device 100F, the AFE 10 is mounted on the lowest layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The logic circuit 300 is mounted on a layer one layer above the layer on which the AFE 10 is mounted. The CPU 50 is mounted on a layer one layer above the layer on which the logic circuit 300 is mounted. The memory 60 is mounted on a layer one layer above the layer on which the CPU 50 is mounted. The RF communication module 41 and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminal 90 is provided on the lower surface S2 of the wiring board 1.

FIG. 11 is a perspective view showing the configuration of the data recording device 100G according to the modified example. The data recording device 100G is different from the data recording device 100 (see FIG. 2) in that the inner layer of the wiring board 1 includes two AFE10A and 10B and two memories 60A and 60B, and the laminated configuration of each component. That is, in the data recording apparatus 100G, the AFE 10A and 10B are mounted in a juxtaposed state in the lowermost layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The logic circuit 300 and the CPU 50 are mounted in a state of being juxtaposed on a layer one layer above the layer on which the AFE 10A and 10B are mounted. The memories 60A and 60B are mounted in a state of being juxtaposed on a layer one layer above the layer on which the logic circuit 300 and the CPU 50 are mounted. The RF communication module 41 and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminals 90A and 90B are provided on the lower surface S2 of the wiring board 1. The input terminal 90A corresponding to AFE10A is arranged in the vicinity of AFE10A, and the input terminal 90B corresponding to AFE10B is arranged in the vicinity of AFE10B.

FIG. 12 is a perspective view showing the configuration of the data recording device 100H according to the modified example. The data recording device 100H differs from the data recording device 100 (see FIG. 2) in the laminated configuration of each component. That is, in the data recording device 100H, the AFE 10 is mounted on the lower surface S2 of the wiring board 1. The logic circuit 300 is mounted on the lowermost layer of the inner layer of the wiring board 1 adjacent to the lower surface S2. The CPU 50 is mounted on a layer one layer above the layer on which the logic circuit 300 is mounted. The memory 60 is mounted on a layer one layer above the layer on which the CPU 50 is mounted. The RF communication module 41 and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminal 90 is provided on the lower surface S2 of the wiring board 1.

FIG. 13 is a perspective view showing the configuration of the data recording device 100I according to the modified example. The data recording device 100I has a different laminated structure of each component from the data recording device 100 (see FIG. 2). That is, in the data recording device 100I, the AFE 10 is mounted on the lower surface S2 of the wiring board 1. The memory 60 is mounted on the lowermost layer of the inner layer of the wiring board 1 adjacent to the lower surface S2. The CPU 50 is mounted on a layer one layer above the layer on which the memory 60 is mounted. The logic circuit 300, the RF communication module 41, and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminal 90 is provided on the lower surface S2 of the wiring board 1.

FIG. 14 is a perspective view showing the configuration of the data recording device 100J according to the modified example. In the data recording device 100J, the logic circuit 300 and the CPU 50 are composed of a single semiconductor chip, and the point that this semiconductor chip is mounted on the upper surface S1 of the wiring board 1 is the data recording device 100 (see FIG. 2). Different from.

FIG. 15 is a perspective view showing the configuration of the data recording device 100K according to the modified example. The data recording device 100K differs from the data recording device 100 (see FIG. 2) in the laminated configuration of each component. That is, in the data recording device 100K, the AFE 10 and the logic circuit 300 are mounted on the lowest layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The memory 60 and the CPU 50 are mounted on a layer immediately above the layer on which the AFE 10 and the logic circuit 300 are mounted. The RF communication module 41 and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminal 90 is provided near the AFE 10 on the lower surface S2 of the wiring board 1.

FIG. 16 is a perspective view showing the configuration of the data recording device 100L according to the modified example. The data recording device 100L is different from the data recording device 100 (see FIG. 2) in that it includes two memories 60A and 60B and the laminated configuration of each component. That is, in the data recording device 100, the AFE 10 and the CPU 50 are mounted on the lowest layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The memories 60A and 60B are mounted on the layer immediately above the layer on which the AFE10 and the CPU 50 are mounted. The logic circuit 300, the RF communication module 41, and the UART 42 are mounted on the upper surface S1 of the wiring board 1. The sensor signal input terminal 90 is provided near the AFE 10 on the lower surface S2 of the wiring board 1.

According to the data recording devices 100A to 100L according to the above modification, the AFE10 (AFE10A, 10B) is arranged at the end in the stacking direction of the components, and the sensor signal is transmitted, similarly to the data recording device 100 (see FIG. 2). Since the input input terminals 90 (90A, 90B) are provided on the substrate surface closest to the AFE10 (AFE10A, 10B), the analog signal wiring from the input terminals 90 (90A, 90B) to the AFE10 (AFE10A, 10B). It is possible to minimize the length of the data, and it is possible to prevent the digital signal wiring penetrating the layers of the wiring board 1 and the analog signal wiring from being close to each other and being in an intersecting state or a parallel state. As a result, it is possible to suppress the superposition of noise on the sensor signal. The arrangement of each component is not limited to the one shown in the figure, and can be appropriately modified.

[Second Embodiment]
FIG. 17 is a circuit block diagram showing an example of the circuit configuration of the data recording device 101 according to the second embodiment of the present invention. In FIG. 17, a plurality of sensors 12 connected to the data recording device 101 are shown together with the data recording device 101. The data recording device 101 is different from the data recording device 100 (see FIG. 1) according to the first embodiment in that the preprocessing circuit 110 and the circuit element 120 are further included.

The preprocessing circuit 110 is a circuit that performs predetermined preprocessing on the sensor signal output from the sensor 12, and is provided corresponding to each of the plurality of sensors 12. The sensor signal preprocessed by the preprocessing circuit 110 is input to the AFE 10 via the sensor signal input port 91.

FIG. 18 is a circuit diagram showing an example of the configuration of the preprocessing circuit 110. FIG. 18 shows a preprocessing circuit 110 that preprocesses the output signal of the distortion gauge 12a as the sensor 12. The preprocessing circuit 110 includes a plurality of resistance elements and circuit elements 111 such as capacitors connected to the strain gauge 12a.

FIG. 19 is a circuit diagram showing another example of the configuration of the preprocessing circuit 110. FIG. 19 shows a preprocessing circuit 110 that preprocesses the output signal of the thermocouple 12b as the sensor 12. The pretreatment circuit 110 includes a plurality of resistance elements and circuit elements 111 such as capacitors connected to the thermocouple 12b.

On the other hand, the circuit element 120 is an electronic component attached to each of the AFE 10, the CPU 50, and the logic circuit 300, and is mounted on the wiring board 1 as an external component of the semiconductor chip constituting the AFE 10, the CPU 50, and the logic circuit 300.

20 and 21 are diagrams showing an example of the circuit element 120, respectively. Note that FIGS. 20 and 21 show a circuit element 120 attached to the logic circuit 300 as an example. The circuit element 120 may be a capacitor and a crystal oscillator connected to an AFE 10, a CPU 50, a power supply circuit constituting the logic circuit 300, a reference voltage circuit, a clock generation circuit, and the like.

FIG. 22 is a perspective view showing the configuration of the data recording device 101 according to the present embodiment. In the present embodiment, the logic circuit 300 is mounted on the upper surface S1 of the wiring board 1. The AFE 10, the memory 60, and the CPU 50 are each provided in the inner layer of the wiring board 1. The wiring board 1 has a multi-layer structure, and the AFE 10, the memory 60, and the CPU 50 are mounted in a laminated state inside the wiring board 1. The AFE 10 is mounted on the lowest layer adjacent to the lower surface S2 of the wiring board 1 among the plurality of inner layers included in the wiring board 1. The CPU 50 is mounted on a layer one layer above the layer on which the AFE 10 is mounted. The memory 60 is mounted on a layer one layer above the layer on which the CPU 50 is mounted. A plurality of circuit elements 120 and a logic circuit 300 attached to each of the AFE 10, the CPU 50, and the logic circuit 300 are mounted on the upper surface S1 of the wiring board 1.

The data recording device 101 includes a wiring board 2 joined to the lower surface S2 of the wiring board 1. The upper surface S3 of the wiring board 2 is provided with an RF communication module 41, a UART 42, an input terminal 90 into which a sensor signal is input, and a plurality of circuit elements 111 constituting a preprocessing circuit 110.

FIG. 23 is a perspective view showing the wiring board 1 and the wiring board 2 separately. As shown in FIG. 23, a land pattern 130 including a land connected to a port 91 for inputting a sensor signal of the AFE 10 is provided on the lower surface S2 of the wiring board 1. The corresponding land pattern 140 corresponding to the land pattern 130, the wiring connecting the corresponding land pattern 140 and the circuit element 111 (not shown), and the circuit element 111 and the input terminal 90 are connected to the upper surface S3 of the wiring board 2. Wiring (not shown) is provided.

According to the data recording device 101 according to the present embodiment, similarly to the data recording device 100 according to the first embodiment, the AFE 10 is arranged at the end of the component in the stacking direction, and the input terminal 90 into which the sensor signal is input. Is provided on the surface of the board closest to the AFE 10, so that the length of the analog signal wiring from the input terminal 90 to the AFE 10 can be minimized, and the digital signal wiring penetrating the layers of the wiring board 1 and the analog signal wiring. It is possible to prevent the signal wirings from being close to each other and being in an intersecting state or a parallel state. As a result, it is possible to suppress the superposition of noise on the sensor signal.

Further, according to the data recording device 101, a plurality of circuit elements 111 constituting the preprocessing circuit 110 are mounted on a wiring board 2 different from the wiring board 1. The configuration of the preprocessing circuit 110 needs to be changed according to the type of the sensor 12. However, by mounting the preprocessing circuit 110 on a wiring board 2 different from the wiring board 1, the wiring board 1 is configured. Can be fixed. That is, by mounting the circuit element 111 on a wiring board 2 separate from the wiring board 1, the wiring board 1 on which the AFE 10, the logic circuit 300, the CPU 50, and the memory 60 are mounted can be used as a general-purpose module applicable to all sensors. Can be configured. As a result, the wiring board 1 can be mass-produced, and the manufacturing cost can be suppressed.

On the other hand, the preprocessing circuit 110 can be configured with the minimum number of elements suitable for the sensor, and the customized portion is minimized in the small-lot, high-mix production, so that the manufacturing cost can be suppressed. As described above, the manufacturing cost can be minimized by combining the wiring board 1 as a general-purpose module that can be expected to have a mass production effect and the wiring board 2 as a customized module of the minimum element suitable for the sensor.

Further, the wiring board 1 on which the AFE 10, the logic circuit 300, the CPU 50 and the memory 60 are mounted is always prepared by mass production, and the wiring board 2 is composed of the minimum elements, so that the design and manufacture can be performed in a short period of time. It is possible.

Here, in order to support a plurality of types of sensors, a plurality of types of preprocessing circuits 110 are mounted on a wiring board 1 on which an AFE 10, a logic circuit 300, a CPU 50, and a memory 60 are mounted, and any one of these is mounted. It is also conceivable to selectively use the kind of pretreatment circuit 110. However, in this case, since the system has a redundant configuration, the system size becomes large and the cost increases.

Further, if the pretreatment circuit 110 is mounted on the wiring board 1 by defining the mounting space of the pretreatment circuit 110, it becomes difficult to minimize the system size. The mounting area required for mounting the preprocessing circuit 110 on the wiring board 1 is larger than the mountable area of the circuit element of the wiring board 1 when only each semiconductor chip and the circuit element 120 associated therewith are mounted. If it is also large, it becomes necessary to increase the area of the wiring board 1 in order to secure a space for mounting the preprocessing circuit 110. It is conceivable that the pretreatment circuit 110 is provided not only on the surface of the wiring board 1 but also on the inner layer, but the heights of the circuit elements 111 constituting the pretreatment circuit 110 vary, and the circuit element 111 is provided on the inner layer of the wiring board 1. If this is provided, the thickness of the wiring board 1 becomes thick, and it becomes difficult to achieve miniaturization of the data recording device. On the other hand, according to the data recording device 101 according to the embodiment of the present invention, each of the wiring board 1 on which the AFE 10, the logic circuit 300, the CPU 50 and the memory 60 are mounted and the wiring board 2 on which the preprocessing circuit 110 is mounted has the minimum size. Since it can be configured with, the size of the entire system can be minimized.

FIG. 24 is a perspective view showing the configuration of the data recording device 101A according to the modified example. The data recording device 101A differs from the data recording device 101 (see FIG. 22) in that a plurality of circuit elements 111, a communication module 41, and a UART 42 constituting the preprocessing circuit 110 are provided on the lower surface S4 of the wiring board 2. .. By providing the plurality of circuit elements 111, the communication module 41, and the UART 42 on the lower surface S4 of the wiring board 2, the area of the wiring board 2 can be reduced as compared with the data recording device 101 (see FIG. 22).

FIG. 25 is a perspective view showing the configuration of the data recording device 101B according to the modified example. The data recording device 101B is characterized in that the sensor signal input terminal 90, a plurality of circuit elements 111 constituting the preprocessing circuit 110, the communication module 41, and the UART 42 are provided on the lower surface S4 of the wiring board 2. (See FIG. 22). By providing the input terminal 90, the plurality of circuit elements 111, the communication module 41, and the UART 42 on the lower surface S4 of the wiring board 2, the area of the wiring board 2 is further reduced as compared with the data recording device 101A (see FIG. 24). be able to.

FIG. 26 is a perspective view showing the configuration of the data recording device 101C according to the modified example. In the data recording device 101C, the wiring board 2 is joined to the lower surface S2 of the wiring board 1 so as to partially expose the lower surface S2 of the wiring board 1. A part of the circuit element 120 attached to the AFE 10, the CPU 50 and the logic circuit 300 is mounted on the upper surface S1 of the wiring board 1, and the other part of the circuit element 120 is mounted on the exposed portion of the lower surface S2 of the wiring board 1. ing. The sensor signal input terminal 90 is provided on the upper surface S3 of the wiring board 2, and the plurality of circuit elements 111, the communication module 41, and the UART 42 constituting the preprocessing circuit 110 are mounted on the lower surface S4 of the wiring board 2. According to the data recording device 101C, when a sufficient space for mounting all the circuit elements 120 cannot be secured on the upper surface S1 of the wiring board 1, the area of the wiring board 1 is not increased, and the circuit elements 120 It can be mounted on the wiring board 1.

FIG. 27 is a perspective view showing the configuration of the data recording device 101D according to the modified example. In the data recording device 101D, the communication module 41, the UART 42, a plurality of circuit elements 121 associated therewith, and the sensor signal input terminal 90 are provided on the upper surface S3 of the wiring board 2, and the lower surface S4 of the wiring board 2 is provided. , A plurality of circuit elements 111 constituting the preprocessing circuit 110 are provided. According to the data recording device 101D, when a sufficient space for mounting the circuit element 111 cannot be secured on the upper surface S3 of the wiring board 2, the wiring board of the circuit element 111 is not increased in area. It can be mounted on 2.

FIG. 28 is a perspective view showing the configuration of the data recording device 101E according to the modified example. The data recording device 101E includes a wiring board 2 joined to the lower surface S2 of the wiring board 1 and a wiring board 3 connected to the wiring board 2 via the connection board 4. An input terminal 90 for inputting a sensor signal is provided on the upper surface S3 of the wiring board 2, and a plurality of circuit elements 111 constituting the preprocessing circuit 110 are provided on the lower surface S4 of the wiring board 2. A communication module 41, a UART 42, and a circuit element 121 associated therewith are provided on the upper surface S5 of the wiring board 3. The connection substrate 4 may be, for example, a flexible substrate made of a plastic film and having flexibility. According to the data recording device 101E, by configuring the connection board 4 with a flexible board, the wiring board 3 can be folded below the wiring board 2, so that the projected area of the data recording device 101E can be reduced.

FIG. 29 is a perspective view showing the configuration of the data recording device 101F according to the modified example. The data recording device 101F includes a wiring board 2 and a wiring board 3 joined to the lower surface S2 of the wiring board 1 so as to partially expose the lower surface S2 of the wiring board 1. AFE10 is mounted on the exposed portion of the lower surface S2 of the wiring board 1. On the upper surface S3 of the wiring board 2, a plurality of circuit elements 111 constituting an input terminal 90 into which a sensor signal is input and a preprocessing circuit 110 are provided. A communication module 41, a UART 42, and a circuit element 121 associated therewith are provided on the upper surface S5 of the wiring board 3.

FIG. 30 is a perspective view showing the configuration of the data recording device 101G according to the modified example. The data recording device 101G is different from the data recording device 101F in that the wiring board 3 is joined to the upper surface S1 of the wiring board 1.

According to the data recording devices 101A to 101G according to the above-described modification, the AFE 10 is arranged at the end of the component in the stacking direction and the sensor signal is input, as in the data recording device 100 according to the first embodiment. Since the input terminal 90 is provided on the surface of the board closest to the AFE 10, the length of the analog signal wiring from the input terminal 90 to the AFE 10 can be minimized, and the digital signal wiring penetrating the layers of the wiring board 1 can be minimized. And, it is possible to prevent the analog signal wirings from being close to each other and being in an intersecting state or a parallel state. As a result, it is possible to suppress the superposition of noise on the sensor signal.

Further, according to the data recording device 101A to 101G according to the modified example, the wiring board 1 can be configured as a general-purpose module applicable to any sensor, similarly to the data recording device 101 (see FIG. 22), and has a mass production effect. Therefore, the manufacturing cost can be suppressed. The preprocessing circuit 110 can be configured with the minimum number of elements suitable for the sensor, and the customized portion is minimized in low-volume, high-mix production, so that the manufacturing cost can be suppressed. Further, according to the data recording device 101A to 101G according to the modified example, the design and manufacture can be performed in a short period of time as in the data recording device 101, and the size of the entire system can be minimized.

1, 2, 3, 8 Wiring boards 4, 9 Connection boards 10, 10A, 10B AFE
12 Sensor 21 Instrumentation amplifier 22 Low-pass filter 23 Multiplexer 24 AD converter 30 Recording control logic circuit 40 Communication control logic circuit 41 RF communication module 42 UART
50 CPU
60, 60A, 60B Memory 90, 90A, 90B Input terminal 100, 100A to 100L, 101, 101A to 101G Data recording device 110 Preprocessing circuit 111, 120 121 Circuit element 130 Land pattern 140 Corresponding land pattern 300 Logic circuit

Claims (11)

A first semiconductor chip in which a first integrated circuit is formed in which an amplifier that amplifies a sensor signal output from a sensor and an analog-to-digital converter that converts the sensor signal amplified by the amplifier into a digital value are integrated. When,
A second semiconductor chip in which a second integrated circuit in which a recording control logic circuit for controlling the recording of digital values and a communication control logic circuit for controlling communication with an external device are integrated is formed.
A third semiconductor chip in which a memory for recording the digital value is formed under the control of the recording control logic circuit, and
A central processing unit that gives commands to the recording control logic circuit,
A first substrate on which the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the central processing unit are mounted.
Including
The first semiconductor chip is mounted on the first surface of the first substrate or the inner layer of the first substrate adjacent to the first surface.
The sensor signal input terminal is provided on the first surface or the side surface of the first substrate .
An analog signal wiring provided between the input terminal of the sensor signal and the first semiconductor chip and into which the sensor signal is input is provided between the first to third semiconductor chips and the central arithmetic processing apparatus. A data recording device configured to avoid crossing or paralleling with the digital signal wiring through which the digital signals transmitted and received in the above are passed. A first semiconductor chip in which a first integrated circuit in which an amplifier for amplifying a sensor signal output from a sensor and an analog-to-digital converter for converting the sensor signal amplified by the amplifier are integrated is formed. When,
A second semiconductor chip in which a second integrated circuit in which a recording control logic circuit for controlling the recording of digital values and a communication control logic circuit for controlling communication with an external device are integrated is formed.
A third semiconductor chip in which a memory for recording the digital value is formed under the control of the recording control logic circuit, and
A central processing unit that gives commands to the recording control logic circuit,
A first substrate on which the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the central processing unit are mounted.
With the second substrate joined to the first surface of the first substrate,
Including
The first semiconductor chip is mounted on the first surface or the inner layer of the first substrate adjacent to the first surface.
The input terminal for the sensor signal is provided on the second board .
An analog signal wiring provided between the input terminal of the sensor signal and the first semiconductor chip and into which the sensor signal is input is provided between the first to third semiconductor chips and the central arithmetic processing apparatus. A data recording device configured to avoid crossing or paralleling with the digital signal wiring through which the digital signals transmitted and received in the above are passed. The first semiconductor chip has a port into which the sensor signal is input.
The first substrate has a land pattern on the first surface including lands connected to the port.
The data recording apparatus according to claim 2, wherein the second substrate includes a land connected to the input terminal and has a corresponding land pattern corresponding to the land pattern on a joint surface with the first substrate. The data recording apparatus according to claim 2 or 3, further comprising a first circuit element provided on the second substrate and constituting a preprocessing circuit for preprocessing the sensor signal. The fourth aspect of claim 4, further comprising a second circuit element provided on the first substrate and associated with at least one of the first integrated circuit, the second integrated circuit, and the central processing unit. Data recording device. The second substrate is joined to the first surface so as to partially expose the first surface, and the second circuit element is mounted on the exposed portion of the first surface. The data recording device according to claim 5. The second substrate is joined to the first substrate so as to partially expose the first surface, and the first semiconductor chip is mounted on the exposed portion of the first surface. The data recording apparatus according to any one of claims 2 to 6. The data recording device according to any one of claims 1 to 7, further comprising a communication module that communicates with the external device under the control of the communication control logic circuit. 28. Data recording device. A communication module that communicates with the external device under the control of the communication control logic circuit is further included.
The data recording apparatus according to claim 4, wherein the first circuit element and the communication module are provided on a surface of the second substrate opposite to a bonding surface with the first substrate. The data recording apparatus according to any one of claims 1 to 10, further comprising a fourth semiconductor chip mounted on the inner layer of the first substrate and on which the central processing unit is formed.

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