JP6538902B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and electro-optical devices, display devices, semiconductor circuits, and electronic devices are all semiconductor devices.

In recent years, there has been a strong demand for multifunctionalization, high integration, high speed, and low power consumption of semiconductor devices represented by semiconductor integrated circuits and the like. In order to realize these requirements, it is necessary to miniaturize the transistors constituting the semiconductor device and to lower the operating voltage. Further, in order to realize a reduction in operating voltage, it is necessary to reduce the threshold voltage of the transistor, but it is also necessary to reduce the variation in threshold voltage.

Patent Document 1 discloses a method of changing a threshold voltage of a transistor by applying a bias voltage to a semiconductor substrate. In addition, according to Patent Document 2, different bias voltages are applied to the semiconductor substrate when the transistor is operating or not operating to reduce the threshold voltage when the transistor is operating, and the threshold voltage is used when the transistor is not operating. How to make it bigger is shown. Further, Patent Document 3 discloses a method of dividing a semiconductor integrated circuit into a plurality of regions and adjusting a bias voltage applied to a semiconductor substrate for each region.

Japanese Patent Application Laid-Open No. 7-176622 Japanese Patent Application Laid-Open No. 11-122047 U.S. Pat. No. 6,448,840

However, in the method disclosed in Patent Document 1, the threshold voltage of the entire transistor included in the semiconductor integrated circuit changes only in the same manner, and the variation can not be reduced. Further, according to the method disclosed in Patent Document 2, since it is necessary to apply a bias voltage to each transistor included in the semiconductor integrated circuit, a dedicated wiring is required for each transistor, and the occupied area tends to be large. Integration is difficult. Further, in the method shown in Patent Document 3,
There is no disclosure of a specific means for supplying a bias voltage for each divided area.

An object of one embodiment of the present invention is to provide a semiconductor device in which variation in threshold voltage of a transistor is reduced.

An object of one embodiment of the present invention is to provide a semiconductor device capable of achieving high integration, high speed, and low power consumption.

The semiconductor device is divided into a plurality of blocks, and the body of the transistor in the block is
By supplying a potential that changes the threshold voltage for each block via the switch,
A variation in threshold voltage of a semiconductor device is reduced.

In addition, the threshold voltage of the transistor included in the operating block is reduced to enable the semiconductor device to operate at high speed. That is, at the same operating speed, the operating voltage can be reduced. Therefore, it is possible to realize a semiconductor device capable of reducing the operating voltage. In addition, the threshold voltage of the transistor included in the block being stopped is increased to reduce the off-state current, and the reduction in power consumption of the semiconductor device can be realized.

One embodiment of the present invention is a semiconductor device including a plurality of blocks, each block including a logic circuit and a switch, and the switch uses an oxide semiconductor for a semiconductor layer in which a channel is formed. A transistor is included and is electrically connected to a body of a transistor included in the logic circuit.

A potential is supplied to a body of a transistor included in the logic circuit through the switch to change a threshold voltage of the transistor included in the logic circuit.

Further, the potential supplied to the body of the transistor included in the logic circuit can be determined in accordance with the potential held in the switch.

One embodiment of the present invention is a semiconductor device including a plurality of blocks, each block including a logic circuit, a first switch, and a second switch, and the first switch;
The second switch includes a transistor using an oxide semiconductor in a semiconductor layer in which a channel is formed, and the first switch is electrically connected to a first body of a first transistor included in the logic circuit. The second switch is electrically connected to a second body of a second transistor included in the logic circuit.

The first potential is supplied to the first body via the first switch to change the threshold voltage of the first transistor, and the second body is connected to the second body via the second switch. To change the threshold voltage of the second transistor.

The supply of the first potential can be performed according to the potential held by the first switch, and the supply of the second potential can be performed according to the potential held by the second switch.

In addition, at least one of the first transistor and the second transistor can be an n-type transistor. In addition, at least one of the first transistor and the second transistor can be a p-type transistor.

According to one embodiment of the present invention, a semiconductor device with reduced threshold voltage variation of a transistor can be provided.

According to one embodiment of the present invention, a semiconductor device capable of achieving high integration, high speed, and low power consumption can be provided.

FIG. 10 is a block diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 5A to 5C illustrate a method for manufacturing a transistor. 5A to 5C illustrate a method for manufacturing a transistor. FIG. 7 illustrates electrical characteristics of a transistor. 5A to 5C illustrate one embodiment of the present invention. The figure explaining the application example of this invention. 5A to 5C illustrate electronic devices. 5A to 5C illustrate electronic devices. 5A to 5C illustrate electronic devices.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and
The description of the repetition is omitted.

Further, ordinal numbers such as "first", "second", and "third" in the present specification and the like are attached to avoid confusion of the constituent elements, and are not limited numerically.

Moreover, in order to make it easy to understand the position, magnitude | size, range, etc. of each structure shown in drawings etc., an actual position, magnitude | size, range, etc. may not be represented. Therefore, the disclosed invention is not necessarily limited to the position, size, range, and the like disclosed in the drawings and the like.

In addition, the functions of the “source” and the “drain” of the transistor may be interchanged when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in the present specification, the terms "source" and "drain" can be used interchangeably.

Further, in the present specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, "electrode" may be used as part of "wiring",
The reverse is also true. Furthermore, the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wirings” are integrally formed.

In addition, voltage refers to a potential difference between two points, and potential refers to electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in general, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply referred to as a potential or a voltage, and the potential and the voltage are often used as synonyms. Therefore, the potential may be read as voltage unless otherwise specified in the present specification.
Voltage may be read as potential.

A transistor is a type of semiconductor element and can realize amplification of current or voltage, switching operation to control conduction or non-conduction, and the like. The transistor in this specification is
IGFET (Insulated Gate Field Effect Transi
stor) and thin film transistor (TFT: Thin Film Transistor)
including.

Embodiment 1
One embodiment of the present invention will be described with reference to FIGS. 1, 2 and 8. FIG. FIG. 1A shows a configuration example of the integrated circuit 101. As shown in FIG. The integrated circuit 101 is composed of a plurality of blocks 102. FIG. 1A illustrates an example in which the integrated circuit 101 includes nine blocks 102 _a to 102 _i. Further, FIG. 1B shows a configuration example of the block 102.

In each block, a wire 106n for supplying a potential VnH to the body of the n-channel transistor (well formed in contact with the diffusion layer of the n-channel transistor)
H and a wiring 106nL for supplying a potential VnL, a wiring 106pH for supplying a potential VpH to a body of a p-channel transistor (a well formed in contact with a diffusion layer of the p-channel transistor), And the wiring 10 for supplying the potential VpL
6pL is connected.

In addition, the wiring 108 n _ 1 and the wiring 108 p _ 1 include the blocks 102 _a to 10.
The wiring 108 n_2 and the wiring 108 p_2 are connected to the block 102 _d to the block 102 _f, and the wiring 108 n_3 and the wiring 108 p_3 are connected to the block 1
It is connected to 02_g to block 102_i.

In addition, the wiring 109_1 includes the block 102_a, the block 102_d, and the block 102_.
The wiring 109_2 is connected to the block 102_b, the block 102_e, and the block 102_h, and the wiring 109_3 is connected to the block 102_c, the block 102_f, and the block 102_i.

In addition, the wirings 109_1 to 109_3, the wiring 106nH, the wiring 106nL, and the wiring 10
6 pH and the wiring 106 pL are connected to the circuit 132, and the wiring 108 n _ 1 to the wiring 10
8n_3 and the wirings 108p_1 to 108p_3 are connected to the circuit 131. The circuits 131 and 132 each have a function of supplying a signal or a potential to the integrated circuit 101 through the above-described wirings.

A block 102 illustrated in FIG. 1B includes a logic circuit 107, a switch 105 nH, a switch 105 nL, a switch 105 pH, and a switch 105 pL. Also, FIG. 1 (C)
A block 102 shown in FIG. 1 has a configuration in which a threshold voltage detection circuit 103 is added to the block 102 shown in FIG. The threshold voltage detection circuit 103 will be described in detail in another embodiment.

Subsequently, the configuration of the block 102 illustrated in FIG. 1B will be described in detail with reference to FIG. A block 102 illustrated in FIG. 2A illustrates an example in which the logic circuit 107 includes an inverter circuit. The logic circuit 107 is not limited to the inverter circuit, and a known logic circuit such as an OR circuit, an AND circuit, a NOR circuit, or a NAND circuit can be applied. Also, the block 102 may have a plurality of logic circuits 107.

The potential VnH supplied from the circuit 132 through the wiring 106nH is supplied to the body of the n-channel transistor in the logic circuit 107 through the switch 105nH. Further, the potential VnL supplied from the circuit 132 through the wiring 106nL is the switch 105n.
The signal is supplied to the body of the n-channel transistor of the logic circuit 107 through L. Further, the potential V pH supplied from the circuit 132 through the wiring 106 pH is the switch 10
5 pH is supplied to the body of the p-channel transistor of the logic circuit 107. The potential VpL supplied from the circuit 132 through the wiring 106 pL is supplied to the body of a p-channel transistor included in the logic circuit 107 through the switch 105 pL.

The body has a function of changing the Vth of the transistor in accordance with the potential supplied to the body. Here, the electrical characteristics of the transistor in which the potential supplied to the body is adjusted and the Vth is changed will be described with reference to the n-channel transistor 300 as an example.
FIG. 8A is a schematic view of a cross-sectional configuration of the n-channel transistor 300. FIG. The transistor 300 is formed on the n-type semiconductor substrate 301, and the diffusion layer 305 a is formed in the p-type well 302.
And the diffusion layer 305 b, and the gate electrode 304 is provided over the gate insulating layer 303. In addition, FIG. 8B illustrates a circuit symbol of the transistor 300. Diffusion layer 305 a or diffusion layer 3
One end 05 b corresponds to the source S, and the other end of the diffusion layer 305 a or the diffusion layer 305 b corresponds to the drain D. The gate electrode 304 corresponds to the gate G, and the p-type well 302 corresponds to the body B.
FIG. 8C shows a change in the current (Ids) flowing between the source S and the drain D when the voltage (Vgs) between the gate G and the source S of the transistor 300 is changed. Figure 8 (C
The horizontal axis of) shows the change of Vgs, and the vertical axis shows the change of Ids on the logarithmic axis. Curve 31
The curve 1 represents the characteristic when the threshold voltage (hereinafter also referred to as "Vth") is Vth1 by adjusting the potential supplied to the body B, and the curve 312 adjusts the potential supplied to the body B It shows the characteristic when the threshold voltage is set to Vth2. Note that Vth1 and Vt
It is assumed that h2 has a relationship of Vth1 <Vth2.

By applying a positive voltage (a potential higher than the potential of the source S) to the body B of the transistor 300, Vth can be reduced (shifted in the negative direction). Further, by applying a negative voltage (a potential lower than the potential of the source S) to the body of the transistor 300,
Vth can be increased (shifted in the positive direction).

Generally, in a logic circuit, when Vgs is 0 V and Ids is large, transient current tends to increase, which contributes to increase in power consumption. In the case of an n-channel transistor, when a negative voltage is applied to the body B to increase Vth, Ids when Vgs is 0 V can be reduced. In the case of a p-channel transistor, when a positive voltage is applied to the body B to increase Vth, Ids can be reduced when Vgs is 0V.

In particular, when Vgs = 0 V is in the subthreshold region, Ids at Vgs of 0 V can be dramatically reduced by increasing Vth (Io in FIG. 8C).
See ff1 and Ioff2).

In addition, when the transistor Vth is reduced, more Ids can be supplied even with the same Vgs, so that the operation speed of the logic circuit can be increased. Thus, body B
By adjusting the voltage applied to the circuit, it is possible to improve the operating speed of the logic circuit and reduce the power consumption.

FIG. 2B illustrates an example of a circuit configuration that can be used for the switch 105 nH and the switch 105 nL. The switch 105 nH, the switch 105 nL, the switch 105 pH, and the switch 105 pL described in this embodiment can all have the same configuration. Therefore, in the present embodiment, the configuration of the switch 105 nH will be mainly described.

The switch 105 nH includes an n-channel transistor 121, an n-channel transistor 122, and a capacitor 123. The gate of the transistor 121 is a wiring 108 nH
, One of the source or the drain of the transistor 121 is connected to the wiring 109, and the other of the source or the drain of the transistor 121 is connected to the node 120. The gate of the transistor 122 is connected to the node 120, one of the source or the drain of the transistor 122 is connected to the wiring 106nH, and the other of the source or the drain of the transistor 122 is connected to the node 126. One electrode of capacitive element 123 is connected to node 120, and the other electrode is connected to terminal 125. Further, the node 126 is connected to the body of an n-channel transistor included in the logic circuit 107.

The switch 105nL is different from the switch 105nH in that the gate of the transistor 121 included in the switch 105nL is connected to the wiring 108nL and one of the source or the drain of the transistor 122 is connected to the wiring 106pL.
It can be made similar to 5 nH.

Next, the operation of the switch 105 nH will be described. The transistor 12 in the wiring 108 nH
When a potential (a high level potential) which turns on 1 is supplied, the potential of the wiring 109 is supplied to the node 120. At this time, when a potential (a high level potential) for turning on the transistor 122 is supplied to the wiring 109, the potential is supplied to the node 120, and the transistor 122 is turned on. When the transistor 122 is turned on, the wiring 106nH and the node 126 are electrically connected, and the switch 105nH can be turned on. Switch 1
By turning on 05 nH, the potential VnH supplied to the wiring 106 nH can be supplied to the node 126. At this time, the switch 105 nL is off (
That is, it is preferable that there is a sufficiently high resistance between the wiring 106nL and the node 126).

After that, when the potential of the wiring 108nH is set to a potential at which the transistor 121 is turned off (low level potential), the potential of the node 120 is maintained at the high level potential. Accordingly, even when the potential of the wiring 109 is changed after that, the switch 105 nH can be maintained in the on state. Note that the capacitor 123 is connected to the node 12 attributable to the off-state current of the transistor 121.
It has a function of suppressing the potential change of 0 and holding the potential of the node 120 more reliably.

In the case where the switch 105nH is turned off, a potential (a low level potential) for turning off the transistor 122 may be supplied to the wiring 109, and a potential for turning on the transistor 121 may be supplied to the wiring 108nH. Then, a potential (a low level potential) for turning off the transistor 122 is supplied to the node 120. After that, the transistor 121 is turned off, whereby the potential of the node 120 is maintained at the low level. Therefore, even if the potential of the wiring 109 changes after that, the switch 105 nH can be maintained in the off state.

When the capacitance of the capacitor 123 is sufficiently larger than the gate capacitance of the transistor connected to the node 120, the transistor 121 is turned off, and the potential of the terminal 125 is changed while the potential of the node 120 is held. , And the potential held at the node 120 can be changed. For example, when the potential of the terminal 125 is 0 V and the potential of the node 120 is 1 V, and then the potential of the terminal 125 is 0.2 V, the potential of the node 120 is 1.2 V
It can be done. The potential of the node 120 can be adjusted by adjusting the potential of the terminal 125 in a state where the potential of the node 120 is held.

Note that although the transistors 121 and 122 are described as n-channel transistors in this embodiment, p-channel transistors may be used for either one or both of them.

Further, in the case where the potential of the node 126 is switched from the potential VnH to the potential VnL or from the potential VnL to the potential VnH, both the switch 105nH and the switch 105nL are once turned off, and then one switch is turned on. By turning off both switches and then turning on one of the switches, a short circuit between the wiring 106VnH and the wiring 106VnL can be prevented, and an increase in power consumption can be suppressed.

The switch 105 pH and the switch 105 pL can also be operated in the same manner as described above.

For a semiconductor layer in which the channels of the transistor 121 and the transistor 122 are formed, an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, or the like can be used. For example, amorphous silicon, microcrystalline germanium, or the like can be used. Alternatively, a compound semiconductor such as silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used.

Note that in particular, the transistor 121 is preferably a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. A transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed has extremely low off-state current, and the node 120
It is possible to hold the potential of Accordingly, the capacitance element 123 can be made smaller or omitted, so that the area occupied by the integrated circuit 101 can be reduced, and high integration of the semiconductor device can be facilitated. In addition, since the potential of the node 120 can be held for a long time, the refresh operation of the node 120 is unnecessary and power consumption can be reduced.

Specifically, a transistor in which an oxide semiconductor is used for a semiconductor layer in which the above-described channel is formed has an off-state current of 1 μm at a channel width of 10 aA (1 × 10 ⁻¹⁷ A /
(μm) or less, furthermore, 1aA (1 × 10 ^-18 A / μm) or less, further 1
It is possible to set zA (1 × 10 ⁻²¹ A / μm) or less, and further 1 yA (1 × 10 ⁻²⁴ A / μm) or less.

In addition, in the transistor including the above oxide semiconductor, the temperature dependence of the on current is hardly observed, and the change in the off current is also very small.

In addition, the transistor including the above oxide semiconductor can reduce the amount of change in Vth even before and after a bias-heat stress test (BT test), and can be a highly reliable transistor. Note that for the transistor 122, a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed may be used. Note that in the structure disclosed in this embodiment, no special high-speed operation is required for the transistor 121 and the transistor 122, but the field-effect mobility is preferably 1 cm ² / Vs or more.

Note that the switch 105 nH, the switch
5 nL, switch 105 pH, and switch 105 pL (hereinafter collectively referred to simply as “the
It is also called a switch 105 ". ) Can be considered to have a function as a memory element.
As a memory element which can be held for a long time, for example, a flash memory can be mentioned, but it is necessary to apply a high electric field to rewrite the flash memory to generate a tunnel current, and in principle the limit of the number of rewrites (about 10000 times) is there. On the other hand, writing of the potential to the node 120 in the switch 105 does not cause deterioration like a flash memory because charge injection due to a tunnel current is not used. Further, since a high electric field is unnecessary, there is no need to provide a booster circuit or the like, and power consumption is also small.

The setting of the switch 105 included in each block 102 can be performed based on data stored in advance in the non-volatile memory when the integrated circuit 101 is started. For example, each block 102
May be sequentially selected by matrix driving.

Further, the potential VnH, the potential VnL, the potential VpH, and the potential VpL may be determined in accordance with the purpose. Here, the high power supply potential Vdd (hereinafter, also simply referred to as “Vdd”) indicates a power supply potential higher than the low power supply potential Vss (hereinafter, also simply referred to as “Vss”). Also,
The low power supply potential Vss indicates a power supply potential lower than the high power supply potential Vdd. Also, the ground potential can be used as Vdd or Vss. For example, when Vdd is a ground potential, Vss is a potential lower than the ground potential, and when Vss is a ground potential, Vdd is a potential higher than the ground potential. Note that, depending on the purpose, potential VnH, potential VnL, potential VpH,
The potential VpL may be higher than Vdd or lower than Vss.

In the above example, two levels of potential VnH, potential VnL, potential VpH, and potential VpL are selected for the n-channel transistor and the p-channel transistor, respectively. Alternatively, one or both may select three or more potentials.

Further, in the above example, although an example is shown in which both the n-channel transistor and the p-channel transistor in the block can change Vth, the present invention is not limited to this, and only one of Vth may be changed. .

In this embodiment, the node 120 is described to hold either the high level potential or the low level potential. However, the potential held at the node 120 is the transistor 122.
The potential may be any potential as long as it is an on state or an off state.

Alternatively, the transistor 122 can be operated in a saturation region so that the potential held at the node 120 and the potential output at the node 126 correspond to each other. For example, the potential held at the node 120 is determined based on the information obtained from the threshold voltage detection circuit 103,
By outputting a potential corresponding to the potential to the node 126, Vth of the transistor included in the logic circuit 107 can be controlled more accurately. Thus, variation in threshold voltage of the transistors included in the integrated circuit 101 can be further reduced.

If the average value of the threshold voltages of the transistors in the block deviates from a predetermined value, it can be corrected by the method described in this embodiment. Also, increase the block's operation speed,
The lowering can also be performed by operating the threshold voltage by the method described in this embodiment.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Second Embodiment
In this embodiment, another configuration example of the switch 105 described in Embodiment 1 will be described.

The switch 145 illustrated in FIG. 3A has a configuration in which a p-channel transistor 124 is added to the switch 105 nH described in Embodiment 1. In the switch 145, the gate of the transistor 124 is connected to the node 120, one of the source or the drain of the transistor 124 is connected to the wiring 106nL, and the other of the source or the drain is the node 12
Connected to 6 By adding a p-channel transistor 124 to the configuration of the switch 105 nH, the switch 145 having the functions of the switch 105 nH and the switch 105 nL.
Can be realized.

The semiconductor layer in which the channel of the transistor 124 is formed can be formed using a material similar to that of the transistor 121 or the transistor 122.

Next, the operation of the switch 145 will be described. When a potential for turning on the transistor 121 is supplied to the wiring 108 connected to the gate of the transistor 121, the potential of the wiring 109 is supplied to the node 120. At this time, when a high level potential is supplied to the wiring 109, the node 120 becomes a high level potential and the transistor 122 is turned on.
In addition, since the transistor 124 is a p-channel transistor, it is turned off.

In addition, when a low level potential is supplied to the wiring 109, the node 120 is set to a low level potential, the transistor 122 is turned off, and the transistor 124 is turned on.
After that, the potential of the node 120 is held by supplying the potential for turning off the transistor 121 to the wiring 108. In this manner, the potential VnH supplied to the node 126 and the potential VnL can be selected by the potential supplied or held at the node 120.

By using the switch 145, the area occupied by the switch can be reduced as compared to the case where both the switch 105nH and the switch 105nL are used. Further, since the wiring 108nH and the wiring 108nL can be integrated into one wiring, the number of wirings in the integrated circuit 101 can be reduced, and the area occupied by the integrated circuit 101 can be reduced. Therefore,
It becomes easy to achieve high integration of semiconductor devices.

The switch 146 illustrated in FIG. 3B has a structure in which a capacitor 127 is added to a wiring connected to the node 126 of the switch 145. By adding the capacitive element 127, the node 126 is
It is possible to prevent discontinuous potential fluctuation of the body connected to the.

In the present embodiment, an example in which the switch 105 nH and the switch 105 nL are replaced with the switch 145 or the switch 146 has been described.
It is also possible to replace 5 pL with switch 145 or switch 146.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Third Embodiment
In this embodiment mode, a switch having a different structure from the switch described in the above embodiment mode will be described.

The switch 147 illustrated in FIG. 4 has a configuration in which a p-channel transistor 128 and an n-channel transistor 129 are added to the configuration of the switch 145 described in Embodiment 2. In the switch 147, the gate of the transistor 128 is connected to the node 120, one of the source or the drain is connected to the wiring 106 pH, and the other of the source or the drain is connected to the node 136. The gate of the transistor 129 is connected to the node 120, one of the source or the drain is connected to the wiring 106pL, and the other of the source or the drain is connected to the node 136. The node 126 is connected to the body of an n-channel transistor in the logic circuit 107, and the node 136 is connected to the body of a p-channel transistor in the logic circuit 107. By adding a p-channel transistor 128 and an n-channel transistor 129 to the configuration of the switch 145, the switch 1 is formed.
A switch 147 having the functions of 05 nH, switch 105 nL, switch 105 pH, and switch 105 pL can be realized.

The semiconductor layer in which the channels of the transistor 128 and the transistor 129 are formed can be formed using a material similar to that of the transistor 121, the transistor 122, or the transistor 124.

Next, the operation of the switch 147 will be described. When a potential for turning on the transistor 121 is supplied to the wiring 108 connected to the gate of the transistor 121, the potential of the wiring 109 is supplied to the node 120. At this time, when a high level potential is supplied to the wiring 109, the node 120 becomes a high level potential, and the transistor 122 and the transistor 12 are turned on.
9 is turned on. In addition, since the transistor 124 and the transistor 128 are p-channel transistors, they are turned off.

In addition, when a low level potential is supplied to the wiring 109, the node 120 becomes a low level potential, and the transistor 122 and the transistor 129 are turned off.
4 and the transistor 128 are turned on. After that, the potential of the node 120 is held by supplying the potential for turning off the transistor 121 to the wiring 108. In this manner, the potential supplied to or held by node 120 causes
nH and a potential VnL can be selected.

By using the switch 147, the area occupied by the switch can be reduced. Also, wiring 1
Since 08 nH and the wiring 108 nL can be integrated into one wiring, the number of wirings in the integrated circuit 101 can be reduced, and the area occupied by the integrated circuit 101 can be reduced. Thus, high integration of the semiconductor device is facilitated.

Further, the Vth of the n-channel transistor and the Vth of the p-channel transistor can be changed almost simultaneously.

When the potential VnL and the potential VpH are used as the same potential, the wiring 106nL and the wiring 1 are used.
Since 06 pH can be collectively used in one wiring, the area occupied by the integrated circuit 101 can be further reduced.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Embodiment 4
The threshold voltage detection circuit 103 may be formed for each block, and the potential VnH, the potential VnL, the potential VpH, and the potential VpL may be determined based on the information obtained from the threshold voltage detection circuit 103 (FIG. 1). (C)). For example, the potential VnH, the potential VnL, the potential VpH, and the potential VpL may be determined by comparing the reference Vth and the Vth obtained from the threshold voltage detection circuit 103.

FIGS. 5A and 5C show a configuration example of the threshold voltage detection circuit 103a that detects the Vth of an n-channel transistor. 5B and 5D show a configuration example of the threshold voltage detection circuit 103b that detects Vth of a p-channel transistor.

The threshold voltage detection circuit 103 a illustrated in FIG. 5A includes an n-channel transistor 111.
, Switch 113, switch 117, and load 114. The drain of the transistor 111 is connected to the high power supply potential Vdd, and the source of the transistor 111 is connected to the node 115. Also, one electrode of the switch 113 is connected to the node 115, and the switch 11
The other electrode of 3 is connected to one electrode of the load 114, and the other electrode of the load 114 is connected to the common wiring. In addition, one electrode of the switch 117 is connected to the node 115, and the other electrode of the switch 117 is connected to the common wiring COM.

The threshold voltage detection circuit 103b illustrated in FIG. 5B is configured by replacing the transistor 111 of the threshold voltage detection circuit 103a with a p-channel transistor 116. Note that
In the threshold voltage detection circuit 103b, the drain of the transistor 116 has a low power supply potential V
Connected to ss.

Load 114 equivalent to logic circuit 107 is set in threshold voltage detection circuit 103, and logic circuit 1
During the operation of 07, the switch 117 of the threshold voltage detection circuit 103 is turned off and the switch 113 is turned on, whereby the threshold voltage detection circuit 103 can be brought into an operation state equivalent to that of the logic circuit 107. it can.

A common potential is supplied to the common wiring COM. In the present embodiment, Vdd is a potential higher than the common potential, and Vss is a potential lower than the common potential.

Subsequently, the operation of the threshold voltage detection circuit 103a shown in FIG. 5A will be described.
The threshold voltage detection circuit 103a can obtain the threshold voltage of the transistor 111 according to the following procedure.

First, a potential for turning off the transistor 111 is supplied to the gate of the transistor 111. Next, when the switch 113 is turned off and the switch 117 is turned on, the potential of the node 115 becomes the common potential. Next, when the switch 117 is turned off, the node 1
Fifteen are in an electrically floating state (floating state). Next, the transistor 111
A potential Vgs (hereinafter, also simply referred to as “Vgs”) that turns on the transistor 111 is supplied to the gate of the transistor. Note that Vgs is a potential satisfying the relationship of VddVddVg> Vth.

When the transistor 111 is turned on, the potential of the node 115 is increased. Node 115
When the potential difference between the gate and the source becomes equal to
Turns off, and the potential rise of the node 115 stops. At this time, the potential of the node 115 is Vgs-Vth. That is, by measuring the potential of the node 115, Vth of the transistor 111 can be detected.

The threshold voltage detection circuit 103b illustrated in FIG. 5B can also detect Vth in the same procedure. However, Vgs applied to the gate of the transistor 116 is Vdd ≦ Vgs
The potential satisfies the relationship of <Vth.

Further, the switch 113 and the switch 117 can be omitted from the configuration of the threshold voltage detection circuit 103a shown in FIG. 5A, and the configuration shown in FIG. 5C can be employed. In addition, the switch 113 and the switch 117 can be omitted from the configuration of the threshold voltage detection circuit 103a illustrated in FIG. 5B, and the configuration illustrated in FIG. 5D can be employed. In the configurations of FIGS. 5C and 5D, the power consumption increases because the switch 113 and the switch 117 are not provided.
Since it is possible to always detect the Vth of the transistor 11 or the transistor 116, the Vth can be detected more accurately and quickly.

One or more threshold voltage detection circuits 103 can be formed in one block 102.

The Vth of the transistor 111 and the transistor 116 is obtained periodically or as needed, and the characteristic variation of the transistors constituting the logic circuit 104 is detected, and the Vth and the reference Vth are compared to obtain the potential VnH, the potential The potentials of VnL, potential VpH, and potential VpL can be set.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Fifth Embodiment
In this embodiment, an example of a method for manufacturing the transistor that can be applied to the transistors described in the above embodiments will be described with reference to FIGS. In this embodiment, as an example of the transistor that can be used for the logic circuit, the switch, and the like described in the above embodiments, the transistor 440 and the transistor 45 which use an oxide semiconductor for the semiconductor layer in which a channel is formed
An example of a method for producing 0 is shown.

First, a sputtering method, a vacuum evaporation method, or a plating method is used to form 100 on the substrate 400.
A conductive layer is formed with a thickness of from nm to 500 nm, preferably from 200 nm to 300 nm, a resist mask is formed over the conductive film by a photolithography method or an inkjet method, and the conductive layer is etched using the resist mask. Thus, an electrode 402 (including other electrodes or wirings formed in the same layer as the electrode 402) is formed. Alternatively, the conductive nanopaste of copper or the like can be discharged onto a substrate by an inkjet method without using a resist mask, and the conductive nanopaste can be formed by baking.

As the substrate 400, a glass substrate, a ceramic substrate, a semiconductor substrate, a plastic substrate having heat resistance to the extent that can withstand the processing temperature of this manufacturing process, or the like can be used. Further, in the case where the substrate does not require light transmission, a substrate provided with an insulating layer on the surface of a metal substrate such as a stainless steel alloy may be used. As the glass substrate, for example, an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass may be used. Alternatively, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and those provided with semiconductor elements on these substrates It may be used as the substrate 400.

Note that as the substrate 400, a flexible substrate (flexible substrate) may be used. When a flexible substrate is used, a transistor, a capacitor, or the like may be manufactured directly on the flexible substrate.
A transistor, a capacitor, or the like may be manufactured over another manufacturing substrate, and then peeled or transferred to a flexible substrate. Note that in order to peel and transfer the manufacturing substrate to the flexible substrate, a peeling layer may be provided between the manufacturing substrate and the transistor, the capacitor, or the like.

The conductive layer to be the electrode 402 can be formed by a sputtering method, a vacuum evaporation method, or a plating method. In addition, the conductive layer is made of aluminum (Al), chromium (Cr), copper (
Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W)
A metal material selected from neodymium (Nd) and scandium (Sc), an alloy material containing the above-described metal element, a nitride material of the above-described metal element, or the like can be used. Alternatively, a material containing a metal element selected from one or more of manganese (Mn), magnesium (Mg), zirconium (Zr), and beryllium (Be) may be used. Alternatively, a semiconductor typified by polycrystalline silicon containing an impurity element such as phosphorus or a silicide such as nickel silicide may be used.

The conductive layer to be the electrode 402 may have a single-layer structure or a stacked-layer structure of two or more layers. For example, a single-layer structure using aluminum containing silicon, a two-layer structure in which titanium is laminated on aluminum, a two-layer structure in which titanium is laminated on titanium nitride, a two-layer structure in which tungsten is laminated on titanium nitride, tantalum nitride Two-layer structure, Cu-Mg-A with tungsten stacked on top
A two-layer structure in which copper is laminated on an l alloy, a three-layer structure in which copper is laminated on titanium nitride and a tungsten is formed thereon, a copper is laminated on tungsten, and a tantalum nitride is further formed thereon There is a three-layer structure etc. By using copper for the conductive layer to be the electrode 402, the electrode 4
The wiring resistance of 02 can be reduced. In addition, by laminating copper with a refractory metal such as tungsten, molybdenum, or tantalum, or a nitride of the metal, diffusion of copper to other layers can be prevented.

In addition, a conductive layer to be the electrode 402 includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium A conductive material containing oxygen, such as zinc oxide, indium tin oxide to which silicon oxide is added, can also be applied. Alternatively, a stacked structure of the conductive material containing oxygen and the material containing the metal element can be employed.

In addition, in order to realize a normally-off switching element, a material having a work function of 5 eV (electron volts) or more, preferably 5.5 eV (electron volts) or more is used as a gate electrode layer. It is preferable to make the threshold voltage positive. Specifically, it has an In-N bond, and the resistivity is 1 × 10 ⁻¹ to 1 × 10 ⁻⁴ Ω · cm, preferably the resistivity is 5 × 10 ⁻² to 1 × 10 ⁻⁴ Ω A material having cm is used as a gate electrode layer. As an example of the material, an In—Ga—Zn-based oxide film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Ga—O film containing nitrogen, an In—Zn— containing nitrogen O
A film, an In-O film containing nitrogen, a metal nitride film (InN or the like), and the like can be given. The etching of the conductive layer can be performed by a dry etching method or a wet etching method. Alternatively, both dry etching and wet etching may be performed in combination.

In the case where the conductive layer is etched by a dry etching method, a gas containing a halogen element can be used as an etching gas. An example of a gas containing a halogen element is chlorine (
Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ) or carbon tetrachloride (C
Chlorinated gases represented by Cl ₄ ) and the like, carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ )
), Fluorine-based gas typified by nitrogen trifluoride (NF ₃ ) or trifluoromethane (CHF ₃ ), hydrogen bromide (HBr) or oxygen can be appropriately used. Further, an inert gas may be added to the etching gas to be used. Further, as a dry etching method, a reactive ion etching (RIE) method can be used.

Also, as a plasma source, capacitively coupled plasma (CCP: Capacitively C)
oupled plasma), inductively coupled plasma (ICP: inductively)
Coupled Plasma), Electron Cyclotron Resonance (ECR: Electron)
Cyclotron Resonance) plasma, helicon wave excited plasma (HW
P: Helicon Wave Plasma), microwave excited surface wave plasma (SW
P: Surface Wave Plasma) or the like can be used. In particular, IC
P, ECR, HWP, and SWP can generate high density plasma. The etching performed by the dry etching method (hereinafter, also referred to as “dry etching processing”) is performed under the etching conditions (amount of power applied to the coil type electrode, applied to the electrode on the substrate side) so that etching can be performed to a desired processed shape. The amount of power required, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted.

The step of forming a resist mask of an arbitrary shape on the conductive layer or the insulating layer by photolithography is referred to as a photolithography step. Generally, after the resist mask is formed, an etching step and a peeling step of the resist mask are performed. There are many. For this reason, unless otherwise specified, in the photolithography process referred to in the present specification, a process of forming a resist mask,
The etching process of the conductive layer or the insulating layer and the peeling process of the resist mask are included.

In addition, by devising the cross-sectional shape of the gate electrode 202, specifically, the cross-sectional shape (the taper angle, the film thickness, and the like) of the end portion, coverage with a layer to be formed later can be improved.

Specifically, the end of the electrode 402 is tapered so that the cross-sectional shape of the electrode 402 is trapezoidal or triangular. Here, the taper angle θ (see FIG. 6A) of the end portion of the electrode 402 is set to 80 ° or less, preferably 60 ° or less, and more preferably 45 ° or less. In addition, taper angle (theta) shows the angle in the said layer which the side and bottom face of the said layer make, when the layer which has a taper-shape is observed from the cross section (plane orthogonal to the surface of a board | substrate) direction. Moreover, the case where a taper angle is less than 90 degrees is called normal taper, and the case where a taper angle is 90 degrees or more is called reverse taper.

In addition, by setting the cross-sectional shape of the end portion of the electrode 402 to a multi-step shape, the covering property of a layer to be coated thereon can be improved. In addition, the cross-sectional shape of the end portion of each layer is not limited to the electrode 402, and the cross-sectional shape of each layer is a forward tapered shape or a step shape to prevent the phenomenon (step break) in which the layer to be coated thereon breaks off. It can be

In addition, an insulating layer may be provided between the substrate 401 and the electrode 402. The insulating layer is formed by sputtering, MBE (Molecular Beam Epitaxy), CVD (Che
Mical Vapor Deposition method, PLD (Pulsed Lase)
r Deposition method, ALD (Atomic Layer Depositi)
on method, MOCVD (Metal Organic Chemical Vapor)
It can form using the Deposition method etc. suitably. Further, high density plasma CVD method using microwave (for example, frequency 2.45 GHz) can be applied. In addition, the insulating layer 201 may be formed using a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicularly to the sputtering target surface, a so-called CP sputtering apparatus.

In addition, the insulating layer is formed of a single layer or a stack of a material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, gallium oxide, silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride. It can be formed. In the present specification, the term "nitriding oxidation" means that the content of nitrogen is higher than that of oxygen as the composition, and the term "oxinitriding" means that the content of oxygen is higher than nitrogen as that composition. Indicates The content of each element is, for example, Rutherford backscattering method (RBS: Ruthe
It can be measured using rford backscattering spectrometry) or the like.

Next, the insulating layer 403 is formed over the substrate 400 and the electrode 402 (see FIG. 6A). The insulating layer 403 is a layer having a convex portion on the surface reflecting the shape of the electrode 402.

As the insulating layer 403, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, gallium zinc oxide, zinc oxide, or a mixture thereof is used by plasma CVD, sputtering, or the like. It can be formed. The insulating layer 403 may be a single layer or a stack.

In this embodiment mode, a silicon oxide film formed by a sputtering method is used as the insulating layer 403. Alternatively, a silicon oxynitride film formed by plasma CVD may be used.

Next, the insulating layer 403 is subjected to a treatment of introducing oxygen 431 (oxygen doping treatment),
An oxygen excess region 481 is formed in the vicinity of the lower surface of the insulating layer 403 and in the vicinity of the electrode 402. Thus, the insulating layer 403 including the oxygen excess region 481 is formed (see FIG. 6B). In the drawing, the oxygen excess region 481 indicated by a dotted line schematically represents the distribution center of the introduced oxygen.

The oxygen 431 contains at least any of oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions.

For the introduction of the oxygen 431 into the insulating layer 403, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used. A gas cluster ion beam may be used as the ion implantation method. In addition, the introduction of oxygen 431 may be performed on the entire surface of the substrate 400 at one time, or, for example, a linear ion beam may be used. In the case of using a linear ion beam, oxygen 431 can be introduced to the entire surface of the insulating layer 403 by relatively moving (scanning) the substrate or the ion beam.

As the supply gas of oxygen 431, a gas containing O may be used, for example, O ₂ gas,
N ₂ O gas, CO ₂ gas, CO gas, NO ₂ gas or the like can be used. Note that a rare gas (for example, Ar) may be contained in the oxygen supply gas.

Also, for example, when oxygen is introduced by ion implantation, the dose of oxygen 431 is 0.5 ×
It is preferable to set 10 ¹⁶ cm ⁻² or more to 5 × 10 ¹⁶ cm ⁻² (for example, 1 × 10 ¹⁶ cm ⁻² ), and acceleration energy to be 50 eV or more to 70 eV (for example, 50 eV). The content of oxygen in the oxide insulating layer 436 including 481 is preferably higher than the stoichiometric composition ratio of the oxide insulating layer 436. Note that a region containing oxygen in excess of such a stoichiometric composition ratio may be present in the oxygen excess region 481.
Note that the implantation depth of the oxygen 431 may be appropriately controlled depending on the implantation conditions.

Next, planarization treatment is performed on the insulating layer 403 including the oxygen excess region 481 to remove convex portions on the top surface. By selectively removing the insulating layer 403 over the electrode 402, the surface is planarized to form a planarized insulating layer 404 (see FIG. 6C).

A region overlapping with the electrode 402 in the insulating layer 403 is selectively removed and flattened by the planarization treatment, so that the distance between the oxygen excess region 481 on the electrode 402 and the top surface of the insulating layer 403 is shortened. On the other hand, since the insulating layer 403 is hardly removed in the region where the electrode 402 is not present in the insulating layer 403, the oxygen excess region 481 is present in the vicinity of the lower surface of the insulating layer 403.
Thus, in the insulating layer 404, the oxygen excess region is provided at a shallower position from the top surface of the oxide insulating layer in the region where the electrode 402 is present, and is provided at a deeper position in other regions (regions where the conductive layer is not present) .

Therefore, in the insulating layer 404 overlapping with the electrode 402, to which an oxide semiconductor layer is provided in a later step, the oxygen excess region 481 can be provided in the vicinity of the oxide semiconductor layer. Oxygen can be efficiently supplied to the layer. Also, the supply of oxygen can be further promoted by heat treatment.

Further, in the insulating layer 404, the oxygen excess region 481 is provided in the vicinity of the lower surface of the insulating layer 404 away from the upper surface of the insulating layer 404 in a region other than the lower portion of the oxide semiconductor layer which needs oxygen supply. Thus, even when heat treatment is performed, unnecessary release of oxygen from the top surface of the insulating layer 404 can be suppressed, and the insulating layer 404 can be maintained in an oxygen excess state.

Note that although an example in which oxygen 431 is introduced into the insulating layer 403 is described in this embodiment, oxygen in the insulating layer 403 can be formed if the insulating layer 403 containing sufficient oxygen can be formed immediately after film formation. 4
The introduction of 31 can be omitted.

The planarization treatment is not particularly limited, but polishing treatment (for example, chemical mechanical polishing (CMP)), dry etching treatment, or plasma treatment can be used.

Then, the oxide semiconductor layer 405 is formed over the insulating layer 404 (see FIG. 6C). The oxide semiconductor layer 405 can be formed using an In—Zn-based oxide, an In—Mg-based oxide, an In—Ga-based oxide, which is a binary metal oxide, or an In—Ga—, which is an oxide of a ternary metal. Zn-based oxide (IGZO
Also written. ), In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La
-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-
Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Z
n-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn
In-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides, and oxides of quaternary metals -Sn-Ga-Zn
A base oxide, an In-Hf-Ga-Zn-based oxide, an In-Sn-Hf-Zn-based oxide, or the like can be used.

Note that, for example, an In—Ga—Zn-based oxide means an oxide having In, Ga, and Zn, and there is no limitation on the ratio of In to Ga to Zn. Also, In, Ga and Zn
Other metal elements may be contained.

In this embodiment, an oxide target having a composition ratio of In: Ga: Zn = 3: 1: 2 [atomic number ratio] is used as a target for forming the oxide semiconductor layer 405 by a sputtering method. An In—Ga—Zn-based oxide (IGZO) is formed to a thickness of 5 nm to 30 nm.

Further, the relative density (filling rate) of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the formed oxide semiconductor layer 405 can be a dense film.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or a hydride is removed as a sputtering gas used in forming the oxide semiconductor layer 405.

First, the substrate 400 formed to the insulating layer 404 is held in the deposition chamber held in a reduced pressure state. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while removing residual moisture in the deposition chamber, and the oxide semiconductor layer 405 is formed over the insulating layer 404 using the above target.
In order to remove moisture remaining in the deposition chamber, an entrapment vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump is preferably used. In addition, as an evacuation means, a turbo molecular pump provided with a cold trap may be used. In the deposition chamber evacuated using a cryopump, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H ₂ O) (more preferably also a compound containing a carbon atom), or the like is evacuated; The concentration of impurities contained in the oxide semiconductor layer 405 which is formed in a chamber can be reduced.

Note that the oxide semiconductor layer 405 may have a structure in which a plurality of oxide semiconductor layers are stacked.
For example, the oxide semiconductor layer 405 is a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, and metal oxides having different compositions for the first oxide semiconductor layer and the second oxide semiconductor layer May be used. For example, a ternary metal oxide may be used for the first oxide semiconductor layer, and a binary metal oxide may be used for the second oxide semiconductor layer. Alternatively, for example, both of the first oxide semiconductor layer and the second oxide semiconductor layer may be oxides of ternary metals.

The constituent elements of the first oxide semiconductor layer and the second oxide semiconductor layer may be the same, and the composition ratio of the two may be different. For example, the atomic ratio of the first oxide semiconductor layer can be expressed as In: Ga: Zn =
Alternatively, the atomic ratio of the second oxide semiconductor layer may be In: 1: 3: 1: 2. Further, the atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor layer is In: Ga: Zn = 2: 1: 3. It may be

At this time, in the first oxide semiconductor layer and the second oxide semiconductor layer, the content ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) may be In> Ga. In addition, the In and Ga contents of the oxide semiconductor layer on the side (back channel side) far from the gate electrode are In ≦≦.
It is good to be Ga.

In oxide semiconductors, the s orbital of heavy metal mainly contributes to carrier conduction, and there is a tendency that the overlap of the s orbital tends to increase by increasing the In content, so It has high mobility as compared with an oxide having a composition of In ≦ Ga. In addition, Ga has a greater formation energy of oxygen vacancies compared to In, and thus oxygen vacancies are less likely to occur.
An oxide having a composition of In ≦ Ga has stable characteristics as compared with an oxide having a composition of In> Ga.

An oxide semiconductor with a composition of In> Ga is applied to the channel side, and In ≦≦ on the back channel side.
By using an oxide semiconductor which has a composition of Ga, mobility and reliability of the transistor can be further improved.

Alternatively, oxide semiconductors with different crystallinity may be applied to the first oxide semiconductor layer and the second oxide semiconductor layer. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS (C Axis Aligned Crystalline).
It may be configured by appropriately combining Oxide Semiconductor).

Here, the CAAC-OS will be described. CAAC-OS is not a complete single crystal nor a complete amorphous. The CAAC-OS is an oxide semiconductor of a crystal-amorphous mixed phase structure having a crystal part in an amorphous phase. Note that the crystal part often fits in a cube whose one side is less than 100 nm. Also, a transmission electron microscope (TEM: Transmis
In the observation image by sion electron microscope, the CAAC-O
The boundary between the amorphous part and the crystal part contained in S is not clear. Also, CAAC by TEM
-Grain boundaries (also called grain boundaries) can not be confirmed in OS. Therefore, CAA
In C-OS, the decrease in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS has a c-axis aligned in a direction perpendicular to the formation surface or surface of the CAAC-OS, and has a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the ab plane. The metal atoms are arranged in layers or the metal atoms and the oxygen atoms are arranged in layers when viewed in the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In the present specification, the term “perpendicular” also includes the range of 85 ° or more and 95 ° or less.

In the CAAC-OS, distribution of crystal parts is not necessarily uniform. For example, CAAC
In the case of crystal growth from the surface side of the oxide semiconductor layer in the formation process of -OS, the proportion of the crystal part in the vicinity of the surface may be higher than the ratio in the vicinity of the formation surface. Also, CAAC
By adding an impurity to −OS, a crystal part may be made amorphous in the impurity added region.

The c-axis of the crystal part included in the CAAC-OS is aligned in a direction perpendicular to the formation surface or surface of the CAAC-OS, so the shape of the CAAC-OS (cross-sectional shape of the formation surface or cross-sectional shape of the surface)
Depending on the direction, they may turn in different directions. Note that the direction of the c-axis of the crystal part is CAAC
-The direction perpendicular to the formation surface or the surface when the OS is formed. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

A transistor using a CAAC-OS can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Thus, the transistor is highly reliable.

Note that part of oxygen included in the oxide semiconductor may be replaced with nitrogen.

In the case of an oxide semiconductor having a crystal part, such as a CAAC-OS, defects in the bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by enhancing surface flatness. . In order to improve surface flatness, an oxide semiconductor is preferably formed over a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.
. It may be formed on a surface of 3 nm or less, more preferably 0.1 nm or less. Ra can be evaluated with an atomic force microscope (AFM). (End of explanation of CAAC-OS.)

When an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor layer and the second oxide semiconductor layer, internal stress of the oxide semiconductor layer 205 and stress from the outside are relieved, and Characteristic variations are reduced, and it is possible to further enhance the reliability of the transistor.

On the other hand, an amorphous oxide semiconductor is apt to absorb an impurity serving as a donor such as hydrogen, and is likely to be n-typed because oxygen vacancies are easily generated. Therefore, the oxide semiconductor layer on the channel side is
It is preferable to apply a crystalline oxide semiconductor such as CAAC-OS.

In addition, in the case of using a channel-etched transistor with a bottom gate structure as the transistor, when an amorphous oxide semiconductor is used on the back channel side, oxygen vacancies are generated by etching treatment when forming the source electrode and the drain electrode, It is easy to be done. Therefore, in the case of using a channel-etched transistor, an oxide semiconductor having crystallinity is preferably used for the oxide semiconductor layer on the back channel side.

Alternatively, the oxide semiconductor layer 405 may have a stacked-layer structure of three or more layers, and the amorphous oxide semiconductor layer may be sandwiched between oxide semiconductor layers having crystallinity of a plurality of layers. In addition, a structure in which an oxide semiconductor layer having crystallinity and an amorphous oxide semiconductor layer are alternately stacked may be employed.

The above structures in the case where the oxide semiconductor layer 405 has a stacked-layer structure of a plurality of layers can be combined with each other as appropriate.

Alternatively, the oxide semiconductor layer 405 may have a stacked-layer structure of a plurality of layers, and oxygen doping treatment may be performed after each oxide semiconductor layer is formed. By performing oxygen doping treatment for each formation of each oxide semiconductor layer,
The effect of reducing oxygen vacancies in the oxide semiconductor can be enhanced.

Subsequently, part of the oxide semiconductor layer 405 is selectively etched by a photolithography step to form an island-shaped oxide semiconductor layer 406 (see FIG. 6D). Oxide semiconductor layer 4
The resist mask for forming 06 may be formed by an inkjet method. When the resist mask is formed by an inkjet method, a photomask is not used, and thus the manufacturing cost can be reduced.

Note that the etching of the oxide semiconductor layer 405 may be either a dry etching method or a wet etching method, or both may be used. The oxide semiconductor layer 40 is formed by wet etching.
When etching is performed, a solution in which phosphoric acid, acetic acid and nitric acid are mixed is used as an etching solution, or
A solution containing oxalic acid can be used. Also, ITO-07N (Kanto Chemical Co., Ltd.)
May be used. In the case where the oxide semiconductor layer 405 is etched by dry etching, for example, dry etching using a high density plasma source such as ECR or ICP can be used.

After the formation of the oxide semiconductor layer 405 or after the formation of the oxide semiconductor layer 406, heating for removing excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer (dehydration or dehydrogenation) is performed. You may process. The temperature of the heat treatment is higher than or equal to 300 ° C and lower than or equal to 700 ° C, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer at 450 ° C. for one hour in a nitrogen atmosphere.

Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus which heats an object by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, GRTA (Gas R
apid Thermal Anneal device, LRTA (Lamp Rapid T)
RTA (Rapid Thermal Anneal) of equipment such as thermal Anneal
al) apparatus can be used. The LRTA apparatus is an apparatus for heating an object by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp and a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high temperature gas. For hot gases,
An inert gas which does not react with an object by heat treatment such as a rare gas such as argon or nitrogen is used.

For example, as heat treatment, GRTA in which the substrate is put in an inert gas heated to a high temperature of 650 ° C. to 700 ° C. and heated for several minutes may be performed.

Note that in the heat treatment, it is preferable that water, hydrogen, and the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1ppm or less, preferably) Is 0.1
It is preferable to set it as ppm or less.

In addition, after the oxide semiconductor layer is heated by heat treatment, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (cavity ring down spectroscopy (CRDS: Ca) is performed in the same furnace.
The moisture content measured with a dew point meter using vity Ring-Down Spectroscopy) is 20 ppm or less (-55 ° C in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less of air. Good. It is preferable that the oxygen gas or the dinitrogen monoxide gas does not contain water, hydrogen and the like. Alternatively, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is 6 N or more, preferably 7 N or more (that is, the impurity concentration in the oxygen gas or dinitrogen monoxide gas is 1 ppm or less, preferably 0.1 ppm or less )
It is preferable to Oxidation by supplying oxygen, which is a main component material of an oxide semiconductor, which has been simultaneously reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or dinitrogen monoxide gas. Oxygen vacancies in the product semiconductor are reduced, and the oxide semiconductor layer can be i-type (intrinsic) or substantially i-type. In this respect, since it is not i-type conversion by adding an impurity element like silicon and the like, it can be said that i-type conversion of an oxide semiconductor includes technical ideas that have not been present in the prior art.

Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times, and may be combined with another heat treatment. Further, the heat treatment promotes the supply of oxygen from the insulating layer 404. In addition, oxygen doping may be performed on the oxide semiconductor layer which has been subjected to dehydration or dehydrogenation treatment, and oxygen may be supplied to the oxide semiconductor layer.

Further, it is preferable that the oxide semiconductor layer be highly purified which hardly contains impurities such as copper, aluminum, and chlorine. In the manufacturing process of the transistor, it is preferable to select a step which does not have the risk of the contamination or adhesion of these impurities on the surface of the oxide semiconductor layer, and in the case of adhesion to the surface of the oxide semiconductor layer, oxalic acid or Exposure to hydrofluoric acid, etc.
Alternatively, impurities in the surface of the oxide semiconductor layer are preferably removed by plasma treatment (N ₂ O plasma treatment or the like). Specifically, the copper concentration in the oxide semiconductor layer is 1 × 1
It is set to 0 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. Further, the concentration of aluminum in the oxide semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less. Further, the chlorine concentration in the oxide semiconductor layer is less than or equal to 2 × 10 ¹⁸ atoms / cm ³ .

In addition, the concentration of an alkali metal such as sodium (Na), lithium (Li), or potassium (K) in the oxide semiconductor layer is 5 × 10 ¹⁶ cm ⁻³ or less, preferably 1 × 10 ¹⁶ c
m ⁻³ or less, more preferably 1 × 10 ¹⁵ cm ⁻³ or less, Li is 5 × 10 ¹⁵ cm ⁻³
Hereinafter, preferably, it is 1 × 10 ¹⁵ cm ⁻³ or less, and K is 5 × 10 ¹⁵ cm ⁻³ or less, preferably 1 × 10 ¹⁵ cm ⁻³ or less.

Next, the source electrode 407 a electrically connected to the oxide semiconductor layer 406, the drain electrode 4
Form 07b (including other electrodes or wires formed in the same layer as this). Various circuits can be formed by using the source electrode 407 a and the drain electrode 407 b to connect to other transistors or elements.

The source electrode 407 a and the drain electrode 407 b can be formed by forming a conductive layer using, for example, a sputtering method, an evaporation method, or the like, and processing using a photolithography step.

As a conductive layer used for the source electrode 407 a and the drain electrode 407 b, for example, Al
Or a metal material containing an element selected from Cr, Cu, Ta, Ti, Mo, W, or a metal nitride material (titanium nitride, molybdenum nitride, tungsten nitride) or the like containing the above-described element as a component. .

In this embodiment, a single-layer tungsten layer is used, a resist mask is formed over the tungsten layer, a first etching for removing about a half of the thickness of the tungsten layer is performed, and the resist mask is reduced by ashing treatment. Then, the second etching is performed using the reduced resist mask, and then the resist mask is removed and the cross-sectional shape shown in FIG. 6D, that is, the source electrode 407a having the projecting region at the lower end portion, and the projecting region Are formed at the lower end portion.

Then, the gate insulating layer 408 is formed to cover the oxide semiconductor layer 406, the source electrode 406a, and the drain electrode 406b (see FIG. 6E).

The thickness of the gate insulating layer 408 is, for example, 1 nm or more and 20 nm or less, and a sputtering method,
The MBE method, the CVD method, the PLD method, the ALD method, the MOCVD method, and the like can be used as appropriate.
Alternatively, the gate insulating layer 408 may be formed using a sputtering apparatus which performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicularly to the sputtering target surface, a so-called CP sputtering apparatus.

As a material of the gate insulating layer 408, silicon oxide, gallium oxide, gallium zinc oxide,
It can be formed using Ga ₂ O ₃ (Gd ₂ O ₃ ), zinc oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, or silicon nitride oxide.
In addition, as another material, an insulating In-Ga-Zn-based oxide can also be used for the gate insulating layer 408.
It can be used as a material of An In—Ga—Zn-based oxide having an insulating property is In:
With an oxide target of Ga: Zn = 1: 3: 2 [atomic number ratio], the substrate temperature is set to room temperature,
The sputtering gas may be formed using argon or a mixed gas of argon and oxygen.

In the case where an oxide semiconductor is used for the semiconductor layer in which a channel is formed, the layer in contact with the semiconductor layer is
It is preferable to use a material containing a component of the same type as the oxide semiconductor forming the semiconductor layer. Such a material has high compatibility with an oxide semiconductor, and when used in a layer in contact with the oxide semiconductor, the interface state between the semiconductor layer and the layer can be favorably maintained. Here, “a component of the same type as the oxide semiconductor” means that one or more elements selected from constituent elements of the oxide semiconductor are included. For example, in the case where the oxide semiconductor is formed using an In-Ga-Zn-based oxide semiconductor material, examples of the insulating material containing the same kind of component include gallium oxide and gallium zinc oxide.

In the case where the gate insulating layer 408 has a stacked structure, a stacked structure of a layer a formed of an insulating material containing the same component as the oxide semiconductor and a layer b including a material different from the component material of the layer a It is also good. For example, in the case where the oxide semiconductor is formed using an In-Ga-Zn-based oxide semiconductor material, the layer a in contact with the oxide semiconductor may be formed of gallium oxide and the layer b may be formed of silicon oxynitride.

In this embodiment mode, gallium oxide formed by a sputtering method is used as the gate insulating layer 408. When gallium oxide is used as the gate insulating layer 408, the same component as the oxide semiconductor layer 406 is included, so that the interface state of the oxide semiconductor layer can be favorable and stable electrical characteristics can be imparted. be able to.

Next, a conductive layer is formed over the gate insulating layer 408 by a sputtering method, an evaporation method, or the like, and the conductive layer is etched to form the gate electrode 409a and the gate electrode 409b.

The material of the gate electrode 409a and the gate electrode 409b can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium or an alloy material containing any of these as main components. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus or a silicide such as nickel silicide may be used. The gate electrode 409a and the gate electrode 409b may have a single-layer structure or a stacked structure.

In this embodiment, a metal oxide containing nitrogen (an In—Ga—Zn-based oxide containing nitrogen) is formed as the gate electrode 409a in contact with the gate insulating layer 408, and the gate electrode 4 is formed thereon.
Form tungsten as 09b. With the use of a metal oxide containing nitrogen as the gate electrode 409a, the threshold voltage of the transistor can be shifted in the positive direction.

Through the above steps, the transistor 440 can be manufactured (see FIG. 7A). The transistor 440 is an example of a top-gate transistor, and FIG. 7A is a cross-sectional view of the transistor 440 in the channel length direction.

In addition, the electrode 402 provided in the insulating layer 404 including the oxygen excess region 481 overlaps with the gate electrode 409 a and the gate electrode 409 b through the channel formation region;
Can function as a back gate. Generally, the back gate is disposed so as to sandwich the channel formation region of the semiconductor layer between the gate and the back gate. The back gate is formed of a conductive layer and can function similarly to the gate. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate. The body disclosed in the specification also has the same function as the back gate electrode. Thus, the body can also be called a back gate.

The gate electrode 409a and the gate electrode 409b are formed to overlap with part of the source electrode 407a and the drain electrode 407b. A region (protruding at the lower end portion of the source electrode 407 a)
Alternatively, the region protruding to the lower end portion of the drain electrode 407 b has a shape capable of improving the coverage of the gate insulating layer 408, and therefore has the effect of alleviating the concentration of electric field, and improves the electrical characteristics and reliability of the transistor. Contribute to the improvement of

Next, an insulating layer 410 covering the gate electrode 409a and the gate electrode 409b is formed (FIG. 7).
(B)). The insulating layer 410, the oxide semiconductor layer 406, or the gate insulating layer 408 functions as a barrier layer (protective layer) having a high function of preventing release of oxygen.

The insulating layer 410 which functions as a barrier layer is the oxide semiconductor layer 406 or the gate insulating layer 4.
A dense layer which can prevent the entry of impurities such as hydrogen and moisture from 08 is preferable.

As a material used for the insulating layer 410 which functions as a barrier layer, for example, gallium oxide, gallium zinc oxide, Ga ₂ O ₃ (Gd ₂ O ₃ ), silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride An inorganic insulating material such as aluminum nitride, silicon nitride oxide, aluminum nitride oxide, or zinc oxide can be used, and a single layer or stacked layers may be used. The insulating layer 410 which functions as a barrier layer can be formed by a plasma CVD method, a sputtering method, a CVD method using a deposition gas, or an MBE method.

Next, the interlayer insulating layer 411 is formed over the insulating layer 410. For the interlayer insulating layer 411, an inorganic insulating material such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride, aluminum nitride, silicon nitride oxide, aluminum nitride oxide, gallium oxide, gallium zinc oxide, or the like can be used. It may be a single layer or a stack.

Then, a cross-sectional view at a stage when the embedded wiring is formed in the interlayer insulating layer 411 corresponds to FIG. A contact hole reaching the source electrode 407a is formed in the interlayer insulating layer 411, a first barrier metal layer 412 is formed, and a copper or copper alloy film for forming the low resistance conductive layer 413 is formed thereon. . The exposed low resistance conductive layer 413 is polished and planarized.
To form a second barrier metal layer 414. The buried interconnection is composed of a first barrier metal layer 412, a second barrier metal layer 414, and a low resistance conductive layer 413 surrounded by the first barrier metal layer 412 and the second barrier metal layer 414. Ru.

The first barrier metal layer 412 and the second barrier metal layer 414 may be made of a conductive material which suppresses diffusion of copper contained in the low resistance conductive layer 413. For example, tantalum nitride, molybdenum nitride, tungsten nitride or the like is used. .

Through the above steps, another semiconductor element, a wiring, or the like can be further formed over the transistor 440 to form a semiconductor device having a multilayer structure. Note that other semiconductor elements, wirings, and the like provided over the transistor 440 can be electrically connected to the embedded wiring.

Note that by omitting the process for manufacturing the electrode 402, the transistor 450 can be formed (see FIG. 7D). The electrode 402 can function as a back gate, but
In particular, when it is not necessary to form the electrode 402, the productivity of the semiconductor device can be improved by omitting the process for manufacturing the electrode 402.

The cross-sectional structures of the transistor 440 and the transistor 450 described in this embodiment are an example, and the cross-sectional shapes of the source electrode 407 a and the drain electrode 407 b are the same,
It is not particularly limited. Although a MOSFET is illustrated as the transistor 440, an IGBT (Insulated Gate Bipolar T) is used as the transistor 440.
ransistor, MESFET (Metal Semiconductor Fi)
It is also possible to use an eld effect transistor) or the like. However, in the case of using an IGBT as the transistor 440, the source electrode corresponds to an emitter terminal, and the drain electrode corresponds to a collector terminal.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Sixth Embodiment
In this embodiment, a configuration example of the switch 105 disclosed in the above embodiment will be described.

FIG. 9A is a circuit diagram of the switch 105. 9B shows the transistor 121.
FIG. 18 is a cross-sectional view illustrating a stacked-layer structure of the switch 105 using a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed and a transistor formed on a semiconductor substrate as the transistor 122.

Note that the transistor 121 exemplifies a structure similar to that of the transistor 450 described in the above embodiment. A transistor using an oxide semiconductor has a long time because of its characteristics.
Enables charge retention of In addition, a transistor formed over a semiconductor substrate can easily operate at high speed.

The semiconductor substrate on which the transistor 122 is formed is a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon
A Silicon on Insulator) substrate or the like can be used.

In this embodiment mode, an example in which a single crystal silicon substrate is used as the substrate 700 and the n-channel transistor 122 is formed in the substrate 700 is described.

First, an impurity element imparting p-type conductivity is added to part of the substrate 700 to form a p-type well 701. The transistor 122 is provided in a region where the p-type well 701 is formed.
That is, the channel formation region 753 of the transistor 122 is formed in the p-type well 701. Boron (B) or the like can be used as the impurity element imparting p-type.

The transistor 122 has a channel formation region 753, an LDD (Lightly Doped).
Drain region or an n-type impurity region 754 functioning as an extension region, an n-type impurity region 755 functioning as a source region or a drain region, a gate insulating layer 752, and a gate electrode 751. Note that the impurity concentration of the n-type impurity region 755 is higher than that of the n-type impurity region 754. Side wall insulating layers 756 are provided on the side surfaces of the gate electrode 751, and
Using gate electrode 751 and sidewall insulating layer 756 as a mask, n-type impurity region 754,
The n-type impurity region 755 can be formed in a self-aligned manner.

The transistor 122 is separated from the other transistors by the element isolation region 789, and the insulating layer 788 and the insulating layer 687 are stacked over the transistor 122. A wiring layer 657 in contact with one of n-type impurity regions 755 and an wiring layer 658 in contact with the other of n-type impurity regions 755 are formed over insulating layer 687 through openings formed in insulating layer 788 and insulating layer 687.
And the wiring layer 659 in contact with the gate electrode 751.

The wiring layer 658 is connected to the p-type impurity region 757 of the transistor 151 included in the logic circuit. The p-type impurity region 757 has a higher impurity concentration than the p-type well 701, and can realize ohmic contact between the wiring layer 658 and the well 701 functioning as a body.

Further, the semiconductor device of this embodiment is not limited to the structure shown in FIG.
A transistor having silicide (salicide) as the transistor 22 or a transistor having no sidewall insulating layer may be used. With the structure having silicide (salicide), the resistance of the source region and the drain region can be further reduced, and the speed of the semiconductor device can be increased. In addition, since the semiconductor device can operate at low voltage, power consumption of the semiconductor device can be reduced.

Although not described in this embodiment, an impurity element imparting n-type conductivity is added to part of the substrate 700 to form an n-type well, and a p-type is formed in a region where the n-type well is formed. It is also possible to form a transistor of Phosphorus (P), arsenic (As), or the like can be used as the impurity element imparting n-type conductivity.

Next, an upper element configuration provided on the lower transistor in the semiconductor device of FIG. 9 will be described.

An insulating layer 684 is stacked on the insulating layer 687 and the wiring layer 657, and the wiring layer 6 is formed on the insulating layer 684.
92 are formed. In addition, an insulating layer 434 and an insulating layer 404 which cover the wiring layer 692 are provided, and an oxide semiconductor layer 406 is formed thereover. Then, over the oxide semiconductor layer 406, a source electrode 407a having a projecting region at a lower end portion and a drain electrode 407b having a projecting region at a lower end portion are formed, and a gate insulating layer is formed over the source electrode 407a and the drain electrode 407b. 408 is provided.

In addition, the capacitor element 123 is formed over the same insulating layer 404 as the transistor 121 without additional steps, and the capacitor element 123 uses the source electrode 407 a as one electrode and the capacitor electrode 693 a and the capacitor electrode 693 b as the other. And the gate insulating layer 408 provided between them as a dielectric. Note that the capacitor electrode 693a and the capacitor electrode 693b are formed in the same step as the gate electrode 409a and the gate electrode 409b.

The wiring layer 692 is electrically connected to the wiring layer 659 through an opening formed in the insulating layer 684. In this embodiment mode, the insulating layer 684 is planarized by a CMP method.

The insulating layer 434 is provided between the transistor 121 and the transistor 122, and functions as a barrier layer so that impurities such as hydrogen which cause deterioration or change in electrical characteristics do not enter the oxide semiconductor layer 406 from the lower layer. Therefore, the insulating layer 434 is preferably formed using a dense inorganic insulating material (eg, aluminum oxide, silicon nitride, or the like) having a high blocking function such as an impurity.

The source electrode 407 a includes the wiring layer 69 through the opening formed in the insulating layer 404 and the insulating layer 434.
Connect with 2 electrically. Note that the transistor 121 can be manufactured according to the manufacturing method described in the above embodiment. Further, another semiconductor element, a wiring, or the like may be formed above the transistor 121.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Seventh Embodiment
In this embodiment, as an example of applying the configuration disclosed in the above embodiment to a semiconductor device,
The CPU (Central Processing Unit) will be described.

FIG. 10A is a block diagram showing a specific configuration of the CPU. C shown in FIG.
The PU is an arithmetic circuit (ALU: Arithmetic logic u) on a substrate 1190.
nit) 1191, ALU controller 1192, instruction decoder 1193
, Interrupt controller 1194, timing controller 1195, register 11
96, register controller 1197, bus interface (Bus I / F) 119
8. Rewritable ROM 1199 and ROM interface (ROM I / F) 1
It consists of 189 blocks. The substrate 1190 uses a semiconductor substrate.
The ROM 1199 and the ROM I / F 1189 may be provided on separate chips. Needless to say, the CPU illustrated in FIG. 10A is merely an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, a plurality of one or more types of the circuits described above may be provided over the substrate 1190.

An instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193 and decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instruction. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or the mask state while the program of the CPU is being executed. The register controller 1197 generates an address of the register 1196 and performs reading and writing of the register 1196 according to the state of the CPU.

The timing controller 1195 also includes an ALU 1191 and an ALU controller 119.
2. Generate a signal that controls the operation timing of the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, timing controller 1195 generates internal clock signal C based on reference clock signal CLK1.
An internal clock generation unit for generating LK2 is provided, and the internal clock signal CLK2 is supplied to the various circuits.

By applying the configuration disclosed in the above embodiment to each block constituting the CPU,
The Vth of the transistors included in each block can be set to an optimal value. Also, CPU
Variations in the Vth of the transistors that make up the circuit can be reduced, and the operation can be stabilized.
Further, by setting the Vth of the transistor to an appropriate value, it is possible to increase the operating speed of the CPU, reduce the off-state current of the transistor, and reduce the power consumption of the CPU.

In the CPU illustrated in FIG. 10A, the memory cell is provided in the register 1196. The memory cell described in the above embodiment can be used for the memory cell of the register 1196.

In the CPU shown in FIG. 10A, the register controller 1197 is an ALU 1191.
In accordance with the instruction from, the selection of the holding operation in register 1196 is performed. That is, in the memory cell included in the register 1196, it is selected whether to hold data by the phase inversion element or hold data by the capacitance element. When retention of data by the phase inversion element is selected, supply of power supply voltage to the memory cell in the register 1196 is performed.
When data retention in the capacitor is selected, data rewriting to the capacitor is performed, and supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

Regarding power supply stop, as shown in FIG. 10 (B) or FIG. 10 (C), a memory cell group, and
This can be performed by providing a switching element between nodes to which the power supply potential VDD or the power supply potential VSS is applied. The circuits of FIGS. 10B and 10C will be described below.

10B and 10C illustrate an example of a structure of a memory circuit including the transistor disclosed in the above embodiment for a switching element which controls supply of power supply potential to a memory cell.

The memory device illustrated in FIG. 10B includes a switching element 1141 and a memory cell group 1143 including a plurality of memory cells 1142. Specifically, each memory cell 1142
The memory cell disclosed in the above embodiment can be used. The memory cell 1142 of the memory cell group 1143 is supplied with the high level power supply potential VDD through the switching element 1141. Furthermore, each memory cell 11 of memory cell group 1143 has
The potential of the signal IN and the potential of the low level power supply potential VSS are given to the reference numeral 42.

In FIG. 10B, the transistor disclosed in the above embodiment is used as the switching element 1141, and the switching of the transistor is controlled by a signal SigA supplied to its gate electrode.

Note that FIG. 10B illustrates a structure in which the switching element 1141 includes only one transistor; however, without particular limitation, a plurality of transistors may be included. When the switching element 1141 includes a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or a combination of series and parallel May be connected.

In FIG. 10B, the switching element 1141 controls supply of the high-level power supply potential VDD to each memory cell 1142 included in the memory cell group 1143, but the switching element 1141 controls low level. The supply of the power supply potential VSS may be controlled.

FIG. 10C illustrates an example of a memory device in which the low-level power supply potential VSS is supplied to each memory cell 1142 in the memory cell group 1143 through the switching element 1141. The switching element 1141 can control supply of the low-level power supply potential VSS to each memory cell 1142 included in the memory cell group 1143.

A switching element is provided between the memory cell group and a node supplied with the power supply potential VDD or the power supply potential VSS, and the operation of the CPU is temporarily stopped and data is retained even when the supply of the power supply voltage is stopped. It is possible to reduce power consumption. Specifically, for example, even while a user of a personal computer stops inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing power consumption. it can.

By applying the configuration disclosed in the above embodiment to each memory cell 1142 included in the memory cell group 1143, Vth of a transistor included in each memory cell 1142 can be set to an optimal value. Further, the Vth variation of the transistors included in the memory cell group 1143 can be reduced, and the operation can be stabilized. Also, Vt of the transistor to be turned on
Since h can be reduced, the operating speed of the memory cell group 1143 can be increased. In addition, since Vth of the transistor to be turned off can be increased, off current of the transistor can be further reduced and power consumption of the memory cell group 1143 can be reduced.

Further, since the switch 105 disclosed in the above embodiment can be used as a memory element for storing information in the node 120, the switch 105 can be used for the memory cell 1142.

In the present embodiment, the CPU has been described as an example, but the transistors disclosed in the above embodiments may be DSP (Digital Signal Processor), custom LS
I, L such as FPGA (Field Programmable Gate Array)
It is also possible to use for SI.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Further, a comparison table of a spin MRAM (spin injection magnetization reversal type MRAM) known as a spintronics device and a memory using an oxide semiconductor is shown in Table 1.

As shown in Table 1, a memory in which a transistor including an oxide semiconductor and a transistor including silicon are combined is largely different in driving method, writing principle, material, and the like from a spintronics device.

In addition, as shown in Table 1, the memory in which a transistor using an oxide semiconductor and a transistor using silicon are combined is more resistant to heat, made 3D (layered structure of three or more layers), and a magnetic field as compared to a spintronics device. It is advantageous in many points such as tolerance. Note that overhead power in Table 1 means that when multiple processors spin on one lock, these processors contend for locks and system performance by creating excessive traffic on the bus and system interconnects. Power that is consumed in the so-called overhead.

As described above, power saving of the CPU can be realized by using a memory using an oxide semiconductor that has many advantages over spintronic devices.

Eighth Embodiment
The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). Examples of the electronic device include a display device such as a television and a monitor, a lighting device, a desktop computer or a notebook personal computer, a word processor, a DVD (Digital Device
Image playback device for playing back still images or moving images stored in recording media such as Versatile Disc, portable CD players, radios, tape recorders, headphone stereos, stereos, cordless handsets, transceivers, portable radios, mobile phones, Car phones, portable game machines, calculators, portable information terminals, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, high-frequency heating devices such as electric shavers, microwave ovens, electric rice cookers, Air conditioners such as electric washing machines, electric vacuum cleaners, air conditioners, dishwashers, dish dryers, clothes dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerators, DNA freezers, smoke detectors, radiation Examples include a measuring instrument, and a medical device such as a dialysis device. Furthermore, industrial devices such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems can also be mentioned. In addition, an engine using petroleum, a moving object driven by an electric motor using electric power from a non-aqueous secondary battery, and the like are also included in the category of electric devices. As the moving body, for example, an electric vehicle (EV), a hybrid vehicle (HEV) having an internal combustion engine and a motor together, a plug-in hybrid vehicle (PHEV)
), These tire wheels are converted to endless tracks, motorized bicycles including electric assist bicycles, motorcycles, electric wheelchairs, electric carts, golf carts, small or large ships, submarines, helicopters, aircrafts, rockets, satellites , Space probes, planet probes, and spacecraft. Specific examples of these electronic devices are shown in FIG. 11 to FIG.

FIG. 11A shows a table 9000 having a display portion. Table 9000 is
A display portion 9003 is incorporated in the housing 9001, and the display portion 9003 can display an image. Note that a structure in which the housing 9001 is supported by four leg portions 9002 is shown. In addition, a power supply cord 9005 for supplying power is included in a housing 9001.

The display portion 9003 has a touch input function, and by touching the display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, screen operation and information can be input, and the other By enabling communication with a home appliance or enabling control, it may be a control device that controls another home appliance by screen operation. For example, with the use of a semiconductor device having an image sensor function, the display portion 9003 can have a touch input function.

In addition, with the hinge provided in the housing 9001, the screen of the display portion 9003 can be erected perpendicularly to the floor, and can also be used as a television set. In a small room, a large screen television device will narrow the free space if installed, but if the display unit is built in the table, the room space can be used effectively.

The configuration disclosed in the above embodiment can also be applied to a display portion. By applying the configuration disclosed in the above embodiment to table 9000, table 9000 having a display portion
Operation can be stabilized and reliability can be improved. In addition, the operating speed can be increased and the power consumption can be reduced.

FIG. 11B shows a portable music player, and a main body 3021 is provided with a display portion 3023, a fixing portion 3022 to be attached to the ear, a speaker, an operation button 3024, an external memory slot 3025 and the like. By applying the transistor or the memory device described in any of the above embodiments to a memory, a CPU, or the like incorporated in the main body 3021, a portable music player (PDA) with more power saving can be obtained.

Furthermore, if the portable music player shown in FIG. 11B is provided with an antenna, a microphone function and a wireless function and cooperated with a mobile phone, hands-free wireless conversation is possible while driving a passenger car or the like.

By applying the configuration disclosed in the above embodiment to the portable music player, the operation of the portable music player can be stabilized and the reliability can be enhanced. In addition, the operating speed can be increased and the power consumption can be reduced.

11C illustrates a computer, which includes a main body 9201 including a CPU, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 92.
Includes 06 mag. The computer is manufactured by using a semiconductor device manufactured using one embodiment of the present invention.

By applying the configuration disclosed in the above embodiment to a computer, the operation of the computer can be stabilized and reliability can be improved. In addition, the operating speed can be increased and the power consumption can be reduced.

12A and 12B illustrate a tablet terminal that can be folded. Figure 12 (A)
Is open, and the tablet terminal includes a housing 9630, a display portion 9631 having a display portion 9631a and a display portion 9631b, a display mode switch 9626, a power switch 9627, a power saving mode switch 9625, and a fastener 9629. , Operation switch 9
628,.

By applying the configuration disclosed in the above embodiment to the tablet terminal, the operation of the tablet terminal can be stabilized and reliability can be improved. In addition, the operating speed can be increased and the power consumption can be reduced.

A portion of the display portion 9631 a can be a touch panel area 9632 a, and data can be input by touching the displayed operation key 9638. Note that the display portion 963
In 1a, as an example, a half area shows a configuration having only a display function, and the other half area shows a configuration having a touch panel function, but the present invention is not limited to this configuration. Display unit 963
The entire region 1a may have a touch panel function. For example, the display unit 96
A keyboard button can be displayed on the entire surface 31 a to form a touch panel, and the display portion 9631 b can be used as a display screen.

Further, in the display portion 9631 b, as in the display portion 9631 a, part of the display portion 9631 b can be used as a region 9632 b of the touch panel. In addition, by touching the position where the keyboard display switching button 9639 on the touch panel is displayed with a finger or a stylus, a keyboard button can be displayed on the display portion 9631 b.

Further, touch input can be performed simultaneously on the touch panel region 9632 a and the touch panel region 9632 b.

In addition, the display mode switching switch 9626 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9625 can optimize display luminance in accordance with the amount of external light at the time of use detected by the light sensor incorporated in the tablet terminal. The tablet type terminal may incorporate not only an optical sensor but also other detection devices such as a sensor for detecting inclination of a gyro, an acceleration sensor or the like.

12A shows an example in which the display areas of the display portion 9631 b and the display portion 9631 a are the same, but is not particularly limited, one size may be different from the other size, and the display quality is also shown. It may be different. For example, a display panel in which one can perform higher definition display than the other may be used.

The tablet terminal is closed in FIG. 12B and the housing 9630 and the solar battery 96 are shown in FIG.
33 includes a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that in FIG. 12B, the battery 9635 is an example of the charge and discharge control circuit 9634.
, DCDC converter 9636 is shown.

Note that since the tablet terminal can be folded in half, the housing 9630 can be closed when not in use. Therefore, since the display portion 9631 a and the display portion 9631 b can be protected, it is possible to provide a tablet terminal which is excellent in durability and excellent in reliability even from the viewpoint of long-term use.

In addition to this, the tablet type terminal shown in FIGS. 12A and 12B has a function of displaying various information (still image, moving image, text image, etc.), a calendar, a date or time, etc. A function of displaying on the display portion, a touch input function of performing touch input operation or editing of information displayed on the display portion, a function of controlling processing by various software (programs), and the like can be provided.

Electric power is applied to the touch panel by a solar cell 9633 mounted on the surface of the tablet terminal.
It can be supplied to a display unit or a video signal processing unit or the like. Note that the solar battery 9633 can charge the battery 9635 efficiently on one surface or two surfaces of the housing 9630, which is preferable. When a lithium ion battery is used as the battery 9635, advantages such as downsizing can be achieved.

The structure and operation of the charge and discharge control circuit 9634 illustrated in FIG.
The block diagram is shown in FIG. In FIG. 12C, a solar battery 9633 and a battery 96 are shown.
35, DCDC converter 9636, converter 9637, switches SW1 to SW3,
The display portion 9631 is illustrated, and the battery 9635 and the DCDC converter 9636 are illustrated.
The converter 9637 and the switches SW1 to SW3 are portions corresponding to the charge and discharge control circuit 9634 shown in FIG.

First, an example of operation in the case where electric power is generated by the solar battery 9633 by external light will be described.
The power generated by the solar cell is DCD to be the voltage for charging the battery 9635.
The C converter 9636 boosts or lowers the voltage. Then, when the power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW 1 is turned on to convert the converter 96.
At 37, the voltage required for the display portion 9631 is boosted or lowered. In addition, the display unit 96
When the display at 31 is not performed, the SW1 is turned off, the SW2 is turned on, and the battery 96 is turned on.
It may be configured to charge 35.

Although the solar cell 9633 is illustrated as an example of the power generation means, it is not particularly limited, and the battery 9635 is charged by another power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). It may be. For example, a non-contact power transmission module that transmits and receives power wirelessly (without contact) to charge the battery, or another charging unit may be combined.

In FIG. 13A, in the television device 8000, a display portion 8002 is incorporated in a housing 8001. The display portion 8002 can display an image and a speaker portion 8003 can output sound.

The display portion 8002 is a light emitting device including a light emitting element such as a liquid crystal display device or an organic EL element in each pixel, an electrophoresis display device, a DMD (Digital Micromirror Devic).
e) A semiconductor display device such as a PDP (Plasma Display Panel) can be used.

The television set 8000 may include a receiver, a modem, and the like. The television device 8000 can receive general television broadcast by a receiver, and further can connect to a wired or wireless communication network via a modem to be unidirectional (sender to receiver) or bidirectional. It is also possible to perform information communication (between the sender and the receiver, or between the receivers, etc.).

In addition, the television set 8000 may include a CPU for performing information communication and a memory. The television set 8000 can use the structure described in the above embodiment.

In FIG. 13A, an air conditioner including an indoor unit 8200 and an outdoor unit 8204 is an example of an electric device using the CPU described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. Figure 13 (A)
In the example, the CPU 8203 is provided in the indoor unit 8200, but
The CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using the CPU described in the above embodiment, a highly reliable air conditioner can be realized.

In FIG. 13A, an electric refrigerator-freezer 8300 is an example of an electric device including the CPU described in the above embodiment. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, and the like. In FIG. 13 (A),
The CPU 8304 is provided in the housing 8301.

By applying the configuration disclosed in the above embodiment to the electric refrigerator-freezer, the operation of the electric refrigerator-freezer can be stabilized and the reliability can be improved. In addition, power consumption can be reduced.

13 (B) and 13 (C) show an example of an electric vehicle which is an example of the electric device.
FIG. 13C is a view related to the inside of the electric vehicle 9700. An electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted in output by the control circuit 9702 and supplied to the driver 9703. The control circuit 9702 is controlled by a processing unit 9704 having a ROM, a RAM, a CPU, and the like (not shown). Power saving can be achieved by using the CPU described in the above embodiment mode for the CPU of the electric vehicle 9700.

Drive device 9703 is configured by combining a DC motor or an AC motor alone, or a motor and an internal combustion engine. The processing device 9704 is based on input information of operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and information at the time of traveling (information of uphill, downhill, etc., load information of drive wheels, etc.) , And outputs a control signal to the control circuit 9702. Control circuit 9
In accordance with a control signal of the processing unit 9704, the control unit 702 adjusts the electrical energy supplied from the secondary battery 9701 to control the output of the driving unit 9703. When an AC motor is mounted, although not shown, an inverter for converting direct current into alternating current is also incorporated.

By applying the configuration disclosed in the above embodiment to the electric vehicle, the electric vehicle can be stably controlled, and the reliability can be enhanced.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

DESCRIPTION OF SYMBOLS 101 integrated circuit 102 block 103 value voltage detection circuit 104 logic circuit 105 switch 107 logic circuit 108 wiring 109 wiring 111 transistor 113 switch 114 load 115 node 116 transistor 117 switch 120 node 121 transistor 122 transistor 123 capacitive element 124 transistor 125 terminal 126 node 127 Capacitive element 128 transistor 129 transistor 131 circuit 132 circuit 136 node 146 switch 147 switch 151 transistor 151 insulating layer 202 gate electrode 205 oxide semiconductor layer 300 transistor 301 n-type semiconductor substrate 302 p-type well 303 gate insulating layer 304 gate electrode 311 Curve 312 Curve 400 Substrate 401 Substrate 402 Electrode 403 Insulation 404 insulating layer 405 oxide semiconductor layer 406 oxide semiconductor layer 408 gate insulating layer 410 insulating layer 411 interlayer insulating layer 412 barrier metal layer 413 low resistance conductive layer 414 barrier metal layer 431 oxygen 434 insulating layer 436 oxide insulating layer 440 transistor 450 Transistor 481 oxygen excess region 657 wiring layer 658 wiring layer 659 wiring layer 684 insulating layer 687 insulating layer 692 wiring layer 700 substrate 701 well 751 gate electrode 752 gate insulating layer 753 channel formation region 754 n-type impurity region 755 n-type impurity region 756 sidewall Insulating layer 757 p-type impurity region 788 insulating layer 789 element isolation region 1141 switching element 1142 memory cell 1143 memory cell group 1190 substrate 1191 ALU
1192 ALU controller 1193 instruction decoder 1194 interrupt controller 1195 timing controller 1196 registers 1197 register controller 1198 bus interface 1199 ROM
3021 main unit 3022 fixed unit 3023 display unit 3024 operation button 3025 external memory slot 8000 television apparatus 8001 housing 8002 display unit 8003 speaker unit 8200 indoor unit 8201 housing 8202 air outlet 8203 CPU
8204 outdoor unit 8300 electric refrigerator-freezer 8301 housing 8302 refrigerator room door 8303 freezer room door 8304 CPU
9000 table 9001 housing 9002 leg 9003 display 9004 display button 9005 power cord 9201 main body 9202 housing 9203 display 9204 keyboard 9205 external connection port 9206 pointing device 9625 switch 9626 switch 9627 power switch 9628 operation switch 9629 tool 9630 housing 9631 Display portion 9633 Solar battery 9634 Charge and discharge control circuit 9635 Battery 9636 DCDC converter 9637 Converter key 9639 Button 9700 Electric car 9701 Secondary battery 9702 Control circuit 9703 Drive device 9704 Processor 102_a block 102_a block 102_b block 102_c block 102_d block 102_e block 102_e block 102_e block 102_g buro Block 102_h block 102a block 103a value voltage detection circuit 103b value voltage detection circuit 105nH switch 105nL switch 105pL switch 106nH wiring 106nL wiring 106pL wiring 106pL wiring 106VnH wiring 106VnL wiring 108n n wiring 108n_2 wiring 108n_3 wiring 108nH wiring line 108 wiring line 108 wiring line Wiring 109_1 Wiring 109_3 Wiring 109a Diffusion layer 305b Diffusion layer 305b Diffusion layer 406a Source electrode 406b Drain electrode 407a Source electrode 407a Gate electrode 409b Gate electrode 493a Capacitance electrode 693b Capacitance electrode 9631a Display portion 9631b Display portion 9632a Region 9632b Region Region

Claims (1)

A first switch, a second switch, and a logic circuit,
The first switch includes a first transistor, a second transistor, and a first capacitive element.
The second switch includes a third transistor, a fourth transistor, and a second capacitive element.
The logic circuit comprises a fifth transistor,
One of the source or the drain of the first transistor is electrically connected to the gate of the second transistor,
The first capacitive element is electrically connected to the gate of the second transistor,
One of the source or the drain of the second transistor is electrically connected to the body of the fifth transistor,
The other of the source and the drain of the second transistor is electrically connected to a first wiring to which a first potential is supplied,
One of the source or the drain of the third transistor is electrically connected to the gate of the fourth transistor,
The second capacitive element is electrically connected to the gate of the fourth transistor,
One of the source or the drain of the fourth transistor is electrically connected to the body of the fifth transistor,
Wherein the other of the source and the drain of the fourth transistor, the second wiring electrically connected to Ru semiconductor device in which the second potential is supplied.

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