JP6540912B2 - 電子部品及びその製造方法 - Google Patents
電子部品及びその製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
- H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
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- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
- H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/019—Manufacture or treatment using temporary auxiliary substrates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図1(a)〜図1(c)〜図6を参照して、第1の実施形態の電子部品の製造方法及び第1の実施形態に係る電子部品を説明する。
図7(a)及び図7(b)〜図9(a)及び図9(b)を参照して、第2の実施形態に係る電子部品の製造方法を説明する。
図10は、本発明に係る電子部品の変形例を説明するための部分切欠き拡大正面断面図である。
図12は、本発明の第3の実施形態に係る電子部品の正面断面図である。
2…接着材
3…金属シート
4…積層体
5…仮固定用粘着剤
6…電子部品素子
6a…圧電体
6b…樹脂層
6d…IDT電極
6e,6f…側面
6g…一方主面
6h,6i…側面
6j…他方主面
7a,7b…端子
8…レジストパターン
8a,8b…開口
9,10,10A,10B…貫通電極
11…樹脂構造体
11a…第1の面
11b…第2の面
12,13…配線
15…電子部品素子
15a…電子部品素子本体
15b,15c…電極ランド
15d,15e…金属バンプ
16…電子部品
21…レジストパターン
21a,21b…開口
22,23…貫通電極
24…樹脂構造体
25…電子部品
31…電子部品
32…電子部品素子
32a…Si半導体チップ
32b…拡散防止膜
33…ゲート電極
34…配線
35…貫通電極
41,51,61,62…電子部品
42a〜42c…端子電極
43a〜43c…金属バンプ
52,55a,55b…配線
53a〜53d…絶縁層
54a〜54d…絶縁層
Claims (13)
- 対向し合う第1の面と第2の面を有する樹脂構造体と、
前記樹脂構造体に内蔵されており、一方主面と対向している他方主面と、前記一方主面と前記他方主面を結ぶ複数の側面とを有し、前記樹脂構造体における前記第1の面で露出している電子部品素子と、
前記樹脂構造体における前記第1の面と前記第2の面とを結ぶように樹脂構造体を貫通している貫通電極と、
を備え、
前記貫通電極が、前記電子部品素子における前記複数の側面のうち少なくとも1つの前記側面に接触している、電子部品。 - 前記貫通電極が複数設けられており、
複数の前記貫通電極が、前記電子部品素子における前記複数の側面のうちのいずれかの前記側面に接触している、請求項1に記載の電子部品。 - 前記複数の貫通電極のうち、少なくとも1つの貫通電極と、残りの少なくとも1つの貫通電極とが、前記電子部品素子における異なる前記側面に接触している、請求項2に記載の電子部品。
- 前記電子部品素子において、前記複数の側面が、対向し合う一対の前記側面を有しており、
前記少なくとも1つの貫通電極が、前記一対の側面のうちの一方の前記側面に接触しており、
前記残りの少なくとも1つの貫通電極が、前記一対の側面のうちの他方の前記側面に接触している、請求項3に記載の電子部品。 - 前記樹脂構造体における前記第1の面または前記第2の面に設けられており、前記貫通電極に電気的に接続されている配線をさらに備える、請求項1〜4のいずれか1項に記載の電子部品。
- 前記電子部品素子の少なくとも前記複数の側面に設けられた拡散防止膜をさらに有し、前記貫通電極が前記拡散防止膜に接触している、請求項1〜5のいずれか1項に記載の電子部品。
- 前記電子部品素子が、Si半導体チップであり、
前記Si半導体チップにおける複数の側面のうちのいずれかの側面上の前記拡散防止膜に、前記貫通電極が接触している、請求項6に記載の電子部品。 - 前記樹脂構造体の前記第1の面または前記第2の面に実装された他の電子部品素子をさらに備える、請求項1〜6のいずれか1項に記載の電子部品。
- 前記樹脂構造体の前記第1の面または第2の面に、他の電子部品が実装されている、請求項1〜8のいずれか1項に記載の電子部品。
- 粘着剤を用いて、金属シート上に電子部品素子を仮固定する工程と、
前記電子部品素子における複数の側面のうちのいずれかの前記側面に接している部分に開口を有し、該開口に前記金属シートが露出している、レジストパターンを形成する工程と、
前記レジストパターンにおける前記開口内において、めっきにより金属膜を形成し、前記電子部品素子の前記側面に接触している貫通電極を形成する工程と、
前記レジストパターンを剥離する工程と、
前記電子部品素子及び前記貫通電極を封止するように、樹脂材料を前記金属シート上に付与する工程と、
前記樹脂材料を硬化させて、樹脂構造体を形成する工程と、
前記金属シートを除去する工程と、
を備える、電子部品の製造方法。 - 前記樹脂材料を付与した後に、プレスする工程をさらに備える、請求項10に記載の電子部品の製造方法。
- 前記金属シートを除去した後に、前記樹脂構造体を薄くし、前記貫通電極を前記樹脂構造体の対向し合う第1の面と第2の面に露出させる、請求項10または11に記載の電子部品の製造方法。
- 前記樹脂構造体の前記第1の面または前記第2の面に、前記貫通電極に電気的に接続されるように配線を設ける工程をさらに備える、請求項12に記載の電子部品の製造方法。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016237299 | 2016-12-07 | ||
| JP2016237299 | 2016-12-07 | ||
| PCT/JP2017/037020 WO2018105233A1 (ja) | 2016-12-07 | 2017-10-12 | 電子部品及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP6540912B2 true JP6540912B2 (ja) | 2019-07-10 |
| JPWO2018105233A1 JPWO2018105233A1 (ja) | 2019-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018554844A Active JP6540912B2 (ja) | 2016-12-07 | 2017-10-12 | 電子部品及びその製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US11004759B2 (ja) |
| JP (1) | JP6540912B2 (ja) |
| CN (1) | CN110050338B (ja) |
| WO (1) | WO2018105233A1 (ja) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20260123505A1 (en) * | 2024-04-30 | 2026-04-30 | Resonac Corporation | Method for manufacturing semiconductor device, and wiring board |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005310954A (ja) | 2004-04-20 | 2005-11-04 | Nec Corp | 半導体パッケージとその製造方法 |
| JP2006013170A (ja) * | 2004-06-25 | 2006-01-12 | Matsushita Electric Works Ltd | 電子部品並びに電子部品の製造方法 |
| FI20060256A7 (fi) | 2006-03-17 | 2006-03-20 | Imbera Electronics Oy | Piirilevyn valmistaminen ja komponentin sisältävä piirilevy |
| JP4752825B2 (ja) | 2007-08-24 | 2011-08-17 | カシオ計算機株式会社 | 半導体装置の製造方法 |
| US7834464B2 (en) * | 2007-10-09 | 2010-11-16 | Infineon Technologies Ag | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device |
| JP5248084B2 (ja) * | 2007-10-26 | 2013-07-31 | 新光電気工業株式会社 | シリコンインターポーザとこれを用いた半導体装置用パッケージおよび半導体装置 |
| US7968378B2 (en) * | 2008-02-06 | 2011-06-28 | Infineon Technologies Ag | Electronic device |
| US7659145B2 (en) * | 2008-07-14 | 2010-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device |
| JP5471268B2 (ja) * | 2008-12-26 | 2014-04-16 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法 |
| JP5535494B2 (ja) * | 2009-02-23 | 2014-07-02 | 新光電気工業株式会社 | 半導体装置 |
| US8169065B2 (en) * | 2009-12-22 | 2012-05-01 | Epic Technologies, Inc. | Stackable circuit structures and methods of fabrication thereof |
| TWI434382B (zh) * | 2011-07-06 | 2014-04-11 | Unimicron Technology Corp | 嵌埋有電子元件之封裝結構及其製法 |
| US8922013B2 (en) * | 2011-11-08 | 2014-12-30 | Stmicroelectronics Pte Ltd. | Through via package |
| JP5949193B2 (ja) * | 2012-06-12 | 2016-07-06 | 富士通株式会社 | 電子装置の製造方法 |
| KR101804496B1 (ko) * | 2013-07-17 | 2017-12-04 | 가부시키가이샤 무라타 세이사쿠쇼 | 전자부품 및 그 제조방법 |
| JP6468017B2 (ja) * | 2015-03-18 | 2019-02-13 | 日立化成株式会社 | 半導体装置の製造方法 |
-
2017
- 2017-10-12 WO PCT/JP2017/037020 patent/WO2018105233A1/ja not_active Ceased
- 2017-10-12 JP JP2018554844A patent/JP6540912B2/ja active Active
- 2017-10-12 CN CN201780075385.XA patent/CN110050338B/zh active Active
-
2019
- 2019-05-15 US US16/412,822 patent/US11004759B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110050338B (zh) | 2023-02-28 |
| WO2018105233A1 (ja) | 2018-06-14 |
| JPWO2018105233A1 (ja) | 2019-07-11 |
| CN110050338A (zh) | 2019-07-23 |
| US20190267303A1 (en) | 2019-08-29 |
| US11004759B2 (en) | 2021-05-11 |
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