JP6572640B2 - Method for fabricating semiconductor light receiving element - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor light receiving element.

  Patent Document 1 discloses a light receiving element.

JP 2006-269978 A

  The light receiving element of Patent Document 1 includes a silicon nitride film provided on a side surface of a semiconductor mesa. A light receiving element having a mesa structure has a mesa side surface made of a semiconductor. The mesa side surface can be covered with a semiconductor having a wider band gap than the band gap of the light receiving layer in the semiconductor mesa. Such a semiconductor is formed by regrowth. However, an insulating film such as a silicon nitride film is used in a light receiving element having a structure to which a semiconductor coating film cannot be applied. Unlike the semiconductor coating, for example, the formation of a silicon nitride (SiN) coating is less difficult to apply due to the element structure. In addition, in an insulating film such as SiN, it is difficult to apply the insulating film and the quality of the insulating film. However, according to the knowledge of the inventors, in the structure in which the insulating film directly covers the side surface of the semiconductor mesa, the light receiving element The leakage current becomes conspicuous. According to the inventor's investigation, the protective film of the light receiving element considers both of the following viewpoints: the ability of the light receiving element to protect the outside world; and the ability to prevent leakage current related to the semiconductor mesa side of the light receiving element.

  One aspect of the present invention has been made in view of such a background, and an object thereof is to provide a method of manufacturing a semiconductor light receiving element having a structure capable of reducing a leakage current related to a semiconductor mesa side surface. To do.

A method of manufacturing a semiconductor light receiving element according to one aspect of the present invention includes a step of preparing a semiconductor epitaxial region including a semiconductor layer for a light receiving layer made of a semiconductor including a group III element and a group V element, and the semiconductor epitaxial region Forming a mask on the main surface of the substrate, etching the semiconductor epitaxial region using the mask, forming a substrate product including a semiconductor mesa formed by the etching, and the substrate product A step of arranging in a plasma processing apparatus, a step of supplying a gas containing at least one of oxygen and N ₂ O to the plasma processing apparatus, and performing a plasma treatment of the substrate product by the plasma of the gas; After the plasma processing, a raw material containing an oxidation source and a silicon source is supplied to the plasma processing apparatus to produce the substrate. Depositing silicon oxide on the surface of the substrate, and forming the substrate product, wherein the light receiving layer reaches a side surface of the semiconductor mesa, and the group III element includes gallium and indium. Including at least one of them.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to one aspect of the present invention, there is provided a method of manufacturing a semiconductor light receiving element having a structure capable of reducing a leakage current related to a semiconductor mesa side surface.

FIG. 1 is a drawing schematically showing main steps in a method for producing a semiconductor light receiving element according to the present embodiment. FIG. 2 is a drawing schematically showing main steps in the method of manufacturing the semiconductor light receiving element according to the present embodiment. FIG. 3 is a drawing schematically showing main steps in the method of manufacturing the semiconductor light receiving element according to the present embodiment. FIG. 4 is a drawing schematically showing main steps in the method for producing the semiconductor light receiving element according to the present embodiment. FIG. 5 is a drawing schematically showing main steps in the method of manufacturing the semiconductor light receiving element according to the present embodiment. FIG. 6 is a drawing showing the passivation structures of several light receiving elements. FIG. 7 is a drawing showing a sketch of a transmission electron microscope image near the side surface of an InGaAs / GaAsSb superlattice to which N ₂ O plasma treatment is applied. FIG. 8 is a diagram showing characteristics of dark current in several light receiving elements. Figure 9 is a diagram showing the relationship between the N 2 _O gas of the deposition temperature of the SiO ₂ deposited on the oxide film formed by plasma treatment and SiO ₂ film stress.

  Next, some specific examples will be described.

A method of manufacturing a semiconductor light receiving element according to one aspect includes: (a) preparing a semiconductor epitaxial region including a semiconductor layer for a light receiving layer made of a semiconductor including a group III element and a group V element; Forming a mask on a main surface of the semiconductor epitaxial region; and (c) etching the semiconductor epitaxial region using the mask to form a substrate product including a semiconductor mesa formed by the etching. (D) placing the substrate product in a plasma processing apparatus; (e) supplying a gas containing at least one of oxygen and N ₂ O to the plasma processing apparatus; A step of performing a plasma treatment of the substrate product; and (f) after the plasma treatment, a raw material including an oxidation source and a silicon source is added to the substrate product. And depositing silicon oxide on the surface of the substrate product, and in the step of forming the substrate product, the light receiving layer reaches a side surface of the semiconductor mesa, and the III The group element includes at least one of gallium and indium.

According to the method for manufacturing a semiconductor light receiving element, when the semiconductor mesa surface of the substrate product is exposed to a plasma of a gas containing at least one of oxygen and N ₂ O, a group III oxidation containing a group III element of the semiconductor layer is performed. An object is formed on the side surface of the light receiving layer located on the side surface of the semiconductor mesa. By growing silicon oxide on the group III oxide, the semiconductor side surface of the light receiving layer is not directly exposed to the silicon in the silicon oxide. With the stacked structure including the group III oxide and the silicon oxide, the interface state density causing the leakage current can be reduced on the side of the semiconductor mesa, and the passivating ability of the silicon oxide can be enjoyed.

  In the method for manufacturing a semiconductor light receiving element according to one embodiment, the stage temperature of the plasma processing apparatus is 150 degrees Celsius or less during the plasma processing.

  According to the method for manufacturing a semiconductor light receiving element, a stage temperature of 150 degrees Celsius or less can provide low film stress to silicon oxide.

  In the method for manufacturing a semiconductor light receiving element according to one embodiment, the semiconductor layer includes InGaAs.

  According to the method for manufacturing a semiconductor light receiving element, the side surface of the semiconductor mesa is covered with a coating film including gallium oxide, indium oxide, and gallium indium oxide.

  In the method for manufacturing a semiconductor light receiving element according to one embodiment, the semiconductor layer has a superlattice structure including a III-V semiconductor layer including antimony as the group V element.

  According to the method of manufacturing a semiconductor light receiving element, the superlattice structure has a side surface having roughness corresponding to the alternating arrangement of superlattice layers constituting the superlattice structure, and the semiconductor side surface is made of gallium oxide. , Covered with a coating film comprising indium oxide and gallium indium oxide.

  In the method for manufacturing a semiconductor light receiving element according to one embodiment, the light receiving layer is an InGaAs layer.

  According to the method for manufacturing the semiconductor light receiving element, the side surface of the InGaAs layer is covered with a coating film including gallium oxide, indium oxide, and gallium indium oxide.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, a method for manufacturing a semiconductor light receiving element and an embodiment of the present invention relating to the semiconductor light receiving element will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

1 to 5 are drawings showing main steps in a method of manufacturing a semiconductor light receiving element according to this embodiment. As shown in part (a) of FIG. 1, in step ST <b> 1, a semiconductor stack 13 is grown on the semiconductor substrate 11 to form an epitaxial substrate E. The semiconductor stack 13 includes a first semiconductor layer 15 for the light receiving layer grown on the main surface 13 a of the semiconductor substrate 11. In the example shown in FIG. 1A, the semiconductor stack 13 further includes a second semiconductor layer 17a and a third semiconductor layer 17b, and the second semiconductor layer 17a and the third semiconductor layer 17b are the first semiconductor. Grown on layer 15. This crystal growth is performed, for example, by metal organic vapor phase epitaxy or molecular beam epitaxy. In the present embodiment, the first semiconductor layer 15 includes a single semiconductor layer 19 and a superlattice semiconductor layer 21. However, the first semiconductor layer 15 for the light receiving layer may include at least one of the single semiconductor layer 19 and the superlattice semiconductor layer 21, and in the following description, the semiconductor stack 13 includes the single semiconductor layer 19 and A structure comprising both superlattice semiconductor layers 21 will be described. If necessary, the semiconductor stack 13 can further include a buffer layer, which is grown on the main surface 13 a of the semiconductor substrate 11 prior to the growth of the first semiconductor layer 15. The material of the buffer layer is, for example, the same material as that of the semiconductor substrate 11. In this embodiment, the epitaxial substrate E includes a semiconductor substrate 11 and a semiconductor epitaxial region, and the semiconductor epitaxial region includes a semiconductor stack 13.
An example of the semiconductor stack 13.
Semiconductor substrate 11: n-type InP.
Single semiconductor layer 19 of the first semiconductor layer 15: n-type or diluted p-type InGaAs.
The superlattice semiconductor layer 21 of the first semiconductor layer 15 is an n-type or diluted p-type InGaAs (5 nm) / n-type or diluted p-type GaAsSb (5 nm) superlattice structure, and the InGaAs / GaAsSb superlattice is of type II. Has a band structure.
Second semiconductor layer 17a: p-type InGaAs.
Third semiconductor layer 17b: p-type InP.
The semiconductor stack 13 may include one of the second semiconductor layer 17a and the third semiconductor layer 17b.
Another example of the semiconductor stack 13.
Semiconductor substrate 11: n-type GaSb.
Substrate upper layer 11a: p-type GaSb.
Superlattice semiconductor layer 21 of the first semiconductor layer 15: a dilute p-type InAs / diluted p-type GaSb superlattice structure, and the InAs / GaSb superlattice has a type II band structure.
Second semiconductor layer 17a: n-type InAs.

  As shown in part (b) of FIG. 1, in step ST <b> 2, a mask 23 for forming a semiconductor mesa is formed on the main surface 13 a of the semiconductor stack 13 by etching. Referring to part (b) of FIG. 1 and part (a) of FIG. 2, the mask 23 has patterns 23 a to 23 i arranged in one element section on the main surface 13 a of the semiconductor stack 13. If necessary, the mask 23 may include a single pattern or a plurality of patterns in one element section. In the example shown in FIG. 2A, the patterns 23a to 23i are arranged in a 3 × 3 two-dimensional array, and this arrangement may be a one-dimensional array. Part (b) of FIG. 1 shows a cross section taken along the line Ib-Ib shown in part (a) of FIG. The material of the mask 23 can be made of, for example, a silicon-based inorganic insulator, and the silicon-based inorganic insulator includes a silicon oxide film and / or a silicon nitride film. In this embodiment, the mask 23 is made of SiN. An outline of the production of the mask 23 will be described. A dielectric film such as a silicon-based inorganic insulating film is grown on the main surface 13a of the semiconductor stack 13 by a chemical vapor deposition (CVD) method. The silicon-based inorganic insulating film is processed by photolithography and etching to form a mask 23 from the silicon-based inorganic insulating film. Specifically, the pattern of the mask 23 is arranged so that pixels are arranged in a horizontal 320 × 256 vertical direction at a pitch of 30 μm in the photodiode array. The size of the pattern for each pixel is, for example, about 20 to 25 μm. A hydrofluoric acid-based etchant is used for etching the silicon-based inorganic insulating film.

After the formation of the mask 23, as shown in FIG. 1C, in step ST3, the epitaxial substrate E is disposed in the etching apparatus 10a, and the epitaxial substrate E is processed by etching using the mask 23. Then, semiconductor mesas 25 a to 25 i are formed from the semiconductor stack 13. This etching can be, for example, wet etching or dry etching. In this embodiment, an inductively coupled plasma-reactive ion etching (ICP-RIE) apparatus can be used as the etching apparatus 10a. For etching the semiconductor stack 13, a hydrogen halide / chlorine gas such as HI and SiCl ₄ is supplied to the etching apparatus 10 a. In the example shown in part (b) of FIG. 2, a mesa array corresponding to the patterns 23 a to 23 i is formed, and this array includes semiconductor mesas 25 a to 25 i. (C) part of FIG. 1 shows the cross section taken along the IIb-IIb line | wire shown by the (b) part of FIG. Each of the semiconductor mesas 25 a to 25 i takes over the layer structure of the semiconductor stack 13. Each semiconductor mesa (25a to 25i) includes a first light receiving layer 27, a second light receiving layer 29, an anode semiconductor layer 31a, and a contact semiconductor layer 31b. The first light receiving layer 27, the second light receiving layer 29, the anode semiconductor layer 31a, and the contact semiconductor layer 31b correspond to the superlattice semiconductor layer 21, the single semiconductor layer 19, the second semiconductor layer 17a, and the third semiconductor layer 17b, respectively. To do. In this embodiment, each of the semiconductor mesas (25a to 25i) is formed by etching the semiconductor stack 13 and the semiconductor substrate 11 to a depth that includes a part of the semiconductor substrate 11.

  In dry etching in forming a semiconductor mesa, a damaged layer is left on the side surfaces of the semiconductor mesas 25a to 25i. This damaged layer is removed by wet etching. Etchant for this purpose is, for example, a mixture of phosphoric acid, hydrogen peroxide solution and water (volume ratio, phosphoric acid / hydrogen peroxide solution / water = 40/8/320) or citric acid, hydrogen peroxide solution and water. (By volume ratio, citric acid / hydrogen peroxide solution / water = 5/10/450). A portion of about 100 nm on the surface of the mesa structure is removed by wet etching. By this etching, the damaged layer is removed from the side surfaces of the semiconductor mesas 25a to 25i. After removing the damaged layer, as shown in FIG. 3A, in step ST4, the mask 23 is removed to form a substrate product S1.

After removing the damaged layer, as shown in FIG. 3B, in step ST5, the substrate product S1 is placed in a plasma processing apparatus 10b such as a plasma CVD apparatus. The substrate temperature of the substrate product S1 is changed while supplying an inert gas, for example, nitrogen gas, to the plasma processing apparatus 10b. The substrate temperature of the substrate product S1 can be in the range of, for example, 100 degrees Celsius or more and 150 degrees Celsius or less. The substrate temperature is controlled as the stage temperature of the plasma processing apparatus 10b, for example. After the temperature control is completed, the first process gas P1 including the oxygen source is supplied to the plasma processing apparatus 10b, and the flow rate of the first process gas P1 is stabilized, and then the plasma 35 of the first process gas P1 is generated. To do. In this embodiment, the process gas can contain at least one of O ₂ and N ₂ O. In a specific example, the discharge is ignited while flowing N ₂ O gas (flow rate: 5.07 × 10 ^{−2 to} 1.69 × 10 ⁻¹ Pa · m ³ / s) in the plasma CVD apparatus. The plasma treatment time can be 30 seconds or more. In this range, the mesa side surface cannot be sufficiently covered with an oxide containing a semiconductor constituent element if it is 30 seconds or less. The plasma treatment time by the plasma 35 can be 180 seconds or less, and in this range, if it is 180 seconds or more, plasma damage accumulates on the side surface of the mesa and dark current deteriorates. In the plasma treatment using a substrate temperature of 100 degrees Celsius or higher, a film is not formed in the subsequent film forming process when the temperature is 100 degrees or lower. In the plasma treatment using the substrate temperature of 150 degrees Celsius or less, the dark current deteriorates due to an increase in the film stress of SiO2 formed in the subsequent film forming process when the temperature is 150 degrees Celsius or more.
An example of plasma processing.
Process gas: N ₂ O gas (flow rate: 1.69 × 10 ⁻¹ Pa · m ³ / s).
Substrate temperature: 100 degrees Celsius.
RF power: 20W-50W.
Discharge time: 30 seconds.
Since the gas species capable of reacting with the oxygen source is not supplied to the plasma CVD apparatus, the amorphous layer on the side surface of the mesa structure of the semiconductor mesas 25a to 25i is formed of the group III constituent element of the semiconductor of the semiconductor mesa by the above plasma treatment. The oxide film is modified and / or the oxide film is formed. This film will be referred to as “formation of oxide film 33” in the following description. Side surfaces and upper surfaces of the mesa structures of the semiconductor mesas 25 a to 25 i are covered with an oxide film 33.

After the plasma generation is completed and the formation of the oxide film is completed, as shown in FIG. 3C, in step ST6, the substrate product S1 is maintained in the plasma processing apparatus 10b while maintaining the first product. The process gas P1 is switched to the second process gas P2. In the present embodiment, the second process gas P2 may include N ₂ O gas and silane-based gas, and the silane-based gas may be, for example, SiH ₄ or Si (OC ₂ H ₅ ) ₄ . The substrate temperature of the substrate product S1 can be, for example, in the range of 100 degrees Celsius or more and 150 degrees Celsius or less, and can be the same as, for example, the temperature when the oxide film 33 is formed. In order to prevent the oxidation source from remaining in the plasma processing apparatus 10b, a sufficient period of flowing the second process gas P2 to the plasma processing apparatus 10b is secured. The type of the second process gas P2 is determined in consideration of the subsequent silicon oxide deposition.

After purging, as shown in part (a) of FIG. 4, in step ST7, while maintaining the substrate product S1 in the plasma processing apparatus 10b, the plasma 38 of the second process gas P2 is ignited and silicon oxidation is performed. A film 37 is formed. In this film formation, for example, SiH ₄ is used as a silane-based gas, and the second process gas P2 includes N ₂ O gas and SiH ₄ . The substrate temperature of the substrate product S1 can be, for example, in the range of 100 degrees Celsius or more and 150 degrees Celsius or less, and can be the same as, for example, the temperature when the oxide film 33 is formed. Further, the thickness of the formed silicon oxide film 37 (for example, SiO ₂ ) can be 200 nm or more and 350 nm or less, and the estimation of the film thickness of the silicon oxide film 37 is a flat place where no mesa is formed. , Using a spectroscopic ellipsometer. Since the same oxidation source as that for the plasma treatment using the first process gas P1 is used for the film formation, the gas switching process can be omitted in the film formation process (for example, the N ₂ purge and the N ₂ O flow rate stabilization waiting process are performed). Unnecessary).
An example of plasma processing.
Process gas: N ₂ O gas and SiH ₄ .
Substrate temperature: 100 degrees Celsius.
RF power: 20W.
Film thickness: 300 nm.
The oxide film 33 on the side surfaces of the semiconductor mesas 25 a to 25 i is covered with a low-stress silicon oxide film 37.

  After the formation of the silicon oxide film 37, as shown in FIG. 4B, in step ST8, while supplying an inert gas, for example, nitrogen gas, to the plasma processing apparatus 10b, the substrate product S1 is supplied. Change the substrate temperature. When the silicon oxide film 37 is formed, the substrate temperature of the substrate product S1 is, for example, in the range of 100 ° C. to 150 ° C., but this temperature is lowered to about room temperature. After reaching the desired substrate temperature, the substrate product S1 is taken out from the plasma processing apparatus 10b. The substrate temperature can be monitored as the stage temperature of the plasma processing apparatus 10b, for example.

  After the substrate product S1 is taken out from the plasma processing apparatus 10b, an opening is formed in the oxide film 33 and the silicon oxide film 37 on the upper surfaces of the semiconductor mesas 25b and 25c in step ST9 as shown in part (c) of FIG. 39 is formed. The opening 39 is used, for example, for the anode electrode to make contact with the upper surfaces of the semiconductor mesas 25b and 25c.

  After forming the opening 39 in the oxide film 33 and the silicon oxide film 37, as shown in FIG. 5A, in step ST10, the semiconductor mesa 25b is formed in the oxide film 33 and the silicon oxide film 37 through the opening 39. , 25c is formed on the upper surface of 25c. In addition, an opening 43 is formed in the oxide film 33 and the silicon oxide film 37, and a cathode electrode 41 b that is in contact with the upper surface of the semiconductor substrate 11 is formed in the oxide film 33 and the silicon oxide film 37 through the opening 43. The substrate product S2 is formed by these steps.

  After forming the anode electrode 41a and the cathode electrode 41b, as shown in FIG. 5B, in step ST11, the back surface of the substrate product S2 (the back surface 11b of the semiconductor substrate 11) is polished to produce a substrate. The thickness of the object S2 is reduced. As a result of polishing, the substrate product S2 has a polished back surface 45b (polished surface) of the semiconductor substrate 45. Through these steps, the substrate product S3 is formed. In the substrate product S3, the upper and side surfaces of the semiconductor mesas 25a, 25b, and 26c are covered with an oxide film 33 and a silicon oxide film 37. Since the side surfaces of all the light receiving layers in the semiconductor mesas 25a, 25b, and 26c are covered with the oxide film 33 and the silicon oxide film 37, the dark current of the photodiode is reduced.

  After the back surface polishing, as shown in FIG. 5C, an antireflection film 47 is formed on the polished surface of the substrate product S2 (the polished back surface 45b of the semiconductor substrate 45) in step ST12. The The antireflection film 47 can be, for example, SiON. Through these steps, the substrate product S4 is formed. If necessary, bump electrodes are formed on the anode electrode 41a and the cathode electrode 41b. The substrate product S4 is separated by cleaving or dicing to form individual semiconductor chips.

  FIG. 6 is a drawing showing the passivation structures of several light receiving elements. Parts (a), (b), and (c) in FIG. 6 represent the light receiving element CONV, the first light receiving element PD1, and the second light receiving element PD2, respectively. The light receiving element CONV, the first light receiving element PD1, and the second light receiving element PD2 have a mesa structure. The passivation structure of the light receiving element CONV is different from the passivation structure of the first light receiving element PD1 and the second light receiving element PD2. The light receiving element CONV, the first light receiving element PD1, and the second light receiving element PD2 include an anode electrode and a cathode electrode, and a bump electrode BP is formed on the anode electrode and the cathode electrode.

Referring to part (a) of FIG. 6, in the light receiving element CONV, SiO ₂ is in direct contact with the side surface of the InGaAs light receiving layer. Therefore, an interface state LV is formed in the vicinity of the junction between the InGaAs light receiving layer and SiO ₂ . These interface states LV become a path of leakage current flowing through the interface.

Referring to FIG. 6B, the first light receiving element PD1 includes a second light receiving layer 29 in the light receiving layer. The side surface of the second light receiving layer 29 is in direct contact with the oxide film 33 formed by, for example, plasma treatment of N ₂ O plasma. This oxide film 33 is covered with an inorganic insulating film typified by a silicon oxide film 37. The oxide film 33 prevents the inorganic insulating film for passivation from coming into direct contact with the semiconductor of the light receiving layer.

Referring to part (c) of FIG. 6, the second light receiving element PD2 includes a first light receiving layer 27 in the light receiving layer. The side surface of the first light receiving layer 27 includes a ridge and a recess corresponding to the layer structure of the superlattice structure in the first light receiving layer 27. Although the side surface of the superlattice structure is not flat compared to the side surface of the second light receiving layer 29, the side surface of the first light receiving layer 27 is directly on the oxide film 33 formed by, for example, plasma treatment of N ₂ O plasma, It is also in contact throughout. This oxide film 33 is covered with an inorganic insulating film typified by a silicon oxide film 37. The oxide film 33 prevents the inorganic insulating film for passivation from coming into direct contact with the semiconductor of the light receiving layer.

FIG. 7 is a drawing showing a sketch of a transmission electron microscope image near the side surface of an InGaAs / GaAsSb superlattice to which N ₂ O plasma treatment is applied. Part (a) of FIG. 7 is a sketch of the area including the side surface of the InGaAs / GaAsSb superlattice to which the N ₂ O plasma treatment for 15 seconds is applied, and part (b) of FIG. 7 shows the N ₂ O part for 30 seconds. It is a sketch of an area including a side surface of an InGaAs / GaAsSb superlattice to which plasma treatment is applied. Specifically, in portions (a) and (b) of FIG. 7, W1 = 4.4 nm, L1 = 12.4 nm, W2 = 2.8 nm, L2 = 9.6 nm, and L3 = 2.5 nm. . In the long N ₂ O plasma treatment, the ridge (protrusion on the mesa side surface) corresponding to the layer structure of the superlattice structure is narrowed, and the recess (groove on the mesa side surface) becomes shallow. As a result of the parts (a) and (b) in FIG. 7, the height of the ridge and the depth of the recess on the side surface of the mesa are, for example, 9.6 nm or less. In order to facilitate the formation of the oxide film, the height of the ridge and the depth of the recess on the side surface of the mesa are preferably 12 nm or less before the plasma treatment, and the interval between adjacent ridges is 4 nm or less. That is good. For example, an oxide film having a thickness of 2 nm or more can be formed by treatment with N ₂ O plasma.

As understood from the experiment according to FIG. 7, the N ₂ O plasma treatment acts to reduce the area of the side surface of the layer structure of the superlattice structure. According to the N ₂ O plasma treatment, the roughness of the side surface of the semiconductor layer constituting the light receiving layer is reduced to reduce the surface of the side surface of the light receiving layer, and the side surface of the semiconductor layer constituting the light receiving layer is slightly oxidized. The side surface of the light receiving layer can be covered with the oxide of the constituent element of the semiconductor of the light receiving layer. This coating with an oxide contributes to a reduction in interface state density at the interface between the semiconductor and the oxide.

FIG. 8 shows characteristics of dark current in several light receiving elements. For example, the notation “1.E-07” on the vertical axis in FIG. 8 represents 1.0 × 10 ⁻⁷ . The following light receiving elements were fabricated: a first light receiving element in which a silicon oxide film was directly deposited on the side surface of a semiconductor mesa having a superlattice layer structure without applying N ₂ O plasma treatment; a layer having a superlattice structure A second light-receiving element in which a silicon oxide film is deposited after N ₂ O plasma treatment for 15 seconds on the side surface of the semiconductor mesa having the structure; and N for 30 seconds on the side surface of the semiconductor mesa having the layer structure of the superlattice structure _A third light receiving element in which a silicon oxide film is deposited after performing ₂ O plasma treatment. The result of having measured the leakage current of these light receiving elements is shown. Each light receiving element had a 20 μm square semiconductor mesa, and the dark current was measured at an absolute temperature of 213 K under an applied voltage of −1.2 volts.
Device name, plasma processing time, dielectric film, leakage current.
First light receiving element: None, silicon nitride, 1200 pA.
Second light receiving element: 15 seconds, silicon oxide, 100 pA.
Third light receiving element: 30 seconds, silicon oxide, 10 pA.
From the viewpoint of leakage current, plasma treatment for 30 seconds or more is preferable.

Figure 9 shows the relationship between the N 2 _O gas deposition temperature of SiO ₂ deposited on the oxide film formed by plasma treatment and the SiO ₂ film stress. For example, film formation in a temperature range of 150 ° C. or less can provide SiO 2 having a compressive stress of 450 MPa (absolute value) or less, which is effective in suppressing an increase in dark current. Film formation in a temperature range of 100 degrees Celsius or more and 150 degrees Celsius or less can provide a compressive stress of 300 MPa or more and 450 MPa or less to SiO ₂ .

  When manufacturing a mesa semiconductor light receiving element, a semiconductor stack including a light receiving layer is epitaxially grown on a compound semiconductor substrate. The semiconductor stack includes a p layer and an n layer. Therefore, the pn junction reaches the side surface of the mesa structure formed by etching from the semiconductor stack. The pn junction on the side surface contributes to the leakage current of the semiconductor light receiving element. In order to reduce the leakage current, the mesa side surface is covered with a protective film. This protective film includes a semiconductor layer wider than the band gap of the light receiving layer, and an insulating film such as silicon nitride (SiN). The semiconductor layer for the protective film is grown by, for example, metal organic vapor phase epitaxy, and this growth is called regrowth. However, in the image sensor, since a plurality of semiconductor mesas for pixels are arranged close to each other, it is not easy to regrow a semiconductor layer on the side surfaces of these semiconductor mesas. Although it is possible to cover the side surface of the semiconductor mesa with an insulating film such as SiN, there is a demand for a semiconductor light receiving element having a further reduced leakage current characteristic.

  As an example, in an infrared image sensor, pixels are arranged at a narrow pitch of 30 μm. Each of these pixels includes a semiconductor mesa. The width of the groove between the semiconductor mesas is about 10 μm, for example, and the depth of the groove is about 5 μm, for example. Thus, it is not easy to find a growth condition for re-growing the semiconductor so as to sufficiently cover the mesa side surface forming the narrow gap.

  Further, when the light receiving layer has a superlattice structure including two types of semiconductor layers having different constituent elements, these semiconductor layers exhibit different side etch amounts for the same etchant. Therefore, a surface structure resulting from the superlattice structure is formed on the etched mesa side surface. After a mesa side surface having such a surface structure is covered with a protective film, a minute gap in the surface structure may be left on the mesa side surface. This gap causes current leakage. The SiN film formed by plasma vapor deposition can cover the mesa side surface by filling minute gaps in the surface structure. However, a carrier trap level is easily formed at the interface between the semiconductor and the insulating film, and a leak current flows through the interface level.

Under such a background, the inventor has an idea that the side surface of the semiconductor mesa is directly covered with the oxide of the constituent element of the semiconductor of the light receiving layer without directly covering the side surface of the semiconductor mesa with the insulating film such as SiN. It came to. One method of directly covering the side surface of the semiconductor mesa with the oxide of the constituent element of the semiconductor of the light receiving layer is, for example, oxidizing the semiconductor of the light receiving layer with an oxidation source. The constituent element of the semiconductor of the light receiving layer includes, for example, a group III element such as gallium and indium, and the oxide of the group III constituent element is, for example, gallium oxide (for example, Ga ₂ O ₃ , band gap 4.8 eV), indium oxide (for example, In ₂ O ₃ , band gap 3.5 eV), gallium indium (eg, GaInO, band gap 3.5 eV to 4.8 eV). These group III oxides have a sufficiently wide band gap as compared with the band gap of the light receiving layer.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  As described above, according to the present embodiment, a method of manufacturing a semiconductor light receiving element having a structure capable of reducing the leakage current related to the semiconductor mesa side surface is provided.

DESCRIPTION OF SYMBOLS 10a ... Etching apparatus, 10b ... Plasma processing apparatus, 11 ... Semiconductor substrate, 13 ... Semiconductor laminated layer, 15 ... 1st semiconductor layer, 17a ... 2nd semiconductor layer, 17b ... 3rd semiconductor layer, 19 ... Single semiconductor layer, 21 DESCRIPTION OF SYMBOLS ... Superlattice semiconductor layer, 23 ... Mask, 25a-25i ... Semiconductor mesa, 33 ... Oxide film, 37 ... Silicon oxide film, 41a ... Anode electrode, 41b ... Cathode electrode, P1 ... 1st process gas, P2 ... 2nd process Gas, S1 ... substrate product, E ... epitaxial substrate.

Claims (4)

A method for producing a semiconductor light receiving element, comprising:
Preparing a semiconductor epitaxial region including a semiconductor layer for a light receiving layer made of a semiconductor comprising a group III element and a group V element;
Forming a mask on the main surface of the semiconductor epitaxial region;
Etching the semiconductor epitaxial region using the mask to form a substrate product including semiconductor mesas formed by the etching;
Placing the substrate product in a plasma processing apparatus;
Supplying a gas containing at least one of oxygen and N ₂ O to the plasma processing apparatus, and performing plasma processing of the substrate product by plasma of the gas;
After the plasma treatment, supplying a raw material containing an oxidation source and a silicon source to the plasma treatment apparatus, and depositing silicon oxide on the surface of the substrate product;
With
In the plasma processing, the stage temperature of the plasma processing apparatus is higher than 100 degrees Celsius and lower than 150 degrees Celsius,
In the step of forming the substrate product, the light receiving layer reaches a side surface of the semiconductor mesa,
The method for producing a semiconductor light receiving element, wherein the group III element includes at least one of gallium and indium. The semiconductor mesa includes a pn junction;
The method for producing a semiconductor light receiving element according to claim 1 , wherein in the step of placing the substrate product in a plasma processing apparatus, the pn junction reaches the side surface of the semiconductor mesa .   The method for producing a semiconductor light receiving element according to claim 1, wherein the semiconductor layer comprises InGaAs.   4. The method of manufacturing a semiconductor light receiving element according to claim 1, wherein the semiconductor layer has a superlattice structure including a III-V semiconductor layer including antimony as the group V element. 5.

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