JP6622106B2 - Compound semiconductor substrate manufacturing method, compound semiconductor substrate, and semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a compound semiconductor substrate, a compound semiconductor substrate, and a semiconductor device.

  InSb thin films have a high electron mobility and are known to be suitable as materials for Hall elements and magnetic sensors. Application to a magnetic sensor requires high sensitivity, low power consumption, and low noise. In other words, high electron mobility, thin film thickness, and good crystallinity are essential. InSb thin films in these electronic devices are formed on a GaAs or InP substrate which is a semi-insulating substrate in order to prevent current leakage. (See Non-Patent Document 1)

Oh et. al. "Journal of Applied Physics", Volume 66, October 1989, p. 3618-3621

  In order to obtain an InSb thin film excellent in workability, the surface state of the InSb thin film is important. If the surface of the InSb thin film is rough, the crystallinity of the film may be deteriorated or disconnected when a film is further formed thereon or when a wiring is formed, resulting in low workability. .

  Accordingly, the present invention has been made in view of such circumstances, and provides a compound semiconductor substrate manufacturing method, a compound semiconductor substrate, and a semiconductor device, which are excellent in workability and include a layer containing In and Sb. With the goal.

As a result of intensive studies to solve the above-mentioned problems, the inventors have found that the surface temperature of the substrate having an electrical resistivity of 1 × 10 ⁵ Ωcm or higher is maintained at 320 ° C. or higher and 360 ° C. or lower on the substrate. An In raw material, an Sb raw material, and a Zn raw material are supplied to each other using a metal organic vapor phase epitaxy method, the zinc concentration is 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less, and the film thickness is A step of growing a first compound semiconductor layer having a thickness of 10 nm or more and 50 nm or less, and a surface temperature of the first compound semiconductor layer being maintained at 460 ° C. or more and 530 ° C. or less on the first compound semiconductor layer; And a method of growing a second compound semiconductor layer by supplying an In raw material and an Sb raw material using a metal organic vapor phase epitaxy method to the above-mentioned problem. Complete the invention Made.

As another aspect of the present invention, a substrate having an electrical resistivity of 1 × 10 ⁵ Ωcm or more, and formed on the substrate, containing In and Sb, and a zinc concentration of 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ^A first compound semiconductor layer that is ¹⁸ cm ⁻³ or less, and a second compound semiconductor layer that is formed on the first compound semiconductor layer and contains In and Sb, the second compound semiconductor layer It was found that the above problems can be solved by a compound semiconductor substrate having an average square roughness of the surface of 0.5 to 0.9 nm, and the present invention has been completed.

  According to one embodiment of the present invention, it is possible to provide a method for manufacturing a compound semiconductor substrate, a compound semiconductor substrate, and a semiconductor device, each including an In and Sb-containing layer with excellent workability.

It is sectional drawing which shows the structural example of the compound semiconductor substrate which concerns on embodiment of this invention. It is sectional drawing which shows the structural example of the semiconductor device which concerns on embodiment of this invention. It is the graph which plotted the relationship between the total film thickness of a 1st InSb layer and a 2nd InSb layer, and the electron mobility of the layer which consists of a 1st InSb layer and a 2nd InSb layer. It is the graph which plotted the relationship between the total film thickness of a 1st InSb layer and a 2nd InSb layer, and the half value width of the layer which consists of a 1st InSb layer and a 2nd InSb layer.

Hereinafter, a mode for carrying out the present invention (hereinafter referred to as the present embodiment) will be described in detail.
<Compound semiconductor substrate>
The compound semiconductor substrate of this embodiment includes a substrate having an electrical resistivity of 1 × 10 ⁵ Ωcm or more, and formed on the substrate, includes In and Sb, and has a zinc concentration of 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ^18. a first compound semiconductor layer that is cm ⁻³ or less, and a second compound semiconductor layer that is formed on the first compound semiconductor layer and contains In and Sb, and on the surface of the second compound semiconductor layer The mean square roughness is 0.5 nm or more and 0.9 nm or less. Thereby, the compound semiconductor substrate excellent in workability is realized.

[substrate]
In the compound semiconductor substrate of this embodiment, as the substrate, an electrical resistivity of 1 × 10 ⁵ Ωcm or more can be used as long as the first compound semiconductor layer and the second compound semiconductor layer can be formed thereon. Not limited. From the viewpoint of forming the first compound semiconductor layer and the second compound semiconductor layer having good crystallinity, the substrate is preferably a substrate having the same crystal symmetry as InSb, and an inexpensive and large substrate is available. Since it is easy to do, it is preferable that it is a board | substrate comprised by any one of GaAs, Si, InAs, or GaSb.

[First compound semiconductor layer]
In the compound semiconductor substrate of the present embodiment, the first compound semiconductor layer is formed on the substrate, contains In and Sb, and has a zinc concentration of 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less. Is a layer. The first compound semiconductor layer is not particularly limited as long as it has a zinc concentration of 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less and contains In and Sb. A mixed crystal may be included.

(Confirmation method of zinc doping)
Presence or absence of zinc doping can be confirmed by measuring the amount of impurity elements using secondary ion mass measurement (SIMS). Further, the concentration of zinc contained in the first compound semiconductor layer to be described later can also be obtained from measurement of the amount of impurity elements using SIMS.

(Confirmation method of containing In and Sb)
The presence or absence of In and Sb can be confirmed by X-ray fluorescence analysis (XRF), Rutherford backscattering spectroscopy (RBS), secondary ion mass measurement SIMS, and X-ray photoelectron spectroscopy (XPS).
In the compound semiconductor substrate of this embodiment, the film thickness of the first compound semiconductor layer may be 10 nm or more and 50 nm or less. As a result, the crystallinity of the second compound semiconductor layer is improved. This is because the film thickness of the first compound semiconductor layer is 10 nm or more and 50 nm or less, and the crystallinity of the second compound semiconductor layer is improved by the mechanism that the dispersion of growth nuclei has a two-dimensional spread. Because.

(Measuring method of film thickness)
The film thickness of the first compound semiconductor layer is measured by cleaved cross-sectional measurement using fluorescent X-ray analysis (XRF), secondary ion mass measurement (SIMS), scanning electron microscope (SEM), or transmission electron microscope (TEM). It is possible.

[Second Compound Semiconductor Layer]
In the compound semiconductor substrate of this embodiment, the second compound semiconductor layer is a layer formed on the first compound semiconductor layer and containing In and Sb. The second compound semiconductor layer is not particularly limited as long as it is a layer containing In and Sb, and may be a mixed crystal containing other atoms. In the second compound semiconductor layer in the compound semiconductor substrate of this embodiment, the mean square roughness of the surface of the second compound semiconductor layer is 0.5 nm or more and 0.9 nm or less.
(Definition of mean square roughness)
The surface square roughness referred to here is a value calculated from surface observation in atomic force microscope (AFM) measurement.

[Layer Consisting of First Compound Semiconductor Layer and Second Compound Semiconductor Layer]
In the compound semiconductor substrate of this embodiment, the layer composed of the first compound semiconductor layer and the second compound semiconductor layer has a thickness of 10 nm to 3000 nm, and is calculated from ω scan rocking curve measurement by X-ray diffraction. The full width at half maximum FWHM may satisfy the range calculated by the following formula (1).
FWHM [arcsec] ≦ 11600 × t ^−0.506 [arcsec] (1)
(T = film thickness (nm) of the first compound semiconductor layer and the second compound semiconductor layer)
As a result, a compound semiconductor substrate having not only excellent workability but also good crystallinity is realized.

(Measuring method of film thickness)
The film thickness of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer is determined by X-ray fluorescence analysis (XRF), secondary ion mass measurement (SIMS), scanning electron microscope (SEM), or transmission electron microscope. It can be measured by cleavage cross-sectional measurement by (TEM).
In the compound semiconductor substrate of the present embodiment, as a method of distinguishing between the first compound semiconductor layer and the second compound semiconductor layer, a method of distinguishing according to the presence or absence of zinc doping may be mentioned. A layer in which the presence of zinc is confirmed by the measurement of the amount of impurity elements using SIMS described above corresponds to the first compound semiconductor layer, and the presence of zinc is not confirmed (only an amount below the measurement limit is detected) Corresponds to the second compound semiconductor layer.

(Definition of half-width FWHM)
The full width at half maximum FWHM here is the peak top when the ω-scan rocking curve by X-ray diffraction is measured with respect to the main surface of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer. It is the angle width at which the diffraction intensity is halved from the peak value of the diffraction intensity.

The layer composed of the first compound semiconductor layer and the second compound semiconductor layer in the compound semiconductor substrate of the present embodiment has a thickness of 10 nm to 1500 nm, and the electron mobility EM is calculated by the following formula (2). The range may be satisfied.
4.8 × 10 ⁻⁶ × t ³ −0.035 × t ² + 84 × t−2000 [cm ² V ⁻¹ s] ≦ EM [cm ² V ⁻¹ s] (2)
(T = film thickness (nm) of the first compound semiconductor layer and the second compound semiconductor layer)
As a result, a compound semiconductor substrate having not only excellent workability but also higher mobility is realized. Thereby, when the compound semiconductor substrate is applied to a device such as a magnetic sensor, a highly sensitive device is realized.

(Measurement method of electron mobility EM)
The electron mobility EM can be measured by performing hole measurement by the Van der Pauw method. Here, since the substrate can be regarded as an insulator, the electron mobility EM of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer is measured by performing hole measurement by the Van der Pauw method. It is possible.
The carrier concentration of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer in the compound semiconductor substrate of the present embodiment may be 1.3 × 10 ¹⁶ cm ⁻³ or more and 1.7 × 10 ¹⁶ cm ⁻³ or less. As a result, a high-resistance compound semiconductor substrate is realized, and a device that consumes less power when realized as a device is realized.

(Definition and measurement method of carrier concentration)
The carrier concentration here means the concentration of electrons contained in the layer composed of the first compound semiconductor layer and the second compound semiconductor layer. The carrier concentration can be measured by performing hole measurement by the Van der Pauw method. Here, since the substrate can be regarded as an insulator, the carrier concentration of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer can be measured by performing hole measurement by the Van der Pauw method. Is possible.

<Semiconductor device>
In addition, a semiconductor device may be manufactured using the compound semiconductor substrate of this embodiment. Specifically, the second compound semiconductor layer of the compound semiconductor substrate may be an active layer. Alternatively, a layer formed of the first compound semiconductor layer and the second compound semiconductor layer of the compound semiconductor substrate may be used as the active layer. Specific examples of the semiconductor device using the second compound semiconductor layer or the layer composed of the first compound semiconductor layer and the second compound semiconductor layer as an active layer include a magnetic sensor, a Hall element, an infrared sensor element, and the like. It is done. Any of them can be produced using a known method. Since this semiconductor device includes a compound semiconductor substrate that is excellent in workability and includes a layer containing In and Sb, it is possible to obtain a high-performance semiconductor device.

<Method for producing compound semiconductor substrate>
Next, the manufacturing method of the compound semiconductor layer of this embodiment is demonstrated.
In the method of manufacturing a compound semiconductor substrate according to the present embodiment, metal organic vapor phase growth is performed on the substrate while maintaining the temperature of the surface of the substrate having an electrical resistivity of 1 × 10 ⁵ Ωcm or more at 320 ° C. or more and 360 ° C. or less. The In raw material, the Sb raw material, and the Zn raw material are supplied using the method, the zinc concentration is 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less, and the film thickness is 10 nm or more and 50 nm or less. Using the metal organic vapor phase growth method on the first compound semiconductor layer while maintaining the temperature of the surface of the first compound semiconductor layer at 460 ° C. or higher and 530 ° C. or lower. And supplying an In raw material and an Sb raw material to grow a second compound semiconductor layer.

By providing each of these steps (first compound semiconductor layer growth step, second compound semiconductor layer growth step), a compound comprising a layer containing In and Sb that is excellent in workability in a predetermined film thickness range. A semiconductor substrate can be obtained.
The first compound semiconductor layer growth step and the second compound semiconductor layer growth step are performed under the same temperature condition (that is, the first compound semiconductor layer and the second compound semiconductor layer are grown under the same temperature condition). ) Causes a problem that the second compound semiconductor layer grows three-dimensionally and the flatness of the surface of the second compound semiconductor layer is greatly impaired.

  On the other hand, as in the present embodiment, the first compound semiconductor layer is grown in a state where the substrate temperature is maintained at 320 ° C. or higher and 360 ° C. or lower, and then the surface temperature of the first compound semiconductor layer is increased. By growing the second compound semiconductor layer while maintaining the temperature at 460 ° C. or higher and 530 ° C. or lower, a compound semiconductor substrate including a layer containing In and Sb having excellent surface flatness and excellent workability is obtained. It becomes possible.

Although the details of this mechanism are not clear, it is presumed that three-dimensional growth from the substrate interface can be suppressed by bringing a layer with a low degree of migration at the beginning of the film forming process.
Further, when the growth of the first compound semiconductor layer is performed by supplying only the In material and the Sb material without supplying the Zn material, the drop starting from the void generated from the substrate is the second compound semiconductor. The problem of precipitation on the layer surface occurs.

On the other hand, as in this embodiment, by supplying the Zn raw material in the step of growing the first compound semiconductor layer and growing the first compound semiconductor layer, the surface flatness is good and the workability is improved. An excellent compound semiconductor substrate including a layer containing In and Sb can be obtained.
The details of this mechanism are presumed to be due to the suppression of dislocations generated from voids in the substrate by incorporating Zn into the first compound semiconductor layer.
The In raw material, the Sb raw material, and the Zn raw material used in the first compound semiconductor layer growth step and the second compound semiconductor layer growth step are not particularly limited as long as they are raw materials that can be used in the metal organic chemical vapor deposition method.

(Measuring method of substrate temperature and surface temperature of first compound semiconductor layer)
The substrate temperature can be measured by performing a pyrometer.
In the compound semiconductor substrate manufacturing method of this embodiment, the In raw material is trimethylindium (TMIn) or triethylindium (TEIn), and the Sb raw material is trimethylantimony (TMSb), triethylantimony (TESb), or trisdimethylaminoantimony ( Any of TDMASb), and the Zn raw material may be dimethylzinc (DMZn) or diethylzinc (DEZn). From the viewpoint of the raw material decomposition temperature, it may be preferable to use the above raw materials.

  Further, in the compound semiconductor substrate manufacturing method of the present embodiment, the substrate may be any one of GaAs, Si, InAs, or GaSb. It is preferable to have the same crystal symmetry as InSb, and since a cheap and large-sized substrate is easily available, the above-described substrate material is preferable.

<Specific example of cross-sectional structure>
Next, a specific example of a cross-sectional structure of the compound semiconductor substrate according to the present embodiment will be described with reference to the drawings. However, in all the drawings described below, parts corresponding to each other are denoted by the same reference numerals, and description of the overlapping parts will be omitted as appropriate. Further, the drawings are schematic, and the length and thickness dimensions of each layer in each drawing are different from the actual ones, and their ratios may be different from the actual ones.

FIG. 1 is a cross-sectional view showing a configuration example of a compound semiconductor substrate 100 according to the present embodiment. As shown in FIG. 1, the compound semiconductor substrate 100 according to this embodiment includes a substrate 1 having an electrical resistivity of 1 × 10 ⁵ Ωcm or more, a first compound semiconductor layer 11 formed on the substrate 1, And the second compound semiconductor layer 12 formed on the compound semiconductor layer 11. The first compound semiconductor layer 11 includes In and Sb, and the concentration of zinc is 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less. The second compound semiconductor layer 12 includes In and Sb, and the average square roughness of the surface is not less than 0.5 nm and not more than 0.9 nm. Thereby, the compound semiconductor substrate excellent in workability is realized.

  Although not shown in FIG. 1, in the compound semiconductor substrate 100 according to the present embodiment, a buffer layer is provided between the substrate 10 and the layer 10 including the first compound semiconductor layer 11 and the second compound semiconductor layer 12. It may be provided. The buffer layer is preferably a layer containing In and Sb from the viewpoint of relaxing lattice mismatch. Moreover, there is no restriction | limiting in particular in the film thickness of a buffer layer, but it is preferable that they are 5 nm or more and 30 nm or less from a viewpoint of keeping the whole film thickness thin.

FIG. 2 is a cross-sectional view illustrating a configuration example of the semiconductor device 200 according to the present embodiment. As shown in FIG. 2, the semiconductor device 200 includes a compound semiconductor substrate 100 and an element 150 formed on the compound semiconductor substrate 100. The element 150 is a Hall element, for example, and has a plurality of electrodes 151 on the upper surface side thereof. The layer 10 including the first compound semiconductor layer 11 and the second compound semiconductor layer 12 included in the compound semiconductor substrate 100 is an active layer (for example, a magnetosensitive layer) that functions as at least a part of the element 150.
FIG. 2 shows the case where the buffer layer 5 is provided between the substrate 10 and the layer 10 including the first compound semiconductor layer 11 and the second compound semiconductor layer 12. In the form, the buffer layer 5 may be omitted.

<Example>
A 4-inch semi-insulating GaAs substrate was prepared. The semi-insulating GaAs substrate had an electric resistivity of 8 × 10 ⁷ Ωcm.
A first InSb layer (first compound semiconductor layer) doped with Zn at three temperatures of 320 ° C., 340 ° C., and 360 ° C. was formed on the semi-insulating GaAs substrate. Trimethylindium (TMIn) or triethylindium (TEIn) was used as the In raw material, and trisdimethylaminoantimony (TDMASb) or trimethylantimony (TMSb) was used as the Sb raw material. Diethyl zinc (DEZn) or dimethyl zinc (DMZn) was used as a raw material for Zn doping. An MOCVD apparatus was used to form the first InSb layer (first compound semiconductor layer) doped with Zn. The first InSb layer was measured for the doping amount of Zn from SIMS measurement, and the film thickness was measured from XRF measurement.

  A second InSb layer (second compound semiconductor layer) was formed on the first InSb layer at three temperatures of 460 ° C., 500 ° C., and 530 ° C. Trimethylindium (TMIn) or triethylindium (TEIn) was used as the In raw material, and trisdimethylaminoantimony (TDMASb) or trimethylantimony (TMSb) was used as the Sb raw material. An MOCVD apparatus was used to form the second InSb layer. From the XRF measurement, the film thickness of the entire InSb layer was measured.

  The sample thus formed was subjected to hole measurement by the Van der Pauw method, and the electron mobility and n-type carrier concentration of the entire InSb layer were measured. Further, X-ray diffraction measurement was performed on the (004) plane, and the half width (FWHM) was measured from the obtained ω rocking curve measurement. Further, atomic force microscope measurement was performed in a range of 10 × 10 μm, and the mean square roughness of the second InSb layer surface was measured.

<Comparative example>
A 4-inch semi-insulating GaAs substrate was prepared. The semi-insulating GaAs substrate had an electric resistivity of 8 × 10 ⁷ Ωcm.
A first InSb layer (first compound semiconductor layer) doped with Zn at three temperatures of 300 ° C., 340 ° C., and 380 ° C. was formed on the semi-insulating GaAs substrate. Trimethylindium (TMIn) was used as the In raw material, and trisdimethylaminoantimony (TDMASb) was used as the Sb raw material. Diethyl zinc (DEZn) was used as a raw material for Zn doping. An MOCVD apparatus was used to form the first InSb layer (first compound semiconductor layer) doped with Zn. The first InSb layer was measured for the doping amount of Zn from SIMS measurement, and the film thickness was measured from XRF measurement.

  A second InSb layer (second compound semiconductor layer) was formed on the first InSb layer at three temperatures of 440 ° C., 500 ° C., and 550 ° C. Trimethylindium (TMIn) was used as the In raw material, and trisdimethylaminoantimony (TDMASb) was used as the Sb raw material. An MOCVD apparatus was used to form the second InSb layer. From the XRF measurement, the film thickness of the entire InSb layer was measured.

  The sample thus formed was subjected to hole measurement by the Van der Pauw method, and the electron mobility and n-type carrier concentration of the entire InSb layer were measured. Further, X-ray diffraction measurement was performed on the (004) plane, and the half width (FWHM) was measured from the obtained ω rocking curve measurement. Further, atomic force microscope measurement was performed in a range of 10 × 10 μm, and the mean square roughness of the second InSb layer surface was measured.

<Result>
Table 1 summarizes the results of the examples. Table 2 summarizes the results of the comparative examples. In Tables 1 and 2, “Seed temperature” means the deposition temperature of the first compound semiconductor layer, and “HT temperature” means the deposition temperature of the second compound semiconductor layer. “Seed film thickness” means the film thickness of the first compound semiconductor layer, and “total film thickness” means the total film thickness of the first compound semiconductor layer and the second compound semiconductor layer. In Table 2, “white turbidity” means that the sample is cloudy and it was difficult to perform various measurements of mobility, carrier concentration, and crystallinity.

From Table 1 and Table 2, it can be seen that Examples 1-20 have a smaller mean square roughness of the surface of the second InSb layer than Comparative Examples 1-8.
FIG. 3 shows the total film thickness (unit: nm) of the first InSb layer and the second InSb layer, the first InSb layer, and the second InSb for Examples 1 to 20 and Comparative Examples 1 to 8. The relationship between the electron mobility (EM) (unit: cm ² / Vs) of a layer composed of layers is plotted. In FIG. 3, the x-axis indicates the film thickness, and the y-axis indicates the electron mobility. FIG. 3 also plots the relationship between film thickness and electron mobility for an InSb layer formed by MBE as a reference example.

As shown in FIG. 3, when a boundary line is drawn between Examples 1 to 20 and Comparative Examples 1 to 8 and Reference Example, this boundary line is y = 4.8 × 10 ⁻⁶ × x ³ − It is approximated by 0.035 × x ² + 84 × x−2000. As can be seen from FIG. 3, y in Examples 1 to 20 is y = 4.8 × 10 ⁻⁶ × x ³ −0.035 × x ² + 84 × x−2000 or more. The InSb layer obtained in the present invention has an electron mobility satisfying the condition of y ≦ 4.8 × 10 ⁻⁶ × x ³ −0.035 × x ² + 84 × x−2000 in the range of 10 ≦ x ≦ 1500. It can be seen that it is high.

  FIG. 4 shows the total film thickness (unit: nm) of the first InSb layer and the second InSb layer, the first InSb layer, and the second InSb layer in Examples 1 to 20 and Comparative Examples 1 to 8. It is a plot of the relationship with the half width (FWHM) (unit: arcsec) of a layer composed of an InSb layer. In FIG. 4, the x-axis indicates the film thickness, and the y-axis indicates the half width. Also in FIG. 4, as a reference example, the relationship between the film thickness and the full width at half maximum is plotted for the InSb layer formed by the MBE method.

As shown in FIG. 4, when a boundary line is drawn between Examples 1 to 20 and Comparative Examples 1 to 8 and the reference example, this boundary line is approximated by y = 11600 × x− ^0.506 . The As can be seen from FIG. 4, y in Examples 1 to 20 is y = 11600 × x− ^0.506 or less. It can be seen that the InSb layer obtained in the present invention has excellent crystallinity that satisfies the condition of y ≦ 11600 × x− ^{0.506 in} the range of 10 ≦ x ≦ 3000.

<Others>
The technical idea of the present invention is not limited to the embodiments and examples described above. Based on the knowledge of those skilled in the art, design changes and the like may be added to the embodiments and examples of the present invention, and the embodiments and examples of the present invention may be arbitrarily combined. The added aspect is also included in the technical idea of the present invention.

DESCRIPTION OF SYMBOLS 1 Board | substrate 5 Buffer layer 10 Layer which consists of 1st compound semiconductor layer and 2nd compound semiconductor layer 11 1st compound semiconductor layer 12 2nd compound semiconductor layer 100 Compound semiconductor substrate 150 Element 151 Electrode 200 Semiconductor device

Claims (10)

In a state where the temperature of the surface of the substrate having an electrical resistivity of 1 × 10 ⁵ Ωcm or higher is maintained at 320 ° C. or higher and 360 ° C. or lower, an In raw material, an Sb raw material, and a Zn are formed on the substrate by metal organic vapor phase epitaxy. And supplying a raw material to grow a first compound semiconductor layer having a zinc concentration of 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less and a film thickness of 10 nm or more and 50 nm or less. ,
In raw material and Sb raw material are supplied onto the first compound semiconductor layer by metalorganic vapor phase epitaxy while the surface temperature of the first compound semiconductor layer is maintained at 460 ° C. or higher and 530 ° C. or lower. And a step of growing a second compound semiconductor layer. The In raw material is trimethylindium (TMIn) or triethylindium (TEIn),
The Sb raw material is any one of trimethylantimony (TMSb), triethylantimony (TESb), or trisdimethylaminoantimony (TDMASb),
The method for producing a compound semiconductor substrate according to claim 1, wherein the Zn raw material is dimethylzinc (DMZn) or diethylzinc (DEZn).   The method for manufacturing a compound semiconductor substrate according to claim 1, wherein the substrate is a substrate made of any one of GaAs, Si, InAs, and GaSb. A substrate having an electrical resistivity of 1 × 10 ⁵ Ωcm or more;
A first compound semiconductor layer formed on the substrate, containing In and Sb, and having a zinc concentration of 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁸ cm ⁻³ or less;
A second compound semiconductor layer formed on the first compound semiconductor layer and containing In and Sb,
A compound semiconductor substrate in which a mean square roughness of a surface of the second compound semiconductor layer is 0.5 nm or more and 0.9 nm or less. The film thickness of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer is 10 nm or more and 3000 nm or less,
The half-value width FWHM calculated from the ω-scan rocking curve measurement by X-ray diffraction of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer satisfies the range calculated by the following formula (1). Item 5. A compound semiconductor substrate according to Item 4.
FWHM [arcsec] ≦ 11600 × t ^−0.506 [arcsec] (1)
(T = film thickness (nm) of the first compound semiconductor layer and the second compound semiconductor layer)   The compound semiconductor substrate according to claim 4 or 5, wherein the film thickness of the first compound semiconductor layer is 10 nm or more and 50 nm or less.   The compound semiconductor substrate according to claim 4, wherein the substrate is a substrate made of any one of GaAs, Si, InAs, or GaSb. The film thickness of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer is 10 nm or more and 1500 nm or less,
The electron mobility EM of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer satisfies the range calculated by the following formula (2). The compound semiconductor substrate as described.
4.8 × 10 ⁻⁶ × t ³ −0.035 × t ² + 84 × t−2000 [cm ² V ⁻¹ s] ≦ EM [cm ² V ⁻¹ s] (2)
(T = film thickness (nm) of the first compound semiconductor layer and the second compound semiconductor layer) 5. The carrier concentration of the layer composed of the first compound semiconductor layer and the second compound semiconductor layer is 1.3 × 10 ¹⁶ cm ⁻³ or more and 1.7 × 10 ¹⁶ cm ⁻³ or less. The compound semiconductor substrate according to claim 8.   A semiconductor device provided with the compound semiconductor substrate as described in any one of Claims 4-9.

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