JP6633656B2 - 配線基板、光半導体素子パッケージおよび光半導体装置 - Google Patents
配線基板、光半導体素子パッケージおよび光半導体装置 Download PDFInfo
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Description
上記の配線基板1における図1、図2の構成を実施例1とし、図3、図4の構成を実施例2とし、配線基板1の接地導体層5において、第1非形成領域5aを設けずに信号導体配線3の第1端部3a直下において、接地導体層5が存在する構成を比較例1とし、シミュレーションによって反射損失および挿入損失を評価した。
2 第1誘電体層
2a 第1面
2b 第2面
3 信号導体配線
3a 第1端部
3b 第2端部
4 接地導体配線
4a 第1端部
4b 第2端部
5 接地導体層
5a,5b 非形成領域
6 第2誘電体層
6a1 第1側面
6b1 第2側面
6a,6b 切り欠き部
10 リード端子
11 光半導体素子
12 ボンディングワイヤ
13 マウント部材
20 基体
2a1 第1辺
2a2 第2辺
2b1 第1辺
2b2 第2辺
30 枠部材
100 光半導体素子パッケージ
200 光半導体装置
Claims (5)
- 矩形板状の第1誘電体層と、
前記第1誘電体層の第1面に位置し、接地電位に接続される接地導体配線であって、第1端部が、前記第1面の第1辺まで延びている接地導体配線と、
前記第1誘電体層の第1面に位置し、信号伝送を行う一対の信号導体配線であって、前記接地導体配線の幅方向両側に、前記信号導体配線と所定の間隔を空けて前記信号導体配線に沿って位置し、第1端部が、前記第1面の前記第1辺まで延びている一対の信号導体配線と、
前記第1誘電体層の第2面に位置し、接地電位に接続される接地導体層であって、平面視で前記信号導体配線の前記第1端部が位置する領域が、前記第1面の第1辺に対向する前記第2面の第1辺から内方に切り欠かれている接地導体層と、
前記接地導体層の、前記第1誘電体層と反対側に位置している矩形板状の第2誘電体層と、を含んでおり、
前記第2誘電体層は、平面視で、前記一対の信号導体配線の前記第1端部が位置する領域および前記一対の信号導体配線の前記第1端部で挟まれる前記接地導体配線の前記第1端部が位置する領域が、前記第2面の第1辺から内方に向かって1つの切欠き部として切り欠かれていることを特徴とする配線基板。 - 前記信号導体配線の第2端部は、前記第1面の前記第1辺に対向する第2辺まで延びており、
前記接地導体配線の第2端部は、前記第1面の前記第2辺まで延びており、
前記接地導体層は、平面視で前記信号導体配線の前記第2端部が位置する領域が、前記第2面の前記第2辺に対向する前記第2面の第2辺側から内方に切り欠かれていることを特徴とする請求項1記載の配線基板。 - 前記第2誘電体層は、前記第1誘電体層の前記第1面の前記第2辺および前記第2面の前記第2辺を含む面と平行な第2側面を有し、平面視で、前記信号導体配線の前記第2端部および前記接地導体配線の前記第2端部が位置する領域が、前記第2側面側から切り欠かれていることを特徴とする請求項2記載の配線基板。
- 光半導体素子が載置される載置領域を含む上面を有する板状の基体と、
前記載置領域を囲むように前記上面に配置される枠部材と、
請求項1〜3のいずれか1つに記載の配線基板であって、前記信号導体配線の前記第1端部が前記枠部材の外部に配置されるように、前記枠部材を貫通している配線基板と、を
備えることを特徴とする光半導体素子パッケージ。 - 請求項4に記載の光半導体素子パッケージと、
前記載置領域に載置された光半導体素子と、
前記信号導体配線と、前記光半導体素子とを電気的に接続する接続部材と、を備えることを特徴とする光半導体装置。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016012943 | 2016-01-27 | ||
| JP2016012943 | 2016-01-27 | ||
| PCT/JP2017/002745 WO2017131092A1 (ja) | 2016-01-27 | 2017-01-26 | 配線基板、光半導体素子パッケージおよび光半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2017131092A1 JPWO2017131092A1 (ja) | 2018-08-09 |
| JP6633656B2 true JP6633656B2 (ja) | 2020-01-22 |
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| JP2017563816A Active JP6633656B2 (ja) | 2016-01-27 | 2017-01-26 | 配線基板、光半導体素子パッケージおよび光半導体装置 |
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| Country | Link |
|---|---|
| US (1) | US10512155B2 (ja) |
| EP (1) | EP3410471B1 (ja) |
| JP (1) | JP6633656B2 (ja) |
| CN (1) | CN108352363B (ja) |
| WO (1) | WO2017131092A1 (ja) |
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| EP3410471B1 (en) * | 2016-01-27 | 2025-04-02 | KYOCERA Corporation | Wiring substrate, optical semiconductor element package, and optical semiconductor device |
| JP6784793B2 (ja) * | 2019-04-12 | 2020-11-11 | 株式会社フジクラ | レーザモジュール及びその製造方法 |
| JP7398877B2 (ja) * | 2019-04-18 | 2023-12-15 | 新光電気工業株式会社 | 半導体装置用ステム及び半導体装置 |
| JP2021027136A (ja) * | 2019-08-02 | 2021-02-22 | CIG Photonics Japan株式会社 | 光モジュール |
| JP7635545B2 (ja) * | 2020-12-18 | 2025-02-26 | セイコーエプソン株式会社 | 発光装置およびプロジェクター |
| US11764077B2 (en) * | 2021-07-23 | 2023-09-19 | Innolux Corporation | Composite layer circuit element and manufacturing method thereof |
| CN114291783B (zh) * | 2021-12-31 | 2024-07-26 | 深圳市信为科技发展有限公司 | 具有微细多引线的压力传感器及其制备方法 |
| CN119547201A (zh) * | 2022-07-11 | 2025-02-28 | 京瓷株式会社 | 布线结构体和电子模块 |
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| EP3410471B1 (en) * | 2016-01-27 | 2025-04-02 | KYOCERA Corporation | Wiring substrate, optical semiconductor element package, and optical semiconductor device |
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2017
- 2017-01-26 EP EP17744322.3A patent/EP3410471B1/en active Active
- 2017-01-26 US US15/768,059 patent/US10512155B2/en active Active
- 2017-01-26 WO PCT/JP2017/002745 patent/WO2017131092A1/ja not_active Ceased
- 2017-01-26 CN CN201780003686.1A patent/CN108352363B/zh active Active
- 2017-01-26 JP JP2017563816A patent/JP6633656B2/ja active Active
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| EP3410471B1 (en) | 2025-04-02 |
| EP3410471A1 (en) | 2018-12-05 |
| US20180352648A1 (en) | 2018-12-06 |
| EP3410471A4 (en) | 2019-09-25 |
| CN108352363B (zh) | 2022-01-21 |
| WO2017131092A1 (ja) | 2017-08-03 |
| CN108352363A (zh) | 2018-07-31 |
| JPWO2017131092A1 (ja) | 2018-08-09 |
| US10512155B2 (en) | 2019-12-17 |
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