JP6680169B2 - Semiconductor device and amplifier - Google Patents

Description

  The present invention relates to a semiconductor device and an amplifier.

  Nitride semiconductors, which have characteristics such as high saturation electron velocity and wide band gap, are being studied for application to high breakdown voltage and high output semiconductor devices. For example, the band gap of GaN, which is a nitride semiconductor, is 3.4 eV, which is larger than the band gaps of Si (1.1 eV) and GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, a nitride semiconductor such as GaN is very promising as a material for a semiconductor device for a power supply that can obtain a high voltage operation and a high output.

  As a semiconductor device using a nitride semiconductor, there have been many reports on a field effect transistor, particularly a high electron mobility transistor (HEMT). For example, in a GaN-based HEMT (GaN-HEMT), attention has been paid to an HEMT composed of AlGaN / GaN using GaN as an electron transit layer and AlGaN as an electron supply layer. In a HEMT made of AlGaN / GaN, strain due to the lattice constant difference between GaN and AlGaN occurs in AlGaN. Due to the piezoelectric polarization generated thereby and the spontaneous polarization difference of AlGaN, a high concentration of 2DEG (two-dimensional electron gas) can be obtained. Therefore, it is expected as a highly efficient switch element and a high withstand voltage power device for electric vehicles.

JP, 2002-359256, A JP, 2010-232503, A

  By the way, when the above GaN-HEMT is used for electric power, a high voltage is applied and a large current flows, so that the temperature of the GaN-HEMT becomes high and the temperature in the region where the GaN-HEMT is formed is high. High and low areas may occur. As described above, when a high temperature region is generated in the region where the GaN-HEMT is formed, it becomes difficult for current to flow in the high temperature region, and further, the current may be destroyed, so that a semiconductor device is obtained. Reliability is reduced.

  Therefore, there is a demand for a highly reliable semiconductor device for electric power.

  According to one aspect of the present embodiment, a first semiconductor layer formed of a semiconductor on a substrate, and a second semiconductor layer formed of a semiconductor on the first semiconductor layer, In a semiconductor device having a gate electrode, a source electrode and a drain electrode formed on the second semiconductor layer, an ohmic contact layer in contact with a semiconductor is formed on the source electrode and the drain electrode, The resistance in the film thickness direction of the ohmic contact layer is lower in the peripheral region than in the central region of the semiconductor device in plan view.

  According to the disclosed semiconductor device, reliability can be improved for power use.

Top view of semiconductor device Sectional view of essential parts of semiconductor device Illustration of heat distribution of semiconductor device Temperature distribution map from the central area to the peripheral area of the semiconductor device Correlation diagram of drain voltage and drain current of semiconductor device The top view of the semiconductor device in 1st Embodiment Sectional drawing of the principal part of the semiconductor device in 1st Embodiment. Explanatory drawing of the semiconductor device in 1st Embodiment Explanatory drawing of the relation between the film thickness of Ta layer and resistance in an ohmic contact layer Temperature distribution diagram from the central region to the peripheral region of the semiconductor device of the first embodiment Correlation diagram of drain voltage and drain current of the semiconductor device of the first embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Sectional drawing cut along dashed-dotted line 12A-12B in FIG. Process drawing of the manufacturing method of the semiconductor device in the first embodiment (2) Sectional drawing cut along the dashed-dotted line 14A-14B in FIG. Process drawing of the manufacturing method of the semiconductor device in the first embodiment (3) Sectional drawing cut along the dashed-dotted line 16A-16B in FIG. Process drawing of the manufacturing method of the semiconductor device in the first embodiment (4) Sectional drawing cut along the dashed-dotted line 18A-18B in FIG. Process drawing of the manufacturing method of the semiconductor device in the first embodiment (5) Sectional drawing cut | disconnected by the dashed-dotted line 20A-20B in FIG. Process drawing of the method for manufacturing a semiconductor device according to the first embodiment (6) Sectional drawing cut along the dashed-dotted line 22A-22B in FIG. Sectional view of essential parts of Modification 1 of the semiconductor device according to the first embodiment. Sectional view of essential parts of Modification 2 of the semiconductor device according to the first embodiment. Sectional view of essential parts of Modification Example 3 of the semiconductor device according to the first embodiment. The top view of the semiconductor device in 2nd Embodiment Process explanatory drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (1) Process explanatory drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (2) Process explanatory drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (3) Explanatory drawing of the discrete packaged semiconductor device in 4th Embodiment. Circuit diagram of the power supply device according to the fourth embodiment Structural diagram of the high-frequency amplifier according to the fourth embodiment

  An embodiment for carrying out the invention will be described below. The same members and the like are designated by the same reference numerals and the description thereof will be omitted.

[First Embodiment]
First, in a GaN-HEMT, which is a semiconductor device using a nitride semiconductor, a temperature distribution is generated when the device is operated, and the reliability as a semiconductor device is reduced will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the semiconductor device as viewed from above, and FIG. 2 is a cross-sectional view taken along the alternate long and short dash line 1A-1B in FIG. In addition, in the present application, “plan view” refers to a field of view of a semiconductor device in a direction normal to a surface on which a gate electrode, a source electrode, and a drain electrode described later are formed.

  As shown in FIG. 2, this semiconductor device is formed by laminating a buffer layer 911 made of a nitride semiconductor, an electron transit layer 921, and an electron supply layer 922 on a substrate 910. The substrate 910 is formed of a semiconductor substrate such as SiC, and the buffer layer 911 is formed of AlN, AlGaN, GaN or the like. The electron transit layer 921 is made of GaN or the like, and the electron supply layer 922 is made of AlGaN or the like. As a result, 2DEG 921a is generated in the electron transit layer 921 in the vicinity of the interface between the electron transit layer 921 and the electron supply layer 922.

  A gate electrode 931, a source electrode 932, and a drain electrode 933 are formed over the electron supply layer 922. In this semiconductor device, as shown in FIG. 1, the gate electrode 931, the source electrode 932, and the drain electrode 933 have a comb-tooth-shaped electrode structure, and the drain electrode 933 is provided between the comb teeth of the source electrode 932. The comb teeth are inside. Further, the comb teeth of the gate electrode 931 are formed between the comb teeth of the source electrode 932 and the comb teeth of the drain electrode 933.

  By the way, when the semiconductor device having such a structure is operated, as shown in FIG. 3, a temperature distribution occurs such that the temperature of the central region of the semiconductor device becomes higher than that of the peripheral region. In addition, in FIG. 3, the isotherm is shown by a two-dot chain line. FIG. 4 shows a temperature distribution from the central region 950A to the peripheral region 950B of the semiconductor device shown in FIG. As shown in FIG. 4, the temperature of the central region 950A is high and is close to 200 ° C., and the temperature decreases toward the peripheral region 950B. In this way, the temperature distribution in which the central region 950A is high and the peripheral region 950B is low is generated because when the semiconductor device is operated, both the central region 950A and the peripheral region 950B generate heat, but the temperature distribution is higher than that in the peripheral region 950B. This is because the central region 950A is less likely to dissipate heat. That is, when the peripheral region 950B generates heat, heat is dissipated toward the outside of the semiconductor device around the peripheral region 950B. Even if the central region 950A generates heat, the peripheral region 950B around the central region 950A also generates heat. Therefore, it is difficult to dissipate heat, and heat is accumulated in the central region 950A. It is to be noted that, in FIG. 4, in the portion where the temperature is sharply increased, the temperature in the vicinity of the gate electrode 931 is likely to be particularly high.

  Thus, when the temperature distribution occurs in the semiconductor device, as shown in FIG. 5, when the semiconductor device is turned on, the drain current flowing in the central region 950A becomes lower than the drain current flowing in the peripheral region 950B. . This is because the temperature of the central region 950A of the semiconductor device is higher than the temperature of the peripheral region 950B.

  Further, in the semiconductor device, when the temperature distribution is generated as shown in FIG. 4, not only the current does not easily flow in a high temperature region, but also deterioration such as an increase in resistance of the electrode portion occurs, which results in a semiconductor device. The life is shortened, and the reliability is lowered. For this reason, when the semiconductor device is operated, it is preferable that the temperature distribution is as uniform as possible, so that the life is long and the reliability is high.

(Semiconductor device)
Next, the semiconductor device according to the first embodiment will be described with reference to FIGS. 6 and 7. FIG. 6 is a plan view of the semiconductor device according to the present embodiment when viewed in plan, and FIG. 7 is a cross-sectional view taken along alternate long and short dash line 6A-6B in FIG.

  The semiconductor device according to the present embodiment is a GaN-HEMT using a nitride semiconductor, and as shown in FIG. 7, a nucleation layer and a buffer (not shown) formed of a nitride semiconductor are formed on the substrate 10. The layer 11, the electron transit layer 21, and the electron supply layer 22 are laminated. The substrate 10 is formed of a semiconductor substrate such as SiC, and the buffer layer 11 is formed of AlN, AlGaN, GaN or the like. The electron transit layer 21 is made of GaN or the like, and the electron supply layer 22 is made of AlGaN or the like. Thus, in the electron transit layer 21, 2DEG 21a is generated near the interface between the electron transit layer 21 and the electron supply layer 22. Although not shown, a spacer layer made of i-AlGaN or the like may be formed between the electron transit layer 21 and the electron supply layer 22, and n-GaN or the like may be formed on the electron supply layer 22. A cap layer may be formed. Further, the electron supply layer 22 may be formed of InAlN or the like. In the present application, the electron transit layer 21 may be referred to as a first semiconductor layer, and the electron supply layer 22 may be referred to as a second semiconductor layer.

  A gate electrode 31, a source electrode 32, and a drain electrode 33 are formed on the electron supply layer 22. Specifically, as shown in FIG. 6, the gate electrode 31, the source electrode 32, and the drain electrode 33 have a comb-tooth-shaped electrode structure, and the drain electrode 33 is provided between the comb teeth of the source electrode 32. The comb teeth are inside. The comb teeth of the gate electrode 31 are formed between the comb teeth of the source electrode 32 and the comb teeth of the drain electrode 33. In the present application, the comb-teeth portion of the gate electrode 31, the source electrode 32, and the drain electrode 33 may be referred to as a finger portion or a comb-teeth portion, and this comb-teeth structure may be referred to as a finger structure. Specifically, the comb tooth portion of the gate electrode 31 in FIG. 6 becomes the finger portion 31 a of the gate electrode 31, the comb tooth portion of the source electrode 32 becomes the finger portion 32 a of the source electrode 32, and the comb tooth portion of the drain electrode 33. Is the finger portion 33a of the drain electrode 33. Therefore, the sectional view of FIG. 7 is a sectional view of the finger portion of each electrode, that is, the finger portion 31a of the gate electrode 31, the finger portion 32a of the source electrode 32, and the finger portion 33a of the drain electrode 33.

  As shown in FIG. 8, the source electrode 32 and the drain electrode 33 are formed of an ohmic contact layer 30a, a barrier metal layer 30b, and a wiring layer 30c which are sequentially stacked on the electron supply layer 22. The ohmic contact layer 30a is formed for ohmic contact with the electron supply layer 22, and is formed of a Ta / Al laminated film or a Ti / Al laminated film. When the ohmic contact layer 30a is a Ta / Al laminated film, the Ta layer 30d is formed on the electron supply layer 22, and the Al layer 30e is formed on the Ta layer 30d. Similarly, when the ohmic contact layer 30a is a Ti / Al laminated film, a Ti layer is formed on the electron supply layer 22, and an Al layer is formed on the Ti layer. In the description of the present embodiment, the case where the ohmic contact layer 30a is formed of a Ta / Al laminated film will be described, but the same applies to the case of a Ti / Al laminated film. The barrier metal layer 30b is formed of Ti / Pt / Au or the like. The wiring layer 30c is made of Au or the like and has a film thickness of several μm.

  In the semiconductor device according to the present embodiment, the Ta layer 30d of the ohmic contact layer 30a is formed to be gradually thinner in the peripheral region than in the central region when the semiconductor device is viewed in plan. Specifically, as shown in FIG. 6, a central region 50A in the central portion of the semiconductor device in plan view, an intermediate region 50B around the central region 50A, and a peripheral region 50C that is a peripheral portion around the intermediate region 50B. Thus, the film thickness of the Ta layer 30d of the ohmic contact layer 30a is changed. That is, as shown in FIG. 8A, the Ta layer 30d of the ohmic contact layer 30a in the central region 50A is thick, and as shown in FIG. 8C, the Ta layer 30d of the ohmic contact layer 30a in the peripheral region 50C is Ta. The layer 30d is formed so as to have a small thickness. Therefore, as shown in FIG. 8B, the Ta layer 30d of the ohmic contact layer 30a in the intermediate region 50B is thinner than the central region 50A and thicker than the peripheral region 50C.

  In the source electrode 32 and the drain electrode 33, a voltage is applied from the wiring layer 30c to the electron supply layer 22 via the barrier metal layer 30b and the ohmic contact layer 30a. Therefore, if the film thickness of the ohmic contact layer 30a is large, the resistance in the film thickness direction is correspondingly increased, and the flowing current is suppressed even when the same voltage is applied.

Specifically, as shown in FIG. 9A, the Ta layer 30d of the ohmic contact layer 30a is formed so that the central region 50A has a thickness of 10 nm, the intermediate region 50B has a thickness of 6 nm, and the peripheral region 50C has a thickness of 2 nm. To do. By changing the film thickness of the Ta layer 30d of the ohmic contact layer 30a as shown in FIG. 9A, the resistance in the film thickness direction of the ohmic contact layer 30a is at the center as shown in FIG. 9B. The area 50A becomes high and the peripheral area 50C becomes low. The resistance in the film thickness direction of the ohmic contact layer 30a in the intermediate region 50B is between the central region 50A and the peripheral region 50C. The resistivity of Al is about 2.6 × 10 ⁻⁷ Ωm, the resistivity of Ti is about 1.3 × 10 ⁻⁷ Ωm, and the resistivity of Ti is about 4.3 × 10 ⁻⁷ Ωm. Is. The film thickness of the ohmic contact layer 30a is about 100 nm.

  Therefore, in the semiconductor device according to the present embodiment, the central region 50A generates less current than the peripheral region 50C when the same voltage is applied, and thus generates less heat. Since heat is less likely to be dissipated in the central region 50A and is easily dissipated in the peripheral region 50C, it is possible to make the temperature distribution uniform when the semiconductor device is operated by suppressing heat generation in the central region 50A.

  Specifically, as shown in FIG. 10, in the semiconductor device of the present embodiment, the temperature distribution in central region 50A, intermediate region 50B, and peripheral region 50C of the semiconductor device can be made substantially uniform. The broken line in FIG. 10 represents the temperature distribution of the semiconductor device having the structure shown in FIGS. Therefore, in the semiconductor device according to the present embodiment, the temperature distribution can be made substantially uniform as shown in FIG. 10, so that the occurrence of deterioration can be suppressed and the life of the semiconductor device can be extended. , Reliability can be improved.

  Further, in the present embodiment, as shown in FIG. 11, when the semiconductor device is turned on, the drain current flowing in central region 50A, the drain current flowing in intermediate region 50B, and the drain current flowing in peripheral region 50C. Is substantially uniform.

  In the ohmic contact layer 30a, when the flowing current is I and the applied voltage is V, heat is generated by Joule heat corresponding to the power P = I × V. However, the applied voltage V is constant, the resistance value does not contribute to the power P, and the current I decreases as the resistance R increases. Therefore, even if the resistance of the ohmic contact layer 30a is increased, the flowing current I is reduced, so that heat generation due to Joule heat does not increase.

(Method of manufacturing semiconductor device)
Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. The nitride semiconductor formed on the substrate 10 is formed by epitaxial growth by MOVPE (Metal-Organic Vapor Phase Epitaxy). When growing a nitride semiconductor by MOVPE, TMA (trimethylaluminum) is used as the Al source gas, TMG (trimethylgallium) is used as the Ga source gas, and NH ₃ is used as the N source gas. (Ammonia) is used.

First, as shown in FIGS. 12 and 13, a nucleation layer, a buffer layer 11, an electron transit layer 21, and an electron supply layer 22 (not shown) are sequentially laminated on the substrate 10 by MOVPE. A SiC substrate is used as the substrate 10, and the nucleation layer (not shown) is formed of an AlN film having a film thickness of 1 nm to 300 nm, for example, 160 nm. The buffer layer 11 is formed of an AlGaN film having a film thickness of 1 nm to 1000 nm, for example, 600 nm. The electron transit layer 21 is formed of an i-GaN film having a thickness of about 3.0 μm. The electron supply layer 22 is formed of n-AlGaN having a film thickness of about 30 nm, and is doped with Si as an n-type impurity element so that the impurity concentration becomes 5 × 10 ¹⁸ cm ⁻³ . As a result, 2DEG 21a is generated in the electron transit layer 21 near the interface between the electron transit layer 21 and the electron supply layer 22. Although not shown, a spacer layer may be formed between the electron transit layer 21 and the electron supply layer 22 by i-AlGaN having a thickness of about 5 nm, and the spacer layer may be formed on the electron supply layer 22. The cap layer may be formed of n-GaN having a film thickness of about 10 nm. The cap layer is doped with Si as an n-type impurity element so that the impurity concentration becomes 5 × 10 ¹⁸ cm ⁻³ . 12 is a plan view, and FIG. 13 is a cross-sectional view taken along the alternate long and short dash line 12A-12B in FIG.

  Next, as shown in FIGS. 14 and 15, the ohmic contact layer 30a in the source electrode 32 and the drain electrode 33 is formed in the central region 50A above the electron supply layer 22. Specifically, a photoresist is applied on the electron supply layer 22, and exposure and development are performed by an exposure device, so that an opening is formed in a region where the source electrode 32 and the drain electrode 33 of the central region 50A are formed. A resist pattern (not shown) is formed. After that, a Ta / Al metal laminated film having a Ta layer 30d with a thickness of about 10 nm and an Al layer 30e with a thickness of about 100 nm is formed by vacuum evaporation. After that, the metal laminated film on the resist pattern is removed by lift-off together with the resist pattern by immersing it in an organic solvent or the like. Thereby, the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 in the central region 50A is formed by the Ta / Al metal laminated film in which the remaining Ta layer 30d has a thickness of about 10 nm and the Al layer 30e has a thickness of about 100 nm. Is formed. 14 is a plan view, and FIG. 15 is a sectional view taken along the chain line 14A-14B in FIG.

  Next, as shown in FIGS. 16 and 17, the ohmic contact layer 30a in the source electrode 32 and the drain electrode 33 is formed in the intermediate region 50B on the electron supply layer 22. Specifically, a photoresist is applied on the electron supply layer 22, and exposure and development are performed by an exposure device to form an opening in a region of the intermediate region 50B where the source electrode 32 and the drain electrode 33 are formed. A resist pattern (not shown) is formed. Then, a Ta / Al metal laminated film having a Ta layer 30d with a thickness of about 6 nm and an Al layer 30e with a thickness of about 100 nm is formed by vacuum evaporation. After that, the metal laminated film on the resist pattern is removed by lift-off together with the resist pattern by immersing it in an organic solvent or the like. Thereby, the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 in the intermediate region 50B is formed by the Ta / Al metal laminated film in which the remaining Ta layer 30d has a thickness of about 6 nm and the Al layer 30e has a thickness of about 100 nm. To form. 16 is a plan view, and FIG. 17 is a sectional view taken along the chain line 16A-16B in FIG.

  Next, as shown in FIGS. 18 and 19, the ohmic contact layer 30a in the source electrode 32 and the drain electrode 33 is formed in the peripheral region 50C on the electron supply layer 22. Specifically, a photoresist is applied on the electron supply layer 22, exposed by an exposure device, and developed to form an opening in a region of the peripheral region 50C where the source electrode 32 and the drain electrode 33 are formed. A resist pattern (not shown) is formed. Then, a Ta / Al metal laminated film having a Ta layer 30d with a thickness of about 2 nm and an Al layer 30e with a thickness of about 100 nm is formed by vacuum evaporation. After that, the metal laminated film on the resist pattern is removed by lift-off together with the resist pattern by immersing it in an organic solvent or the like. Thus, the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 in the central region 50A is formed by the Ta / Al metal laminated film in which the remaining Ta layer 30d has a thickness of about 2 nm and the Al layer 30e has a thickness of about 100 nm. To form. After that, heat treatment is further performed in a nitrogen atmosphere at a temperature of 400 ° C. to 900 ° C., for example, 580 ° C. to establish ohmic contact of the ohmic contact layer 30 a in the source electrode 32 and the drain electrode 33. 18 is a plan view, and FIG. 19 is a sectional view taken along the chain line 18A-18B in FIG.

  Next, as shown in FIGS. 20 and 21, the gate electrode 31 is formed on the electron supply layer 22. Specifically, after forming a SiN film (not shown) on the entire surface, a resist pattern (not shown) having an opening is formed in a region where the gate electrode 31 is formed. After that, the electron supply layer 22 is exposed by removing the SiN film in the opening of the resist pattern by RIE (Reactive Ion Etching) or the like. After that, a resist pattern (not shown) is removed by an organic solvent or the like, and then a photoresist is applied again, and exposure and development are performed by an exposure device to form an opening (not shown) in a region where the gate electrode 31 is formed. Forming a resist pattern. After that, a metal laminated film of Ni / Au is formed by vacuum evaporation, and then the metal laminated film on the resist pattern is removed by lift-off together with the resist pattern by immersing it in an organic solvent or the like. As a result, the gate electrode 31 is formed on the electron supply layer 22 by the remaining metal laminated film. 20 is a plan view and FIG. 21 is a cross-sectional view taken along the chain line 20A-20B in FIG.

  Next, as shown in FIGS. 22 and 23, a barrier metal layer 30b and a wiring layer 30c are sequentially formed on the ohmic contact layer 30a in the source electrode 32 and the drain electrode 33. An insulating film such as SiN is formed on the electron supply layer 22 in the regions excluding the finger portions of the source electrode 32 and the drain electrode 33, and the regions excluding the finger portions of the source electrode 32 and the drain electrode 33 are , Is formed on this insulating film. 22 is a plan view, and FIG. 23 is a cross-sectional view taken along one-dot chain line 22A-22B in FIG.

  Thus, the semiconductor device in this embodiment can be manufactured.

  In the above description, the case where the Ta layer 30d in the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 is formed so that the central region 50A is thick and the peripheral region 50C is thin is described. However, in the semiconductor device according to the present embodiment, as shown in FIG. 24, the thickness of the Al layer 30e of the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 is thicker in the central region 50A and thinner in the peripheral region 50C. You may form so. That is, as shown in FIG. 24A, the thickness of the Al layer 30e in the central region 50A is large, and as shown in FIG. 24C, the thickness of the Al layer 30e in the peripheral region 50C is small. You may form. Therefore, as shown in FIG. 24B, the film thickness of the Al layer 30e in the intermediate region 50B is smaller than that in the central region 50A and thicker than that in the peripheral region 50C. Specifically, the Ta layer 30d is formed to have a thickness of about 2 nm, the Al layer 30e of the central region 50A has a thickness of about 200 nm, the Al layer 30e of the intermediate region 50B has a thickness of about 150 nm, and the peripheral region 50C has a thickness of about 150 nm. The Al layer 30e is formed to have a thickness of about 100 nm. Although Al has a low resistivity, if the film thickness is increased, the resistance in the film thickness direction of the ohmic contact layer 30a becomes higher. Therefore, the same effect can be obtained, although it is not as great as when the film thickness of the Ta layer 30d is changed. You can

  Further, in the semiconductor device according to the present embodiment, as shown in FIG. 25, both the Ta layer 30d and the Al layer 30e of the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 are thicker in the central region 50A, The peripheral region 50C may be formed to be thin. That is, as shown in FIG. 25A, the Ta layer 30d and the Al layer 30e in the central region 50A have a large film thickness, and as shown in FIG. 25C, the Ta layer 30d and the Al layer 30e in the peripheral region 50C. You may form so that the film thickness of may be thin. Therefore, as shown in FIG. 25B, the Ta layer 30d and the Al layer 30e in the intermediate region 50B are formed to have a smaller film thickness than the central region 50A and a larger film thickness than the peripheral region 50C. Specifically, in the central region 50A, the Ta layer 30d is formed to have a film thickness of about 10 nm, and the Al layer 30e is formed to have a film thickness of about 200 nm. In the intermediate region 50B, the Ta layer 30d is formed to have a film thickness of about 6 nm and an Al layer is formed. The film thickness of 30e is about 150 nm. Further, in the peripheral region 50C, the Ta layer 30d is formed with a thickness of about 2 nm and the Al layer 30e is formed with a thickness of about 100 nm. Even more by gradually changing the film thicknesses of both the Ta layer 30d and the Al layer 30e. It is possible to greatly change the resistance of the ohmic contact layer 30a in the central region 50A and the peripheral region 50C.

  Further, since Ta has a higher resistivity than Al, the thickness of the ohmic contact layer 30a is kept constant and the thicknesses of the Ta layer 30d and the Al layer 30e are gradually changed as shown in FIG. May be That is, with the film thickness of the ohmic contact layer 30a being constant, as shown in FIG. 26A, in the central region 50A, the film thickness of the Ta layer 30d is thick and the film thickness of the Al layer 30e is thin. Further, as shown in FIG. 26C, in the peripheral region 50C, the Ta layer 30d is thin and the Al layer 30e is thick. Therefore, as shown in FIG. 26B, the Ta layer 30d in the intermediate region 50B is formed to be thinner than the central region 50A and thicker than the peripheral region 50C, and the Al layer 30e is thicker than the central region 50C. , Thicker than the central region 50A and thinner than the peripheral region 50C. Specifically, in the central region 50A, the Ta layer 30d is formed to have a thickness of about 10 nm, and the Al layer 30e is formed to have a thickness of about 100 nm. The film thickness of 30e is about 104 nm. Further, in the peripheral region 50C, the Ta layer 30d is formed with a thickness of about 2 nm and the Al layer 30e is formed with a thickness of about 108 nm.

[Second Embodiment]
Next, a second embodiment will be described. In this embodiment, as shown in FIG. 27, a central region 50A, an intermediate region 50B, and a peripheral region 50C are formed along the finger portions of each electrode. That is, the thickness of the ohmic contact layer in the source electrode 32 and the drain electrode 33 does not change in the middle of the finger portion. The states of the ohmic contact layer 30a, the barrier metal layer 30b, and the wiring layer 30c in the central region 50A, the intermediate region 50B, and the peripheral region 50C in the present embodiment are the same as those shown in FIG. Note that, in FIG. 27, for convenience, only the drain electrode 33 is formed in the intermediate region 50B, but the source electrode 32 may be formed in the intermediate region 50B. Therefore, in the description of the present embodiment, although not shown in the drawings, it is assumed that the source electrode 32 is also formed in the intermediate region 50B.

  Specifically, the film thickness of the Ta layer 30d of the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 in the central region 50A is formed to be about 10 nm without changing in the middle of the finger portion. Further, the Ta layer 30d of the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 in the intermediate region 50B is formed to have a thickness of about 6 nm without changing in the middle of the finger portion. Further, the film thickness of the Ta layer 30d of the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 in the peripheral region 50C is formed to be about 2 nm without changing in the middle of the finger portion.

  The contents other than those described above are the same as in the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described. The present embodiment is a method of manufacturing a semiconductor device in which the ohmic contact layer 30a in the source electrode 32 and the drain electrode 33 is formed by a method different from that of the first embodiment. Specifically, first, the same steps as the steps in FIGS. 12 and 13 in the first embodiment are performed.

  Next, as shown in FIG. 28, a Ta layer 30d having a film thickness of about 4 nm is formed in a region of the central region 50A on the electron supply layer 22 where the source electrode 32 and the drain electrode 33 are formed. Specifically, a photoresist is applied on the electron supply layer 22, and exposure and development are performed by an exposure device, so that an opening is formed in a region where the source electrode 32 and the drain electrode 33 of the central region 50A are formed. A resist pattern (not shown) is formed. After that, the Ta layer 30d is formed to a film thickness of about 4 nm by vacuum vapor deposition, and is immersed in an organic solvent or the like to remove the Ta layer 30d above the resist pattern together with the resist pattern by lift-off. As a result, the Ta layer 30d having a thickness of about 4 nm is formed in the region of the central region 50A where the source electrode 32 and the drain electrode 33 are formed.

  Next, as shown in FIG. 29, a Ta layer 30d having a thickness of about 4 nm is formed in the regions where the source electrode 32 and the drain electrode 33 are formed in the central region 50A and the intermediate region 50B. Specifically, a photoresist is applied on the electron supply layer 22, and exposure and development are performed by an exposure device to form the source electrode 32 and the drain electrode 33 in the central region 50A and the intermediate region 50B. A resist pattern (not shown) having an opening is formed. After that, the Ta layer 30d is formed to a film thickness of about 4 nm by vacuum vapor deposition, and is immersed in an organic solvent or the like to remove the Ta layer 30d above the resist pattern together with the resist pattern by lift-off. As a result, the Ta layer 30d having a thickness of about 8 nm is formed in the region where the source electrode 32 and the drain electrode 33 are formed in the central region 50A, and the region where the source electrode 32 and the drain electrode 33 are formed in the intermediate region 50B. Then, the Ta layer 30d having a film thickness of about 4 nm is formed.

  Next, as shown in FIG. 30, a Ta layer 30d having a film thickness of about 2 nm and an Al layer 30e having a film thickness of about 100 nm are formed in a region where the source electrode 32 and the drain electrode 33 are formed. Specifically, a photoresist (not shown) having an opening in a region where the source electrode 32 and the drain electrode 33 are formed by applying a photoresist on the electron supply layer 22 and performing exposure and development with an exposure device. Form a pattern. Then, a Ta / Al metal laminated film having a Ta layer 30d with a thickness of about 2 nm and an Al layer 30e with a thickness of about 100 nm is formed by vacuum evaporation. Thereafter, the ohmic contact layer 30a of the source electrode 32 and the drain electrode 33 is formed by removing the metal laminated film on the resist pattern together with the resist pattern by lift-off by immersing it in an organic solvent or the like. As a result, the Ta layer 30d having a film thickness of about 10 nm and the Al layer 30e having a film thickness of about 100 nm are formed in the region of the central region 50A where the source electrode 32 and the drain electrode 33 are formed. Further, in the region of the intermediate region 50B where the source electrode 32 and the drain electrode 33 are formed, the Ta layer 30d having a thickness of about 6 nm and the Al layer 30e having a thickness of about 100 nm are formed. Further, in the region of the peripheral region 50C where the source electrode 32 and the drain electrode 33 are formed, the Ta layer 30d having a film thickness of about 2 nm and the Al layer 30e having a film thickness of about 100 nm are formed. After that, heat treatment is further performed in a nitrogen atmosphere at a temperature of 400 ° C. to 900 ° C., for example, 580 ° C. to establish ohmic contact in the source electrode 32 and the drain electrode 33.

  After that, by performing the steps shown in FIGS. 20 to 23 in the first embodiment, the semiconductor device in the present embodiment can be manufactured.

  The contents other than those described above are the same as in the first embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high frequency amplifier.

  The semiconductor device according to the present embodiment is a discrete package of any of the semiconductor devices according to the first to third embodiments, and a semiconductor device thus discretely packaged will be described with reference to FIG. Incidentally, FIG. 31 schematically shows the inside of a discretely packaged semiconductor device, and the arrangement of electrodes and the like are different from those shown in the first to third embodiments. There is.

  First, the semiconductor device manufactured in the first to third embodiments is cut by dicing or the like to form the HEMT semiconductor chip 410 of a GaN-based semiconductor material. The semiconductor chip 410 is fixed onto the lead frame 420 with a die attach agent 430 such as solder. The semiconductor chip 410 corresponds to the semiconductor device according to the first to third embodiments.

  Next, the gate electrode 411 is connected to the gate lead 421 by the bonding wire 431, the source electrode 412 is connected to the source lead 422 by the bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by the bonding wire 433. The bonding wires 431, 432, 433 are made of a metal material such as Al. In addition, in the present embodiment, the gate electrode 411 is a gate electrode pad and is connected to the gate electrode 31 of the semiconductor device according to the first to third embodiments. Further, the source electrode 412 is a source electrode pad and is connected to the source electrode 32 of the semiconductor device according to the first to third embodiments. The drain electrode 413 is a drain electrode pad, and is connected to the drain electrode 33 of the semiconductor device according to the first to third embodiments.

  Next, resin molding is performed with the mold resin 440 by the transfer molding method. In this way, a HEMT discrete packaged semiconductor device using a GaN-based semiconductor material can be manufactured.

  Next, the power supply device and the high frequency amplifier according to the present embodiment will be described. The power supply device and the high frequency amplifier according to this embodiment are the power supply device and the high frequency amplifier using any of the semiconductor devices according to the first to third embodiments.

  First, the power supply device according to the present embodiment will be described with reference to FIG. The power supply device 460 in the present embodiment includes a high voltage primary side circuit 461, a low voltage secondary side circuit 462, and a transformer 463 arranged between the primary side circuit 461 and the secondary side circuit 462. The primary circuit 461 includes an AC power supply 464, a so-called bridge rectification circuit 465, a plurality of switching elements (four in the example shown in FIG. 32) 466, one switching element 467, and the like. The secondary circuit 462 includes a plurality of switching elements (three in the example shown in FIG. 32) 468. In the example shown in FIG. 32, the semiconductor device according to the first to third embodiments is used as the switching elements 466 and 467 of the primary side circuit 461. The switching elements 466 and 467 of the primary circuit 461 are preferably normally-off semiconductor devices. The switching element 468 used in the secondary circuit 462 is a normal MISFET (metal insulator semiconductor field effect transistor) formed of silicon.

  Next, the high frequency amplifier according to the present embodiment will be described with reference to FIG. The high frequency amplifier 470 in the present embodiment may be applied to, for example, a power amplifier for a base station of a mobile phone. The high frequency amplifier 470 includes a digital predistortion circuit 471, a mixer 472, a power amplifier 473, and a directional coupler 474. The digital predistortion circuit 471 compensates for the non-linear distortion of the input signal. The mixer 472 mixes the input signal with the non-linear distortion compensated with the AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal. In the example shown in FIG. 33, the power amplifier 473 has any of the semiconductor devices according to the first to third embodiments. The directional coupler 474 monitors the input signal and the output signal. In the circuit shown in FIG. 33, for example, by switching the switch, the output signal can be mixed with the AC signal by the mixer 472 and sent to the digital predistortion circuit 471.

  Although the embodiments have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope described in the claims.

Regarding the above description, the following supplementary notes will be disclosed.
(Appendix 1)
A first semiconductor layer formed of a semiconductor on the substrate;
A second semiconductor layer formed of a semiconductor on the first semiconductor layer;
A gate electrode, a source electrode and a drain electrode formed on the second semiconductor layer,
In a semiconductor device having
An ohmic contact layer in contact with the semiconductor is formed on the source electrode and the drain electrode,
The resistance of the ohmic contact layer in the film thickness direction is lower in the peripheral region than in the central region of the semiconductor device in plan view.
(Appendix 2)
The semiconductor device according to appendix 1, wherein the film thickness of the ohmic contact layer is smaller in the peripheral region than in the central region.
(Appendix 3)
The ohmic contact layer is formed by a layer containing Ta or Ti formed on the second semiconductor layer side and a layer containing Al formed on the layer containing Ta or Ti,
3. The semiconductor device according to appendix 1 or 2, wherein the thickness of the layer containing Ta or Ti is smaller in the peripheral region than in the central region.
(Appendix 4)
The ohmic contact layer is formed by a layer containing Ta or Ti formed on the second semiconductor layer side and a layer containing Al formed on the layer containing Ta or Ti,
3. The semiconductor device according to appendix 1 or 2, wherein the layer containing Al has a film thickness that is smaller in the peripheral region than in the central region.
(Appendix 5)
4. The semiconductor device according to appendix 3, wherein the layer including Al has a film thickness that is smaller in the peripheral region than in the central region.
(Appendix 6)
Each of the source electrode and the drain electrode is formed by a finger structure having a plurality of finger portions,
The central region is a central portion of a region in which the plurality of finger portions are formed,
6. The semiconductor device according to any one of appendices 1 to 5, wherein the peripheral region is a peripheral portion of a region where the plurality of finger portions are formed.
(Appendix 7)
The source electrode and the drain electrode are
A barrier metal layer is formed on the ohmic contact layer,
A wiring layer is formed on the barrier metal layer,
7. The semiconductor device according to any one of appendices 1 to 6, wherein the wiring layer is made of a material containing Au.
(Appendix 8)
8. The semiconductor device according to any one of appendices 1 to 7, wherein the first semiconductor layer and the second semiconductor layer are made of a nitride semiconductor.
(Appendix 9)
The first semiconductor layer is formed of a material containing GaN,
8. The semiconductor device according to any one of appendices 1 to 7, wherein the second semiconductor layer is formed of a material containing AlGaN or InAlN.
(Appendix 10)
A power supply device comprising the semiconductor device according to any one of appendices 1 to 9.
(Appendix 11)
An amplifier comprising the semiconductor device according to any one of appendices 1 to 9.

10 substrate 11 buffer layer 21 electron transit layer 21a 2DEG
22 electron supply layer 30a ohmic contact layer 30b barrier metal layer 30c wiring layer 30d Ta layer 30e Al layer 31 gate electrode 31a finger portion (gate electrode)
32 source electrode 32a finger part (source electrode)
33 drain electrode 33a finger part (drain electrode)
50A central area 50B intermediate area 50C peripheral area

Claims (10)

A first semiconductor layer formed of a semiconductor on the substrate;
A second semiconductor layer formed of a semiconductor on the first semiconductor layer;
A gate electrode, a source electrode and a drain electrode formed on the second semiconductor layer,
In a semiconductor device having
An ohmic contact layer in contact with the semiconductor is formed on the source electrode and the drain electrode,
The resistance of the ohmic contact layer in the film thickness direction is lower in the peripheral region than in the central region of the semiconductor device in plan view.   The semiconductor device according to claim 1, wherein the ohmic contact layer is thinner in the peripheral region than in the central region. The ohmic contact layer is formed by a layer containing Ta or Ti formed on the second semiconductor layer side and a layer containing Al formed on the layer containing Ta or Ti,
3. The semiconductor device according to claim 1, wherein the film thickness of the layer containing Ta or Ti is smaller in the peripheral region than in the central region. The ohmic contact layer is formed by a layer containing Ta or Ti formed on the second semiconductor layer side and a layer containing Al formed on the layer containing Ta or Ti,
3. The semiconductor device according to claim 1, wherein the thickness of the layer containing Al is smaller in the peripheral region than in the central region.   4. The semiconductor device according to claim 3, wherein the thickness of the layer containing Al is smaller in the peripheral region than in the central region. Each of the source electrode and the drain electrode is formed by a finger structure having a plurality of finger portions,
The central region is a central portion of a region in which the plurality of finger portions are formed,
The semiconductor device according to claim 1, wherein the peripheral region is a peripheral portion of a region where the plurality of finger portions are formed. The source electrode and the drain electrode are
A barrier metal layer is formed on the ohmic contact layer,
A wiring layer is formed on the barrier metal layer,
The semiconductor device according to claim 1, wherein the wiring layer is formed of a material containing Au.   8. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed of a nitride semiconductor. The first semiconductor layer is formed of a material containing GaN,
The semiconductor device according to claim 1, wherein the second semiconductor layer is formed of a material containing AlGaN or InAlN.   An amplifier comprising the semiconductor device according to claim 1.

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