JP6801598B2 - Open / close detection device and machine tools - Google Patents

Description

The present invention relates to an open / close detection device and a machine tool for detecting the open / close of a switch.

Conventionally, an open / close detection device includes an output terminal and an input terminal connected via a switch. The open / close detection device has a configuration for suppressing the influence of chattering of the switch. For example, when a predetermined number of times indicating on or off of the switch is set in advance and a signal indicating the on or off of the predetermined number of times is input, the open / close detection device detects the opening or closing of the switch. Considering that the chattering time becomes longer due to the deterioration of the switch, the open / close detection device increases the predetermined number of times after the lapse of a predetermined time (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2012-124006

However, since the open / close detection device increases a predetermined number of times, it takes a long time to detect the opening or closing of the switch.

Further, in order to suppress the influence of chattering, the open / close detection device may use a low-pass filter having a resistor and a capacitor. When a low-pass filter is used, the high-frequency waveform is reduced from the signal output from the output terminal, and the open / close detection device cannot recognize the high-frequency pulse. When the wavelength of the pulse waveform is lengthened to a low frequency in order to recognize a high-frequency pulse, it takes a long time to detect the opening or closing of the switch.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide an open / close detection device and a machine tool capable of detecting the opening or closing of a switch in a short time.

The open / close detection device according to the present invention includes an output terminal that outputs a signal, an input terminal connected to the output terminal via a switch, and a detection unit that detects open / close of the switch based on an input signal from the input terminal. An opening / closing detection device comprising a storage unit that stores an identification code corresponding to the switch, the output terminal outputs a signal indicating the identification code, and the detection unit outputs an input code indicated by the input signal. When matches the identification code, the closing of the switch is detected, and when the input code indicated by the input signal does not match the identification code, the opening of the switch is detected.

In the present invention, the detection unit detects the opening / closing of the switch based on the match or mismatch between the identification code corresponding to the switch and the input code. When chattering has occurred, the identification code and the input code do not match, and the detection unit detects the opening of the switch. When the chattering converges, the identification code and the input code match, and the detection unit immediately detects that the switch is closed.

The open / close detection device according to the present invention is provided with a plurality of output terminals and input terminals, respectively, and the plurality of output terminals and input terminals are connected to each other via the plurality of switches, and the plurality of said devices unique to each switch are connected. The storage unit stores the identification code, and the detection unit executes comparison between the plurality of identification codes and the plurality of input codes in parallel.

In the present invention, a plurality of output terminals and input terminals are connected to the plurality of switches, respectively. The detection unit executes a comparison between each of the plurality of identification codes unique to each switch and the plurality of input codes from each input terminal in parallel. Therefore, the detection unit can detect the opening / closing of the switch in a short time as compared with the case where a plurality of identification codes and a plurality of input codes from each input terminal are sequentially compared.

The open / close detection device according to the present invention includes an input register in which the identification code is composed of a binary number, has a plurality of bits, and stores the input code, and the detection unit includes the identification code and the input register. The opening / closing of the switch is detected by comparing the input codes stored in.

In the present invention, since the binary identification code and the input code are compared, the detection unit can determine the identification code and the input code match or mismatch in a short time.

The open / close detection device according to the present invention includes a second input register having a plurality of bits, and when the switch is closed, the input has a first sampling cycle capable of storing any of 1 and 0 in the identification code. The input code is stored in the register, and when the switch is closed, the input code is stored in the second input register at a second sampling cycle capable of storing either 1 or 0 in the identification code.

In the present invention, it is determined that the input code stored in the second input register and the code indicating the opening or closing of the predetermined switch match or do not match with a continuous predetermined bit smaller than the total number of bits of the identification code. .. Therefore, the detection unit can detect the opening and closing of the switch in a short time with predetermined reliability as compared with the case of determining the match or mismatch between the input code and the identification code stored in the input register in the first sampling cycle.

The machine tool according to the present invention includes a switch and the above-mentioned open / close detection device for detecting the open / close of the switch.

In the present invention, the detection unit detects the opening / closing of the switch based on the match or mismatch between the identification code corresponding to the switch and the input code. When chattering has occurred, the identification code and the input code do not match, and the detection unit detects the opening of the switch. When the chattering converges, the identification code and the input code match, and the detection unit immediately detects that the switch is closed.

In the open / close detection device and machine tool according to the present invention, the detection unit detects the open / close of the switch based on the match or mismatch between the identification code and the input code corresponding to the switch. When chattering has occurred, the identification code and the input code do not match, and the detection unit detects the opening of the switch. When the chattering converges, the identification code and the input code match, and the detection unit immediately detects that the switch is closed. The open / close detector detects the closing of the switch immediately after the chattering converges. Further, the length of the identification code is constant, and the time required for determining the match or mismatch between the identification code and the input code is not long. Further, the open / close detection device does not need to use a low-pass filter. Therefore, the open / close detection device can detect the opening or closing of the switch in a short time.

It is a block diagram which shows the opening / closing detection device which concerns on Embodiment 1. It is explanatory drawing explaining the output of the code from the output register, and the input of the code to the input register. It is a timing chart which shows the determination cycle, identification code, switch open / close, input signal, the first sampling period and input code. It is a flowchart explaining the open / close detection process which detects the open / close of a switch. It is a block diagram which shows the opening / closing detection device which concerns on Embodiment 2. FIG. It is a block diagram which shows the output register and the input register. It is a block diagram which shows the opening / closing detection device which connected the 1st switch to the 2nd input terminal by mistake. It is a figure which shows an example of the signal waveform of the 1st output terminal, the 1st input terminal, the 2nd output terminal and the 2nd input terminal in the open / close detection apparatus which connected the 1st switch to the 2nd input terminal by mistake. It is a block diagram which shows the opening / closing detection device which concerns on Embodiment 3. It is a timing chart which shows the determination cycle, identification code, switch open / close, input signal, first sampling cycle, second sampling cycle, second input code, input code, open / close signal. It is a flowchart explaining the open / close detection process which detects the open / close of a switch. It is a flowchart explaining the 2nd open / close detection process which detects open / close of a switch.

(Embodiment 1)
Hereinafter, the present invention will be described with reference to the drawings showing the open / close detection device according to the first embodiment. FIG. 1 is a block diagram illustrating an open / close detection device. The open / close detection device includes a substrate 20, an FPGA 1 (Field Programmable Gate Array) mounted on the substrate 20, and a connector 13 for connecting the substrate 20 and the switch 14.

The FPGA 1 includes an output terminal 7, an input terminal 8, an output register 2, an input register 3, a storage unit 4, a timer 5, a detection unit 6, and a transmission terminal 9. The output terminal 7 is connected to one end of the switch 14 via a physically isolated signal converter 10 and a FET 11 (Field Effect Transistor). The input terminal 8 is connected to the other end of the switch 14 via a physically isolated signal converter 15 and an amplifier 16. The signal converters 10 and 15 are, for example, an optical isolator having a photocoupler, a transformer isolation having a transformer coil, or a capacitive isolation having a capacitor. The signal converters 10 and 15 insulate the switch 14 side region operating at a high voltage from the FPGA 1 side region operating at a low voltage.

The output terminal 7 is connected to the gate 11a of the FET 11. The power supply 12 is connected to the drain 11b of the FET 11. The source 11c of the FET 11 is connected to one end of the switch 14 via the connector 13. The other end of the switch 14 is connected to the input side of the amplifier 16 via the connector 13 and the signal converter 15. The output side of the amplifier 16 is connected to the input terminal 8.

The output register 2 and the input register 3 each store an 8-bit code. The output register 2 and the input register 3 may store the code in a number of bits other than 8 bits. The storage unit 4 stores a unique identification code corresponding to the switch 14. The timer 5 measures the determination cycle and the sampling cycle. The detection unit 6 detects the opening / closing of the switch 14 based on the identification code and the input code stored in the input register 3.

FIG. 2 is an explanatory diagram illustrating the output of the code from the output register 2 and the input of the code to the input register 3. The FPGA 1 sets the identification code stored in the storage unit 4 in the output register 2. The output register 2 outputs the identification code bit by bit from the output terminal 7 in order from the left, and the FPGA 1 shifts the output register 2 to the left one by one as shown by the arrow in FIG. The input register 3 inputs the code bit by bit in order from the input terminal 8 from the right, and the FPGA 1 shifts the input register 3 to the left one by one as shown by the arrow in FIG.

The identification code output from the output register 2 is input to the gate 11a of the FET 11 via the signal converter 10, and the source 11c outputs a signal indicating the identification code. When the switch 14 is closed, the signal indicating the identification code is input to the input terminal 8 via the signal converter 15 and the amplifier 16. The input register 3 stores the signal input to the input terminal 8, that is, the input code. When the switch 14 is open, the identification code is not input to the input terminal 8.

If the configuration is different from that of the output register 2 or FET 11, for example, if the power supply of another circuit is erroneously connected to the output terminal 7 or if the wire is broken, the identification code is input to the input terminal 8 regardless of whether the switch 14 is opened or closed. do not do. That is, the state is the same as when the switch 14 is open.

FIG. 3 is a timing chart showing a determination cycle, an identification code, opening / closing of a switch 14, an input signal, a first sampling cycle, and an input code. In FIG. 3, T1 to T3 indicate the determination cycle between two adjacent pulses of the determination cycle shown in the uppermost row. The identification code, that is, the output signal, has a waveform, the upper side of which indicates 1 and the lower side of which indicates 0. When the switch 14 is opened or closed, the upper side indicates closed and the lower side indicates open. A broken line indicates a portion where chattering occurs when the switch 14 is opened and closed. The upper side of the input signal indicates 1, and the lower side indicates 0. t1 to t8 indicate the time points at which the input signal is sampled, and the first sampling period is indicated between the adjacent time points. The first sampling period is a period in which any code 1 or 0 in the identification code can be stored. Each determination cycle T1 to T3 includes sampling time points t1 to t8. The upper side of the input code indicates 1 and the lower side indicates 0.

FIG. 4 is a flowchart illustrating an opening / closing detection process for detecting the opening / closing of the switch 14. The FPGA 1 stores an 8-bit identification code stored in the storage unit 4, for example, "10101100" in the output register 2 (step S1), and clears the input register 3 (step S2). The FPGA 1 refers to the timer 5 and waits until the sampling cycle elapses from the sampling time of the previous input signal (step S3: NO). For example, if the previous sampling time point is t1, the FPGA 1 waits until the time point t2, and if the previous sampling time point is t8, the FPGA 1 waits until the time point t1 in the next determination cycle. When the sampling cycle has elapsed (step S3: YES), the FPGA 1 outputs a 1-bit signal from the output register 2 (step S4), and stores the 1-bit input signal in the input register 3 (step S5).

FPGA 1 determines whether or not the determination cycle has elapsed (step S6). When the determination cycle has not elapsed (step S6: NO), the FPGA 1 shifts the output register 2 to the left by 1 bit (step S7) and the input register 3 to the left by 1 bit (see step S8, FIG. 2). ), Return the process to step S3.

When the determination cycle has elapsed (step S6: YES), the detection unit 6 determines whether or not the input code stored in the input register 3 matches the identification code stored in the storage unit 4 (step S9). When the determination cycle has elapsed, at each sampling time point t1 to t8, the input register 3 stores a 1-bit input signal and stores an 8-bit input code.

When the input code matches the identification code (step S9: YES), the detection unit 6 detects the closing of the switch 14 and transmits a signal indicating the closing of the switch 14 from the transmission terminal 9 to the external device (step S10). The process returns to step S3. When the input code does not match the identification code (step S9: NO), the detection unit 6 detects the opening of the switch 14 and transmits a signal indicating the opening of the switch 14 from the transmission terminal 9 to the external device (step S11). The process returns to step S3. If the wiring is erroneous, for example, if the power supply of another circuit is erroneously connected to the output terminal 7 or if the wire is broken, the identification code is not input to the input terminal 8 and the input code becomes the identification code. Does not match (step S9: NO). Also in this case, the detection unit 6 detects the opening of the switch 14 and transmits a signal indicating the opening of the switch 14 from the transmission terminal 9 to the external device (step S11). The signal indicating the opening of the switch 14 includes a signal considered to be the opening of the switch 14.

In the determination cycle T1, the switch 14 is open. The input signal is 0 at each sampling time point t1 to t8 in the determination cycle T1. The input register 3 has an 8-bit input code “00000000000” and does not match the identification code “10101100”. The detection unit 6 detects the opening of the switch 14.

In the determination cycle T2, the switch 14 is closed and chattering is occurring. At each sampling time point t1 to t8 in the determination cycle T2, the FPGA 1 samples the input signal, and the input register 3 stores the 8-bit input code “00101000”. The input code does not match the identification code "10101100". The detection unit 6 detects the opening of the switch 14. When the switch 14 is closed and chattering is occurring, the detection unit 6 detects the opening of the switch 14. The judgment cycle is longer than the time during which chattering occurs.

In the determination cycle T3, the switch 14 is closed and chattering has not occurred. At each sampling time point t1 to t8 in the determination cycle T3, the FPGA 1 samples the input signal, and the input register 3 stores the 8-bit input code “10101100”. The input code matches the identification code, and the detection unit 6 detects that the switch 14 is closed.

In the open / close detection device according to the first embodiment, the detection unit 6 detects the open / close of the switch 14 based on the match or mismatch between the identification code and the input code corresponding to the switch 14. When chattering has occurred, the identification code and the input code do not match, and the detection unit 6 detects the opening of the switch 14. When the chattering converges, the identification code and the input code match, and the detection unit 6 immediately detects the closing of the switch 14. The open / close detection device detects the closing of the switch 14 immediately after the chattering converges. Further, the length of the identification code is constant, and the time required for determining the match or mismatch between the identification code and the input code is not long. Further, the open / close detection device does not need to use a low-pass filter. Therefore, the open / close detection device can detect the opening or closing of the switch 14 in a short time. Further, even if the wiring or disconnection occurs, the switch 14 is considered to be open, so that the safety can be improved.

Further, since the binary identification code and the input code are compared, the detection unit 6 can determine the identification code and the input code match or mismatch in a short time. Moreover, since it is not necessary to use a low-pass filter, it is not necessary to consider the time constant of the low-pass filter. Further, since the identification code is used as compared with the case where the pulse signal is simply output from the output terminal 7 and the output pulse signal is input to the input terminal 8 to detect the opening / closing of the switch 14, the determination is highly reliable.

(Embodiment 2)
Hereinafter, the present invention will be described with reference to the drawings showing the open / close detection device according to the second embodiment. FIG. 5 is a block diagram illustrating an open / close detection device. As shown in FIG. 5, the FPGA 1 includes first output terminals 7 (1) to nth output terminals 7 (n) and first input terminals 8 (1) to nth input terminals 8 (n). The first output terminal 7 (1) to the nth output terminal 7 (n) and the first input terminal 8 (1) to the nth input terminal 8 (n) are the first switch 14 (1) to the nth switch 14 (n). ) Are connected to each. That is, the first output terminal 7 (1) and the first input terminal 8 (1) are connected to the first switch 14 (1). Similarly, the nth output terminal 7 (n) and the nth input terminal 8 (n) are connected to the nth switch 14 (n). In FIG. 5, the description of the signal converters 10, 15, FET 11, power supply 12, and amplifier 16 is omitted.

The storage unit 4 stores n identification codes unique to each of the first switch 14 (1) to the nth switch 14 (n). When the identification code is composed of 8 bits, the storage unit 4 can store up to 256 unique identification codes.

FIG. 6 is a block diagram illustrating the output register 2 and the input register 3. As shown in FIG. 6, the output register 2 includes a first output register unit 2 (1) to an nth output register unit 2 (n) corresponding to the first switch 14 (1) to the nth switch 14 (n). The input register 3 includes a first input register unit 3 (1) to an nth input register unit 3 (n) corresponding to the first switch 14 (1) to the nth switch 14 (n). The FPGA 1 executes the above-mentioned open / close detection process in parallel for each of the first switch 14 (1) to the nth switch 14 (n). That is, the detection unit 6 executes the comparison between the input codes stored in the first input register units 3 (1) to the nth input register units 3 (n) and the n identification codes in parallel.

The pulse signals are simply output from the first output terminal 7 (1) to the nth output terminal 7 (n), and each output pulse signal is sent to the first input terminal 8 (1) to the nth input terminal 8 (n). When inputting in order and detecting the opening / closing of all the first switch 14 (1) to the nth switch 14 (n), a waiting time occurs between the output time of the pulse signal and the output time of the next pulse signal. Since the waiting time is cumulative, it takes a long time to complete the open / close detection process. On the other hand, the detection unit 6 of the second embodiment compares the input codes stored in the first input register units 3 (1) to the nth input register units 3 (n) with the n identification codes in parallel. Therefore, the opening / closing of the first switch 14 (1) to the nth switch 14 (n) can be detected in a shorter time than in the case of detecting the opening / closing of each switch in order.

FIG. 7 is a block diagram illustrating an open / close detection device in which the first switch 14 (1) is mistakenly connected to the second input terminal 8 (2), and FIG. 8 is a block diagram in which the first switch 14 (1) is mistakenly connected to the second input terminal 8 (2). Of the first output terminal 7 (1), the first input terminal 8 (1), the second output terminal 7 (2), and the second input terminal 8 (2) in the open / close detection device connected to the two input terminals 8 (2). It is a figure which shows an example of a signal waveform.

As shown in FIG. 7, when the first switch 14 (1) is mistakenly connected to the second input terminal 8 (2), the output signal of the first output terminal 7 (1) is the first input as shown in FIG. Do not input to terminal 8 (1), but input to second input terminal 8 (2). Therefore, the input code input to the first input terminal 8 (1) does not match the identification code corresponding to the first switch 14 (1), in other words, the output signal of the first output terminal 7 (1). The input code input to the second input terminal 8 (2) does not match the identification code corresponding to the second switch 14 (2), in other words, the output signal of the second output terminal 7 (2). By comparing each input signal whose input codes do not match, the user can identify the terminal connected incorrectly.

Of the configurations of the open / close detection device according to the second embodiment, the same configurations as those of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

(Embodiment 3)
Hereinafter, the present invention will be described with reference to the drawings showing the open / close detection device according to the third embodiment. FIG. 9 is a block diagram illustrating an open / close detection device. The open / close detection device includes a second input register 30 and a second transmission terminal 19. The FPGA 1 stores the input code in the input register 3 in the first sampling cycle in which both the codes 1 and 0 in the identification code can be stored. The FPGA 1 stores the input code in the second input register 30 in the second sampling cycle capable of storing either 1 or 0 in the identification code. Hereinafter, the input code stored in the second input register 30 will be referred to as a second input code.

FIG. 10 is a timing chart showing a determination cycle, an identification code, opening / closing of a switch 14, an input signal, a first sampling cycle, a second sampling cycle, a second input code, an input code, and an opening / closing signal. As shown in FIG. 10, k1 to k8 indicate the time points at which the input signal is sampled, and the second sampling period is indicated between the adjacent time points of the determination cycles shown in the uppermost stage. Each determination period T1 to T3 includes sampling time points k1 to k8. The upper side of the second input code indicates 1, and the lower side indicates 0. The open / close signal indicates an open signal or a close signal transmitted by the second transmission terminal 19 by the second open / close detection process.

The FPGA 1 samples the input signal at the sampling time points k1 to k8 and stores it in the second input register 30. As shown in FIG. 10, when the switch 14 is closed, for example, at sampling time points k1 to k8 in the determination cycle T3, the FPGA 1 can store only the identification code 1 in the second input register 30, and the identification code can be stored in the second input register 30. 0 cannot be stored in the second input register 30. In other words, the output terminal 7 outputs an output signal, that is, an identification code, with a waveform such that the waveform becomes 1 at the sampling time points k1 to k8. When the waveform of the output signal becomes 0 at the sampling time points k1 to k8, chattering has occurred.

FIG. 11 is a flowchart illustrating an opening / closing detection process for detecting the opening / closing of the switch 14. The FPGA 1 stores an 8-bit identification code stored in the storage unit 4, for example, "10101100" in the output register 2 (step S21), and clears the input register 3 (step S22). The FPGA 1 refers to the timer 5 and waits until the sampling cycle elapses from the sampling time of the previous input signal (step S23: NO). When the sampling cycle has elapsed (step S23: YES), the FPGA 1 outputs a 1-bit signal from the output register 2 (step S24), and stores the 1-bit input signal in the input register 3 (step S25).

The FPGA 1 refers to the timer 5 and waits until the second sampling cycle elapses from the second sampling time of the previous input signal (step S26: NO). When the second sampling cycle has elapsed (step S26: YES), the FPGA 1 stores a 1-bit input signal in the second input register 30 (step S27). The second input register 30 stores an 8-bit code like the input register 3, and shifts to the left each time a 1-bit input signal, that is, a code is stored (see FIG. 2). The second input register 30 may store the code in a number of bits other than 8 bits.

FPGA 1 determines whether or not the determination cycle has elapsed (step S28). When the determination cycle has not elapsed (step S28: NO), the FPGA 1 shifts the output register 2 to the left by 1 bit (step S29) and the input register 3 to the left by 1 bit (step S30, see FIG. 2). ), The process is returned to step S23.

When the determination cycle has elapsed (step S28: YES), the detection unit 6 determines whether or not the input code stored in the input register 3 matches the identification code stored in the storage unit 4 (step S31). When the determination cycle has elapsed, at each sampling time point t1 to t8, the input register 3 stores a 1-bit input signal and stores an 8-bit input code.

When the input code matches the identification code (step S31: YES), the detection unit 6 detects the closing of the switch 14 and transmits a signal indicating the closing of the switch 14 from the transmission terminal 9 to the external device (step S32). The process returns to step S23. When the input code does not match the identification code (step S31: NO), the detection unit 6 detects the opening of the switch 14 and transmits a signal indicating the opening of the switch 14 from the transmission terminal 9 to the external device (step S33). The process returns to step S23.

FIG. 12 is a flowchart illustrating a second open / close detection process for detecting the open / close of the switch 14. The FPGA 1 executes the second open / close detection process in a routine different from the open / close detection process. The detection unit 6 of the FPGA 1 reads the second input register 30 (step S41) and determines whether or not the right 4 bits, that is, the lower 4 bits are 1111 (step S42). In step S27 described above, the FPGA 1 stores the input signal in the second input register 30. When the lower 4 bits are 1111 (step S42: YES), the detection unit 6 transmits a signal indicating that the switch 14 is closed from the second transmission terminal 19 to the external device (step S43), and returns the process to step S41.

When the lower 4 bits are not 1111 (step S42: NO), the detection unit 6 determines whether or not the lower 4 bits are 0000 (step S44). When the lower 4 bits are 0000 (step S44: YES), the detection unit 6 transmits a signal indicating the opening of the switch 14 from the second transmission terminal 19 to the external device (step S45), and returns the process to step S41. If the lower 4 bits are not 0000 (step S44: NO), the detection unit 6 returns the process to step S41.

In the determination cycle T1, the switch 14 is open. At each sampling time point k1 to k8 in the determination cycle T1, all the input signals are 0. The input code of the lower 4 bits of the second input register 30 is "0000" (step S44: YES), and the detection unit 6 detects the opening of the switch 14 (step S45).

In the determination cycle T2, the switch 14 is closed and chattering is occurring. At each sampling time point k1 to k8 in the determination cycle T2, the FPGA 1 samples the input signal and stores the input code in the second input register 30. At time points k1 to k4, the second input code is "0010" and includes 0 and 1 (step S42: NO, step S44: NO). At time points k5 to k8, the second input code is "1111" (step S42: YES). At the sampling time k8 in the determination cycle T2, “1111” is stored in the lower 4 bits of the second input register 30, and the detection unit 6 detects that the switch 14 is closed (step S43).

While the switch 14 is closed and chattering is occurring, the detection unit 6 does not detect the opening / closing of the switch 14. When the chattering converges, the detection unit 6 detects that the switch 14 is closed. Since the detection unit 6 can determine the opening / closing of the switch 14 a plurality of times during the determination cycle T2, the detection unit 6 can detect the opening / closing of the switch 14 earlier than the case where the determination is made after the elapse of the determination cycle.

In the determination cycle T3, the switch 14 is closed and chattering has not occurred. At each sampling time point k1 to k8 in the determination cycle T3, the FPGA 1 samples the input signal and stores the input code "1111" in the lower 4 bits of the second input register 30 (step S42: YES). The detection unit 6 detects that the switch 14 is closed (step S43).

In the second open / close detection process, the open / close of the switch 14 is detected based on the lower 4 bits of the second input register 30, but the open / close of the switch 14 is detected based on the lower 3 bits or less or the lower 5 bits or more. It may be detected.

In the open / close detection device according to the third embodiment, the input code stored in the second input register 30 and the predetermined switch 14 are opened or closed with consecutive predetermined bits smaller than the total number of bits of the identification code. It is determined whether or not the code matches the symbol indicating. Therefore, the detection unit 6 can detect the opening and closing of the switch 14 in a short time with predetermined reliability as compared with the case of determining the match or mismatch between the input code and the identification code stored in the input register 3 in the first sampling cycle.

The open / close detection device is installed in an external device. For example, when the switch 14 is open, the external device stops, and when the switch 14 is closed, the external device operates. For safety, detection of closing is more important than detection of opening of switch 14. The closing of the switch 14 in which the external device operates is reliably detected by matching the input code and the identification code stored in the input register 3 in the first sampling cycle.

On the other hand, it is desirable to detect the opening and closing of the switch 14 in a short time when it is not related to the operation of the external device, for example, when determining an error in the control program or when issuing a warning. In this case, with fewer consecutive predetermined bits, it is determined in the second sampling cycle that the input code stored in the second input register 30 matches or does not match the predetermined code indicating the opening or closing of the switch 14. The detection unit 6 can detect the opening and closing of the switch 14 in a short time with predetermined reliability.

Among the configurations of the open / close detection device according to the third embodiment, the same components as those of the first or second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The above-mentioned open / close detection device is provided on a machine tool including, for example, a spindle, a work holding unit, a control device, and an emergency stop switch. The open / close detection device detects the open / close of the emergency stop switch. When the emergency stop switch closes, the input code stored in the input register 3 and the identification code match in the first sampling cycle, and the open / close detection device detects closing, the control device stops the spindle and the work holding unit. The control device functions as a stop execution device. When the open / close detection device detects open, the stop execution device stops, and when it detects close, the stop execution device operates.

When the emergency stop switch is closed, the input code stored in the second input register 30 matches the code indicating the closing of the switch 14, and the open / close detection device detects the closing, the control device determines an error, for example, in the control program. Do or issue a warning. The open / close detection device may detect the open / close of a switch other than the emergency stop switch, for example, a screen changeover switch on the display unit of the machine tool, or a limit switch provided on the door that opens / closes when the work is attached / detached to / from the work holding portion. ..

The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The technical features described in each example can be combined with each other and the scope of the invention is intended to include all modifications within the claims and scope equivalent to the claims. Will be done.

1 FPGA
3 Input register 4 Storage unit 6 Detection unit 7 Output terminal 7 (1) to 7 (n) 1st output terminal to nth output terminal 8 Input terminal 8 (1) to 8 (n) 1st input terminal to nth input Terminal 14 Switch 14 (1) -14 (n) First switch to nth switch 30 Second input register

Claims (5)

An open / close detection device including an output terminal that outputs a signal, an input terminal connected to the output terminal via a switch, and a detection unit that detects the open / close of the switch based on the input signal from the input terminal.
A storage unit that stores an identification code corresponding to the switch is provided.
The output terminal outputs a signal indicating the identification code, and outputs a signal indicating the identification code.
The detection unit detects the closing of the switch when the input code indicated by the input signal matches the identification code, and opens the switch when the input code indicated by the input signal does not match the identification code. Open / close detection device that detects. A plurality of output terminals and input terminals are provided, respectively.
The plurality of output terminals and input terminals are connected to each other via the plurality of switches.
The storage unit stores a plurality of the identification codes unique to each switch.
The open / close detection device according to claim 1, wherein the detection unit performs comparison between the plurality of identification codes and the plurality of input codes in parallel. The identification code is composed of binary numbers.
It has a plurality of bits and has an input register for storing the input code.
The opening / closing detection device according to claim 1 or 2, wherein the detection unit compares the identification code with the input code stored in the input register to detect the opening / closing of the switch. It has a second input register with multiple bits
When the switch is closed, the input code is stored in the input register in the first sampling cycle in which both the codes 1 and 0 in the identification code can be stored.
When the switch is closed, the input code is stored in the second input register at a second sampling cycle capable of storing either 1 or 0 in the identification code.
With consecutive predetermined bits smaller than the total number of bits of the identification code, it is determined whether or not the input code stored in the second input register matches or does not match the predetermined code indicating the opening or closing of the switch. The open / close detection device according to claim 3, which detects the open / close of a switch. A switch that opens the contacts in a safe state and closes the contacts in other states,
A machine tool including the open / close detection device according to any one of claims 1 to 4, which detects the open / close of the switch.

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