JP6860845B2 - Compound semiconductor device - Google Patents

Description

The present invention relates to a compound semiconductor device, and more particularly to a compound semiconductor device having a functional electrode.

A high electron mobility transistor (HEMT) is known as a nitride compound semiconductor device using a gallium nitride (GaN) compound semiconductor. In particular, the n-channel conductive type HEMT has high electron (carrier) mobility and is excellent in high frequency characteristics.

The HEMT includes a gallium nitride (GaN) layer that functions as a carrier traveling layer (channel layer) and an aluminum gallium nitride (AlGaN) that functions as a carrier supply layer (barrier layer) laminated on the GaN layer by heterojunction. It is composed of a nitride-based semiconductor functional layer having a layer. Two-dimensional electron gas (2DEG) in which high-mobility electrons (electrons) travel near the heterojunction of the channel layer due to the spontaneous polarization of nitride semiconductors and the piezo electric field using lattice mismatch between the channel layer and the barrier layer. : Two-dimensional electron gas) Channel is generated. A source electrode and a drain electrode are connected to the two-dimensional electron gas channel, and a gate electrode is arranged between the source electrode and the drain electrode. In a HEMT having such a structure, a low on-resistance can be realized by a two-dimensional electron gas channel.

In Patent Document 1 below, a functional electrode of an opposite conductive electrode layer is arranged on a two-dimensional electron gas channel in at least a part of a region surrounding the HEMT and reduces the carrier concentration of the two-dimensional electron gas channel. A nitride-based semiconductor device including an outer peripheral region having the above is disclosed. The disclosed nitride-based semiconductor device does not generate a two-dimensional electron gas channel directly under the functional electrode, and has a function of holding the nitride-based semiconductor device in a normally-off state regardless of the operation of the nitride-based semiconductor device. As a result, the leak current flowing into the HEMT can be suppressed.

Japanese Unexamined Patent Publication No. 2011-124385

However, the functional electrode of the counterconducting electrode layer has a problem that the characteristics of the counterconducting type are weakened or deteriorated by moisture or hydrogen. Further, since the field plate and the electrodes are provided on the nitride-based semiconductor functional layer, a TEOS film or the like is formed on the electrodes in order to alleviate the step between these electrodes and the region where the electrodes are not provided. However, the TEOS film is relatively easy for water and hydrogen to penetrate, and even if a film that does not allow water and hydrogen to pass through is provided on the TEOS film, the TEOS film is exposed on the side surface of the diced compound semiconductor device. As a result, water and hydrogen invade from the side surface side of the TEOS film.

The present invention has been made to solve the above problems. Therefore, the present invention is to provide a compound semiconductor device capable of preventing moisture and moisture from entering from the outside of the semiconductor device.

In order to solve the above problems, the compound semiconductor device of the present invention is arranged on a first compound semiconductor layer having a two-dimensional carrier gas channel and a first compound semiconductor layer, and functions as a carrier supply layer. The second compound semiconductor layer, the first electrode provided on the two-dimensional carrier gas channel, and the second electrode electrically connected to the two-dimensional carrier gas channel and disposed apart from the first electrode. The compound semiconductor element region provided with the electrodes and at least a part of the outer peripheral region surrounding the compound semiconductor element region are arranged on the two-dimensional carrier gas channel to reduce the carrier concentration of the two-dimensional carrier gas channel. A layer composed of a functional electrode, an auxiliary electrode arranged on the outer peripheral region so as to surround the periphery of the compound semiconductor element region from the outside of the functional electrode, and TEOS arranged on the compound semiconductor element region and the auxiliary electrode. an upper electrode disposed on the layer made of TEOS, surrounds the periphery of the compound semiconductor element region from the outside of the functional electrode, a groove reaching the auxiliary electrodes through a layer made of TEOS, and an upper electrode auxiliary electrode The connection electrode formed in the groove and the element separation groove arranged on the outer peripheral region of the auxiliary electrode are provided , and are arranged between the upper electrode, the connection electrode, and the upper electrode and the connection electrode. At least one of the intervening metals formed extends to the outside of the element separation groove.

According to the present invention, it is possible to provide a compound semiconductor device in which the invasion of water and hydrogen is relatively suppressed and the deterioration of the characteristics of the functional electrode is suppressed.

It is sectional drawing (cross-sectional view of the part cut by the F1-F1 cutting line shown in FIG. 2) of the nitride compound semiconductor apparatus which concerns on Example 1 of this invention. It is a top view of the nitride compound semiconductor apparatus which concerns on Example 1. FIG.

Next, examples of the present invention will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, the drawings are schematic and differ from the actual ones. In addition, there may be parts in which the relations and ratios of the dimensions of the drawings are different from each other.

In addition, the examples shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention specifies the arrangement of each component as follows. Not something to do. The technical idea of the present invention can be modified in various ways within the scope of claims.

(Example 1)
Example 1 of the present invention describes an example in which the present invention is applied to a nitride-based compound semiconductor device in which the compound semiconductor device region is a HEMT.

[Structure of Nitride-based Compound Semiconductor Equipment]
As shown in FIG. 1, the nitride-based compound semiconductor device 1 according to the first embodiment has a first compound semiconductor layer 31 having a two-dimensional carrier gas channel 310 and functioning as a carrier traveling layer, and a first compound. A second compound semiconductor layer 32 arranged on the semiconductor layer 31 and functioning as a carrier supply layer (barrier region), a first electrode 61 provided on the two-dimensional carrier gas channel 310, and a two-dimensional carrier gas. A compound semiconductor element region 10 including a second electrode 42 electrically connected to the channel 310 and disposed apart from the first electrode 61, and a region surrounding the compound semiconductor element region 10. At least a part thereof is provided on the two-dimensional carrier gas channel 310, and includes an outer peripheral region 11 having an opposite conductive functional electrode 62 that reduces the carrier concentration of the two-dimensional carrier gas channel 310.

The first compound semiconductor layer 31 and the second compound semiconductor layer 32 construct a compound semiconductor functional layer 3, and the compound semiconductor element region 10 is formed in the compound semiconductor functional layer 3. The compound semiconductor device 10 is an n-channel conductive HEMT having an electron as a carrier in Example 1. Therefore, the two-dimensional carrier gas channel 310 is a two-dimensional electron gas channel. The lattice constant of the semiconductor constituting the second compound semiconductor layer 32 is smaller than the lattice constant of the semiconductor constituting the first compound semiconductor layer 31, and the band gap of the second compound semiconductor layer 32 is the first compound semiconductor layer. Larger than the bandgap of 31.

As shown in FIG. 1, the compound semiconductor functional layer 3 is arranged on the substrate 2. In the first embodiment, a silicon substrate (for example, a silicon single crystal substrate) that can realize a large diameter and can be manufactured at low cost is used for the substrate 2. The compound semiconductor functional layer 3 is provided with a buffer layer 33 on the back surface of the first compound semiconductor layer 31 facing the second compound semiconductor layer 32, and the compound semiconductor functional layer 3 is crystallized via the buffer layer 33. It is arranged on the substrate 2 in a state where the property is ensured. The buffer layer 33 may not be provided, and the function of the buffer layer 33 may be provided in the first compound semiconductor layer 31.

The compound semiconductor functional layer 3 is made of a group III nitride-based semiconductor material here. Typical group III nitride semiconductors are Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x
It is represented by + y ≦ 1). Further, in Example 1, the composition ratio x1 of Al (aluminum) of the first compound semiconductor layer 31 of the compound semiconductor functional layer 3 is in the range of 0 ≦ x1 <1, and the Al of the second compound semiconductor layer 32 When the composition ratio x2 is in the range of 0 <x2 ≦ 1 and the composition ratio x2 of Al is larger than the composition ratio x1 of Al (x1 <x2), the first compound semiconductor layer 31 is Al _x1 Ga. It is composed of a nitride semiconductor material represented by _1-x1 N, and the second compound semiconductor layer 32 is composed of a nitride semiconductor material represented by _{Al x2} Ga _{1-x2 N.} For example, the compound semiconductor functional layer 3 is a first compound semiconductor layer 31 made of AlGaN.
A laminated structure of a second compound semiconductor layer 32 made of and AlGaN, or a first made of GaN.
The compound semiconductor layer 31 and the second compound semiconductor layer 32 made of AlGaN are laminated, or the first compound semiconductor layer 31 made of AlGaN and the second compound semiconductor layer 32 made of AlN are laminated. To.

In Example 1, the film thickness of the first compound semiconductor layer 31 is, for example, 0.5 μm-10.0 μ.
Set to m. When a GaN layer is used for the first compound semiconductor layer 31, this GaN layer is, for example, a non-doped layer set to a film thickness of 3.0 μm. The film thickness of the second compound semiconductor layer 32 is set to, for example, 5 nm to 100 nm, and when the second compound semiconductor layer 32 is an AlGaN layer, the Al composition is set to, for example, 0.1-0.4. Specifically, the film thickness is 2.
An AlGaN layer, which is a non-doped layer having an Al composition of 0.26 at 5 nm, is used. For the buffer layer 33, for example, a laminated structure in which a plurality of GaN layers and aluminum nitride (AlN) layers are alternately laminated is used.

In the compound semiconductor functional layer 3, the first compound semiconductor layer 31 and the second compound semiconductor layer 3
A two-dimensional carrier gas channel based on spontaneous polarization and piezo polarization of the first compound semiconductor layer 31 and the second compound semiconductor layer 32 on the surface portion of the first compound semiconductor layer 31 near the heterojunction interface with 2. 310 is generated. The two-dimensional carrier gas channel 310 functions as a channel region of electrons (carriers) having high mobility in the compound semiconductor device region (here, HEMT) 10. Although detailed description is omitted, the present invention can also be used for a p-channel conductive type HEMT, in which case the two-dimensional carrier gas channel 310 becomes a two-dimensional hole gas channel.

As shown in FIG. 1, the compound semiconductor element region 10 is composed of a first electrode 61 formed on the compound semiconductor functional layer 3 having a two-dimensional carrier gas channel 310 and a compound semiconductor functional layer 3. A second electrode 42 that is ohmic-connected to the dimensional carrier gas channel 310, and a third electrode 41 that is ohmic-connected to the two-dimensional carrier gas channel 310 so as to sandwich the first electrode 61 between the second electrode 42. It has. In the compound semiconductor element region (HEMT) 10, a potential higher than the potential applied to the third electrode 41 is applied to the second electrode 42, and when the first electrode 61 is turned on, the second electrode 42 is turned on. A current flows from the third electrode 41 to the third electrode 41 (electrons as carriers flow in the opposite direction).

Here, the second electrode 42 functions as a drain electrode, and the third electrode 41 functions as a source electrode. The second electrode 42 and the third electrode 41 are two-dimensional carrier gas channels 31.
It is an ohmic electrode connected to 0 with a low resistance. Further, in the first embodiment, at least one of the third electrode 41 and the second electrode 42 is a two-dimensional carrier gas of the first compound semiconductor layer 31 from the surface of the second compound semiconductor layer 32 of the compound semiconductor functional layer 3. It may be arranged in a connection hole (through hole or via hole) formed toward the channel 310 and have a low resistance between the two-dimensional carrier gas channel 310 and the channel 310. In Example 1, the second electrode 42 and the third electrode 41 are both laminated with a Ti (titanium) layer having a film thickness of, for example, 10 nm to 50 nm, and a film thickness of, for example, 25 nm to 1000 nm. It is composed of a laminated film with an Al layer having.

The first electrode 61 is a control electrode or a gate electrode, and is arranged on the second compound semiconductor layer 32. As shown in FIG. 1, in the first embodiment, the first electrode 61 is dug from the surface of the second compound semiconductor layer 32 toward the two-dimensional carrier gas channel 310 in the second compound semiconductor layer 32. It may be arranged in a recess (recess or recess).

The functional electrode 62 in the outer peripheral region 11 may be made of the same electrode material as the first electrode 61. In the first embodiment, the functional electrode 62 uses a p-type metal oxide which is a conductive type opposite to the conductive type of the two-dimensional carrier gas channel 310. As this p-type metal oxide, any one of nickel oxide (NiO _x , x = 1 to 2), iron oxide, cobalt oxide, manganese oxide, and copper oxide can be practically used. Here, for the functional electrode 62, for example, NiO _x having a film thickness of 20 nm to 1000 nm is used.

Further, a p-type nitride semiconductor can be used for the functional electrode 62. As the p-type nitride semiconductor, any one of p-type doped AlGaN, p-type doped GaN, and p-type doped InGaN can be practically used. For example, for the functional electrode 62, p-type doped GaN having a film thickness of 80 nm-120 nm doped with magnesium (Mg) is used.

The p-type metal oxide or p-type nitride semiconductor used for these functional electrodes 62 is composed of a single-layer film, but may be composed of a plurality of multi-layer films. Further, the functional electrode 62 may change the p-type concentration gradually or stepwise. For example, the p-type concentration of the functional electrode 62 is set thinner as the distance from the surface of the second nitride semiconductor layer 32 increases. Further, the functional electrode 62 may be a laminated film in which a p-type metal oxide semiconductor and a p-type nitride semiconductor are combined.

For the functional electrode 62, a nickel (Ni) layer having a film thickness of, for example, 10 nm to 1000 nm can be used on a p-type metal oxide or p-type nitride semiconductor. Further, a gold (Au) layer having a film thickness of, for example, 0.1 μm to 3.0 μm, and a titanium (Ti) layer having a film thickness of, for example, 5 nm to 100 nm can be used on the gold layer.

As shown in FIG. 2, the functional electrode 62 (outer peripheral region 11) extends over the entire circumference along the outer edge of the compound semiconductor functional layer 3 so as to surround the compound semiconductor device region 10. The functional electrode 62 has a ring shape that surrounds the outer periphery of the compound semiconductor element 10 when viewed from above. The functional electrode 62 applies a fixed potential through an external terminal in order to more reliably prevent a leak current. For example, the external terminal is connected to the substrate 2, and the potential applied to the substrate 2, for example, the same potential as the ground potential is applied to the external terminal. The functional electrode 62 may be in a floating state in which a fixed potential is not applied. As a result, the functional electrode 62 may be partially and intermittently arranged along the outer edge of the compound semiconductor functional layer 3 when it has the same function as when it is arranged all around. Since the first electrode layer 601 having a conductive type (p type) opposite to the conductive type (n type) of the two-dimensional carrier gas channel 310 is formed in the functional electrode 62, the triangular potential well is pulled up. The level of the conduction band level E _c is pushed up higher than the _{Fermi level E f.} The functional electrode 62 can p-invert the two-dimensional carrier gas channel 310 directly under the functional electrode 62 and hold it in a normally-off state, and suppress a leak current flowing into the compound semiconductor element 10 through the side wall of the compound semiconductor functional layer 3. ..

As shown in FIG. 1, the auxiliary electrode 63 is provided in the outer peripheral region 11 of the compound semiconductor functional layer 3, where the auxiliary electrode 63 is outside the functional electrode 62 and surrounds the compound semiconductor element 10. It extends over the entire circumference along the outer edge of the semiconductor functional layer 3. The electrode material of the auxiliary electrode 63 may be the same electrode material as the functional electrode 62, or may be the same electrode material as the third electrode 41. That is, the material may or may not affect the two-dimensional carrier gas channel 310. The auxiliary electrode 63 may be in a floating state to which no potential is applied, or may be electrically connected to the third electrode (source electrode) 41.

A first insulating resin layer 71 made of TEOS is arranged on the compound semiconductor functional layer 3 and on the electrodes 41, 42, 61, 62, 63. The first insulating resin layer 71 relaxes the step caused by the electrodes 41, 42, 61, 62, 63 and the like, and the upper surface and the electrode of the first insulating resin layer 71 on the electrodes 41, 42, 61, 62, 63 and the like. A comparatively gentle surface is formed between the upper surface of the first insulating resin layer 71 and the region where 41, 42, 61, 62, 63 and the like are not provided. Upper electrodes 81 and 82 connected to a bonding wire or a metal plate are arranged on the first insulating resin layer 71. The upper electrode 81 is electrically connected to the electrode 63 by connection electrodes 83 and 85 provided in holes penetrating the first insulating resin layer 71. Here, as shown in FIG. 1, an intervening metal 84 is arranged between the connection electrode 83 and the connection electrode 85, and the upper electrode 81 is electrically connected to the electrode 63.

Further, as shown in FIG. 1, the electrode 42 has a connection electrode 86 and a connection electrode 88 provided in a through hole provided in the first insulating resin layer 71, and an intervening metal 87 is arranged between them. ing. As a result, the electrode 42 is electrically connected to the upper electrode 82 on the first insulating resin layer 71. Although not shown in FIG. 1, in the cross section of another cut compound semiconductor device 1, the electrode 41 and the electrode 61 also pass through the first insulating resin layer 71 through the connection electrodes in the respective holes to pass through the first insulating resin layer. It is connected to each upper electrode on 71.

As shown in FIG. 2, the hole (or the connecting portion) provided with the connecting portion connecting the auxiliary electrode 63 and the upper electrode is the outer circumference of the compound semiconductor element 10 and is the entire circumference along the outer edge of the compound semiconductor functional layer 3. Have been placed. As a result, the side surface of the first insulating resin layer 71 is exposed by dicing, but the connecting portions 83 and 85 connecting the auxiliary electrode 63 and the upper electrode 81 surround the functional electrode 62 from the outside over the entire circumference. , The invasion of moisture and hydrogen from the outside on the side surface side of the first insulating resin layer 71 can be satisfactorily suppressed. Therefore, even if the functional electrode 62 is a material whose characteristics are deteriorated by moisture or hydrogen, the moisture or hydrogen reaches the functional electrode 62 by the connecting portions 83, 85 connected to the auxiliary electrode 63 surrounding the outside of the functional electrode 62. Therefore, deterioration of the characteristics of the functional electrode 62 can be suppressed, and an increase in the leakage current can be suppressed even if moisture invades from the outside.

Further, the second insulating resin layer covers the upper electrode 81 connected to the auxiliary electrode 63 and the exposed upper surface of the first insulating resin layer 71. The second insulating resin layer is made of, for example, a silicon nitride film, a silicon oxide film, or polyimide, and is made of an insulating material having a higher density than the first insulating resin layer 71. Thereby, water or hydrogen invading from above the compound semiconductor device 1 can be satisfactorily suppressed.
Further, although not shown in FIG. 1, there are NiO, hafnium oxide (HfO), silicon oxidation (SiO ₂ ), and silicon nitride (Si _{3) between the first insulating resin layer 71 and the compound semiconductor functional layer 3.} Any one of N ₄ ), aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), and magnesium oxide (MgO) can be practically used. For example, a NiO layer having a film thickness of 2 nm to 500 nm can be used as the insulating film.

A plurality of element separation grooves 91 are arranged outside the auxiliary electrode 63, all around or partially separated along the outer edge of the compound semiconductor functional layer 3. Although the element separation groove 91 is shown in the example of reaching the buffer layer 33, it is sufficient that the element separation groove 91 is formed to a depth of at least reaching the two-dimensional carrier gas channel 310.

As shown in FIG. 2, the element separation groove may be composed of a plurality of ring-shaped grooves such as an inner ring and an outer ring. When viewed in a plane, at least one of the connecting portions 83 and 85 connecting the upper electrode 81 or the upper electrode 81 and the auxiliary electrode 63 and the intervening metal 84 extends to the outside of the element separation groove. The compound semiconductor device is easily warped by providing the element separation groove, but at least one of the connecting portions 83 and 85 connecting the upper electrode 81 or the upper electrode 81 and the auxiliary electrode 63 and the intervening metal 84 is provided in this way. As a result, damage due to warpage of the compound semiconductor device 1 can be suppressed, and the ability of the compound semiconductor device 1 to cope with the warping force can be enhanced.

(Other Examples)
As mentioned above, the present invention has been described by a plurality of embodiments, but the statements and drawings that form part of this disclosure do not limit the invention. The present invention relates to various alternative embodiments.
It can be applied to examples and operational techniques.

For example, the present invention relates to the first electrode 61 of the compound semiconductor element 10, the functional electrode 62 of the outer peripheral region 11, and the auxiliary electrode 63 in the nitride compound semiconductor device 1 according to the above-mentioned Examples 1 to 5. It may be configured to be made of, for example, a Schottky electrode material that does not have a conductive type.

Further, in the present invention, instead of the nitride-based compound semiconductor device 1 described above, the first compound semiconductor layer 31 is gallium arsenide (GaAs) and the second compound semiconductor layer 32 is aluminum gallium arsenide (AlGaAs). It can be applied to a compound semiconductor device provided with a compound semiconductor functional layer 3.

The present invention can be widely applied to a compound semiconductor device in which moisture and hydrogen are relatively difficult to penetrate, regardless of the operation of the compound semiconductor device.

1 ... Nitride-based compound semiconductor device 10 ... Compound semiconductor element region 11 ... Outer peripheral region 2 ... Substrate 3 ... Compound semiconductor functional layer 31 ... First compound semiconductor layer 310 ... Two-dimensional carrier gas channel 32 ... Second compound semiconductor layer 41 ... Third electrode 42 ... Second electrode 61 ... First electrode 62 ... Functional electrode 63 ... Auxiliary electrode 71 ... First insulating resin layer

Claims (6)

A first compound semiconductor layer having a two-dimensional carrier gas channel and
A second compound semiconductor layer disposed on the first compound semiconductor layer and functioning as a carrier supply layer,
The first electrode provided on the two-dimensional carrier gas channel and
A second electrode that is electrically connected to the two-dimensional carrier gas channel and is disposed apart from the first electrode.
Compound semiconductor device region with
A functional electrode that is disposed on the two-dimensional carrier gas channel in at least a part of the outer peripheral region that surrounds the compound semiconductor device region and reduces the carrier concentration of the two-dimensional carrier gas channel.
Auxiliary electrodes arranged on the outer peripheral region so as to surround the periphery of the compound semiconductor device region from the outside of the functional electrode, and
A layer made of TEOS disposed on the compound semiconductor device region and the auxiliary electrode,
An upper electrode arranged on the layer made of TEOS and
A groove that surrounds the compound semiconductor device region from the outside of the functional electrode, penetrates the layer made of the TEOS and reaches the auxiliary electrode, connects the upper electrode and the auxiliary electrode, and is formed in the groove. Connection electrode and
It is provided with an element separation groove disposed on the outer peripheral region outside the auxiliary electrode.
A compound semiconductor characterized in that at least one of the upper electrode, the connection electrode, and an intervening metal arranged between the upper electrode and the connection electrode extends to the outside of the element separation groove. apparatus. The upper electrode is covered with a film composed of at least one selected from a silicon nitride film, a silicon oxide film, and a polyimide film made of a material having a higher density than the layer made of TEOS. Item 2. The compound semiconductor apparatus according to Item 1. The compound semiconductor device according to any one of claims 1 to 2, wherein the auxiliary electrode is floating or electrically connected to an electrode having a small potential among the first electrode and the second electrode. The functional electrode of said outer peripheral region includes an electrode layer having an opposite conductivity type as the two-dimensional carrier gas channel, the electrode layer is a metal oxide semiconductor or a nitride semiconductor, or the metal oxide semiconductor and the nitride The compound semiconductor device according to any one of claims 1 to 3, wherein the compound semiconductor device is composed of a combination with a semiconductor. The compound semiconductor device according to any one of claims 1 to 4, wherein the upper electrode extends to the outside of the element separation groove. A first compound semiconductor layer having a two-dimensional carrier gas channel and
A second compound semiconductor layer disposed on the first compound semiconductor layer and functioning as a carrier supply layer,
The first electrode provided on the two-dimensional carrier gas channel and
A second main electrode that is electrically connected to the two-dimensional carrier gas channel and is disposed apart from the first electrode.
Compound semiconductor device region with
A functional electrode of a P-type nitride semiconductor or a metal oxide, which is disposed on the two-dimensional carrier gas channel in at least a part of the outer peripheral region surrounding the compound semiconductor device region,
Auxiliary electrodes arranged on the outer peripheral region so as to surround the periphery of the compound semiconductor device region from the outside of the functional electrode, and
A layer made of TEOS disposed on the compound semiconductor device region and the auxiliary electrode,
An upper electrode arranged on the layer made of TEOS and
A groove that surrounds the compound semiconductor device region from the outside of the functional electrode, penetrates the layer made of TEOS, and reaches the auxiliary electrode.
A connection electrode formed in the groove by connecting the upper electrode and the auxiliary electrode,
It is provided with an element separation groove disposed on the outer peripheral region outside the auxiliary electrode.
A compound semiconductor characterized in that at least one of the upper electrode, the connection electrode, and an intervening metal arranged between the upper electrode and the connection electrode extends to the outside of the element separation groove. apparatus.

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