JP6863093B2 - Light receiving element and its manufacturing method - Google Patents

Description

The present invention relates to a light receiving element and a method for manufacturing the same.

A light receiving element having a mesa structure and receiving light to generate an electric signal is known (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2001-144278

For example, when the light receiving element is an infrared sensor or the like, it is preferable to reduce the pitch between mesas in order to increase the number of pixels. Further, in order to reduce the dark current, it is preferable to provide the electrode near the light absorption layer. However, if the pitch between mesas is reduced, it becomes difficult to form electrodes.

Therefore, it is an object of the present invention to provide a light receiving element capable of forming an electrode while reducing the pitch between mesas and a method for manufacturing the same.

The method for manufacturing a light receiving element according to the present invention includes a first conductive type first layer, a light absorption layer, and a second conductive type second layer, which are sequentially laminated on a semiconductor substrate formed of a compound semiconductor. And the step of growing the semiconductor layer including the second conductive type third layer, the first opening, and the second opening separated from the first opening and wider than the first opening. The first mask is formed so that the step of forming the first mask to be held on the semiconductor layer and the etching of the semiconductor layer proceed more than the portion in the first opening in the second opening. It has a step of etching the semiconductor layer using the semiconductor layer, a third opening overlapping the first opening, and a fourth opening overlapping the second opening and wider than the second opening. A step of forming the second mask on the semiconductor layer, and an n-type structure in which a mesa is formed in a region of the semiconductor layer sandwiched between the third openings and the first layer is formed in the fourth opening. A step of etching the semiconductor layer using the second mask so that a contact region is formed, and a first electrode electrically connected to the third layer is formed on the mesa, and the n It has a step of forming a second electrode electrically connected to the first layer on the mold contact region, and the mesa is the first layer, the light absorbing layer, the second layer and the first layer. The n-type region of the semiconductor layer including the three layers, which is covered with the first mask and is exposed from the fourth opening of the second mask after etching with the second mask. It is a contact area.

The light receiving element according to the present invention includes a semiconductor substrate formed of a compound semiconductor, a first conductive type first layer, a light absorption layer, and a second conductive type second layer which are sequentially laminated on the semiconductor substrate. , And a semiconductor layer including the second conductive type third layer and having a mesa, a terrace, an n-type contact region and a groove formed from the central side to the outer peripheral side of the semiconductor substrate, and provided on the mesa. The first electrode, which is electrically connected to the third layer, is provided from the top of the terrace to the inside of the groove, and is in contact with and electrically connected to the first layer in the n-type contact region. The mesa and the terrace include the first layer, the light absorbing layer, the second layer and the third layer, and the n-type contact region is the first layer. It is formed.

According to the above invention, it is possible to reduce the pitch between mesas and form electrodes.

FIG. 1A is a plan view illustrating the light receiving element according to the first embodiment. FIG. 1B is a cross-sectional view taken along the line AA of FIG. 1A. 2 (a) and 2 (b) are cross-sectional views illustrating a method for manufacturing a light receiving element. FIG. 3A is a plan view illustrating a method for manufacturing a light receiving element, and FIG. 3B is a cross-sectional view taken along line AA of FIG. 3A. 4 (a) to 4 (c) are cross-sectional views illustrating a method for manufacturing a light receiving element. FIG. 5A is a plan view illustrating a method for manufacturing a light receiving element, and FIG. 5B is a cross-sectional view taken along line AA of FIG. 5A. 6 (a) to 6 (c) are cross-sectional views illustrating a method for manufacturing a light receiving element. FIG. 7A is a cross-sectional view illustrating the light receiving element according to Comparative Example 1. FIG. 7B is a cross-sectional view illustrating the light receiving element according to Comparative Example 2. FIG. 7C is a cross-sectional view illustrating the light receiving element according to Comparative Example 3.

[Explanation of Embodiments of the Invention]
First, the contents of the embodiments of the present invention will be listed and described.

One embodiment of the present invention includes (1) a first conductive type first layer, a light absorption layer, a second conductive type second layer, and a second conductive type layer, which are sequentially laminated on a semiconductor substrate formed of a compound semiconductor. It has a step of growing a semiconductor layer including the second conductive type third layer, a first opening, and a second opening separated from the first opening and wider than the first opening. The first mask is used in the step of forming the first mask on the semiconductor layer and in the semiconductor layer so that etching proceeds more in the second opening than in the first opening. A third opening having a step of etching the semiconductor layer, a third opening overlapping the first opening, and a fourth opening overlapping the second opening and having a width larger than that of the second opening. An n-type contact composed of a first layer in the step of forming the two masks on the semiconductor layer and a mesa formed in a region of the semiconductor layer sandwiched between the third openings. The step of etching the semiconductor layer using the second mask and the first electrode electrically connected to the third layer are formed on the mesa so that a region is formed, and the n-type is formed. It comprises a step of forming a second electrode electrically connected to the first layer on the contact region, and the mesa is the first layer, the light absorbing layer, the second layer and the third layer. The region of the semiconductor layer including the layer, which is covered with the first mask and is exposed from the fourth opening of the second mask, is the n-type contact after etching with the second mask. This is a method for manufacturing a light receiving element that becomes a region. As a result, the second electrode and the first layer can be electrically connected through the n-type contact region. Further, since the second electrode does not have to be provided between the mesas, the pitch between the mesas can be reduced.
(2) In the step of forming the second mask, the second mask may be formed from the first mask by removing the portion of the first mask adjacent to the second opening. This simplifies the process.
(3) The step of forming the first mask includes the step of forming the first opening and the second opening in the first mask by etching using the first photoresist, and the second mask. The step of forming the fourth opening may include a step of forming the fourth opening by removing a portion of the first mask adjacent to the second opening by etching with a second photoresist. This simplifies the process. Further, the areas of the first resist mask and the second resist mask are reduced, and the generation of the altered layer is suppressed. Etching is less likely to be hindered by the altered layer, and the first resist mask and the second resist mask are effectively removed.
(4) In the step of etching using the second mask, the region overlapping the first opening and the third opening of the semiconductor layer is etched up to the first layer, and the third opening of the semiconductor layer is etched. A terrace including the first layer, the light absorption layer, the second layer and the third layer is formed in a region sandwiched between the portion and the fourth opening, and the second opening and the fourth opening are formed. A groove reaching the semiconductor substrate may be formed at a position overlapping the opening. By etching twice, a mesa and an n-type contact region can be formed, which simplifies the process.
(5) The n-type contact region may be located between the terrace and the groove. The distance between the second electrode and the light absorption layer can be reduced, and the dark current caused by lattice defects and impurities in the first layer can be reduced.
(6) The first mask has the first opening in a grid pattern, the second mask has the second opening in a grid pattern overlapping the first opening, and the second mask is attached. In the step of etching the semiconductor layer using the semiconductor layer, a plurality of mesas may be formed in a region of the semiconductor layer surrounded by the third opening.
(7) The width of the second opening may be 10 times or more the width of the first opening, and the width of the fourth opening may be 10 times or more the width of the third opening. As a result, etching with a microloading effect is performed.
(8) The first layer may be an n-type superlattice layer, and the second layer may be a p-type superlattice layer. The second electrode connected to the first layer has an n-type conductive type, and the first electrode connected to the first layer has a p-type conductive type.
(9) A step of forming an insulating film covering the upper surface and the side surface of the mesa and the terrace, respectively, and a fifth opening located on the mesa, the n-type contact region, and the groove in the insulating film. It has a step of forming a sixth opening located above, the first electrode is in contact with the third layer exposed from the fifth opening, and the second electrode is the sixth. It may come into contact with the first layer exposed from the opening. The insulating film insulates the second electrode from the light absorbing layer and the second layer. Further, the compound semiconductor layer can be protected by the insulating film.
(10) A semiconductor substrate formed of a compound semiconductor, a first conductive type first layer, a light absorption layer, a second conductive type second layer, and the second conductive type, which are sequentially laminated on the semiconductor substrate. A semiconductor layer including the conductive type third layer of the above, and having a mesa, a terrace, an n-type contact region and a groove formed from the central side to the outer peripheral side of the semiconductor substrate, and the third layer provided on the mesa. A first electrode electrically connected to the layer and a second electrode provided from above the terrace to the inside of the groove and in contact with and electrically connected to the first layer in the n-type contact region. The mesa and the terrace include the first layer, the light absorbing layer, the second layer and the third layer, and the n-type contact region is a light receiving light formed by the first layer. It is an element. As a result, the second electrode and the first layer can be electrically connected in the n-type contact region. Further, since the second electrode does not have to be provided between the mesas, the pitch between the mesas can be reduced.

[Details of Embodiments of the present invention]
Specific examples of the light receiving element and the method for manufacturing the light receiving element according to the embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

(First Embodiment)
FIG. 1A is a plan view illustrating the light receiving element 100 according to the first embodiment. FIG. 1B is a cross-sectional view taken along the line AA of FIG. 1A. Black dots in the figure indicate that a plurality of mesas 13 and the like are provided.

(Light receiving element 100)
As shown in FIG. 1A, the light receiving element 100 is a rectangular chip, and one side is, for example, 5 mm or more and 20 mm or less. As shown in FIG. 1B, the light receiving element 100 includes a semiconductor substrate 10 and a semiconductor layer 11. The semiconductor substrate 10 is formed of, for example, n-type gallium antimonide (GaSb) having a thickness of 300 μm or more and 700 μm or less. The semiconductor layer 11 includes an n-type semiconductor layer 12 (first layer), a light absorption layer 14, a p-type semiconductor layer 16 (second layer), and a p-type contact layer 18 (third layer) in order from the one closest to the semiconductor substrate 10. Layers) are laminated. A buffer layer made of, for example, GaSb may be provided between the n-type semiconductor layer 12 and the semiconductor substrate 10. An antireflection film 21 is provided on the lower surface of the semiconductor substrate 10 (the surface opposite to the semiconductor layer 11).

The n-type semiconductor layer 12 has, for example, an n-type GaSb / InAs superlattice structure in which a GaSb layer and an indium arsenide layer are laminated and doped with silicon (Si). The thickness is, for example, 1-5 μm and the doping concentration is, for example, 2 × 10 ¹⁸ cm ^-3 . The light absorption layer 14 has, for example, a non-doped GaSb / InAs superlattice structure, and has a thickness of, for example, 1 to 4 μm. The p-type semiconductor layer 16 has, for example, a p-type GaSb / InAs superlattice structure doped with beryllium (Be). The thickness is, for example, 0.2 to 0.8 μm, and the doping concentration is, for example, 2 × 10 ¹⁸ cm ^-3 . The superlattice structure has a type II band structure. The p-type contact layer 18 is formed of, for example, p-type GaSb, and has a thickness of, for example, 0.05 to 0.4 μm.

The n-type semiconductor layer 12, the p-type semiconductor layer 16, and the p-type contact layer 18 have a high transmittance (for example, 90% or more) with respect to infrared light, and transmit infrared light. The light absorption layer 14 receives infrared light having a wavelength of, for example, 3 to 15 μm. That is, when infrared light is incident on the semiconductor substrate 10 side, for example, it is photoelectrically converted in the light absorption layer 14 of the light receiving element 100, and the light absorption layer 14 generates photocarriers (electrons and holes). That is, the light receiving element 100 functions as a photodiode. A current due to the photocarrier flows through a reading circuit or the like connected to the light receiving element 100, and for example, image information is generated based on the current.

A mesa 13, terraces 15 and 19, and a groove 17 are formed from the central side to the outer peripheral side of the semiconductor substrate 10 of the light receiving element 100. The plurality of mesas 13 are provided in a two-dimensional array in the central portion of the light receiving element 100. The mesas 13, terraces 15 and 19 include an n-type semiconductor layer 12, a light absorption layer 14, a p-type semiconductor layer 16 and a p-type contact layer 18. Each mesa 13 functions as a photodiode. The groove 17 reaches the n-type semiconductor layer 12. The height of the mesa 13 is equal to the height of the terrace 15. The mesas 13 are separated by a groove reaching the n-type semiconductor layer 12, and are electrically connected by the n-type semiconductor layer 12. A terrace 15 is provided so as to surround the area where the mesa 13 is provided. A groove 17 surrounding the terrace 15 is provided on the outer peripheral side of the terrace 15, and the groove 17 is further surrounded by the terrace 19 on the outer peripheral side.

An n-type contact region 12a is provided between the terrace 15 and the groove 17, and an n-type contact region 12b is provided between the groove 17 and the terrace 19. As shown in FIG. 1A, the n-type contact region 12a surrounds the terrace 15, and the n-type contact region 12b surrounds the groove 17. As shown in FIG. 1 (b), the n-type contact regions 12a and 12b are plateau-like regions, which are formed of the n-type semiconductor layer 12 and come into contact with the electrode 24. The groove 17 is sandwiched between n-type contact regions 12a and 12b.

The pitch (distance between adjacent mesas 13) P1 of the mesas 13 shown in FIGS. 1 (a) and 1 (b) is, for example, 0.5 to 3 μm. The width W1 of the terrace 15 is, for example, 50 to 100 μm, the width W2 of the groove 17 is, for example, 20 to 290 μm, and the width W3 of the terrace 19 is, for example, 55 to 300 μm. The width W1 of the terrace 15 is larger than the width of the mesa 13, for example, twice or more the width of the mesa 13. The width W4 of the n-type contact region 12a shown in FIG. 1B is, for example, 3 to 30 μm, and the width W5 of the n-type contact region 12b is, for example, 0 to 30 μm. That is, the n-type contact region 12b does not have to be provided.

As shown in FIG. 1 (b), the surfaces (top and side surfaces) of the mesas 13, terraces 15 and 19 are covered with the insulating film 20. The insulating film 20 is formed of, for example, an insulator having a thickness of 100 to 400 nm, such as silicon oxide (SiO ₂ ) or silicon nitride (SiN). The insulating film 20 has an opening 20a (fifth opening) on the mesa 13 and an opening 20b (sixth opening) between the terraces 15 and 19. The p-type contact layer 18 is exposed from the opening 20a, and the n-type semiconductor layer 12 and the semiconductor substrate 10 are exposed from the opening 20b. The n-type contact regions 12a and 12b and the groove 17 are located inside the opening 20b.

The electrode 22 is provided on the mesa 13 and comes into contact with the p-type contact layer 18 exposed from the opening 20a. The electrodes 24 are provided from the top of the terrace 15 to the inside of the groove 17 and the top of the terrace 19, contact the n-type semiconductor layer 12 in the n-type contact regions 12a and 12b, and contact the semiconductor substrate 10 inside the groove 17. To do. The p-type semiconductor layer 16, the p-type contact layer 18, and the electrode 22 are electrically connected to each other. The p-type semiconductor layer 16 and the p-type contact layer 18 are p-type semiconductor layers, and the electrode 22 functions as a p-type electrode. The n-type semiconductor layer 12 and the electrode 24 are electrically connected in the n-type contact regions 12a and 12b. The n-type semiconductor layer 12 has a conductive type different from that of the p-type semiconductor layer 16 and the like, and is an n-type semiconductor layer. The electrode 24 functions as an n-type electrode and has a reference potential (for example, a ground potential). The electrodes 22 and 24 are made of, for example, titanium (Ti), platinum (Pt), and gold (Au) laminated in order from the bottom. Bumps formed of, for example, indium (In) may be provided on the electrodes 22 and 24. The bump is used for electrical connection between the light receiving element 100 and the readout circuit.

(Manufacturing method of light receiving element 100)
2 (a) and 2 (b), FIGS. 4 (a) to 4 (c), and 6 (a) to 6 (c) are cross-sectional views illustrating a method for manufacturing the light receiving element 100. FIG. 3A is a plan view illustrating a method for manufacturing the light receiving element 100, and FIG. 3B is a cross-sectional view taken along line AA of FIG. 3A. FIG. 5A is a plan view illustrating a method for manufacturing the light receiving element 100, and FIG. 5B is a cross-sectional view taken along line AA of FIG. 5A.

As shown in FIG. 2A, an n-type semiconductor layer 12, a light absorption layer 14, a p-type semiconductor layer 16 and a p-type contact layer 18 are epitaxially grown on a wafer-state semiconductor substrate 10 in this order. Prior to the growth of the n-type semiconductor layer 12, the buffer layer may be grown on the semiconductor substrate 10. For growth, for example, an organic metal vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method can be used. An insulator film mask layer 40 (first mask) formed of an insulator such as _{SiN or SiO 2} having a thickness of 0.5 to 2 μm is provided on the upper surface of the p-type contact layer 18. A resist mask 42 (first resist mask) is formed by applying a photoresist having a thickness of 1 to 3 μm on the insulator film mask layer 40 and performing resist patterning. The resist mask 42 is formed with openings 42a and 42b, and the insulator film mask layer 40 is exposed from the openings 42a and 42b.

As shown in FIG. 2B, the insulator film mask layer 40 is molded by, for example, dry etching using a fluorine-based gas. The insulator film mask layer 40 exposed from the openings 42a and 42b of the resist mask 42 is removed, an opening 40a (first opening) is formed on the center side of the insulator film mask layer 40, and the center on the outer peripheral side. An opening 40b (second opening) is formed so as to surround the portion. The p-type contact layer 18 is exposed from the openings 40a and 40b.

As shown in FIG. 3A, the opening 40b is separated from the opening 40a. The opening 40a is, for example, a grid, and the opening 40b is a ring-shaped opening surrounding the opening 40a. As shown in FIGS. 3A and 3B, after removing the resist mask 42, dry etching using, for example, a halogen-based gas is performed. The shaded area in FIG. 3A is the portion to be etched. The portion of the semiconductor layer 11 exposed from the openings 40a or 40b is etched to form grooves 41 and 43. The width W6 of the opening 40a and the groove 41 is, for example, equal to the pitch P1 shown in FIGS. 1A and 1B, and is 0.5 to 3 μm. The width W7 of the opening 40b and the groove 43 is equal to, for example, the width W2 of the groove 17 shown in FIGS. 1 (a) and 1 (b), and is, for example, 20 to 290 μm. At this time, the etching proceeds more greatly in the opening 40b having a wider width than in the opening 40a having a smaller width (microloading effect). The etching time is determined according to the width of the opening, the material of the semiconductor layer 11, the desired etching depth, and the like.

As shown in FIG. 4A, a photoresist is applied on the insulator film mask layer 40 and resist patterning is performed to form a resist mask 44 (second resist mask). The resist mask 44 covers the groove 41 of the semiconductor layer 11 and has an opening 44a. The opening 44a of the resist mask 44 is larger than the groove 43 of the semiconductor layer 11 and the opening 40b of the insulator film mask layer 40, and the groove 43 and the opening 40b are located inside the opening 44a. In the insulator film mask layer 40, the regions 40c and 40d adjacent to the opening 40a are exposed from the opening 44a. The region 40c is located between the groove 43 and the groove 41, and the region 40d is located on the outer peripheral side of the groove 43. The width of the region 40c is, for example, 10 to 50 μm, and the width of the region 40d is, for example, 0 to 50 μm. That is, the region 40d may not be present.

As shown in FIG. 4B, the resist mask 44 is used as a mask, and the regions 40c and 40d of the insulator film mask layer 40 are removed by wet etching using, for example, hydrofluoric acid. As a result, the insulator film mask layer 40 (second mask) is formed with an opening 40e (fourth opening) larger than the opening 40b at a position overlapping the opening 40b. The opening 40a remains (third opening). As shown in FIG. 4C, the resist mask 44 is removed and the insulator film mask layer 40 remains.

As shown in FIGS. 5A and 5B, the semiconductor layer 11 is dry-etched using the insulator film mask layer 40 and, for example, a halogen-based gas. The shaded area of FIG. 5A is the portion to be etched. The etching time is determined according to the width of the opening, the material of the semiconductor layer 11, the desired etching depth, and the like. Due to the microloading effect, etching proceeds more greatly in the opening 40e than in the opening 40a of the insulator film mask layer 40. In the opening 40a, the groove 41 shown in FIG. 3B is further etched to form a groove reaching the n-type semiconductor layer 12. In the opening 40e, the groove 43 is further etched to form a groove 17 that reaches the semiconductor substrate 10. A mesa 13 is formed in a region of the semiconductor layer 11 surrounded by a grid-like opening 40a, and a terrace 15 is formed in a region sandwiched between the opening 40a and the opening 40e. That is, as shown in FIG. 5A, a plurality of mesas 13 arranged in a two-dimensional array are formed, and a ring-shaped groove 17 and a terrace 15 are formed on the outside thereof. The portions of both sides of the groove 17 of the semiconductor layer 11 are etched up to the n-type semiconductor layer 12, and the n-type contact regions 12a and 12b are formed. A terrace 19 is formed on the outer peripheral side of the opening 40e.

As shown in FIG. 6A, after removing the insulating film mask layer 40, the insulating film 20 is formed by, for example, a chemical vapor deposition (CVD) method. The insulating film 20 covers the surfaces of the mesas 13, the terraces 15 and 19, and the bottom surface of the groove 17. As shown in FIG. 6B, the insulating film 20 is etched to form the openings 20a and 20b by, for example, dry etching using a fluorine-based gas or wet etching using buffered hydrofluoric acid. The grooves 17, the n-shaped contact regions 12a and 12b are located inside the opening 20b.

As shown in FIG. 6 (c), the electrodes 22 and 24 are provided, for example, by a vapor deposition method and a lift-off method. The electrode 22 comes into contact with the p-type contact layer 18 exposed from the opening 20a. The electrode 24 is provided from the top of the terrace 15 to the surface of the n-type contact region 12a, the inside of the groove 17, and further over the n-type contact region 12b. The electrode 24 contacts the n-type semiconductor layer 12 in the n-type contact regions 12a and 12b, and contacts the semiconductor substrate 10 in the groove 17. An antireflection film 21 is formed on the lower surface of the semiconductor substrate 10, and the light receiving element 100 is formed by dicing the wafer. In addition, for example, bumps may be provided on the electrodes 22 and 24.

(Comparative Example 1)
FIG. 7A is a cross-sectional view illustrating the light receiving element 100R according to Comparative Example 1. The description of the same configuration as that of the first embodiment will be omitted. The pitch P2 between the mesas 13 shown in FIG. 7 (a) is larger than the pitch P1 shown in FIG. 1 (b). Therefore, the electrode 24 can be provided between the mesas 13. However, since the pitch P2 is large, the number of mesas 13 that can be formed on the light receiving element 100R is smaller than that of the light receiving element 100, and the number of pixels when used as an infrared sensor is small, for example. In order to increase the number of pixels, a large number of mesas 13 may be provided, but the light receiving element 100R becomes large.

(Comparative Example 2)
FIG. 7B is a cross-sectional view illustrating the light receiving element 200R according to Comparative Example 2. The description of the same configuration as that of the first embodiment will be omitted. The pitch between the mesas 13 is P1 which is smaller than P2 of Comparative Example 1. Therefore, many mesas 13 can be provided, but it is difficult to provide electrodes 24 between the mesas 13. Therefore, the electrode 24 may be provided in the groove 17a located on the outer peripheral side of the semiconductor substrate 10 with respect to the mesa 13.

In Comparative Example 2, the mesa 13, the terraces 15 and 19, and the groove 17a are formed by a single etching. That is, the groove 17a is formed at the same time as the groove between the mesas 13. However, due to the microloading effect, the progress of etching becomes higher in the region between the terraces 15 to 19 having a wider width than between the mesas 13 having a smaller width, and the etching does not stop at the n-type semiconductor layer 12. As a result, as shown by the broken line in FIG. 7B, the groove 17b reaching to the semiconductor substrate 10 is formed. In this case, it is difficult to electrically connect the n-type semiconductor layer 12 and the electrode 24. By thickening the n-type semiconductor layer 12, a groove 17a having the n-type semiconductor layer 12 on the bottom surface can be formed. However, crystal defects of the n-type semiconductor layer 12 may occur and the dark current may increase.

(Comparative Example 3)
FIG. 7C is a cross-sectional view illustrating the method for manufacturing the light receiving element according to Comparative Example 3. As shown in FIG. 7C, a resist mask 42 is used to mold the insulator film mask layer 40. The resist mask 42 in Comparative Example 3 has an opening 42a, but does not have an opening 42b. The insulator film mask layer 40 is formed by etching using the resist mask 42, and the mesa 13 is formed by etching using the insulator film mask layer 40. After that, a terrace, a groove, and the like are formed by etching with a mask covering the mesa 13. However, since the area of the resist mask 42 is large, an altered layer may be generated from the resist mask 42 during etching. The altered layer inhibits etching and makes it difficult to remove the resist mask after etching.

On the other hand, according to the present embodiment, the semiconductor layer 11 is further etched by using the insulator film mask layer 40 having the openings 40a and 40b as shown in FIGS. 3A and 3B. As shown in FIGS. 5A and 5B, the semiconductor layer 11 is etched using a mask having openings 40a and 40e. The opening 40a is separated from the openings 40b and 40e. Further, the widths of the openings 40b and 40e are larger than those of the openings 40a. Therefore, the etching proceeds more in the openings 40b and 40e than in the openings 40a. As a result, mesas 13, terraces 15 and 19 are formed, and grooves 17, n-type contact regions 12a and 12b are formed in the opening 40e. As shown in FIG. 6C, the electrodes 24 are formed on the n-type contact regions 12a and 12b and come into contact with the n-type semiconductor layer 12.

That is, by performing etching twice, n-type contact regions 12a and 12b are formed on the outer peripheral side of the light receiving element 100 with respect to the mesa 13, and the electrodes 24 and the n-type semiconductor layer 12 are formed in the n-type contact regions 12a and 12b. Can be electrically connected. Since the electrode 24 is located near the light absorption layer 14, the dark current can be reduced. Since it is not necessary to provide electrodes between the mesas 13, the pitch P1 between the mesas 13 can be reduced as shown in FIGS. 1 (a) and 1 (b). By forming a large number of mesas 13, it is possible to increase the number of pixels of the light receiving element 100.

Of the semiconductor layer 11, the region covered by the insulator film mask layer 40 during the first etching and exposed from the opening 40e during the second etching is the n-type contact region 12a after the second etching. And 12b. By adjusting the etching range in this way, the n-type contact regions 12a and 12b can be formed, so that the process is simplified. Further, the process is simplified because the mesas 13, the grooves 17, the terraces 15 and 19, and the n-type contact regions 12a and 12b are formed by the two etchings.

As shown in FIGS. 4A and 4B, the opening 40e is formed by removing the portion of the insulator film mask layer 40 adjacent to the opening 40b. In other words, the opening 40e is formed by enlarging the opening 40b. This simplifies the process. For example, the insulator film mask layer 40 may be removed after the first etching, another mask having a wide opening including the groove 43 may be provided, and the second etching may be performed using the mask.

As shown in FIG. 2A, the resist mask 42 for molding the insulator film mask layer 40 has an opening 42b, and as shown in FIG. 4A, the resist mask 44 has an opening 44a. By etching the insulator film mask layer 40 with such resist masks 42 and 44, openings 40a, 40b and 40e are formed in the insulator film mask layer 40. Therefore, the process is simplified. Also, the resist masks 42 and 44 have wide openings 42b and 44a. Therefore, the areas of the resist masks 42 and 44 are smaller than those of Comparative Example 3, and the generation of the altered layer is suppressed. As a result, etching inhibition by the altered layer is unlikely to occur, and the resist masks 42 and 44 are effectively removed.

As shown in FIG. 1 (b), the n-type contact region 12a is located between the terrace 15 and the groove 17. As a result, the distance between the electrode 24 and the light absorption layer 14 can be reduced. That is, the volume of the n-type semiconductor layer 12 interposed between the light absorption layer 14 and the electrode 24 becomes smaller. Therefore, for example, dark current caused by lattice defects and impurities in the n-type semiconductor layer 12 can be reduced.

As shown in FIGS. 3A and 5A, the openings 40a of the insulator film mask layer 40 are in a grid pattern. As shown in FIG. 5B, the mesa 13 is formed in the portion surrounded by the opening 40a by etching. The plurality of mesas 13 are arranged in a two-dimensional array. By reducing the width W6 of the opening 40a, the pitch P1 between the mesas 13 can be reduced. By forming a large number of mesas 13, it is possible to increase the number of pixels of the light receiving element 100. The opening 40a is not in a grid pattern, and may be, for example, a plurality of grooves. A mesa 13 is formed in a region of the semiconductor layer 11 sandwiched between the openings 40a.

The width W7 of the opening 40b shown in FIGS. 3A and 3B is, for example, 10 times or more the width W6 of the opening 40a. The width of the opening 40e shown in FIGS. 5A and 5B is, for example, 10 times or more the width of the opening 40a. As a result, etching with a microloading effect is performed. That is, the progress of etching is higher in the openings 40b and 40e than in the openings 40a. As a result, the grooves 17, the n-type contact regions 12a and 12b can be formed.

The insulating film 20 covers the upper surface and the side surface of the mesa 13 and the terrace 15, respectively. As a result, the semiconductor layer 11 can be protected from foreign matter, moisture and the like. Further, since the insulating film 20 is interposed between the light absorption layer 14, the p-type semiconductor layer 16, the p-type contact layer 18, and the electrode 24, they are insulated. Since the etching is performed from above, it is difficult to remove only a part of the insulating film 20 covering the side surfaces of the terraces 15 and 19 to expose the side surfaces of the n-type semiconductor layer 12. Therefore, as shown in FIG. 6B, it is preferable to provide flat n-type contact regions 12a and 12b and remove the insulating film 20 on the flat n-type contact regions 12a and 12b to form the opening 20b. The electrode 22 and the p-type contact layer 18 come into contact with each other at the opening 20a of the insulating film 20, and the electrode 24 and the n-type semiconductor layer 12 come into contact with each other at the opening 20b. As a result, the electrode 22 functions as a p-type electrode and the electrode 24 functions as an n-type electrode.

The electrode 24 is provided from above the terrace 15 to the n-type contact region 12a, the groove 17, and the n-type contact region 12b, and covers the surfaces thereof. Therefore, the bonding strength of the electrode 24 is improved, and peeling and disconnection are suppressed. Since the electrode 24 comes into contact with the upper surfaces and side surfaces of the n-type contact regions 12a and 12b, the contact resistance is reduced. Since the electrode 24 and the n-type semiconductor layer 12 can be connected in the n-type contact region 12a, the n-type contact region 12b does not have to be provided.

The n-type semiconductor layer 12, the light absorption layer 14, and the p-type semiconductor layer 16 each have a superlattice structure including different semiconductor layers. For example, the n-type semiconductor layer 12 is a GaSb / InAs n-type superlattice layer, and the p-type semiconductor layer 16 is a GaSb / InAs p-type superlattice layer. Dark currents may be generated due to lattice defects and impurities in these layers. By providing the electrodes 22 on the mesa 13 and the electrodes 24 on the n-type contact regions 12a and 12b, the distance between the electrodes 22 and 24 and the light absorption layer 14 is reduced. As a result, the dark current can be suppressed. The material of each layer may be changed. For example, the light absorption layer 14 may be a GaSb / InAsSb superlattice layer. Further, the semiconductor layer 11 having a superlattice structure is lattice-matched with the semiconductor substrate 10 of GaSb. The semiconductor substrate 10 may be formed of another compound semiconductor.

The n-type semiconductor layer 12 and the p-type semiconductor layer 16 may have different conductive types, and one of the layers is n-type and the other is p-type. The n-type semiconductor layer 12, the light absorption layer 14, and the p-type semiconductor layer 16 may be formed of other semiconductors such as compound semiconductors other than the GaSb / InAs superlattice structure. The light absorption layer 14 absorbs light having a wavelength different from that in the infrared light band, and the n-type semiconductor layer 12 and the p-type semiconductor layer 16 have high transmittance (for example, 90% or more) with respect to light of the wavelength. You may. Although the semiconductor substrate 10 is said to be formed of GaSb, it may be formed of another compound semiconductor.

10 Semiconductor substrate 11 Semiconductor layer 12 n-type semiconductor layer 12a, 12b n-type contact area 13 Mesa 14 Light absorption layer 15, 19 Terrace 16 p-type semiconductor layer 17, 17a, 17b, 41, 43 Groove 18 p-type contact layer 20 Insulation Films 20a, 20b, 40a, 40b, 40e, 44a Openings 22, 24 Electrodes 40 Insulator film mask layer 40c, 40d Region 42, 44 Resist mask 100 Light receiving element

Claims (10)

A first conductive type first layer, a light absorption layer, a second conductive type second layer, and the second conductive type third layer, which are sequentially laminated on a semiconductor substrate formed of a compound semiconductor. And the process of growing the semiconductor layer including
A step of forming a first mask having a first opening and a second opening separated from the first opening and having a width larger than that of the first opening on the semiconductor layer.
A step of etching the semiconductor layer using the first mask so that etching proceeds more in the second opening than in the first opening of the semiconductor layer.
A second mask having a third opening that overlaps the first opening and a fourth opening that overlaps the second opening and is wider than the second opening is placed on the semiconductor layer. The process of forming and
The second mask is used so that a mesa is formed in the region of the semiconductor layer sandwiched between the third openings and an n-type contact region composed of the first layer is formed in the fourth opening. The step of etching the semiconductor layer and
A step of forming a first electrode electrically connected to the third layer on the mesa and forming a second electrode electrically connected to the first layer on the n-type contact region. Have,
The mesa includes the first layer, the light absorption layer, the second layer and the third layer.
Of the semiconductor layer, the region covered by the first mask and exposed from the fourth opening of the second mask becomes the n-type contact region after etching with the second mask. Method of manufacturing the element. The light receiving element according to claim 1, wherein in the step of forming the second mask, a portion of the first mask adjacent to the second opening is removed to form the second mask from the first mask. Manufacturing method. The step of forming the first mask includes a step of forming the first opening and the second opening in the first mask by etching with the first photoresist.
The step of forming the second mask includes a step of forming the fourth opening by removing a portion of the first mask adjacent to the second opening by etching with a second photoresist. The method for manufacturing a light receiving element according to claim 1 or 2. In the step of etching using the second mask, the region overlapping the first opening and the third opening of the semiconductor layer is etched up to the first layer, and the third opening of the semiconductor layer and the third opening are described. A terrace including the first layer, the light absorbing layer, the second layer and the third layer is formed in the region sandwiched between the fourth opening and the second opening and the fourth opening. The method for manufacturing a light receiving element according to any one of claims 1 to 3, wherein a groove reaching the semiconductor substrate is formed at an overlapping position. The method for manufacturing a light receiving element according to claim 4, wherein the n-type contact region is located between the terrace and the groove. The first mask has the first opening in a grid pattern.
The second mask has the third opening in a grid pattern that overlaps with the first opening.
According to any one of claims 1 to 5, in the step of etching the semiconductor layer using the second mask, a plurality of mesas are formed in a region of the semiconductor layer surrounded by the third opening. The method for manufacturing a light receiving element according to the description. The width of the second opening is 10 times or more the width of the first opening.
The method for manufacturing a light receiving element according to any one of claims 1 to 6, wherein the width of the fourth opening is 10 times or more the width of the third opening and is larger than the width of the second opening. The first layer is an n-type superlattice layer.
The method for manufacturing a light receiving element according to any one of claims 1 to 7, wherein the second layer is a p-type superlattice layer. A step of forming an insulating film covering the upper surface and the side surface of the mesa and the terrace, respectively.
The insulating film has a step of forming a fifth opening located above the mesa, the n-type contact region, and a sixth opening located above the groove.
The first electrode comes into contact with the third layer exposed from the fifth opening, and is brought into contact with the third layer.
The method for manufacturing a light receiving element according to claim 4 , wherein the second electrode comes into contact with the first layer exposed from the sixth opening. A semiconductor substrate made of a compound semiconductor and
The semiconductor substrate includes a first conductive type first layer, a light absorption layer, a second conductive type second layer, and the second conductive type third layer which are sequentially laminated on the semiconductor substrate. A semiconductor layer in which mesas, terraces, n-type contact regions and grooves are formed in this order from the central side to the outer peripheral side of the semiconductor layer.
A first electrode provided on the mesa and electrically connected to the third layer,
A second electrode that is continuously provided on the terrace, inside the n-type contact region, and inside the groove, is in contact with the first layer in the n-type contact region, and is electrically connected to the first layer. Equipped with
The n-type contact region is located between the terrace and the groove.
The mesa and the terrace include the first layer, the light absorption layer, the second layer and the third layer.
The n-type contact region is a light receiving element formed of the first layer.

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