JP6890964B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that simplifies the circuit configuration of a power supply board.

A ball game machine such as a pachinko machine is equipped with a symbol start port provided on the game board, a symbol display unit for displaying a series of symbol variation modes by a plurality of display symbols, and a large winning opening for opening and closing the opening / closing plate. It is composed of. Then, when the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is set, and after the game ball is paid out as the prize ball, the displayed symbol is changed for a predetermined time on the symbol display unit. After that, when the symbol is stopped in a predetermined mode such as 7, 7, 7, a big hit state is reached, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate a jackpot game state is determined by a jackpot lottery executed on the condition that a game ball wins a prize at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become. For example, when the lottery result is in the winning state, an effect operation called a reach action or the like is executed for about 20 seconds, and then special symbols are arranged.

By the way, this type of game machine is generally configured by being divided into a plurality of circuit boards, and typically, a main control board that executes a big hit lottery to control the game operation in an integrated manner. , A payout control board that pays out game balls, one or more effect control boards that control lamp effect, voice effect, accessory effect, image effect, etc., and a power supply board that distributes the DC voltage required for each control board. And (Patent Documents 1 to 3).

Further, in these gaming machines, a backup power supply is provided on the main control board and the payout control board, and a power failure detection circuit is provided on the power supply board to quickly and appropriately detect the power cutoff state and maintain the game state in the event of a power failure. Therefore, the player is not disadvantaged. Then, on the premise of such a circuit configuration, the applicant has proposed a power supply board that prevents the occurrence of malfunction as much as possible (Patent Document 4).

Japanese Unexamined Patent Publication No. 2015-196037 Japanese Unexamined Patent Publication No. 2015-1906036 Japanese Unexamined Patent Publication No. 2015-131095 Japanese Unexamined Patent Publication No. 2015-205117

By the way, this type of gaming machine generally has a short product life, and it is necessary to develop new models with different playability one after another. Moreover, when changing models, it is necessary to have an examination by a public institution including the power supply board. There is a problem that the burden is not small. Therefore, it is conceivable to reduce the inspection burden by limiting the power supply board to the minimum functions and standardizing it.

However, if the power supply board is simplified and the backup power supply is arranged on another circuit board, there is a possibility that the backup power supply connection abnormality or the like is left unattended.

That is, in a circuit configuration in which the backup power supply is arranged together with the power supply board (see Patent Document 4), the backup power supply is distributed along with other DC voltages via the same connector in the same path. , It turns out immediately that the control circuit board does not work.

However, when the power supply board and the backup power supply board are separated from each other, even if there is a connection error with the backup power supply board, as long as another DC voltage is normally supplied to the control circuit board. Since there is no hindrance to the control operation, the abnormal connection state is left unattended, and the interests of the player are not protected in the event of an important power failure.

The present invention has been made in view of the above problems, and provides a gaming machine in which an abnormal state is not left unattended even if a backup power supply is arranged on a circuit board different from other power supply circuits. The purpose.

In order to solve the above problems, the present invention is a gaming machine capable of executing a lottery process based on a predetermined switch signal and executing a game operation according to the lottery result, and executing the lottery process. A second control means that centrally controls the game operation and a second control means that executes the prize ball control operation based on a serial prize ball instruction accompanied by a start bit and a stop bit, which is serially transmitted from the first control means . and a control unit, the DC voltage generated by rectifying the AC voltage of the AC power source to be distributed to the gaming machine is configured to have a DC generating means for distribution to the first control means and said second control means The first control means is configured to have a transmission port for serially transmitting the serial prize ball instruction accompanied by the start bit and the stop bit at a predetermined baud rate [bps]. The computer circuit includes a computer circuit that receives the serial prize ball instruction via the receiving port and executes the prize ball control operation, and the computer circuit is a volatile memory of the computer circuit even after the AC power supply is cut off. The backup power supply board equipped with the backup power supply that maintains the stored contents of the above is configured not to shift to the subsequent processing unless a normal judgment is made after the power is turned on, and the speed is an integral multiple of the baud rate [bps]. When the start bit, the stop bit, and the serial prize ball instruction are level-determined a plurality of times for each bit based on the determination clock that changes with, and it is not determined that all of them are at the same level. Is configured to handle errors .

As described above, according to the present invention, the power supply board is simplified and no problem occurs, such as arranging the backup power supply on a circuit board different from other power supply circuits.

It is a perspective view which shows the pachinko machine of this Example. It is a schematic front view of the game board of this embodiment. It is a block diagram which shows the whole circuit structure of this Example. It is a circuit block diagram which shows the main part of the main control board and the payout control board. The internal configuration of the payout control board including the power failure detection circuit and the power supply reset circuit is illustrated. The interface circuit with the ball lender in the payout control board is illustrated. The launch control circuit of the payout control board is illustrated. It is a flowchart explaining the control operation of a main control part. It is a drawing explaining the prize ball command of a main control part. It is a time chart explaining the transmission / reception operation of a prize ball command. It is a flowchart explaining the control operation of a payout control unit.

Hereinafter, the present invention will be described in detail based on Examples. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably attached to the island structure, and a front frame 3 that is pivotally attached to the island structure via a hinge 2 fixed to the wooden outer frame 1. It is composed of.

A game board 5 is detachably attached to the front frame 3 from the front side using a one-touch connector, not from the back side, and a glass door 6 and a front plate 7 are freely openable and closable on the front side thereof. It is worn. Here, the one-touch connector means connection connectors C1 to C3 (see FIG. 3) in which a plurality of contacts are connected by one mounting operation and a plurality of contacts are separated by one separation operation.

Illumination lamps such as LED lamps are arranged in a substantially C shape on the outer periphery of the glass door 6. On the other hand, a speaker is arranged under the glass door 6.

An upper plate 8 for storing a game ball for launch is mounted on the front plate 7, and a lower plate 9 for storing a game ball overflowing or extracted from the upper plate 8 and a launch handle are below the front frame 3. 10 is provided. The launch handle 10 launches a game ball with a striking mallet that operates with a strength corresponding to the rotation angle thereof.

Here, the striking mallet is driven by the firing solenoid SLe, and the ball feed solenoid SLf is functioning in preparation for launching until the striking mallet functions. Further, as shown in FIG. 3, the firing handle 10 includes a strength volume VR whose firing intensity of the firing solenoid SLe can be adjusted, a touch sensor TCH which detects whether or not the player is touching the firing handle 10, and a touch sensor TCH. A launch stop switch STOP, in which the player instructs the launch stop, is arranged.

Then, the launch intensity signal VR indicating the rotation position of the launch handle 10, the touch sensor signal TCH of the touch sensor TCH, and the stop switch signal STOP, which are the outputs of the intensity volume VR, are transmitted to the launch control circuit 30 of the payout control board. It is configured to be transmitted (see FIGS. 3 and 4).

On the other hand, a chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and the operation is possible. The button chance state is a game state provided as needed.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation for a card-type ball lending machine is provided, and a frequency display unit NUM (FIG. 4) for displaying the remaining amount of the card as a three-digit number and a predetermined amount of money are displayed. A ball lending switch for instructing the ball lending of the game ball and a return switch for instructing the return of the card at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 composed of an outer rail and an inner rail made of metal is provided in an annular shape, and a central opening HO extending to the back side is provided substantially in the center thereof. Has been done. A display device DS composed of a liquid crystal color display is arranged at the bottom of the central opening HO.

Further, in the space formed in front of the display device DS, an effect movable body AMU (movable accessory) is arranged so as to be able to move up and down. The effect movable body AMU is composed of a fixed member FIX that is held by the elevating mechanism ALV and raised and lowered, and a rotating member ROT that is supported by the fixed member FIX and rotates.

The elevating operation of the elevating mechanism ALV and the rotating operation of the rotating member ROT are realized by the rotation of the effect motors M1 to Mn composed of the stepping motor. At normal times, the effect movable body AMU stands by in a state of being suspended by the elevating mechanism ALV.

A symbol start opening 15, a large winning opening 16, a normal winning opening 17, and a gate 18 are arranged at appropriate positions in the game area. Each of these winning openings 15 to 18 has a detection switch inside, so that the passage of a game ball can be detected.

The display device DS is a device that displays a specific symbol related to the jackpot state in a variable manner and displays a background image, various characters, and the like in an animation manner. This display device DS has special symbol display units Da to Dc in the central portion and a normal symbol display unit 19 in the upper right portion. Then, in the special symbol display units Da to Dc, a reach effect for expecting a big hit state is executed, and in the special symbol display units Da to Dc and its surroundings, a notice effect for uncertainly notifying the result of success or failure is executed. Will be done.

The normal symbol display unit 19 displays a normal symbol, and when a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates by a predetermined time, and a lottery is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the random value is displayed and stopped.

The symbol start port 15 is configured to be opened and closed by an electric tulip provided with a pair of left and right opening / closing claws, and when the stop symbol after the change of the normal symbol display unit 19 hits and displays the symbol, the opening / closing claw is specified. It is open only for a period of time or until a predetermined number of game balls are detected.

In the electric tulip, the second solenoid SL2 is energized and opened via the switch circuit PS by the power transistor at the timing when the control signal CLT2 reaches the L level (see FIG. 4). In addition, unlike the configuration of FIG. 2, when the normal winning opening 17 is configured to be openable and closable, the normal winning opening is opened and closed by the third solenoid SL3 whose energization is controlled by the control signal CTL3.

When the game ball wins the symbol start opening 15, the displayed symbols of the special symbol display units Da to Dc fluctuate by a predetermined time, and are determined based on the lottery result according to the winning timing of the game ball to the symbol start opening 15. Stop at the stop symbol. In addition, in the special symbol display units Da to Dc and their surroundings, a notice effect may be executed during a series of symbol effects. Further, as a kind of advance notice effect, the effect movable body AMU may descend to the position of the central opening HO. Then, the lowered effect movable body AMU rotates clockwise or counterclockwise, and then rises to the original position.

The jackpot 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display units Da to Dc is a jackpot symbol such as "777", the "big hit game" A special game called "" has been started, and the opening / closing plate 16a is opened. The opening / closing plate 16a is opened when the first solenoid SL1 is energized at the timing when the control signal CTL1 reaches the L level (see FIG. 4).

After a predetermined time elapses after the opening / closing plate 16a of the large winning opening 16 is opened, or when a predetermined number (for example, 10) of game balls win a prize, the opening / closing plate 16a closes. In such an operation, the special game is continued up to, for example, 15 times, and is controlled in a state advantageous to the player. If the stop symbol after the change of the special symbol display units Da to Dc is a specific symbol among the special symbols, the privilege that the game after the end of the special game is in a high probability state is given.

FIG. 3 is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the above operations, and shows a game machine that is connected to the hall computer HC and the ball lending machine LEN and operates by receiving AC24V. There is. Various game information INFs and abnormality information are transmitted to the hall computer HC, and various information is transmitted and received between the ball lending machine LEN and the game machine GM during the ball lending operation.

As shown in the figure, this game machine GM has a power supply board 20 that receives AC24V and outputs three types of DC voltages (5V, 12V, 35V), a main control board 21 that centrally handles game control operations, and a main control board 21. An effect control board 22 that executes lamp effect and voice effect based on the control command CMD received from the control board 21, and an image control board that drives the display device DS based on the control command CMD'received from the effect control board 22. It is mainly composed of the 23 and the payout control board 24 that controls the payout motor Mo to pay out the game ball based on the control command SYO received from the main control board 21.

The control command CMD output from the main control board 21 is first transmitted to the effect control board 22, and the control command CMD'output from the effect control board 22 is the image interface board 37 together with the 1-bit length strobe signal STB. Is transmitted to the image control board 23 via the above. On the other hand, the control command SYO for the prize ball output from the main control board 21 is transmitted to the payout control board 24 via the main board relay board 34.

The control command CMD and the control command CMD'are 16-bit length parallel data, and are transmitted in parallel from the main control board 21 to the image control board 23 in two steps every 8 bits. Therefore, the command transmission line from the main control board 21 to the image control board 23 has a total length of 9 bits including the strobe signal STB.

On the other hand, the control command CMD'transmitted from the effect control board 22 to the image control board 23 is collectively transmitted in parallel with a 16-bit length. Therefore, the command transmission line from the effect control board 22 to the image control board 23 has a total length of 17 bits including the strobe signal STB', but even if a large number of control commands are continuously transmitted and received, the processing can be performed quickly. There is an advantage that can be finished.

In this embodiment, the control command (prize ball command) SYO transmitted from the main control board 21 to the payout control board 24 is composed of parallel data having an 8-bit length. The prize ball command SYO has a total of 10 bits by adding the start bit START and the stop bit STOP before and after, and is serially transmitted in an asynchronous method without transmitting the transmission clock (see FIG. 10A).

Computer circuits including one-chip microcomputers MCOM1 to MCOM4 are mounted on the main control board 21, the effect control board 22, the image control board 23, and the payout control board 24, respectively. Therefore, in this specification, the main control unit 21, the effect control unit 22, and the image are collectively referred to functionally as a general term for the circuits mounted on the control boards 21 to 24 and the interface board 37, and the operations realized by the circuits. It may be referred to as a control unit 23 and a payout control unit 24. That is, in this embodiment, the image control board 23 and the image interface board 37 constitute the image control unit 23. All or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 are sub control units.

By the way, in this embodiment, the circuit configuration of the power supply board 20 is simplified to realize the componentization of the power supply board that does not require public inspection. Specifically, the power supply board 20 receives a rectifier circuit that rectifies AC24V, a power factor improvement circuit that receives the output of the rectifier circuit, and three types of DC voltages (35V, 12V, 5V) that receive the output of the power factor improvement circuit. ) Is composed of a step-down DC / DC converter, and the power reset signal RST indicating power on / off and the power failure signal ABN are not output.

In this embodiment, the power supply reset signal RST is generated by each of the payout control board 24, the main control board 21, and the effect control board 22 based on the DC voltage distributed (RST1 to RST3), and the power supply is cut off. The signal ABN is generated on the payout control board 24 based on the AC voltage AC24V distributed on the payout control board 24, and is transmitted to the one-chip microcomputer MCOM4 of the main control board 21 and the one-chip microcomputer MCOM1 of the main control board 21.

As described above, in the embodiment, since the power supply reset signal RST and the power failure signal ABN that affect the game control operation are not output from the power supply board 20, there is virtually no risk of misuse or modification of the power supply board 20, and it is publicly available. Confirmation inspection at a target institution is not required.

Corresponding to this configuration, the payout control board 24 of this embodiment is provided with a power supply-related circuit 29 that receives a DC voltage (12V, 5V) from the power supply board 20, and the power supply-related circuit 29 has a power supply reset signal. RST1 and power failure signal ABN are generated.

Further, the backup power supply board 27 in which the electric double layer capacitor Cbk is arranged is provided separately from the power supply board 20 and the payout control board 24, and the payout control board 24 receives the DC voltage VBB (5V) received from the power supply board 20. , The backup power supply board 27 is supplied with power through the power supply line VBB to charge the electric double layer capacitor Cbc (see FIG. 4). After the power is cut off, the charging voltage VBB of the electric double layer capacitor Cbk functions as the backup power supply VBB of the one-chip microcomputers MCOM4 and MCOM1 mounted on the payout control board 24 and the main control board 21, and each one-chip microcomputer has a charge voltage VBB. The stored contents of the built-in RAM are surely maintained.

As shown in FIG. 4, 5 V is supplied from the payout control board 24 to the backup power supply board 27 via the backflow prevention diode D1. Further, the payout control board 24 is formed with an inspection line LN that reaches the ground of the backup power supply board 27 via the light emitting diode D2 and the current limiting resistor r, and the payout control board 24 and the backup power supply board 27 are normal. When connected to, the light emitting diode D2 is configured to light up.

Since the above circuit configuration is adopted, the potential of the inspection line LN is at the ground level when the payout control board 24 and the backup power supply board 27 are normally connected, while it is at the 5V level when not connected. Therefore, in this embodiment, the potential of the inspection line LN is determined when the power is turned on to confirm the normal connection state with the backup power supply board 27, and if the normal connection state cannot be confirmed, the game operation is started. I try not to. Since the light emitting diode D2 is in the extinguished state when the game operation is not started, the clerk can immediately grasp the content of the abnormality.

Since it has the above configuration, in this embodiment, there is no possibility that the connection abnormality between the payout control board 24 and the backup power supply board 27 is overlooked, and the game state may not be stored and saved in the event of a power failure, and the interests of the player may not be protected. Absent. That is, in this embodiment, the adverse effect of having the backup power supply board 27 as a separate board configuration has been eliminated.

The capacitance C of the electric double layer capacitor Cbk used as a backup power source is appropriately about 0.3F to 1F, and is 0.45F in this embodiment. Therefore, even if the battery is charged with a constant current charging current of 0.5 A, it takes t = C * V / I = 0.45 * 5 / 0.5 = 4.5 seconds to charge from 0 V to 5 V. It will be necessary. Therefore, when the power is turned on, the potential of the power supply line VBB can be quickly determined to determine that the capacitor Cbk has reached the usage limit.

Next, the distribution relationship of DC voltage will be summarized. The three types of DC voltages (35V, 12V, 5V) generated by the power supply board 20 are first distributed to the payout control board 24. Then, two types of DC voltages (12V, 5V) are distributed to the main control board 21 via the connector C1 and the main board relay board 34 after passing through the payout control board 24.

Further, the three types of DC voltages (35V, 12V, 5V) generated by the power supply board 20 are distributed to the effect control board 22 via the connector C2 and the power supply relay board 35, and are distributed to the image control board 23. Two types of DC voltages (12V, 5V) are distributed via the effect control board 22 and the image interface board 37.

Corresponding to the above configuration, the payout control board 24 and the main control board 21 generate power reset signals RST1 and RST2, respectively, based on the two types of DC voltages (12V and 5V) distributed to the internal circuits. The power is reset. Similarly, the effect control board 22 and the image control board 23 also generate a power supply reset signal RST3 based on the two types of DC voltages (12V, 5V) distributed, and inside the effect control board 22 and the image control board 23. The circuit is power reset.

By the way, the gaming machine GM is roughly classified into a frame-side member GM1 surrounded by a broken line in FIG. 3 and a board-side member GM2 fixed to the back surface of the gaming board 5. The frame-side member GM1 and the board-side member GM2 are electrically connected by connection connectors C1 to C3 which are centrally arranged at one location. Each of the connection connectors C1 to C3 has a plurality of contacts, and all of the contacts C1 to C3 are one-touch connectors that are connected by one mounting operation and separated by one separation operation.

The frame-side member GM 1 includes a front frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. It is fixedly installed in. On the other hand, the board-side member GM2 is replaced in response to the model change, and a new board-side member GM2 is attached to the frame-side member GM1 instead of the original board-side member. All except the frame-side member GM1 are board-side members GM2.

As shown in the broken line frame of FIG. 3, the frame side member GM 1 includes a power supply board 20, a payout control board 24, a signal relay board 25, a launch relay board 26, a backup power supply board 27, and an external terminal board 28. , A frame relay board 31 and a lamp drive board 32 are included, and these circuit boards are fixed to appropriate positions in the front frame 3.

The payout control board 24 is used to rotationally drive a one-chip microcomputer MCOM4 having a CPU whose processing unit is 8 bits, a power supply-related circuit 29 that generates a power supply reset signal RST1 and a power failure signal ABN, and a payout motor Mo. The payout drive circuit DR that generates the drive signals Φ1 to Φ4 of the above, the ball feed solenoid SLf that controls the launch of the game ball, and the launch control circuit SH that generates the drive signal of the launch solenoid SLe are mounted.

The signal relay board 25 transfers the drive signals Φ1 to Φ4 received from the payout drive circuit DR to the payout motor Mo to rotationally drive the payout motor Mo. Further, the signal relay board 25 receives detection signals from various detection sensors and transfers them to the one-chip microcomputer MCOM4 of the payout control board 24.

The detection signal received by the signal relay board 25 is not particularly limited, but in this embodiment, the door frame opening signal indicating that the glass door 6 and the front frame 7 have been opened, and the game ball are clogged and cannot be paid out. A ball jam detection signal indicating that there is no game ball to be paid out, a supply shortage detection signal indicating that there is no game ball to be paid out, and a counting switch signal indicating that the game ball has been paid out are included.

Next, the launch relay board 26 supplies the solenoid signal SLf received from the launch control circuit SH to the ball feed solenoid SLf, and realizes the launch control operation together with the launch solenoid SLe. Further, on the launch relay board 26, regarding the launch handle 10 operated by the player, a launch stop switch STOP for instructing the launch stop of the game ball, a touch sensor TCH indicating that the player is touching the launch handle 10, and a touch sensor TCH indicating that the player is touching the launch handle 10. , The signal from the intensity volume VR indicating the rotation position of the firing handle 10 is received, and each received signal is transferred to the one-chip microcomputer MCOM4 of the payout control board 24.

The external terminal board 28 is a circuit board that relays the game information INF to be transmitted to the hall computer HC, and the game information INF is generated by the main control board 21, the main board relay board 34, the connector C1 and the payout. The circuit is connected to the external terminal board 28 via the control board 24 (see FIG. 4).

A plurality of LEDs are connected to the lamp drive board 33, and the drive data for driving these LED groups is used as a serial signal in the one-chip microcomputer MCOM2 of the effect control board 22 → frame relay board 36 → connector C3 →. It is transmitted to a plurality of LED drivers mounted on the lamp drive board 32 via the frame relay board 31. Similarly, the audio signal for the audio effect generated by the effect control board 22 is also supplied to the plurality of speakers via the frame relay board 36 → the connection connector C3 → the frame relay board 31.

Further, the frame relay board 31 receives the switch signal from the chance button 11, and is a one-chip microcomputer of the effect control board 22 via the connector C3 → the frame relay board 36 as a serial signal combined with other signals. It is transmitted to MCOM2.

Although the frame-side member GM1 has been mainly described above, on the back surface of the game board 5, a main control board 21, an effect control board 22, an image control board 23, and an image interface board 37 are provided as board-side member GM2. It is fixed together with the display device DS and other circuit boards.

As shown in FIG. 3, an initialization switch SW operated by a staff member is connected to the main control board 21. The initialization switch SW is a switch that determines whether or not to initialize the work area of the built-in RAM of the one-chip microcomputers MCOM1 and MCOM4 of the main control unit 21 and the payout control unit 24. Then, the RAM clear signal CLR indicating that the initialization switch SW has been turned ON is commonly transmitted to the one-chip microcomputer MCOM1 of the main control unit 21 and the one-chip microcomputer MCOM4 of the payout control unit 24 (FIG. 4). reference).

Further, the main control unit 21 is connected to each game component of the game board 5 via the game board relay board 33. Then, while receiving the switch signal of the detection switch built in each of the winning openings 15 to 18 on the game board, the solenoids SL1 to SL3 such as the electric tulip are driven.

The effect control board 22 reproduces and outputs a voice signal based on instructions from the one-chip microcomputer MCOM2 that controls the effect operation such as voice effect, lamp effect, and movable effect by the effect movable body, and the one-chip microcomputer MCOM2. A voice synthesis circuit (voice processor) SND, a voice memory that stores compressed voice data that is the original data of the voice signal to be reproduced, and a digital amplifier AMP that receives the digital voice signal of the voice synthesis circuit SND and amplifies it in class D. Have been placed.

Further, the lamp drive board 38 and the lamp motor drive board 39 are connected to the effect control board 22, and the lamp group and the motor groups M1 to Mx connected to the drive boards 38 and 39 are appropriately driven. By doing so, a lamp effect and a movable effect are realized.

On the other hand, the image control board 23 generates image data for one frame of the display device DS based on the instructions from the one-chip microcomputer MCOM3 that receives the control command CMD'from the effect control board 22 and the one-chip microcomputer MCOM3. An image processor VDP that outputs images and a CG memory that stores basic data for image production are arranged. Then, the one-chip microcomputer MCOM3 controls the image processor VDP based on the control command CMD'to realize an image effect synchronized with the lamp effect, the sound effect, and the movable effect in the effect control unit 22.

Next, FIG. 4 is a block diagram showing the internal configurations of the main control unit 21 and the payout control unit 24 in a little more detail. As shown in the figure, the 35V generated by the power supply board 20 is distributed to the firing control circuit SH of the payout control unit 24 to become the power supply voltage of the firing solenoid SLe and the ball feed solenoid SLf. Further, 35V distributed to the main control board 21 via the payout control unit 24 becomes the power supply voltage of the solenoids SL1 to SL3.

The solenoids SL1 to SL3 arranged on the main control board 21 are connected to a power switch PS having a built-in power transistor that is ON / OFF controlled based on the control signals CTL1 to CTL3. Then, the one-chip microcomputer MCOM1 appropriately controls the control signals CTL1 to CTL3, so that the solenoids SL1 to SL3 appropriately open and close the electric tulips and the grand prize opening 16.

On the other hand, regarding the launch solenoid SLe and the ball feed solenoid SLf, the energization time and energization are not based on the control of the one-chip microcomputer MCOM4, but based on the initial setting value to the launch control circuit SH and the output signal of the launch intensity volume VR. The timing, energization cycle, etc. are controlled by the launch control circuit SH. However, in order for the launch control circuit SH to start the launch control operation, (1) the ball lending machine LEN is normally connected, and (2) the launch permission signal SHOOT is received from the main control unit 21. It becomes an operation start condition. Further, when (3) the player releases the firing handle 10 or (4) the player instructs the firing stop, the firing control circuit SH naturally stops the firing operation (operation stop). conditions).

Adding an explanation about the above-mentioned operation start condition, as shown in FIG. 4, the launch control circuit SH is connected to the ball lending machine LEN via the ball lending relay unit LK1 and the relay board LK2 (see FIG. 6). ), The energization signal POUT indicating the connection state with the ball lending machine LEN is received. Further, the launch control circuit SH is circuit-connected so as to receive a launch permission signal SHOOT from the one-chip microcomputer MCOM1 of the main control unit 21.

FIG. 7A illustrates the internal configuration of the launch control circuit SH, and the launch control circuit SH includes an energization signal POUT, a logically inverted launch permission signal SHOOT, and a logically inverted stop switch signal. An AND circuit that receives the STOP, the touch sensor signal TCH, and the touch sensor signal TCH is built in. Here, when the connection with the ball lending machine LEN is established, the energization signal becomes POUT = H (see FIG. 6), and if the main control unit 21 permits the launch, the launch permission signal becomes SHOOT = H (ST15 in FIG. 8). If the stop switch is not operated, the stop switch signal becomes STOP = H, and when the player touches the firing handle 10, the touch sensor signal becomes TCH = L.

FIG. 7B illustrates the internal configuration of the touch sensor. When the player holds the firing handle 10, the sense transistor Qs is in the ON state, and the touch sensor signal TCH = L. Then, under the conditions of energization signal POUT = H, launch permission signal SHOOT = H, stop switch signal STOP = H, and touch sensor signal TCH = L, the output of the AND circuit becomes H level, and the frequency division operation of the frequency divider is permitted. Then, the game ball is intermittently launched at a legal predetermined cycle determined by the frequency of the output signal.

On the other hand, if any of the above conditions is not satisfied, the game ball will not be fired. The firing operation of the game ball is realized by intermittently energizing the firing solenoid SLe, but the firing intensity is controlled according to the energizing current of the firing solenoid SLe defined based on the value of the firing intensity VR. Will be done. Further, the ball feed solenoid SLf is energized in accordance with the launch cycle, and the launch ball is set at a predetermined position.

Continuing the description with respect to FIG. 4, the power supply-related circuit 29 of the payout control board 24 includes an AC detection circuit DET that receives AC 24V from the power supply board 20 and a DC determination circuit JG1 that receives DC 12V and 5V from the power supply board 20. It is configured to have. Here, the AC detection circuit DET is a circuit that detects whether the AC power supply is in the on state or the cutoff state. Further, the DC determination circuit JG1 generates a power supply reset signal RST1 based on the DC voltage (12V, 5V), detects that the AC power supply (AC24V) is cut off, and generates a power interruption signal ABN. It is configured.

As described above, the two types of DC voltages (12V, 5V) distributed on the payout control board 24 are transferred to the main control board 21, and the electronic elements including the one-chip microcomputer MCOM1 and the winning openings 15 to 18 are used. It becomes the power supply voltage of the detection switch built in. Further, in this embodiment, the DC determination circuit JG1 is also provided on the main control board 21, and the DC determination circuit JG1 is a power source for the main control board based on two types of DC voltages (12V, 5V). The reset signal RST2 is generated. As described above, in this embodiment, since the power supply reset signal RSTi is not transmitted, there is no possibility that the one-chip microcomputer MCOMi is abnormally reset due to the influence of noise or the like.

FIG. 4 also describes important control signals transmitted and received between the main control board 21 and the payout control board 24. As shown in the figure, in this embodiment, 4-bit length error information and 1-bit length notification signal PWON / Err are transmitted from the payout control board 24 to the main control board 21. The notification signal is a power-on signal PWON indicating that the payout control operation of the payout control board 24 is ready for the payout control operation at the time of power-on, and is transmitted to the one-chip microcomputer MCOM1 of the main control board 21. .. Further, this 1-bit length notification signal functions as a communication abnormality signal Err indicating a communication abnormality of the prize ball command SYO after the power is reset, and when an abnormality is detected in the reception process of the prize ball command SYO, the main control is performed. The L-level communication abnormality signal Err is transmitted to the one-chip microcomputer MCOM1 on the board 21.

On the other hand, the 4-bit length error information is specifically a supply shortage detection signal, a ball clogging detection signal, a door frame opening signal, and a counting error signal. Here, the supply shortage detection signal, the ball clogging detection signal, and the door frame opening signal each correspond to the same type of detection signal received by the signal relay board 25. That is, the out-of-supply detection signal, the ball clogging detection signal, and the door frame opening signal received by the signal relay board 25 are first transmitted to the one-chip microcomputer MCOM4, and after appropriate abnormality handling processing is performed, the same type of error occurs. As information, it is transmitted to the one-chip microcomputer MCOM1 of the main control board 21.

Further, the counting error signal is related to the counting switch signal received by the signal relay board 25, and the one-chip microcomputer MCOM4 determines the matching between the number of game balls that should have been paid out and the cumulative value of the counting switch signal. If they do not match, they are transmitted as a counting error signal from the one-chip microcomputer MCOM4 to the one-chip microcomputer MCOM1.

On the payout control board 24 from the main control board 21, a RAM clear signal CLR indicating that the initialization switch SW has been operated, a launch permission signal SHOOT for permitting the launch operation of the game ball, and the number of game ball payouts are specified. The prize ball command SYO to be used is transmitted by a signal line having a length of 1 bit each. As shown in the figure, the prize ball command SYO is transmitted in one direction from the serial transmission port SIOTX of the one-chip microcomputer MCOM1 to the serial reception port SIORX of the one-chip microcomputer MCOM4.

As described with respect to FIG. 3, the external terminal board 28 receives a game information INF of about 10 bits from the one-chip microcomputer MCOM1 of the main control board 21, and also receives a prize ball from the one-chip microcomputer MCOM4 of the payout control board 24. The prize ball signal for specifying the number and the error information such as the door frame opening signal are received and transferred to the hall computer HC.

FIG. 5A is a circuit diagram showing the AC detection circuit DET constituting the power supply-related circuit 29 of the payout control board 24 and the DC determination circuit JG1, and also shows the connection relationship with the one-chip microcomputer MCOM4. There is. Further, FIG. 5C is a circuit diagram showing the DC determination circuit JG2 of the main control board 21, and FIG. 5B is a time chart illustrating the operation of the DC determination circuits JG1 and JG2.

As shown in FIG. 5A, the AC detection circuit DET is mainly composed of a full-wave rectifier circuit that rectifies AC 24V and a photocoupler PH1 that receives the rectified output of the full-wave rectifier circuit. The photodiode D of the photocoupler PH1 is configured such that a detection current limited by the current limiting resistor R1 flows while the protection diode D3 absorbs the reverse voltage.

Therefore, in the power-on state, the phototransistor Tr of the photocoupler PH1 is turned on, and a detection voltage Vsc of about 5 V is output to the output resistor R2. Even if the detection current fluctuates due to the photodiode D receiving the rectified output (pulsating current), the fluctuation of the detection voltage Vsc is absorbed by the smoothing capacitor C1.

On the other hand, when the power supply is cut off, the phototransistor Tr of the photocoupler PH1 is turned off, so that the detection voltage Vsc drops to the ground level. However, in the photocoupler PH of the embodiment, the turn-off time required to shift from the ON state to the OFF state is about 0.1 mS, so that the phototransistor Tr is OFF in the momentary power failure state in which the AC power supply is temporarily cut off. It doesn't work. That is, in this embodiment, the influence of power supply noise and the like is eliminated by using the photocoupler PH1 for the AC detection circuit DET.

Next, the DC determination circuit JG1 and the DC determination circuit JG2 are each composed of a power supply voltage monitoring IC shown in a narrow frame. As shown in the figure, the abnormal output terminal OUTc of the DC determination circuit JG1 receives a power supply voltage of 5V through the current limiting resistor R8. In this DC determination circuit JG1, the abnormal output terminal OUTc is the output terminal of the inverting power failure signal ABN bar, and after being logically inverted to the power failure signal ABN through the NAND gate G3, the input port and buffer circuit of the one-chip microcomputer MCOM4. It is transmitted to the BUF.

The buffer circuit BUF of the embodiment is an Inverting Schmitt Triger type, but the power interruption signal ABN is circulated by the buffer circuit BUF to eliminate the logical inversion, and then the input of the one-chip microcomputer MCOM1 of the main control board 21. It is transmitted to the port (see FIG. 4). The supply shortage detection signal, ball jam detection signal, counting error signal, door frame opening signal, and power-on signal PWON / communication abnormality signal Err are output from the output port of the one-chip microcomputer MCOM4 in a logically inverted state. , After being logically inverted by the Inverting Schmitt Triger type buffer circuit BUF, it is transmitted to the input port of the one-chip microcomputer MCOM1 of the main control board 21 (see FIG. 4).

On the other hand, the reset terminal RST1 of the DC determination circuit JG1 is connected to the ground via the noise absorbing capacitor C4 and receives a power supply voltage of 5V through the current limiting resistor R9. The reset terminal RST1 of the DC determination circuit JG1 is connected to the reset terminal of the one-chip microcomputer MCOM4 through the NAND gates G4 and G5 to supply the power supply reset signal RST1. Further, the reset terminal RST1 is also connected to the clear terminal CLR terminal of the latch circuit LT through the NAND gates G4 and G6 to supply the IO reset signal IORST1.

The latch circuit LT is composed of a D-type flip-flop, and is configured to acquire an EXS signal, a PRDY signal, an error lamp signal ERR, and a prize ball signal via the data bus of the one-chip microcomputer MCOM4. There is. Then, based on the chip select signal CS, the EXS signal and the PRDY signal acquired in the latch circuit LT are transmitted to the ball lender LEN, and the prize ball signal acquired in the latch circuit LT is transmitted to the hall computer HC. .. Further, the error lamp signal ERR drives an error lamp (not shown) and turns on the error lamp in the event of an abnormality.

As shown in FIG. 5C, the circuit configuration of the DC determination circuit JG2 arranged on the main control board 21 is almost the same as the DC determination circuit JG1 of the payout control board 24 described above, and the DC determination circuit JG2 is inverted. The configuration is the same as that of the DC determination circuit JG1 except that the power failure signal ABN bar is not generated, that is, the abnormal output terminal OUTc is not used.

That is, the power supply reset signal RST2 output from the DC determination circuit JG2 is supplied to the reset terminal of the one-chip microcomputer MCOM1, and the same signal is also supplied to the clear terminal CLR terminal of the latch circuit LT as the IO reset signal IORST2. ing. As shown in the figure, the output of the latch circuit LT of the main control unit 21 includes a firing permission signal SHOOT, and the power of the latch circuit LT is reset when the power is turned on, so that the firing permission signal SHOOT is generated at this timing. It will definitely be L level.

Based on the above, returning to FIG. 5A, the circuit configuration of the payout control unit 24 will be continued. As shown in the figure, the power supply voltage monitoring IC has three monitoring terminals Vsa, Vsb, and Vsc, and comparators CMa, CMb, and CMc are built in corresponding to the respective monitoring terminals Vsa, Vsb, and Vsc. .. A transistor Q3 that operates ON based on the output value of the comparator CMc is built in, and an inverting power failure signal ABN bar is output to the abnormal output terminal OUTc, which is an open collector terminal of the transistor Q3.

Here, the input voltage Vsc of the third terminal is the AC detection voltage Vsc of the AC detection circuit DET, and becomes a significant value immediately after the power is turned on. Therefore, the output of the comparator CMc becomes H level immediately after the power is turned on, and the transistor Q3 quickly turns on, so that the inverting power failure signal ABN bar becomes L level immediately after the power is turned on. Therefore, the power failure signal ABN supplied to the one-chip microcomputer MCOM4 becomes H level immediately after the power is turned on.

As described above, in this embodiment, the power failure signal ABN supplied to the one-chip microcomputer MCOM4 becomes H level immediately after the power is turned on, and this operating state does not change unless the AC power supply is cut off. On the other hand, when the AC power supply is cut off, the voltage Vsc of the third terminal quickly drops toward zero volt, so that the output of the comparator CMc changes to the L level. As a result, the transistor Q3 makes an OFF transition, and the inverting power failure signal ABN bar rises to the H level.

As described above, the inverting power failure signal ABN bar is transmitted to the input port of the one-chip microcomputer MCOM4 as a power failure signal ABN via the NAND gate G3. Further, the inverting power failure signal ABN bar is transmitted to the input port of MCOM1 as a power failure signal ABN via the NAND gate G3 and the buffer circuit BUF.

Therefore, the two one-chip microcomputers MCOM1 and MCOM4 can know the cutoff state of the AC power supply at substantially the same timing, and can quickly finish the necessary power cut processing before the DC power supply is cut off. Then, after the DC power supply is completely cut off, the backup power supply VBB functions to maintain the stored contents of the built-in RAMs of the one-chip microcomputers MCOM1 and MCOM4. Since the photocoupler PH1 is used for the AC detection circuit DET, the power interruption signal ABN does not occur in the momentary power failure state of the AC power supply, as described above.

Subsequently, the power supply reset signal RST1 relating to the DC power supply will be described. As shown in FIGS. 5A and 5C, the first terminal Vsa is substantially open by being connected to the ground by the capacitor C3. Therefore, in the steady state where the DC voltage 5V is a specified level, the first terminal Vsb is about 1.4V based on the voltage dividing ratio of the voltage dividing resistors R6 and R7 inside the element. The voltage of the first terminal Vsa is supplied to the comparator CMA, but since the input voltage on the other side of the comparator CMA is about 1.24 V, the output of the comparator CMA is in a steady state where the DC voltage 5 V is a specified level. Is the L level.

On the other hand, the second terminal Vsb is configured to supply a detection voltage obtained by dividing a DC voltage of 12 V by voltage dividing resistors R4 and R5. Then, in the steady state where the DC voltage 12V is a specified level, the resistance values of the voltage dividing resistors R4 and R5 are set so that the second terminal Vsb is about 1.6V. The voltage of the second terminal Vsb is supplied to the comparator CMb, but since the input voltage on the other side of the comparator CMb is about 1.24V, the output of the comparator CMb becomes the L level in the steady state.

Based on the above steady operation, in the steady state where the DC voltage of 5V and 12V is the specified level, the output of the OR gate G1 becomes the L level, and the L level voltage is supplied to the S input terminal of the RS flip-flop FF. become. As will be described later, in this steady state, an L level voltage is supplied to the R input terminal of the RS flip-flop FF.

The steady state in which the DC voltages of 5V and 12V are at the specified level has been described above, but in the power-on state and at the transient timing in which the DC voltages 5V and 12V gradually increase, the first terminal Vsa and the second terminal are always used. Since the voltage of Vsb is lower than 1.24V, the output of the OR gate G1 becomes H level at this time. Then, the H level voltage is supplied to the S input terminal of the RS flip-flop FF, and the L level voltage is supplied to the R input terminal, so that the RS flip-flop FF is set and the Q output becomes the H level. Become.

Therefore, immediately after the power is turned on, the transistor Q1 is quickly turned on, and as a result, the output of the comparator CM2 is also H level, and the transistor Q2 is turned on. The timing T1 in FIG. 5B shows this transition operation, and the power reset signal RST1 quickly reaches the L level when the power is turned on.

Continuing the explanation of the transient timing when the DC voltage 5V, 12V rises, after that, when the DC voltage 5V, 12V further rises and approaches the specified level, the S input terminal of the RS flip-flop FF, which is the output of the OR gate G1, becomes , L level, and correspondingly, the R input terminal changes to H level. Therefore, the RS flip-flop FF is reset at this timing, and as a result, the transistor Q1 makes an OFF transition, and the charging operation to the capacitor CT is started.

The timing T2 and the timing T5 in FIG. 5B indicate the start of charging of the capacitor CT, and thereafter, the potentials of the inverting input terminals (−) of the comparators CM1 and CM2 gradually increase. Then, when an appropriate charging time Tpo elapses (timing T2, T6), the output of the comparator CM2 transitions to the L level, so that the transistor Q2 operates OFF, and as a result, the power supply reset signal RST1 changes to the H level. To do. Corresponding to this operation, the output of the comparator CM1 also becomes the L level, and both the S input terminal and the R input terminal of the RS flip-flop FF become the L level.

As described above, the optimum reset period Tpo is secured by maintaining the power supply reset signal RST1 at the L level from the timing T2 to the timing T3. In this embodiment, the reset period Tpo of the payout control board 24 is about 470 mS, whereas the reset period Tpo of the main control board 21 is set to about 1S, which is sufficiently longer than that, and the payout control board 21 is set. 24 will start up quickly.

As described above, in the main control board 21 and the payout control board 24, the optimum reset period Tpo required for the normal start-up of the one-chip microcomputers MCOM1 and MCOM4 is secured for the power supply reset signals RST2 and RST1, and the subsequent normal operation is performed. Is guaranteed.

By the way, when at least one of the DC voltages 5V and 12V drops, the output of the OR gate G1 changes to the H level, so that the RS flip-flop FF is set. As a result, the power supply reset signal RST1 becomes L level when the transistor Q1 makes an ON transition. The timings T4 and T7 in FIG. 5B show this operating state, and at this timing, the power supply reset signal RST1 changes to the L level, and the one-chip microcomputer MCOM4 is in the operating stopped state. Therefore, even if either the DC voltage of 5V or the DC voltage of 12V drops abnormally in the normal power supply state in which the AC power supply is supplied, the one-chip microcomputer does not go into a runaway state.

On the other hand, when the AC power supply is cut off, the AC detection circuit DET detects the cutoff of the AC power supply and outputs a power failure signal ABN prior to the start of the DC voltage drop at the timing T7. Since the one-chip microcomputers MCOM4 and MCOM1 that have received the power interruption signal ABN have completed the necessary power interruption processing, no problem occurs even if the power supply reset signal RST1 changes to the L level thereafter.

Continuing to explain the significance of the power supply reset signal RST1, as shown in FIG. 5A, the power supply reset signal RST1 of the payout control board 24 is also supplied to the clear terminal CLR of the latch circuit LT as the IO reset signal IORST1. There is. Therefore, the EXS signal and PRDY signal transmitted to the ball lending machine LEN and the prize ball signal transmitted to the hall computer HC are surely cleared by the power reset signal RST1 (IORST1), and the power reset period Tpo During that time, the clear state is maintained under any noise environment.

As a result, it is surely prevented that the hall computer HC misidentifies the prize ball performance and that the ball lending machine LEN starts the error handling operation. If the configuration of this embodiment is not adopted, an abnormal level signal or an abnormal pulse is output in a time zone in which the power supply is unstable immediately after the power is turned on, that is, in a time zone corresponding to the power supply reset period Tpo. There is a risk, but in this embodiment there is no possibility. Further, since the data cleared by the power reset signal RST1 includes the drive data for turning on the error lamp, the error lamp does not turn on unreasonably and the staff in the game hall is not confused. ..

FIG. 6A illustrates the relationship between the relay board LK2 (see FIG. 4) that transmits and receives a control signal to and from the ball lender LEN and the payout control board 24, and is a latch mounted on the payout control board 24. The circuit LT (see FIG. 5) and the ball rental relay unit LK1 (FIG. 4) are shown. Further, FIG. 6B shows a communication protocol between the ball lending machine LEN and the payout control board 24.

As shown in the figure, the payout control board 24 receives the continuity confirmation signal VL, the BRDY signal, and the BRQ signal, which are DC voltages, from the ball lender LEN, while the PRDY signal and EXS are received from the ball lender LEN. It is outputting a signal. As shown in FIG. 6B, for example, in the ball lending operation in which 25 pieces are used as a payout unit, the payout control board 24 starts the operation of outputting an H level PRDY signal to the ball lending machine LEN. It becomes a condition (operation (a)). Then, after that, one unit of game balls is paid out by the movements (b) to (f), and then 25 game balls are paid out every time the movements (c') to the movements (f') are repeated. Finally, the operation (g) is executed to end the series of ball lending operations.

In order to accurately execute the above ball lending operation, the relay board LK2 of the embodiment includes five photocouplers PH2 to PH6 operating at a DC voltage of 12 V, a current limiting resistor r of each photodiode, and each phototransistor. The current limiting resistor R of the above is arranged. Then, the PRDY signal and the EXS signal output to the latch circuit LT are transmitted to the photocouplers PH2 and PH3 via the sink driver SK1 at an appropriate timing shown in FIG. 6B, and are transmitted to the ball lender LEN. Be transmitted. Here, the sink driver SK1 is a switching element that executes a sink operation (sink) in which the ON current flowing into the current limiting resistor r from the DC voltage 12V is drawn into the element.

In response to the above operation, the ball lender LEN constantly feeds the continuity confirmation signal (DC voltage) VL and outputs the BRDY signal and the BRQ signal at appropriate timings shown in FIG. 6 (b). Output to the control board. Then, the continuity confirmation signal VL, the BRDY signal, and the BRQ signal are transmitted to the sink driver SK2 via the photocouplers PH4 to PH6. In the case of the embodiment, the sink driver SK2 is a switching element that executes a sink operation that draws the ON current flowing into the load resistance RL from the power supply voltage 5V into the element, and has a built-in clamp circuit Clamp or the like that absorbs the overvoltage. There is.

The voltage level is modified from 12V to 5V corresponding to the one-chip microcomputer MCOM4 by passing through the sink driver SK2, but the level-converted BRDY signal and BRQ signal are transmitted to the one-chip microcomputer MCOM4, respectively. .. Further, the continuity confirmation signal VL becomes an H level energization signal POUT via the sink driver SK2 and is transmitted to the launch control circuit SH. As described with respect to FIG. 7, the H-level energization signal POUT is a condition for permitting the firing operation of the game ball. Therefore, when the ball lending machine LEN and the payout control board 24 are not connected from the time when the power is turned on, or when the connection between the payout control board 24 and the ball lending machine LEN is interrupted during the game operation, the game ball Is not started, and the occurrence of an abnormal situation is immediately revealed to the player.

Subsequently, the control operations of the main control unit 21 and the payout control unit 24 will be described. FIG. 8 is a flowchart illustrating the operation of the main control unit, which is a main routine (FIG. 8 (a)) executed after a CPU reset and a timer interrupt routine (FIG. 8) that is activated every predetermined time τm (= 4 mS). 8 (b)) and.

When the CPU of the one-chip microcomputer MCOM1 is reset based on the power reset signal RST2, the internal register of the one-chip microcomputer MCOM1 is initially set (ST2) after the CPU is set to the interrupt disabled state (ST1). As described with respect to FIG. 5C, when the CPU is reset based on the power reset signal RST2, the output of the latch circuit LT is cleared based on the IO reset signal IORST2. Therefore, the launch permission signal SHOOT becomes an OFF (= L) level when the power supply is reset, and the launch permission signal SHOOT is transmitted to the payout control unit 24. As shown in FIGS. 4 and 7, the L-level launch permission signal SHOOT is transmitted to the launch control circuit SH of the payout control unit 24, so that the launch of the game ball is prohibited at this timing.

Next, the RAM clear signal CLR indicating that the initialization switch SW has been operated is acquired and temporarily stored, and while clearing the watchdog timer WDT built in the one-chip microcomputer MCOM1 (ST4), the power-on signal PWON Waits for H level (ST5).

The power-on signal PWON is a signal indicating that the payout control unit 24 is ready for the payout operation (ST50 in FIG. 11), and is a signal for matching the control operations of the main control unit 21 and the payout control unit 24. Is. The reset period Tpo of the power reset signal RST2 of the main control unit 21 is about 1S, whereas the reset period Tpo of the power reset signal RST1 of the payout control unit 24 is set to about half of that. Normally, at the time of determination in step ST5, the main control unit 21 receives the power-on signal PWON at the ON (= H) level, and immediately shifts to the process in step ST6.

Then, when the initialization switch SW is turned ON, the RAM clear signal CLR is at the ON level (ST6), the backup flag BFL stored in the power supply monitoring process is destroyed (ST7), or the built-in If the checksum value of the RAM does not match the value before the power failure (ST7 to ST9), it is determined that the stored contents of the internal RAM are not maintained, and the internal RAM is cleared to zero (ST10).

Further, the RAM clear command CMD, which is a control command indicating that the built-in RAM has been zero-cleared, is transmitted to the effect control unit 22 (ST11). Then, the effect control unit 22 transmits the control command CMD'corresponding to the received RAM clear command CMD to the image control unit 23. The RAM clear command CMD is not transmitted to the payout control unit 24. However, since the payout control unit 24 is configured to receive the RAM clear signal CLR transmitted to the main control unit 21 in common (FIG. 4), the same type of RAM clear is based on the RAM clear signal CLR. The process can be executed (ST42 to ST48 in FIG. 11).

On the other hand, when it is determined that the stored contents of the internal RAM are correctly maintained (ST9 is determined to be Y), the backup flag BFL and the communication abnormality flag TXer are cleared (ST12), and the internal CTC circuit of the one-chip microcomputer MCOM1 is cleared. Is initially set, and then the CPU is set to the interrupt enabled state in order to start the timer interrupt operation (ST14).

By the above processing, the game control operation can be started in the main control unit 21, so that the ON level launch permission signal SHOOT is output to permit the launch of the game ball (ST15), and the infinite loop process is started. To do.

Subsequently, the timer interrupt processing that is started every 4 mS will be described. First, it is determined whether or not the AC power supply is cut off based on the level of the power interruption signal ABN transmitted from the payout control unit 24 (see FIG. 4), and if it is determined that the AC power supply is cut off, After executing the necessary backup process and setting the backup flag BFL to a predetermined value (5AH), it waits for the CPU to be reset and the DC power supply to be shut off (ST20). The backup process includes a process of calculating and storing a checksum value.

On the other hand, when the power failure is not determined, the random number value for the lottery process is updated (ST21), and the timer values for various game operations are subtracted and updated (ST22). In addition, various switch signals including a switch signal of a detection switch built in the winning openings 15 to 18, a communication abnormality signal Err transmitted from the payout control unit 24, and an abnormality signal related to payout transmitted from the payout control unit 24. (ST23). As described with respect to FIG. 4, the communication abnormality signal Err indicates the presence or absence of a communication abnormality of the prize ball command SYO, and is transmitted on the same transmission line as the power-on signal PWON determined in step ST5.

Next, the abnormality determination process is executed based on the switch signal acquired in the process of step ST23, the abnormality flag for abnormality notification is set in the abnormality determination value, and other necessary processes are executed (ST24). .. For example, when the communication abnormality signal Err is at an abnormality level, the communication abnormality flag TXer is set to the ON state, and the emission permission signal SHOOT is changed to the prohibition level (= L).

As will be described later, in this embodiment, when the communication of the prize ball command SYO is abnormal, the payout control unit 24 stops paying out the game ball (see FIG. 11C), but the payout is fired in accordance with this payout stop operation. By changing the permission signal SHOOT to the prohibition level (= L), the launch of the game ball is prohibited.

Next, when a game ball is won, a prize ball command SYOi that specifies the number of prize balls is created in the command buffer BUFF shown in FIG. 9 (b) (ST25). Then, the prize ball command SYOi read from the command buffer BUFF is serially transmitted to the payout control unit 24 through the procedure shown in FIG. 9 (c) (ST26).

As a result of the communication abnormality (Err = L), even after the communication abnormality flag TXer is turned ON and the firing operation is prohibited (ST24), the necessary prize ball command SYOi is repeatedly stored in the command buffer BUFF. (ST25). Since the stored contents of this command buffer BUFF are maintained by the backup power supply VBB even after the power supply is cut off, the winning state of the game ball until the occurrence of the communication abnormality does not disappear. That is, the winning state is stored and maintained as a prize ball command stored in the command buffer BUFF.

FIG. 9A illustrates the configuration of the prize ball command SYOi, and based on the output of the detection switch of the winning opening, any of the prize ball commands of 1 byte length SY01 to SY15 is shown in FIG. 9 (b). ) Is stored in the command buffer BUFF. Although 15 types of prize ball commands SY01 to SY15 are prepared, not all of them need to be used.

Further, in the present embodiment, in all the prize ball commands SYOi, by associating a predetermined significant bit with the remaining dummy bits, it is possible to easily detect a communication abnormality or transmission of an illegal command. FIG. 9A exemplifies a simple configuration for convenience of explanation, and the upper 4 bits (dummy bits) and the lower 4 bits are obtained so that when the upper 4 bits and the lower 4 bits are added to each other, the hexadecimal number FFH is obtained. (Significant bit) is associated.

In the configuration example of FIG. 9A, the lower 4 bits (1 to 15) specify the number of prize balls, and the payout control unit 24 adds bits to the upper 4 bits and the lower 4 bits (matching calculation). Therefore, it is possible to determine the occurrence of a communication abnormality. Further, when the prize ball command SYOj that is not supposed to be transmitted is transmitted, it can be determined that it is an invalid command. In this embodiment, the parity bit is not provided, but when the parity bit is provided, an invalid command is detected based on the matching operation between the dummy bit excluding the parity bit and the significant bit.

The prize ball command SYOi having such a configuration is serially output from the serial transmission port SIOTX of the one-chip microcomputer MCOM1 and serially received by the serial reception port SIORX of the one-chip microcomputer MCOM4. Note that FIG. 9 (c) illustrates the configuration of the serial transmission port SIOTX, and FIG. 9 (d) illustrates the configuration of the serial reception port SIORX.

As shown in FIG. 9C, the serial transmission port SIOTX outputs the transmission data register RPt in which the CPU writes 1-byte data and the 1-byte data transferred from the transmission data register RPt one bit at a time at a predetermined communication speed. It is configured to have a transmission shift register RSt to be used and a status register STt that specifies whether or not writing to the transmission data register RPt is possible (empty state / full state).

On the other hand, as shown in FIG. 9D, the serial reception port SIORX is a reception shift register RSr that acquires a serial signal (prize ball command SYOi) bit by bit, and a reception in which 1-byte data is transferred from the reception shift register RSr. It is configured to have a data register RPr and a status register STR for specifying information related to abnormalities in reception operation.

As will be described later, the abnormalities in the receiving operation include noise errors, overrun errors, and framing errors, and the corresponding bits of the status register Str are set in response to the detected abnormalities. Further, it is specified that 1-byte data is transferred from the reception shift register RSr to the reception data register RPr based on a predetermined bit (received data full bit) of the status register Str.

As shown in FIG. 10A, the serial signal of the embodiment includes an L-level start bit START (1 bit), an 8-bit length prize ball command, and an H-level stop bit STOP (1 bit). All 10 bits are continuous. Then, in this embodiment, these 10 bits are serially transmitted at a communication speed (baud rate) of about 9600 bps (bit per second).

As shown in the figure, this embodiment adopts an asynchronous serial transmission method that does not transmit a transmission clock, and the serial signal line is at H level in the non-communication idle state. Then, in the idle state, the H-level serial signal line drops to the L level by the start bit START, and then, after 8-bit data is transmitted, the serial signal line rises to the H level by the stop bit STOP. Then, it returns to the original idle state.

In this embodiment, the serial transmission port SIOTX and the serial reception port SIORX match the operations of serial transmission and serial reception based on the determination clock RT having the same frequency of 16 times the baud rate (9600 bps). 10 (c) to 10 (e) show the relationship between the start bit START, the data bit, and the stop bit STOP and the determination clock RT.

As shown in FIG. 10C, when the serial receiving port SIORX detects the falling edge of the serial signal line, it starts the counting operation of the determination clock RT, and then, for example, the third, fifth, and seventh. The start bit START bit is matched and determined in synchronization with the determination clock RT. In this case, normally, all L levels are detected, but if H level is detected in any of them, the noise error bit of the status register Str is set as a noise error. After that, when the 16th determination clock RT is detected, it is determined that the prize ball command SYOi is transmitted thereafter.

As shown in FIG. 10 (c), the serial reception port SIORX receives, for example, the 8th, 9th, and 10th judgment clock RTs in the judgment clock RT starting from the 1st after receiving the start bit START. The logical value of the first bit of the prize ball command is determined in synchronization with. The 8th, 9th, and 10th judgment values should be 0 or 1 in common, but in the unlikely event that they do not match, the value determined by the majority decision logic is acquired in the reception shift register RSr. At the same time, the noise error bit of the status register STR is set as a noise error.

The subsequent processing is the same, and when the 16th determination clock RT is detected, the same determination processing and acquisition processing are repeated, assuming that the next bit of the prize ball command SYOi is started thereafter. As described above, in this embodiment, since the data bits of the prize ball command SYOi are acquired near the center of the 16 determination clocks RTs that continue from the 1st to the 16th, the serial transmission port SIOTX and the serial reception Even if there is a slight deviation in the frequency of the determination clock RT between the port SIORX and the port SIORX, an unreasonable operation does not occur in the one-unit transmission / reception operation completed in about 10 bits.

In this way, after acquiring the 8-bit length prize ball command SYOi, the operation shown in FIG. 10E is executed. That is, in the determination clock RT starting from the first after receiving the final bit of the prize ball command, for example, the stop bit STOP is H in synchronization with the eighth, ninth, and tenth determination clock RTs. Make sure it is a level. In this case, normally, all H levels are detected, but if the L level is detected in any of them, the noise error bit of the status register Str is set as a noise error.

Further, when the L level is selected as a result of the majority decision logic, the framing error bit of the status register Str is set as an important communication abnormality has occurred.

Since it operates as described above, the communication error stored in the status register STR includes a noise error indicating that an error has been detected in any of the start bit, data bit, and stop bit, and framing in which the stop bit cannot be detected. It will contain errors. Further, the status register Str also stores an overrun error indicating that the reception shift register RSr has received the next 8 bits before the data in the reception data register RPr is read by the CPU.

As described above, there is a concern that various abnormalities may occur in serial transmission, but according to repeated experiments by the present inventor, it has been confirmed that noise errors and framing errors do not actually occur. Further, since the timer interrupt cycle τm (4 mS) of the main control unit 21 and the timer interrupt cycle τs (= 2 ms) of the payout control unit 24 are appropriately set, an overrun error does not occur.

9 (e) and 10 (b) show this relationship, and show a case where the prize ball command SYOi is continuously transmitted by the main control unit 21. As shown in the figure, the elapsed time from the end of transmission of the prize ball command SYOi to the end of transmission of the next prize ball command SYOi + 1 is τm on average, and timer interrupt processing (FIGS. 8 (b) and 11 (b)). ), If the maximum deviation time that may be shifted due to the influence of other processing is estimated as δ, the minimum value of the elapsed time from the end of transmission of the prize ball command SYOi to the end of transmission of the next prize ball command SYOi + 1 is It becomes τm-2 * δ.

On the other hand, the elapsed time from the start of receiving the prize ball command SYOi to the start of receiving the next prize ball command SYOi + 1 in the payout control unit 24 is τs on average, in addition to the timer interrupt processing (FIG. 10B). Assuming that the maximum deviation time that may be shifted due to the influence of the processing of is estimated as δ, the maximum value of the elapsed time from the start of receiving the prize ball command SYOi to the end of receiving the next prize ball command SYOi + 1 is τs + 2 *. It becomes δ.

Therefore, in the case of τm-2 * δ≤τs + 2 * δ, there is a possibility of an overrun error, but in this embodiment, the timer interrupt period (τm, τs) of the main control unit 21 and the payout control unit 24 is set. , Τm >> τs + 4 * δ, so (τm-2 * δ)-(τs + 2 * δ) = τm-τs-4 * δ >> 0, and there is a risk of overrun error. Absent. That is, regarding the prize ball command SYO, the prize ball command SYOi is normally acquired by the timely reception process (ST73 in FIG. 11B) in the timer interrupt process without invoking the serial reception interrupt or the like. Can be done.

Next, the prize ball command transmission process (ST26) will be described more specifically based on FIG. 9 (c). First, the communication abnormality flag TXer is determined (ST35), and in the case of a communication abnormality state (TXer = ON), the process ends without doing anything. As described above, in this embodiment, since the prize ball command SYO is not transmitted after the communication abnormality state occurs, the prize ball command SYO of the command buffer BUFF does not disappear, and the winning state of the game ball is correctly stored. Be maintained.

On the other hand, when the communication is not in an abnormal state (TXer = OFF), the status register STt is then referred to, and whether or not the transmission data register RPt is empty (Empty) is determined by the Empty bit of the status register STt (the empty status register STt). ST36). As described with respect to FIG. 9E, in this embodiment, the timer interrupt periods (τm, τs) of the main control unit and the payout control unit are τm = 4mS and τs = 2mS, and τm >> τs + 4 * δ. Since the condition of is satisfied, the determination in step ST36 must always be an Empty determination. However, in the unlikely event that a Nonempty determination is made, it is determined that there is a serious device trouble, and the communication abnormality flag TXer is set to the ON state. As a result, after that, the prize ball command SYO is not transmitted to the payout control unit 24.

However, in a normal case, the transmission data register RPt is always in the Empty state. In this case, the oldest prize ball command SYO stored in the command buffer BUFF is written to the transmission data register RPt. (ST38). Then, after that, the serial transmission port SIOTX automatically starts the transmission operation, starts the 10-bit serial transmission operation shown in FIG. 10A, and finishes the transmission operation after about 10/9600 ≈ 1 mS. Set the Empty bit of the status register STt to the ON state (Empty).

Since the above operation is automatically executed on the serial transmission port SIOTX, the CPU deletes the transmitted prize ball command SYO from the command buffer BUFF and organizes the command buffer BUFF following the process of step ST38. And finish the process (ST39). As a result, in the next timer interrupt, the oldest remaining prize ball command SYO will be serially transmitted to the payout control unit 24.

Since the description with respect to FIG. 9 has been described above, the description of the timer interrupt processing of the main control unit 21 will be continued by returning to FIG. When the processing of step ST26 is completed, the normal symbol processing (ST28) and the normal electric accessory processing (ST30) are executed as appropriate depending on whether or not the normal symbol display unit 19 fluctuates, and the symbol start port 15 (ST31). Then, if it is a big hit, the big winning opening 16 is opened and closed to execute the special electric accessory processing (ST33).

Finally, the necessary control command CMD is transmitted to the effect control unit 24 (ST34). At this time, if the communication error flag TXer is ON, the voice notification and image display will indicate "A communication error has occurred. Please call a staff member. ], And a communication abnormality notification command CMD for contacting the player is transmitted.

In the case of this embodiment, the communication abnormality flag TXer once set to the ON state has a configuration that does not disappear until the power is reset again (see ST12), so that the communication abnormality notification command is repeatedly transmitted by the processing of step ST34. Therefore, the effect control unit 22 and the image control unit 23 do not extinguish the voice notification and the image notification until the abnormality is resolved. After that, the communication abnormality can be resolved by shutting off the AC power supply by the staff, confirming the connection of the connector C1 and the like, and then returning the power supply. , It has been confirmed that such a communication abnormality does not occur in practice.

Subsequently, the operation of the payout control unit 24 will be described. FIG. 11 is a flowchart illustrating the operation of the payout control unit 24, which is a main routine (FIG. 11 (a)) executed after the CPU is reset and a timer interrupt routine (= 2 mS) that is started every predetermined time τs (= 2 mS). 11 (b)) and.

When the CPU of the one-chip microcomputer MCOM4 is reset based on the power reset signal RST1, the internal register of the one-chip microcomputer MCOM4 is initially set (ST2) after the CPU is set to the interrupt disabled state (ST1). As a result, the output of the output port built into the one-chip microcomputer MCOM4 is cleared, and the supply shortage detection signal, the ball clogging detection signal, the counting error signal, and the door frame opening output to the buffer circuit BUF of FIG. 5 (a) are cleared. All the signals are at the normal L level, and the power-on signal PWON is also at the L level.

Next, in order to determine the normal connection with the backup power supply board 27, the potential of the inspection line LN is determined (ST42). Under normal conditions, the potential of the inspection line LN is at the L level (see FIG. 4), but in the unlikely event that it is disconnected (disconnected), it will be at the H level. Therefore, when it is determined that the device is not connected, the infinite loop process is started as it is. At the timing of step ST42, since the CPU is in the interrupt disabled state, the operation shown in FIG. 11B is not executed.

Moreover, since the power-on signal PWON output from the payout control unit 24 remains at the L level, the main control unit 21 cannot escape from the processes of steps ST4 to ST4, and the gaming machine does not start. Therefore, the non-connection abnormality with the backup power supply board 27 will be detected by the staff before the start of business, and there is no possibility that the abnormal state of the backup power supply VBB will continue for many days.

On the other hand, when a normal connection is confirmed in step ST42, the CPU is in the interrupt enabled state through the processes of steps ST43 to ST49, and the power-on signal is turned on (ST50). The processing of steps ST43 to ST49 is almost the same as the processing of steps ST6 to ST14 of FIG. 8 in the main control unit 21 except for step ST11.

Subsequently, the timer interrupt processing will be described with reference to FIG. 11 (b). First, the power supply monitoring process for determining the power failure signal ABN and executing the necessary backup process when the power failure is abnormal is executed (ST70). The specific operation content is the same as the process of step ST20 in the main control unit 21.

Next, a switch signal related to a supply shortage detection signal, a ball clogging detection signal, a counting error signal, a door frame opening signal, and the like is acquired (ST71), and a timer value related to the payout operation is subtracted and updated (ST72).

Next, the serial reception port SIORX is accessed, and if the prize ball command SYO is received, it is acquired (ST73). FIG. 11C is a flowchart showing the prize ball command reception process. First, the corresponding bit (received data full bit) of the status register Str is referred to, and it is determined whether 1-byte data has been acquired (Data Full) or whether the received data does not exist (Not Full). (ST60).

Here, if it is in the Not Full state, the process ends without doing anything. On the other hand, in the Data Full state, the presence or absence of a communication abnormality is determined by referring to the noise error bit and the framing error bit of the status register Str (ST61). As described above, the noise error bit determines whether or not any of the communication abnormalities shown in FIGS. 10 (c) to 10 (e) has occurred during the acquisition of 1-byte data of the prize ball command SYO. Shown. Further, the framing error bit indicates whether or not a communication abnormality in which the stop bit cannot be detected has occurred after acquiring 1-byte data which is a prize ball command.

Then, when it is determined that some kind of communication abnormality has occurred, the communication abnormality signal Err is changed to the L level (ST65). As a result, the main control unit 21 grasps that the prize ball command has not been transmitted normally, controls the firing permission signal SHOOT to the OFF state (ST24 in FIG. 8B), and then wins the prize. The transmission of the ball command SYO is stopped (ST35 in FIG. 9C). The communication abnormality signal Err changed to the L level is returned to the normal H level in the subsequent processing of step ST50 after the power supply is reset.

As shown in FIG. 11C, when it is determined that some kind of communication abnormality has occurred, the prize ball start process (ST64) is skipped, so that the game ball is not paid out to the player. At first glance, this may seem like a disadvantage to the player, but (1) the possibility of communication abnormalities is extremely low (experimentally almost zero), and (2) when communication abnormalities occur, staff members It is expected that customer service will be provided in which a staff member throws a game ball into the winning opening after the power is reset after the maintenance work by (3). Considering that even if the prize ball operation is executed, the player who cannot confirm the execution remains dissatisfied, it is most rational to skip the prize ball start process (ST64) when the communication is abnormal. Be done.

The meaning of not paying out the game ball to the player has been described above. However, following the process of step ST65, the process of reading the 1-byte acquisition data related to the communication error (Read access) and the process of writing to the status register Str. (Write access) clears all noise error bits.

This is because the payout control unit 24 reads out the prize ball command SYO that has been transmitted before the main control unit 21 executes the transmission stop processing of the prize ball command SYO (ST35 in FIG. 9C). This is a process to prevent it. That is, since the noise error bit is cleared (ST66), the next prize ball command can be acquired at the time of the next timer interrupt of the payout control unit 24, and unless a communication abnormality occurs (ST61: Normal), The payout operation corresponding to this prize ball command can be executed (ST62 to ST64).

Next, the normal operation in which no communication abnormality occurs will be described. Since the timing of step ST62 is the Data Full state in which the received data is stored in the received data register RPr, the CPU reads the prize ball command SYO from the received data register RPr (ST62). Next, for the prize ball command SYO, a matching operation is executed between the dummy bit and the significant bit, and it is confirmed that the command is not an invalid command (ST63). When the prize ball command SYO has the configuration shown in FIG. 9A, it is determined whether or not the bit addition result of the upper 4 bits and the lower 4 bits is FFH. It is also determined whether or not the prize ball command SYO that should not be transmitted has been received.

Then, in the unlikely event that a predetermined calculation result cannot be obtained by these matching operations, the process proceeds to step ST65, the firing operation and the prize ball operation are stopped, and the communication abnormality notification operation is started. (ST34). This is to respond appropriately to the occurrence of illegal activities. In addition, it is virtually unthinkable that one bit of a legitimate prize ball command will be garbled and the matching operation will fail in the state where communication abnormalities such as noise error and framing error do not occur. The content of the abnormality notification in the case of failure may be the content considering the possibility of the occurrence of illegal acts.

Since the prize ball command reception process (ST73) has been described above, the description will be continued by returning to FIG. 11 (b). When the prize ball command reception process (ST73) is completed, the processes related to the ball lending operation (ST74, ST75) are executed, and the prize ball operation set to start in the process of step ST64 in FIG. In order to execute the ball lending operation, the drive data Φ1 to Φ4 of the payout motor Mo are appropriately updated (ST76).

Next, if an abnormality in the payout operation such as ball clogging or out of supply is detected, that fact is transmitted to the main control unit 21 (ST77), and the drive data Φ1 to Φ4 updated in step ST76 are transmitted. Output to the payout motor Mo to finish interrupt processing (ST78).

Although the examples have been described in detail above, the specific description contents are not particularly limited to the present invention and can be appropriately changed.

GM gaming machine 21 Main control means 24 Payout control means 20 DC generation means 24 Main circuit board 27 Backup power supply board

Claims (2)

A gaming machine capable of executing a lottery process based on a predetermined switch signal and executing a game operation according to the lottery result.
A first control means for the central overall control of the game operation by running the lottery process, the serially transmitted from the first control means, based on the serial prize balls instruction with the start and stop bits prize balls A second control means that executes a control operation, and a DC generation means that distributes a DC voltage generated by rectifying the AC voltage of an AC power supply distributed to the game machine to the first control means and the second control means. Consists of,
The first control means is configured to have a transmission port for serially transmitting the serial prize ball instruction accompanied by the start bit and the stop bit at a predetermined baud rate [bps].
The second control means includes a computer circuit that receives the serial prize ball instruction via the receiving port and executes the prize ball control operation.
The computer circuit
After interruption of the AC power source is also the backup power board backup power to maintain the contents stored in the volatile memory is mounted in the computer circuit, after power, unless the normality determination, it is configured so as not to shift to subsequent processing and along with that,
Based on the determination clock that changes at a speed that is an integral multiple of the baud rate [bps], the start bit, the stop bit, and the serial prize ball instruction are all level-determined a plurality of times for each bit. A gaming machine characterized in that it is configured to perform error processing when it is not determined that the two are at the same level. The DC generating means is configured to further distribute an AC voltage to the second controlling means.
The second control means is a transistor whose power supply voltage is a DC voltage distributed by the DC generation means, and is a power failure detection transistor that operates ON / OFF based on the AC voltage distributed by the DC generation means. Further possessed and configured
The gaming machine according to claim 1, wherein when the DC voltage or the AC voltage drops abnormally, the power failure detection transistor operates OFF to output an abnormal level signal.

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