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JP6897455B2 - Electronic devices and manufacturing methods for electronic devices - Google Patents
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JP6897455B2 - Electronic devices and manufacturing methods for electronic devices - Google Patents

Electronic devices and manufacturing methods for electronic devices Download PDF

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JP6897455B2
JP6897455B2 JP2017185868A JP2017185868A JP6897455B2 JP 6897455 B2 JP6897455 B2 JP 6897455B2 JP 2017185868 A JP2017185868 A JP 2017185868A JP 2017185868 A JP2017185868 A JP 2017185868A JP 6897455 B2 JP6897455 B2 JP 6897455B2
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sealing
main surface
electronic device
sealing portion
substrate
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JP2019062418A (en
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好彦 横山
好彦 横山
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Seiko Epson Corp
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Description

本発明は、電子デバイスおよび電子デバイスの製造方法に関する。 The present invention relates to an electronic device and a method for manufacturing the electronic device.

半導体基板を用いて形成する、例えばトランジスター等の素子を含む半導体装置や電子デバイスにおいて、素子の周囲の空洞を密閉する方法として、特許文献1では、素子とメッシュ構造のフィルターとを形成した半導体基板に、素子との間に空洞を形成しつつ、素子を覆うカバー膜を設け、半導体基板の裏面側からフィルターに達するバイアホールに、半導体基板の裏面側からバイアホールを介してフィルターを覆う薄膜を形成することで、素子周囲の空洞を密閉性良く短時間で密閉する半導体装置の製造方法が開示されている。 As a method of sealing a cavity around an element in a semiconductor device or electronic device including an element such as a transistor, which is formed by using a semiconductor substrate, Patent Document 1 describes a semiconductor substrate in which the element and a filter having a mesh structure are formed. A cover film covering the device is provided while forming a cavity between the device and the device, and a thin film covering the filter from the back surface side of the semiconductor substrate via the via hole is provided on the via hole that reaches the filter from the back surface side of the semiconductor substrate. A method for manufacturing a semiconductor device that seals a cavity around an element with good airtightness in a short time by forming the device is disclosed.

特開2009−170588号公報Japanese Unexamined Patent Publication No. 2009-170588

しかしながら、特許文献1に記載の製造方法では、素子周囲の空洞を密閉するためにバイアホールを介してメッシュ構造のフィルターを覆う薄膜を形成する際に、封止用の薄膜がフィルターのメッシュ部から空洞内に入り込み、素子表面に付着し、特性が劣化してしまうという課題があった。 However, in the manufacturing method described in Patent Document 1, when a thin film covering a filter having a mesh structure is formed through a via hole in order to seal a cavity around an element, a thin film for sealing is released from the mesh portion of the filter. There is a problem that it enters the cavity, adheres to the surface of the element, and deteriorates its characteristics.

本発明は、上述の課題の少なくとも一部を解決するためになされたものであり、以下の形態又は適用例として実現することが可能である。 The present invention has been made to solve at least a part of the above-mentioned problems, and can be realized as the following forms or application examples.

[適用例1]本適用例に係る電子デバイスは、素子基板の第1の主面と、前記第1の主面に接合される蓋部と、によって構成される収容空間に、素子部が収容されている電子デバイスであって、前記素子基板の前記第1の主面とは反対の第2の主面側に開口を備える凹部と、前記凹部の底部と前記第1の主面とで構成されるメンブレン部と、を有し、前記メンブレン部は、前記メンブレン部を貫通する封止孔を備え、前記メンブレン部の前記第1の主面側である第1の面および前記封止孔は、多孔質の第1の封止部で覆われており、前記メンブレン部の前記第2の主面側である第2の面(前記凹部の底部)および前記第1の封止部の前記第2の主面側の封止部面は、第2の封止部で覆われている、ことを特徴とする。 [Application Example 1] In the electronic device according to this application example, the element portion is accommodated in an accommodation space composed of a first main surface of the element substrate and a lid portion joined to the first main surface. The electronic device is composed of a recess having an opening on the second main surface side of the element substrate opposite to the first main surface, a bottom portion of the recess, and the first main surface. The membrane portion is provided with a sealing hole penetrating the membrane portion, and the first surface of the membrane portion on the first main surface side and the sealing hole are , A second surface (bottom of the recess) of the membrane portion, which is covered with a porous first sealing portion and is on the second main surface side of the membrane portion, and the first sealing portion of the first sealing portion. The sealing portion surface on the main surface side of No. 2 is covered with the second sealing portion.

本適用例によれば、素子基板と蓋部とによって構成される収容空間を、素子基板に設けられた封止孔を収容空間側から多孔質の第1の封止部で覆い、第1の封止部の封止孔側の封止部面を金属の第2の封止部で覆うことにより、気密封止することができる。なお、封止孔を収容空間側から塞ぐ第1の封止部が多孔質であるため、第2の封止部の粒子が第1の封止部の内部を通り、収容空間まで達することができない。つまり、第1の封止部が複雑に繋がった多数の細孔により構成されている。そのため、第2の封止部を成膜中に、第2の封止部の粒子が第1の封止部を構成する多数の細孔に付着するので、収容空間に入り込むことがない。従って、収容空間を気密封止する際に、第2の封止部の粒子が素子部に付着し、素子部の特性が劣化することを低減することができ、安定な特性を有する電子デバイスを得ることができる。 According to this application example, the accommodating space composed of the element substrate and the lid portion is covered with a porous first sealing portion from the accommodating space side in a sealing hole provided in the element substrate, and the first By covering the sealing portion surface on the sealing hole side of the sealing portion with a second sealing portion of metal, airtight sealing can be performed. Since the first sealing portion that closes the sealing hole from the accommodation space side is porous, the particles of the second sealing portion may pass through the inside of the first sealing portion and reach the accommodation space. Can not. That is, the first sealing portion is composed of a large number of pores that are intricately connected. Therefore, during the film formation of the second sealing portion, the particles of the second sealing portion adhere to a large number of pores constituting the first sealing portion, so that the particles do not enter the accommodation space. Therefore, when the accommodation space is airtightly sealed, it is possible to reduce the particles of the second sealing portion from adhering to the element portion and deteriorating the characteristics of the element portion, and an electronic device having stable characteristics can be obtained. Obtainable.

[適用例2]上記適用例に記載の電子デバイスにおいて、前記第1の封止部は、酸化アルミニウムのスパッタ膜であることが好ましい。 [Application Example 2] In the electronic device described in the above application example, the first sealing portion is preferably a sputtered film of aluminum oxide.

本適用例によれば、第1の封止部が酸化アルミニウムであるため、酸化アルミニウムをスパッタリングすることで、容易に多孔質の酸化アルミニウムのスパッタ膜を形成することができる。 According to this application example, since the first sealing portion is aluminum oxide, a porous aluminum oxide sputtered film can be easily formed by sputtering aluminum oxide.

[適用例3]上記適用例に記載の電子デバイスにおいて、前記第2の封止部は、金属膜又は金属酸化膜であることが好ましい。 [Application Example 3] In the electronic device described in the above application example, the second sealing portion is preferably a metal film or a metal oxide film.

本適用例によれば、第2の封止部が、金属膜又は金属酸化膜であるため、緻密な膜を容易に形成することができ、収容空間を高い気密性で維持することができる。 According to this application example, since the second sealing portion is a metal film or a metal oxide film, a dense film can be easily formed and the accommodation space can be maintained with high airtightness.

[適用例4]上記適用例に記載の電子デバイスにおいて、前記金属膜が前記第2の主面に配設される導電膜から延設されていることが好ましい。 [Application Example 4] In the electronic device described in the above application example, it is preferable that the metal film extends from a conductive film disposed on the second main surface.

本適用例によれば、第2の主面に配設される導電膜の形成と同時に収容空間を気密封止する第2の封止部を形成することができ、高い生産性を得ることができる。 According to this application example, it is possible to form a second sealing portion for airtightly sealing the accommodation space at the same time as forming the conductive film disposed on the second main surface, and high productivity can be obtained. it can.

[適用例5]本適用例に係る電子デバイスの製造方法は、素子部が形成されたSOI基板を準備する基板準備工程と、前記SOI基板の前記素子部が形成されている側の第1の主面に、多孔質の第1の封止部を形成する第1の封止部形成工程と、前記SOI基板の前記第1の主面に、前記素子部の収容空間を構成する蓋部を接合する蓋部接合工程と、平面視における前記SOI基板の前記第1の封止部の形成領域内に、前記SOI基板の前記第1の主面と反対の第2の主面側に開口し、前記SOI基板によるメンブレン部を構成する凹部を形成する凹部形成工程と、前記SOI基板の前記第1の主面と反対の第2の主面側から前記凹部の底部の一部を除去し、前記メンブレン部に封止孔を形成する封止孔形成工程と、前記収容空間を所定の空間環境とし、前記封止孔を金属の第2の封止部で気密封止する封止工程と、を含む、ことを特徴とする。 [Application Example 5] The method for manufacturing an electronic device according to this application example includes a substrate preparation step of preparing an SOI substrate on which an element portion is formed, and a first method on the side of the SOI substrate on which the element portion is formed. A first sealing portion forming step of forming a porous first sealing portion on the main surface, and a lid portion forming an accommodation space for the element portion are provided on the first main surface of the SOI substrate. In the lid joining step of joining and in the formation region of the first sealing portion of the SOI substrate in a plan view, an opening is made on the second main surface side of the SOI substrate opposite to the first main surface. A recess forming step of forming the recess forming the membrane portion by the SOI substrate and a part of the bottom portion of the recess are removed from the second main surface side opposite to the first main surface of the SOI substrate. A sealing hole forming step of forming a sealing hole in the membrane portion, a sealing step of setting the accommodation space as a predetermined space environment, and airtightly sealing the sealing hole with a second sealing portion of metal. It is characterized by including.

本適用例によれば、素子部が形成されたSOI基板に多孔質の第1の封止部を形成し、蓋部を接合した後にSOI基板の第1の封止部と重なる位置に封止孔を形成し、封止孔を第2の封止部で覆うことで、SOI基板と蓋部とによって構成され、素子部が収容される収容空間を気密封止することができる。なお、第1の封止部が多孔質であるため、封止孔を金属の第2の封止部で気密封止する際に、金属の第2の封止部が第1の封止部の内部を通り、収容空間まで達することができない。つまり、第1の封止部が複雑に繋がった多数の細孔により構成されている。そのため、第2の封止部を成膜中に、第2の封止部の粒子が第1の封止部を構成する多数の細孔に付着するので、収容空間に入り込むことがない。従って、収容空間を気密封止する際に、第2の封止部の粒子が素子部に付着し、素子部の特性が劣化することを低減することができ、安定な特性を有する電子デバイスを製造することができる。 According to this application example, a porous first sealing portion is formed on the SOI substrate on which the element portion is formed, and the lid portion is joined and then sealed at a position overlapping the first sealing portion of the SOI substrate. By forming the holes and covering the sealing holes with the second sealing portion, the accommodation space formed by the SOI substrate and the lid portion and accommodating the element portion can be hermetically sealed. Since the first sealing portion is porous, when the sealing hole is hermetically sealed with the second sealing portion of the metal, the second sealing portion of the metal is the first sealing portion. It cannot reach the containment space through the interior of the building. That is, the first sealing portion is composed of a large number of pores that are intricately connected. Therefore, during the film formation of the second sealing portion, the particles of the second sealing portion adhere to a large number of pores constituting the first sealing portion, so that the particles do not enter the accommodation space. Therefore, when the accommodation space is airtightly sealed, it is possible to reduce the particles of the second sealing portion from adhering to the element portion and deteriorating the characteristics of the element portion, so that an electronic device having stable characteristics can be obtained. Can be manufactured.

[適用例6]上記適用例に記載の電子デバイスの製造方法において、前記封止工程は、前記第2の主面側に導電膜を形成する導電膜形成工程を含む、ことが好ましい。 [Application Example 6] In the method for manufacturing an electronic device according to the above application example, it is preferable that the sealing step includes a conductive film forming step of forming a conductive film on the second main surface side.

本適用例によれば、第2の主面に形成される導電膜の形成と同時に収容空間を気密封止する第2の封止部を形成することができ、高い生産性を得ることができる。 According to this application example, it is possible to form a second sealing portion that airtightly seals the accommodation space at the same time as forming the conductive film formed on the second main surface, and high productivity can be obtained. ..

第1実施形態に係る電子デバイスの蓋部を省略した平面外観図。The plan view which omitted the lid part of the electronic device which concerns on 1st Embodiment. 図1中のA−A線の断面を示す断面図。The cross-sectional view which shows the cross section of the line AA in FIG. 図2中のB部の部分拡大図。A partially enlarged view of part B in FIG. 第1実施形態に係る電子デバイスの製造方法を示すフローチャート図。The flowchart which shows the manufacturing method of the electronic device which concerns on 1st Embodiment. 第1実施形態に係る電子デバイスの製造工程を示す断面図。The cross-sectional view which shows the manufacturing process of the electronic device which concerns on 1st Embodiment. 第1実施形態に係る電子デバイスの製造工程を示す断面図。The cross-sectional view which shows the manufacturing process of the electronic device which concerns on 1st Embodiment. 第1実施形態に係る電子デバイスの製造工程を示す断面図。The cross-sectional view which shows the manufacturing process of the electronic device which concerns on 1st Embodiment. 第1実施形態に係る電子デバイスの製造工程を示す断面図。The cross-sectional view which shows the manufacturing process of the electronic device which concerns on 1st Embodiment. 第1実施形態に係る電子デバイスの製造工程を示す断面図。The cross-sectional view which shows the manufacturing process of the electronic device which concerns on 1st Embodiment. 第1実施形態に係る電子デバイスの製造工程を示す断面図。The cross-sectional view which shows the manufacturing process of the electronic device which concerns on 1st Embodiment. 第2実施形態に係る電子デバイスの構造を示す断面図。The cross-sectional view which shows the structure of the electronic device which concerns on 2nd Embodiment. 第2実施形態に係る電子デバイスの製造方法を示すフローチャート図。The flowchart which shows the manufacturing method of the electronic device which concerns on 2nd Embodiment. 第3実施形態に係る電子デバイスの構造を示す断面図。The cross-sectional view which shows the structure of the electronic device which concerns on 3rd Embodiment.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、以下に示す各図においては、各構成要素を図面上で認識され得る程度の大きさとするため、各構成要素の寸法や比率を実際の構成要素とは適宜に異ならせて記載する場合がある。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each of the drawings shown below, in order to make each component large enough to be recognized on the drawing, the dimensions and ratios of each component may be described differently from the actual components as appropriate. is there.

<第1実施形態>
[電子デバイスの構造]
先ず、第1の実施形態に係る電子デバイス1について、図1、図2、および図3を参照して説明する。
図1は、第1の実施形態に係る電子デバイス1の蓋部20を省略した平面外観図であり、図2は、図1中のA−A線の断面を示す断面図であり、図3は、図2中のB部の部分拡大図である。なお、図1〜図3、および以下に示す図5〜図11、図13では、互いに直交する3つの軸として、X軸、Y軸、Z軸を図示している。
<First Embodiment>
[Structure of electronic device]
First, the electronic device 1 according to the first embodiment will be described with reference to FIGS. 1, 2, and 3.
FIG. 1 is a plan external view in which the lid 20 of the electronic device 1 according to the first embodiment is omitted, and FIG. 2 is a cross-sectional view showing a cross section of the line AA in FIG. Is a partially enlarged view of part B in FIG. In addition, in FIGS. 1 to 3 and 5 to 11 and 13 shown below, the X axis, the Y axis, and the Z axis are shown as three axes orthogonal to each other.

図2および図3に示すように第1実施形態に係る電子デバイス1は、単結晶シリコンのシリコン基板層とシリコン層との間に、酸化シリコン層が挿入された、いわゆるSOI(Silicon on Insulator)基板、あるは単結晶シリコンを主材料とするシリコン基板などの半導体基板を基板材料M(図示しない)として形成される素子基板10と、素子基板10の第1の主面10aに接合される蓋部20と、を備えている。 As shown in FIGS. 2 and 3, the electronic device 1 according to the first embodiment has a so-called SOI (Silicon on Insulator) in which a silicon oxide layer is inserted between a silicon substrate layer and a silicon layer of single crystal silicon. An element substrate 10 formed of a substrate, or a semiconductor substrate such as a silicon substrate whose main material is single crystal silicon, as a substrate material M (not shown), and a lid joined to a first main surface 10a of the element substrate 10. A unit 20 and a unit 20 are provided.

蓋部20は、素子基板10の第1の主面10aに対向する側に蓋部キャビティー21を有し、素子基板10の第1の主面10aと蓋部20の接合面20aとが接合されることにより収容空間Sの一部を構成する。蓋部20の材料は特に限定は無いが、ガラスが好適に用いられる。 The lid portion 20 has a lid portion cavity 21 on the side of the element substrate 10 facing the first main surface 10a, and the first main surface 10a of the element substrate 10 and the joint surface 20a of the lid portion 20 are joined. As a result, a part of the accommodation space S is formed. The material of the lid portion 20 is not particularly limited, but glass is preferably used.

素子基板10は、SOI基板の酸化シリコン(SiO2)層と、シリコン(Si)層と、が積層された素子形成層11と、シリコン(Si)層の基部12と、により構成される。素子基板10は、いわゆるMEMS(Micro Electro Mechanical System)によって形成される、例えば振動子であるような素子部13が形成され、素子部13の形成領域の基部12には基部キャビティー16が形成され、基部キャビティー16と、蓋部20の蓋部キャビティー21と、によって素子部13を収容する収容空間Sが構成される。 The element substrate 10 is composed of an element forming layer 11 in which a silicon oxide (SiO 2 ) layer and a silicon (Si) layer of an SOI substrate are laminated, and a base 12 of the silicon (Si) layer. The element substrate 10 is formed by a so-called MEMS (Micro Electro Mechanical System), for example, an element portion 13 such as an oscillator is formed, and a base cavity 16 is formed at a base portion 12 of a formation region of the element portion 13. The base cavity 16 and the lid cavity 21 of the lid 20 form a storage space S for accommodating the element portion 13.

素子基板10の基部キャビティー16の外郭部における第1の主面10aには、多孔質の第1の封止部30が設けられている。また、素子基板10と蓋部20とが重なる方向からの平面視で(Z軸方向から見て)、素子基板10の第1の封止部30と重なる領域には、第1の主面10aとは反対の第2の主面10b側に開口する凹部17が設けられており、凹部17の底部17aと第1の主面10aとで構成されるメンブレン部15を有している。つまり、メンブレン部15は、素子形成層11に形成されており、中央部にメンブレン部15を貫通する封止孔14が設けられている。 A porous first sealing portion 30 is provided on the first main surface 10a of the outer shell portion of the base cavity 16 of the element substrate 10. Further, in a plan view from the direction in which the element substrate 10 and the lid portion 20 overlap (when viewed from the Z-axis direction), the first main surface 10a is located in the region overlapping the first sealing portion 30 of the element substrate 10. A recess 17 that opens on the side of the second main surface 10b opposite to the above is provided, and has a membrane portion 15 composed of a bottom portion 17a of the recess 17 and a first main surface 10a. That is, the membrane portion 15 is formed in the element forming layer 11, and a sealing hole 14 penetrating the membrane portion 15 is provided in the central portion.

メンブレン部15の、第1の主面10a側である第1の面15aおよび封止孔14は、多孔質の第1の封止部30で覆われており、メンブレン部15の第2の主面10b側である第2の面15b(凹部17の底部17a)および第1の封止部30の第2の主面10b側の封止部面30aは、金属の第2の封止部40で覆われている。 The first surface 15a and the sealing hole 14 on the first main surface 10a side of the membrane portion 15 are covered with the porous first sealing portion 30, and the second main surface of the membrane portion 15 is covered. The second surface 15b (bottom 17a of the recess 17) on the surface 10b side and the sealing portion surface 30a on the second main surface 10b side of the first sealing portion 30 are the metal second sealing portion 40. It is covered with.

第1の主面10aにおいて、平面視で(Z軸方向から見て)、第1の封止部30、封止孔14、および凹部17の平面形状は、図1に示すように、矩形である。なお、本実施形態に係る電子デバイス1では、第1の封止部30、封止孔14、および凹部17の平面形状が矩形である形態を例示するが、これに限定されず、多角形や円形や楕円形でも構わない。また、それぞれが重なり合う第1の封止部30、封止孔14、および凹部17が1か所、形成されている形態を例示するが、これに限定されず、複数形成されていても良い。 On the first main surface 10a, in a plan view (viewed from the Z-axis direction), the planar shapes of the first sealing portion 30, the sealing hole 14, and the recess 17 are rectangular as shown in FIG. is there. In the electronic device 1 according to the present embodiment, a form in which the plane shape of the first sealing portion 30, the sealing hole 14, and the recess 17 is rectangular is exemplified, but the present invention is not limited to this, and is not limited to a polygonal shape. It may be circular or oval. Further, the embodiment in which the first sealing portion 30, the sealing hole 14, and the recess 17 that overlap each other are formed at one place is illustrated, but the present invention is not limited to this, and a plurality of sealing portions 30 may be formed.

第1の封止部30を構成する材料は、酸化アルミニウムが好ましく、第1の封止部30は、酸化アルミニウムをスパッタリングすることで形成されている。そのため、多数の細孔を有する多孔質の酸化アルミニウムのスパッタ膜を容易に形成することができる。なお、第1の封止部30が多数の細孔により構成されているため、収容空間Sの圧力と収容空間S外部と圧力とを同一とすることができ、例えば、電子デバイス1を減圧雰囲気中で第2の封止部40を成膜することで、収容空間Sを減圧雰囲気で気密封止することができる。また、第1の封止部30は、収容空間Sへ通じる細孔が複雑に繋がって形成されている。そのため、第2の封止部40を成膜中に、第2の封止部の粒子が第1の封止部30を構成する多数の細孔に付着するので、第2の封止部の粒子が収容空間に入り込むことを防止することができる。 The material constituting the first sealing portion 30 is preferably aluminum oxide, and the first sealing portion 30 is formed by sputtering aluminum oxide. Therefore, a porous aluminum oxide sputtered film having a large number of pores can be easily formed. Since the first sealing portion 30 is composed of a large number of pores, the pressure in the accommodation space S and the pressure outside the accommodation space S can be made the same. For example, the electronic device 1 has a reduced pressure atmosphere. By forming the second sealing portion 40 in the film, the accommodation space S can be hermetically sealed in a reduced pressure atmosphere. Further, the first sealing portion 30 is formed by intricately connecting pores leading to the accommodation space S. Therefore, during the film formation of the second sealing portion 40, the particles of the second sealing portion adhere to a large number of pores constituting the first sealing portion 30, so that the particles of the second sealing portion 30 are attached. It is possible to prevent particles from entering the containment space.

第2の封止部40を構成する材料は、金属膜又は金属酸化膜が好ましい。金属膜は、例えば、Au、Ag、Cu、Al、Pt等の金属であり、金属酸化膜は、例えば、ITO(Indium Tin Oxide)、IZO(Indium Zinc Oxide)、In33、SnO2、Sb含有SnO2、Al含有ZnO等の酸化物系導電材料等であることが好適である。第2の封止部40が金属膜又は金属酸化膜であるため、緻密な膜を容易に形成することができる。そのため、封止孔14における第1の封止部30の封止部面30aに点在する細孔に第2の封止部40の緻密な膜が入り込み、第1の封止部30の細孔を塞ぎ、その後、第2の封止部40が封止部面30aの上に積層されて封止孔14を塞ぐことで、収容空間Sを気密封止することができる。 The material constituting the second sealing portion 40 is preferably a metal film or a metal oxide film. The metal film is, for example, a metal such as Au, Ag, Cu, Al, Pt, and the metal oxide film is, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), In 3 O 3 , SnO 2 , It is preferable that an oxide-based conductive material such as Sb-containing SnO 2 or Al-containing ZnO is used. Since the second sealing portion 40 is a metal film or a metal oxide film, a dense film can be easily formed. Therefore, the dense film of the second sealing portion 40 enters the pores scattered on the sealing portion surface 30a of the first sealing portion 30 in the sealing hole 14, and the first sealing portion 30 is thin. The accommodation space S can be hermetically sealed by closing the holes and then stacking the second sealing portion 40 on the sealing portion surface 30a to close the sealing holes 14.

上述したように、第1実施形態に係る電子デバイス1では、素子基板10と蓋部20とによって構成される収容空間Sを、素子基板10に設けられた封止孔14を収容空間S側から多孔質の第1の封止部30で覆い、第1の封止部30の封止孔14側の封止部面30aを金属の第2の封止部40で覆うことにより、気密封止することができる。なお、封止孔14を収容空間S側から塞ぐ第1の封止部30が多孔質であるため、金属の第2の封止部40が第1の封止部30の内部を通り、収容空間Sまで達することができない。つまり、第1の封止部30が複雑に繋がった多数の細孔により構成されている。そのため、第2の封止部40を成膜中に、第2の封止部の粒子が第1の封止部30を構成する多数の細孔に付着するので、収容空間Sに入り込むことがない。従って、収容空間Sを気密封止する際に、第2の封止部40の粒子が素子部13に付着し、素子部13の特性が劣化することを低減することができ、安定な特性を有する電子デバイス1を得ることができる。 As described above, in the electronic device 1 according to the first embodiment, the accommodating space S composed of the element substrate 10 and the lid 20 is provided with the sealing hole 14 provided in the element substrate 10 from the accommodating space S side. Airtight sealing is performed by covering with a porous first sealing portion 30 and covering the sealing portion surface 30a on the sealing hole 14 side of the first sealing portion 30 with a metal second sealing portion 40. can do. Since the first sealing portion 30 that closes the sealing hole 14 from the accommodation space S side is porous, the second sealing portion 40 of the metal passes through the inside of the first sealing portion 30 and is accommodated. The space S cannot be reached. That is, the first sealing portion 30 is composed of a large number of pores in which the first sealing portion 30 is intricately connected. Therefore, during the film formation of the second sealing portion 40, the particles of the second sealing portion adhere to a large number of pores constituting the first sealing portion 30, so that the particles may enter the accommodation space S. Absent. Therefore, when the accommodation space S is hermetically sealed, it is possible to reduce the particles of the second sealing portion 40 from adhering to the element portion 13 and deteriorating the characteristics of the element portion 13, and to provide stable characteristics. The electronic device 1 to have can be obtained.

また、第1の封止部30が酸化アルミニウムであるため、酸化アルミニウムをスパッタリングすることで、容易に多孔質の酸化アルミニウムのスパッタ膜を形成することができる。また、スパッタリング以外の真空成膜方法を適宜用い、用いる材料も好適に選定しても良い。 Further, since the first sealing portion 30 is made of aluminum oxide, a porous aluminum oxide sputtered film can be easily formed by sputtering aluminum oxide. Further, a vacuum film forming method other than sputtering may be appropriately used, and the material to be used may be preferably selected.

また、第2の封止部40が、金属膜又は金属酸化膜であるため、緻密な膜を容易に形成することができ、収容空間Sを高い気密性で維持することができる。 Further, since the second sealing portion 40 is a metal film or a metal oxide film, a dense film can be easily formed, and the accommodation space S can be maintained with high airtightness.

[電子デバイスの製造方法]
次に、第1実施形態に係る電子デバイス1の製造方法について、図4〜図10を参照して説明する。
図4は、第1実施形態に係る電子デバイス1の製造方法を示すフローチャート図であり、図5〜図10は、第1実施形態に係る電子デバイス1の製造工程を示す断面図である。
[Manufacturing method of electronic devices]
Next, the manufacturing method of the electronic device 1 according to the first embodiment will be described with reference to FIGS. 4 to 10.
FIG. 4 is a flowchart showing a manufacturing method of the electronic device 1 according to the first embodiment, and FIGS. 5 to 10 are cross-sectional views showing a manufacturing process of the electronic device 1 according to the first embodiment.

〔基板準備工程〕
先ず、基板準備工程(S1)として、SOI基板を基板材料M(図示しない)として、図5に示すように素子部13が形成された素子基板10を準備する。素子基板10には、素子形成層11に素子部13が形成され、素子部13の形成領域の基部12には基部キャビティー16が形成されている。
[Board preparation process]
First, as a substrate preparation step (S1), the element substrate 10 on which the element portion 13 is formed is prepared as shown in FIG. 5, using the SOI substrate as the substrate material M (not shown). On the element substrate 10, the element portion 13 is formed in the element forming layer 11, and the base cavity 16 is formed in the base portion 12 of the forming region of the element portion 13.

〔第1の封止部形成工程〕
基板準備工程(S1)によって準備された素子基板10に対して第1の封止部形成工程(S2)が実行される。第1の封止部形成工程(S2)は、図6に示すように、後述する封止孔形成工程(S5)において形成される封止孔を囲うように平面形状の多孔質の第1の封止部30が形成される。第1の封止部30は、多孔質を有する酸化アルミニウムなどが好適に用いられる。第1の封止部30は、酸化アルミニウムを第1の主面10aの上にスパッタリング法により成膜された後に、フォトリソグラフィ法などによってパターニング形成されたレジストマスクを用いて所定の形状に形成される。
[First sealing portion forming step]
The first sealing portion forming step (S2) is executed on the element substrate 10 prepared by the substrate preparation step (S1). In the first sealing portion forming step (S2), as shown in FIG. 6, a planar porous first sealing hole is surrounded so as to surround the sealing hole formed in the sealing hole forming step (S5) described later. The sealing portion 30 is formed. For the first sealing portion 30, porous aluminum oxide or the like is preferably used. The first sealing portion 30 is formed into a predetermined shape by using a resist mask patterned and formed by a photolithography method or the like after a film of aluminum oxide is formed on the first main surface 10a by a sputtering method. To.

〔蓋部接合工程〕
蓋部接合工程(S3)では、素子基板10の第1の主面10aに、蓋部20の接合面20aを配置し、素子基板10の第1の主面10aに蓋部20を接合する。蓋部20は、本例ではガラス製の蓋部を用いる場合を例示するが、これに限定されず、例えばセラミックス、金属などであっても良い。
[Cover joining process]
In the lid joining step (S3), the joining surface 20a of the lid 20 is arranged on the first main surface 10a of the element substrate 10, and the lid 20 is joined to the first main surface 10a of the element substrate 10. In this example, the lid portion 20 exemplifies the case where a glass lid portion is used, but the lid portion 20 is not limited to this, and may be, for example, ceramics, metal, or the like.

図7に示すように、蓋部20は一方の側に蓋部キャビティー21を有し、蓋部キャビティー21を素子基板10に対向させるように蓋部20を配置させて素子基板10に接合させることにより、蓋部キャビティー21と、基部12の基部キャビティー16と、によって素子部13を収容する収容空間Sが構成される。 As shown in FIG. 7, the lid portion 20 has a lid portion cavity 21 on one side, and the lid portion 20 is arranged so that the lid portion cavity 21 faces the element substrate 10 and is joined to the element substrate 10. The lid cavity 21 and the base cavity 16 of the base 12 form a storage space S for accommodating the element portion 13.

蓋部20と、素子基板10と、の接合は、蓋部20の接合面20aと、素子基板10の第1の主面10aと、を例えば蓋部20にホウ珪酸ガラスを用い、シリコンを主成分とする素子基板10とを陽極接合する方法、あるいは、蓋部20の接合面20aと、素子基板10の第1の主面10aと、の間に低融点ガラス紛体を介して、融着接合させる方法、などが好適に用いられる。 The lid 20 and the element substrate 10 are joined by using the joint surface 20a of the lid 20 and the first main surface 10a of the element substrate 10, for example, borosilicate glass for the lid 20, and mainly silicon. A method of anodic bonding the element substrate 10 as a component, or fusion bonding between the bonding surface 20a of the lid portion 20 and the first main surface 10a of the element substrate 10 via a low melting point glass powder. A method of allowing the device to be used is preferably used.

〔凹部形成工程〕
凹部形成工程(S4)は、図8に示すように、素子基板10と蓋部20とが重なる方向からの平面視(Z軸方向から見て)における素子基板10の第1の封止部30の形成領域内に、基部12を形成するシリコンを素子形成層11に至るまでエッチングによって除去し、素子基板10の第1の主面10aと反対の第2の主面10b側に開口し、素子基板によるメンブレン部15を構成する凹部17を形成する。凹部17を形成することで、素子形成層11によるメンブレン部15が形成され、凹部17の底部17aにメンブレン部15の第2の面15bが現れる。
[Recess formation process]
In the recess forming step (S4), as shown in FIG. 8, the first sealing portion 30 of the element substrate 10 in a plan view (viewed from the Z-axis direction) from the direction in which the element substrate 10 and the lid portion 20 overlap each other. The silicon forming the base 12 is removed by etching up to the element forming layer 11 in the forming region of the element substrate 10, and the element is opened on the second main surface 10b side opposite to the first main surface 10a of the element substrate 10 to form the element. A recess 17 forming the membrane portion 15 made of the substrate is formed. By forming the recess 17, the membrane portion 15 is formed by the element forming layer 11, and the second surface 15b of the membrane portion 15 appears on the bottom 17a of the recess 17.

〔封止孔形成工程〕
封止孔形成工程(S5)は、図9に示すように、平面視で(Z軸方向から見て)、第1の封止部30と凹部17との重なる領域の素子形成層11を形成する酸化シリコンおよびシリコンを第1の封止部30に至るまでエッチングによって除去し、封止孔14を形成する。つまり、メンブレン部15の第2の面15b(凹部17の底部17a)の一部をエッチングして除去することで、メンブレン部15に封止孔14を形成する。
[Sealing hole forming process]
In the sealing hole forming step (S5), as shown in FIG. 9, in a plan view (viewed from the Z-axis direction), the element forming layer 11 in the region where the first sealing portion 30 and the recess 17 overlap is formed. Silicon oxide and silicon to be removed are removed by etching up to the first sealing portion 30, and a sealing hole 14 is formed. That is, a sealing hole 14 is formed in the membrane portion 15 by etching and removing a part of the second surface 15b (bottom portion 17a of the recess 17) of the membrane portion 15.

〔封止工程〕
次に、収容空間Sの空間環境を所定の環境に維持する封止工程(S6)が実行される。封止工程(S6)では、収容空間Sと、収容空間Sの外部と、の間に配設される多孔質の第1の封止部30と封止孔14とを介して、収容空間Sの内部空間の気体、例えば空気、を抜気し、収容空間Sを減圧状態に保持する。
[Sealing process]
Next, a sealing step (S6) for maintaining the spatial environment of the accommodation space S in a predetermined environment is executed. In the sealing step (S6), the accommodating space S is interposed between the accommodating space S and the outside of the accommodating space S, and the porous first sealing portion 30 and the sealing hole 14. The gas in the internal space of the above, for example, air, is evacuated, and the accommodation space S is maintained in a reduced pressure state.

その後、図10に示すように、封止工程(S6)は、収容空間Sの所望の空間環境である減圧雰囲気状態を保持したまま、封止孔14を覆うように第2の主面10b側から第2の封止部40を形成し、収容空間Sが気密封止され、第1実施形態に係る電子デバイス1が得られる。具体的には、収容空間S内を減圧雰囲気状態として、メンブレン部15の第2の主面10b側である第2の面15bと、メンブレン部15の上に形成されている第1の封止部30の封止部面30aとを、スパッタリング法により形成した第2の封止部40で覆うことにより、収容空間Sが気密封止される。 After that, as shown in FIG. 10, in the sealing step (S6), the second main surface 10b side is covered so as to cover the sealing hole 14 while maintaining the reduced pressure atmosphere state which is the desired space environment of the accommodation space S. A second sealing portion 40 is formed from the above, and the accommodation space S is hermetically sealed to obtain the electronic device 1 according to the first embodiment. Specifically, the inside of the accommodation space S is set to a reduced pressure atmosphere, and the second surface 15b on the second main surface 10b side of the membrane portion 15 and the first sealing formed on the membrane portion 15 are formed. The accommodation space S is airtightly sealed by covering the sealing portion surface 30a of the portion 30 with the second sealing portion 40 formed by the sputtering method.

ここで、第2の封止部40は、金属膜又は金属酸化膜が好ましい。金属膜は、例えば、Au、Ag、Cu、Al、Pt等の金属であり、金属酸化膜は、例えば、ITO(Indium Tin Oxide)、IZO(Indium Zinc Oxide)、In33、SnO2、Sb含有SnO2、Al含有ZnO等の酸化物系導電材料等であることが好適である。 Here, the second sealing portion 40 is preferably a metal film or a metal oxide film. The metal film is, for example, a metal such as Au, Ag, Cu, Al, Pt, and the metal oxide film is, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), In 3 O 3 , SnO 2 , It is preferable that an oxide-based conductive material such as Sb-containing SnO 2 or Al-containing ZnO is used.

以上の工程により、高い気密性を有する電子デバイス1を製造することができる。 By the above steps, the electronic device 1 having high airtightness can be manufactured.

上述したように、第1実施形態に係る電子デバイス1において、素子部13が形成された素子基板10(SOI基板)に多孔質の第1の封止部30を形成し、蓋部20を接合した後に素子基板10の第1の封止部30と重なる位置に封止孔14を形成し、封止孔14を第2の封止部40で覆うことで、素子基板10と蓋部20とによって構成され、素子部13が収容される収容空間Sを気密封止することができる。なお、第1の封止部30が多孔質であるため、封止孔14を金属の第2の封止部40で気密封止する際に、金属の第2の封止部40が第1の封止部30の内部を通り、収容空間Sまで達することができない。つまり、第1の封止部30が多数の細孔により構成されているため、収容空間Sへ直線的に連通する細孔が形成され難い。そのため、金属の第2の封止部40が成膜中に第1の封止部30を構成する多数の細孔に付着するので、収容空間Sに入り込むことがない。従って、収容空間Sを気密封止する際に、第2の封止部40が素子部13に付着し、素子部13の特性が劣化することを低減することができ、安定な特性を有する電子デバイス1を製造することができる。 As described above, in the electronic device 1 according to the first embodiment, the porous first sealing portion 30 is formed on the element substrate 10 (SOI substrate) on which the element portion 13 is formed, and the lid portion 20 is joined. After that, a sealing hole 14 is formed at a position overlapping the first sealing portion 30 of the element substrate 10, and the sealing hole 14 is covered with the second sealing portion 40 to form the element substrate 10 and the lid portion 20. The accommodation space S in which the element unit 13 is accommodated can be hermetically sealed. Since the first sealing portion 30 is porous, when the sealing hole 14 is hermetically sealed by the second sealing portion 40 of the metal, the second sealing portion 40 of the metal is first. It cannot reach the accommodation space S through the inside of the sealing portion 30 of the above. That is, since the first sealing portion 30 is composed of a large number of pores, it is difficult to form pores that linearly communicate with the accommodation space S. Therefore, since the second sealing portion 40 of the metal adheres to a large number of pores constituting the first sealing portion 30 during the film formation, it does not enter the accommodation space S. Therefore, when the accommodation space S is hermetically sealed, it is possible to reduce that the second sealing portion 40 adheres to the element portion 13 and the characteristics of the element portion 13 are deteriorated, and the electrons having stable characteristics can be reduced. Device 1 can be manufactured.

<第2実施形態>
[電子デバイスの構造]
次に、第2実施形態に係る電子デバイス1aについて、図11を参照して説明する。
図11は、第2実施形態に係る電子デバイス1aの構造を示す断面図である。なお、第2実施形態に係る電子デバイス1aは、第1実施形態に係る電子デバイス1に備える第2の封止部40の形態が異なり、その他の構成要素は同じである。従って、第2実施形態に係る電子デバイス1aの説明には、第1実施形態に係る電子デバイス1と同じ構成要素には同じ符号を付し、説明は省略する。
<Second Embodiment>
[Structure of electronic device]
Next, the electronic device 1a according to the second embodiment will be described with reference to FIG.
FIG. 11 is a cross-sectional view showing the structure of the electronic device 1a according to the second embodiment. The electronic device 1a according to the second embodiment has a different form of the second sealing portion 40 provided in the electronic device 1 according to the first embodiment, and other components are the same. Therefore, in the description of the electronic device 1a according to the second embodiment, the same components as those of the electronic device 1 according to the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

第2実施形態に係る電子デバイス1aは、図11に示すように、メンブレン部15に設けられた封止孔14を気密封止する第2の封止部40aが形成されている。第2の封止部40aは、素子基板10の第2の主面10b側に形成された導電膜50が、基部12の凹部17まで延設されて形成されている。つまり、第2の封止部40aと導電膜50とは電気的に接続されおり、同一の材料で構成することができる。
なお、第2の主面10b側に形成された導電膜50は、素子基板10の第2の主面10bを実装基板に対向して実装した際に、実装基板からのノイズをシールドするためのものであり、収容空間Sに収容された素子部13への外部ノイズの影響を低減することができる。
As shown in FIG. 11, the electronic device 1a according to the second embodiment is formed with a second sealing portion 40a for airtightly sealing the sealing hole 14 provided in the membrane portion 15. The second sealing portion 40a is formed by extending the conductive film 50 formed on the second main surface 10b side of the element substrate 10 to the recess 17 of the base portion 12. That is, the second sealing portion 40a and the conductive film 50 are electrically connected and can be made of the same material.
The conductive film 50 formed on the second main surface 10b side is for shielding noise from the mounting substrate when the second main surface 10b of the element substrate 10 is mounted facing the mounting substrate. Therefore, the influence of external noise on the element unit 13 accommodated in the accommodation space S can be reduced.

導電膜50を構成する材料は、金属膜が好ましく、例えば、Au、Ag、Cu、Al、Pt等の金属がスパッタリング法によって成膜されるのが好適である。 The material constituting the conductive film 50 is preferably a metal film, and for example, it is preferable that a metal such as Au, Ag, Cu, Al, or Pt is formed by a sputtering method.

上述したように、第2実施形態に係る電子デバイス1aでは、封止孔14を気密封止する第2の封止部40aが導電膜50から延設されて形成されている。そのため、第2の主面10bに配設される導電膜50の形成と同時に収容空間Sを気密封止する第2の封止部40aを形成することができ、高い生産性を得ることができる。 As described above, in the electronic device 1a according to the second embodiment, the second sealing portion 40a for airtightly sealing the sealing hole 14 is formed so as to extend from the conductive film 50. Therefore, the second sealing portion 40a that airtightly seals the accommodation space S can be formed at the same time as the formation of the conductive film 50 arranged on the second main surface 10b, and high productivity can be obtained. ..

[電子デバイスの製造方法]
次に、第2実施形態に係る電子デバイス1aの製造方法について、図12を参照して説明する。
図12は、第2実施形態に係る電子デバイス1aの製造方法を示すフローチャート図である。なお、第2実施形態に係る電子デバイス1aの製造方法は、第1実施形態に係る電子デバイス1の製造方法における封止工程(S6)が異なる。従って、第1実施形態と同じ製造方法である基板準備工程(S1)〜封止孔形成工程(S5)の説明は省略する。
[Manufacturing method of electronic devices]
Next, a method of manufacturing the electronic device 1a according to the second embodiment will be described with reference to FIG.
FIG. 12 is a flowchart showing a manufacturing method of the electronic device 1a according to the second embodiment. The method for manufacturing the electronic device 1a according to the second embodiment is different from the sealing step (S6) in the method for manufacturing the electronic device 1 according to the first embodiment. Therefore, the description of the substrate preparation step (S1) to the sealing hole forming step (S5), which are the same manufacturing methods as in the first embodiment, will be omitted.

〔封止工程〕
第2実施形態としての電子デバイス1aの製造方法における封止工程(S60)は、図12に示すように、導電膜形成工程(S61)を含んでいる。
[Sealing process]
As shown in FIG. 12, the sealing step (S60) in the method for manufacturing the electronic device 1a as the second embodiment includes a conductive film forming step (S61).

〔導電膜形成工程〕
導電膜形成工程(S61)は、導電膜50、例えば、Au、Ag、Cu、Al、Pt等の金属を、素子基板10の第2の主面10b側からスパッタリングし、素子基板10の第2の主面10b、メンブレン部15の第2の面15b、および第1の封止部30の封止部面30aの上に積層することで、メンブレン部15に設けられた封止孔14を気密封止する第2の封止部40aを形成することができる。
[Conducting film forming process]
In the conductive film forming step (S61), the conductive film 50, for example, a metal such as Au, Ag, Cu, Al, Pt, is sputtered from the second main surface 10b side of the element substrate 10, and the second main surface of the element substrate 10 is formed. By laminating on the main surface 10b, the second surface 15b of the membrane portion 15, and the sealing portion surface 30a of the first sealing portion 30, the sealing holes 14 provided in the membrane portion 15 are aired. A second sealing portion 40a to be tightly sealed can be formed.

上述したように、第2実施形態に係る電子デバイス1aの製造方法において、封止工程(S60)の製造方法では,導電膜50を形成する導電膜形成工程(S61)によって、素子基板10の第2の主面10bに導電膜50を形成する際に、メンブレン部15に設けられた封止孔14を覆う第2の封止部40aを同時に形成することができる。従って、高い気密性を有する電子デバイス1aを高い生産性で製造することができる。 As described above, in the manufacturing method of the electronic device 1a according to the second embodiment, in the manufacturing method of the sealing step (S60), the conductive film forming step (S61) for forming the conductive film 50 is performed to form the element substrate 10. When the conductive film 50 is formed on the main surface 10b of 2, the second sealing portion 40a that covers the sealing hole 14 provided in the membrane portion 15 can be formed at the same time. Therefore, the electronic device 1a having high airtightness can be manufactured with high productivity.

<第3実施形態>
[電子デバイスの構造]
次に、第3実施形態に係る電子デバイス1bについて、図13を参照して説明する。
図13は、第3実施形態に係る電子デバイス1bの構造を示す断面図である。なお、第3実施形態に係る電子デバイス1bは、第1実施形態に係る電子デバイス1に備える凹部17の形態が異なり、その他の構成要素は同じである。従って、第3実施形態に係る電子デバイス1bの説明には、第1実施形態に係る電子デバイス1と同じ構成要素には同じ符号を付し、説明は省略する。
<Third Embodiment>
[Structure of electronic device]
Next, the electronic device 1b according to the third embodiment will be described with reference to FIG.
FIG. 13 is a cross-sectional view showing the structure of the electronic device 1b according to the third embodiment. The electronic device 1b according to the third embodiment has a different form of the recess 17 provided in the electronic device 1 according to the first embodiment, and other components are the same. Therefore, in the description of the electronic device 1b according to the third embodiment, the same components as those of the electronic device 1 according to the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

第3実施形態に係る電子デバイス1bは、図13に示すように、素子基板10に設けられた凹部17bが、第1の主面10a側から第2の主面10bに向かって広がるテーパー部を有している。なお、本実施形態では、テーパー部が凹部17bに設けられているが、凹部17bの途中から設けられていても構わない。また、封止孔14に設けられていても構わない。 As shown in FIG. 13, the electronic device 1b according to the third embodiment has a tapered portion in which the recess 17b provided in the element substrate 10 extends from the first main surface 10a side toward the second main surface 10b. Have. In the present embodiment, the tapered portion is provided in the recess 17b, but the tapered portion may be provided in the middle of the recess 17b. Further, it may be provided in the sealing hole 14.

上述したように、第3実施形態に係る電子デバイス1bでは、凹部17bが第2の主面10bに向かって広がるテーパー部を有しているので、第2の主面10b側から第2の封止部40を成膜し、メンブレン部15に設けられた封止孔14を気密封止する際に、第2の封止部40を封止孔14へ到達させ易くなり、高い気密性を有する電子デバイス1bを得ることができる。 As described above, in the electronic device 1b according to the third embodiment, since the recess 17b has a tapered portion extending toward the second main surface 10b, the second sealing is performed from the second main surface 10b side. When the sealing portion 40 is formed and the sealing hole 14 provided in the membrane portion 15 is airtightly sealed, the second sealing portion 40 can be easily reached to the sealing hole 14 and has high airtightness. The electronic device 1b can be obtained.

1,1a,1b…電子デバイス、10…素子基板、10a…第1の主面、10b…第2の主面、11…素子形成層、12…基部、13…素子部、14…封止孔、15…メンブレン部、15a…第1の面、15b…第2の面、16…基部キャビティー、17,17b…凹部、17a…底部、20…蓋部、20a…接合面、21…蓋部キャビティー、30…第1の封止部、30a…封止部面、40,40a…第2の封止部、50…導電膜、S…収容空間。 1,1a, 1b ... Electronic device, 10 ... Element substrate, 10a ... First main surface, 10b ... Second main surface, 11 ... Element forming layer, 12 ... Base, 13 ... Element part, 14 ... Sealing hole , 15 ... Membrane part, 15a ... First surface, 15b ... Second surface, 16 ... Base cavity, 17, 17b ... Recessed part, 17a ... Bottom, 20 ... Lid part, 20a ... Joint surface, 21 ... Lid part Cavity, 30 ... first sealing portion, 30a ... sealing portion surface, 40, 40a ... second sealing portion, 50 ... conductive film, S ... accommodating space.

Claims (7)

SOI基板で構成された素子基板と、前記素子基板の第1の主面に接合される蓋部と、を備え、前記素子基板と前記蓋部との間に構成される収容空間に、素子部が収容されている電子デバイスであって、
前記素子基板は、前記第1の主面および前記素子部を含む素子形成層と、前記第1の主面とは反対側の第2の主面を含む基部と、を備え、
前記基部は、平面視で前記素子部と重なっている領域に、前記収容空間を構成しているキャビティが設けられており、
前記素子基板は、平面視で前記第1の主面の前記蓋部が接合された部分と前記キャビティとの間に配置され、前記基部の記第2の主面側に開口を備えるとともに前記第1の主面側を底部とする凹部と、前記底部と前記第1の主面とで構成されるメンブレン部と、を有し、
前記メンブレン部は、前記メンブレン部を貫通する封止孔を備え、
前記メンブレン部の前記第1の主面側である第1の面および前記封止孔は、多孔質の第1の封止部で覆われており、
前記メンブレン部の前記第2の主面側である第2の面(前記凹部の底部)および前記第1の封止部の前記第2の主面側の封止部面は、第2の封止部で覆われている、
ことを特徴とする電子デバイス。
An element substrate composed of an SOI substrate and a lid portion joined to the first main surface of the element substrate are provided, and the element portion is provided in a storage space formed between the element substrate and the lid portion. Is an electronic device that houses
The element substrate includes an element forming layer including the first main surface and the element portion, and a base including a second main surface opposite to the first main surface.
The base portion is provided with a cavity constituting the accommodation space in a region overlapping the element portion in a plan view.
The element substrate is disposed between the first of said lid portion is bonded portion of the principal surface in plan view and said cavity includes a front Symbol opening the second main surface side of the base Rutotomoni has a recess the bottom of the first main surface side, and a configured membrane portion between said bottom portion said first main surface,
The membrane portion includes a sealing hole that penetrates the membrane portion.
The first surface of the membrane portion, which is the first main surface side, and the sealing hole are covered with a porous first sealing portion.
The second surface (bottom of the recess) of the membrane portion on the second main surface side and the sealing portion surface of the first sealing portion on the second main surface side are second sealed. Covered with a stop,
An electronic device characterized by that.
前記第1の封止部は、酸化アルミニウムのスパッタ膜であることを特徴とする請求項1に記載の電子デバイス。 The electronic device according to claim 1, wherein the first sealing portion is a sputtered film of aluminum oxide. 前記第2の封止部は、金属膜であることを特徴とする請求項1又は請求項2に記載の電子デバイス。 The electronic device according to claim 1 or 2, wherein the second sealing portion is a metal film. 前記第2の封止部は、金属酸化膜であることを特徴とする請求項1又は請求項2に記載の電子デバイス。The electronic device according to claim 1 or 2, wherein the second sealing portion is a metal oxide film. 前記金属膜が前記第2の主面に配設される導電膜から延設されていることを特徴とする請求項3に記載の電子デバイス。 The electronic device according to claim 3, wherein the metal film extends from a conductive film disposed on the second main surface. 素子部が形成されたSOI基板を準備する基板準備工程と、
前記SOI基板の前記素子部が形成されている側の第1の主面に、多孔質の第1の封止部を形成する第1の封止部形成工程と、
前記SOI基板の前記第1の主面に、前記素子部の収容空間を構成する蓋部を接合する蓋部接合工程と、
平面視における前記SOI基板の前記第1の封止部の形成領域内に、前記SOI基板の前記第1の主面と反対の第2の主面側に開口し、前記SOI基板によるメンブレン部を構成する凹部を形成する凹部形成工程と、
前記SOI基板の前記第1の主面と反対の第2の主面側から前記凹部の底部の一部を除去し、前記メンブレン部に封止孔を形成する封止孔形成工程と、
前記収容空間を所定の空間環境とし、前記封止孔を金属の第2の封止部で気密封止する封止工程と、を含む、
ことを特徴とする電子デバイスの製造方法。
The substrate preparation process for preparing the SOI substrate on which the element part is formed, and
A first sealing portion forming step of forming a porous first sealing portion on the first main surface of the SOI substrate on the side where the element portion is formed, and a step of forming the first sealing portion.
A lid joining step of joining a lid portion constituting an accommodation space of the element portion to the first main surface of the SOI substrate, and a lid joining step.
In a plan view, an opening is made in the formation region of the first sealing portion of the SOI substrate on the side of the second main surface opposite to the first main surface of the SOI substrate, and the membrane portion made of the SOI substrate is formed. The recess forming step of forming the constituent recesses and the recess forming process
A sealing hole forming step of removing a part of the bottom portion of the recess from the second main surface side opposite to the first main surface of the SOI substrate to form a sealing hole in the membrane portion.
A sealing step of setting the accommodating space as a predetermined space environment and airtightly sealing the sealing hole with a second sealing portion of metal is included.
A method of manufacturing an electronic device.
前記封止工程は、前記第2の主面側に導電膜を形成する導電膜形成工程を含むことを特徴とする請求項に記載の電子デバイスの製造方法。 The method for manufacturing an electronic device according to claim 6 , wherein the sealing step includes a conductive film forming step of forming a conductive film on the second main surface side.
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