JP6905802B2 - Display driver and semiconductor device - Google Patents

Description

The present invention relates to a display driver that drives a display device in response to a video signal and a semiconductor device in which the display driver is formed.

For example, in a liquid crystal display panel as a display device, a plurality of gate signal lines extending in the horizontal direction of the two-dimensional screen and a plurality of source lines extending in the vertical direction of the two-dimensional screen are arranged so as to intersect each other. There is. Further, the liquid crystal display panel includes a source driver that applies a gradation voltage corresponding to the brightness level of each pixel represented by the input video signal to each of the source lines, and a gate driver that applies a scanning signal to the gate signal line. , (See, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2004-301946

By the way, when the display panel becomes large, the horizontal length of the screen of the display device becomes larger than the size of the source driver, and accordingly, each output terminal of the source driver and each of the source lines of the display device There is a difference in the length of each of the wires that connect the wires individually. Therefore, the source line connected to the source driver via a relatively long wire has a higher gradation voltage sent from the source driver than the source line connected to the source driver via a relatively short wire. The delay time it takes to actually reach it increases. As a result, there is a problem that a phenomenon in which a brightness difference occurs in the screen of the display panel, that is, so-called display unevenness occurs.

Therefore, an object of the present invention is to provide a display driver and a semiconductor device capable of performing image display in which display unevenness is suppressed.

The display driver according to the present invention includes a plurality of amplifiers that supply a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness level of each pixel to a plurality of data lines of a display device. The driver specifies the time from receiving the gradation voltage for each of the plurality of amplifiers until the voltage value of the display drive voltage reaches the voltage value corresponding to the gradation voltage as the output delay time. Each of the plurality of amplifiers amplifies the gradation voltage, including an output delay setting unit that receives the output delay data to be generated and generates an output delay control signal corresponding to the output delay time for each of the plurality of amplifiers. The amplification unit includes an amplification unit that outputs the displayed voltage as the display drive voltage and an output delay adjustment unit that adjusts the output delay of the amplification unit based on the output delay control signal, and the amplification unit transmits the display drive voltage. A differential circuit that generates an output voltage drive signal having a level corresponding to the difference between the output line, the voltage of the output line, and the gradation voltage, and the output voltage drive signal received at its own gate end. Whether the output delay adjusting unit precharges the gate end of the output transistor based on the output delay control signal, including an output transistor that sends a current having a magnitude corresponding to the output voltage drive signal to the output line. It has a precharge circuit that adjusts the output delay time depending on whether or not it is. Further, another display driver according to the present invention supplies a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness levels of each pixel to a plurality of data lines of the display device. A display driver including an amplifier, which receives output delay data for each of the plurality of amplifiers and specifies the time from receiving the gradation voltage to outputting the display drive voltage as an output delay time. Each of the amplifiers includes an output delay setting unit that generates an output delay control signal corresponding to the output delay time, and each of the plurality of amplifiers outputs a voltage obtained by amplifying the gradation voltage as the display drive voltage. The amplification unit includes an output delay adjusting unit that adjusts the output delay of the amplification unit based on the output delay control signal, and the amplification unit includes an output line for transmitting the display drive voltage, an output terminal, and the like. The output delay adjusting unit includes an output switch that connects or disconnects the output line and the output terminals, and is represented by the output delay control signal when an increase or decrease in the brightness level is detected. The output switch is set to the cutoff state only during the output delay time.

The semiconductor device according to the present invention includes a plurality of amplifiers that supply a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness levels of each pixel to a plurality of data lines of the display device. A semiconductor device in which a driver is formed, from receiving the gradation voltage for each of the plurality of amplifiers until the voltage value of the display drive voltage reaches a voltage value corresponding to the gradation voltage. Each of the plurality of amplifiers includes an output delay setting unit that receives output delay data that specifies time as an output delay time and generates an output delay control signal corresponding to the output delay time for each of the plurality of amplifiers. The amplification unit includes an amplification unit that outputs a voltage obtained by amplifying the gradation voltage as the display drive voltage, and an output delay adjustment unit that adjusts the output delay of the amplification unit based on the output delay control signal. , An output line that transmits the display drive voltage, a differential circuit that generates an output voltage drive signal having a level corresponding to the difference between the voltage of the output line and the gradation voltage, and the output voltage drive signal itself. The output delay adjusting unit includes an output transistor that receives a current at the gate end of the output voltage and sends a current of a magnitude corresponding to the output voltage drive signal to the output line. It has a precharge circuit that adjusts the output delay time depending on whether or not the gate end is precharged. In addition, another semiconductor device according to the present invention supplies a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness levels of each pixel to a plurality of data lines of the display device. An output in which a display driver including an amplifier is formed, and the time from receiving the gradation voltage to outputting the display drive voltage for each of the plurality of amplifiers is designated as an output delay time. Each of the plurality of amplifiers includes an output delay setting unit that receives delay data and generates an output delay control signal corresponding to the output delay time for each of the plurality of amplifiers, and each of the plurality of amplifiers is a voltage obtained by amplifying the gradation voltage. The amplification unit includes an amplification unit that outputs the display drive voltage and an output delay adjustment unit that adjusts the output delay of the amplification unit based on the output delay control signal, and the amplification unit transmits the display drive voltage. The output delay adjusting unit includes a line and an output terminal, and includes an output switch that connects or disconnects the output line and the output terminals, and when an increase or decrease in the brightness level is detected, the output delay The output switch is set to the cutoff state only during the output delay time represented by the control signal.

According to the display driver according to the present invention, it is possible to adjust the output delay time of each of the plurality of amplifiers that apply the plurality of display drive voltages to the plurality of data lines of the display device by the output delay data. As a result, even if there is a difference in the wiring delay due to the wiring connecting the display driver and each of the plurality of data lines of the display device, the data is sent from the display device without changing the internal configuration of the display driver. It is possible to reduce the difference in the delay time required for the display drive voltage to reach each data line. Therefore, according to the present invention
It is possible to suppress display unevenness in the screen caused by the delay time difference by corresponding to various forms of wiring delay associated with wiring connecting the display driver and display device without incurring an increase in manufacturing cost. Become.

It is a block diagram which shows the structure of the display device 10 including the display driver which concerns on this invention. It is a block diagram which shows the internal structure of a data driver 13. It is a block diagram which shows the internal structure of an output amplifier part 133. It is a figure which shows an example of the correspondence relationship between the output delay data MOD and the output delay control signals SWa, SWb, and SWc. It is a circuit diagram which shows the internal structure of the amplifier AP _1. It is a circuit diagram which shows an example of the internal structure of the PC control part CNT. It is a time chart for explaining the operation of amplifier AP _1. It is a figure which shows an example of the delay form based on the 1st delay mode which reflected the output delay by _{amplifiers AP 1 to AP n in the} wiring delay by printed wiring individually connected to data lines D _{1 to} D _n. .. It is a figure which shows an example of the delay form based on the 2nd delay mode which reflected the output delay by _{amplifiers AP 1 to AP n in the} wiring delay by printed wiring individually connected to data lines D _{1 to} D _n. .. It is a figure which shows an example of the delay form based on the 3rd delay mode which reflected the output delay by _{amplifiers AP 1 to AP n in the} wiring delay by printed wiring individually connected to data lines D _{1 to} D _n. .. It is a block diagram which shows another example of the internal structure of an output amplifier part 133. It is a figure which shows another example of the correspondence relation between the output delay data MOD and the output delay control signals SWa, SWb, and SWc. It is a circuit diagram which shows the internal structure of the amplifier AG _1. It is a time chart for explaining the operation of amplifier AG _1. The figure which shows another example of the delay form based on the 1st delay mode which reflected the output delay by _{amplifiers AP 1 to AP n in the} wiring delay by printed wiring individually connected to data lines D _{1 to} D _{n, respectively.} Is. The figure which shows another example of the delay form based on the 2nd delay mode which reflected the output delay by _{amplifiers AP 1 to AP n in the} wiring delay by printed wiring individually connected to data lines D _{1 to} D _{n, respectively.} Is. The figure which shows another example of the delay form based on the 3rd delay mode which reflected the output delay by _{amplifiers AP 1 to AP n in the} wiring delay by printed wiring individually connected to data lines D _{1 to} D _{n, respectively.} Is.

Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a display device 10 including a display driver according to the present invention. As shown in FIG. 1, the display device 10 includes a drive control unit 11, a scanning driver 12, a data driver 13, and a display device 20 including a liquid crystal or organic EL panel.

_{The display device 20 has m horizontal scanning lines S 1 to} S _m each extending in the horizontal direction of the 2D screen (m is a natural number of 2 or more) and n each extending in the vertical direction of the 2D screen. _{The number of data lines D 1 to} D _n (n is a natural number of 2 or more) is formed. Further, a display cell carrying a pixel is formed in a region of each intersection of the horizontal scanning line and the data line, that is, a region surrounded by a broken line in FIG.

Based on the input video signal VS, the drive control unit 11 generates a series of pixel data PDs that represent the brightness level of the pixels for each pixel, for example, as 6-bit data, and the video data signal VD including the series of the pixel data PDs. Is supplied to the data driver 13. Further, the drive control unit 11 detects a horizontal synchronization signal from the input video signal VS and supplies the horizontal synchronization signal to the scanning driver 12.

Scan driver 12 in synchronism with the horizontal synchronizing signal supplied from the drive control unit 11 generates a horizontal scanning pulse sequentially to this scan line S ₁ to S _m, each of the display devices 20, alternatively applied do.

FIG. 2 is a block diagram showing an internal configuration of the data driver 13 as a display driver. The data driver 13 is formed by being divided into a single semiconductor chip or a plurality of semiconductor chips.

As shown in FIG. 2, the data driver 13 includes a data latch unit 131, a gradation voltage generation unit 132, and an output amplifier unit 133.

The data latch unit 131 sequentially captures a series of pixel data PDs included in the video data signal VD supplied from the drive control unit 11. At this time, the data latch unit 131, every time one horizontal scanning line of the pixel data PD (n number of) incorporation is made, the gray voltage generator the n pixel data PD as pixel data Q ₁ to Q _n It is supplied to the unit 132 and the output amplifier unit 133.

_{The gradation voltage generation unit 132 converts the pixel data Q 1 to} Q _n supplied from the data latch unit 131 into _{gradation voltages V 1 to} V _n having voltage values corresponding to the respective luminance levels, and outputs an amplifier. It is supplied to the unit 133.

The output amplifier unit 133 _{generates n} voltages obtained by individually amplifying _{the gradation voltages V 1 to} V _{n as display drive voltages G 1 to} G _{n, and data lines D 1 to} D of the display device 20. Supply to _n.

FIG. 3 is a block diagram showing an example of the internal configuration of the output amplifier unit 133.

As shown in FIG. 3, the output amplifier unit 133 includes an output delay setting unit DST and amplifiers AP _{1 to AP n} .

The output delay setting unit DST receives the output delay data MOD supplied via the external terminal of the data driver 13. The output delay data MOD may be stored in a user register (not shown) built in the data driver 13. At this time, the output delay setting unit DST takes in the output delay data MOD stored in this user register.

The output delay data MOD is data _{for designating the output delay time of each of the amplifiers AP 1 to AP n} , and represents, for example, one of the following first to third delay modes.

That is, first, the amplifiers AP _{1 to AP n are the amplifier group CHa composed of the amplifiers AP 1 to AP r} (r is an integer of 2 or more) responsible for displaying the display in the left region of the screen by the display device 20, and the central region. It is divided into an amplifier group CHb consisting of amplifiers AP _{r + 1 to AP k} (k is an integer larger than r) responsible for display drive and an amplifier group CHc consisting of amplifiers _{AP k + 1 to AP n responsible for display drive in the right region.} do.

Here, in the first delay mode, as shown in FIG. 4, the output delay time W1 is specified as the output delay time of each of the amplifier groups CHa and CHb, and the output delay time of the amplifier group CHc is longer than the output delay time W1. Specify the output delay time W2. Further, in the second delay mode, as shown in FIG. 4, the output delay time W2 is designated as the output delay time of the amplifier group CHa, and the output delay time W1 is designated as the output delay time of each of the amplifier groups CHb and CHc. Further, in the third delay mode, as shown in FIG. 4, the output delay time W1 is designated as the output delay time of the amplifier groups CHa and CHc, and the output delay time W2 is designated as the output delay time of the amplifier group CHb.
Then, the output delay setting unit DST generates output delay control signals SWa, SWb and SWc corresponding to the output delay times of each of the amplifier groups CHa, CHb and CHc specified in the output delay data MOD. For example, when the output delay data MOD represents the first delay mode as shown in FIG. 4, the output delay setting unit DST generates the output delay control signals SWa and SWb of the logic level 1 corresponding to the output delay time W1. At the same time, an output delay control signal SWc having a logic level of 0 corresponding to the output delay time W2 is generated.

Then, the output delay setting unit DST supplies the output delay control signal SWa generated as described above to the amplifier group CHa (AP _{1 to AP r} ), and supplies the output delay control signal SWb to the amplifier group CH b _{(AP r + 1} to AP r + 1). It _{is supplied to AP k} ), and the output delay control signal SWc is supplied to the amplifier group CHc (AP _{k + 1 to AP n} ).

Each of the amplifiers AP _{1 to AP n is provided in association with the gradation voltage V 1 to} V _n and the pixel data Q, respectively. The amplifiers AP _{1 to AP n} are output terminals OT provided corresponding to the display drive voltages G _{1 to} G _n obtained by individually amplifying the gradation voltages V _{1 to} V _{n with a gain of 1.} Output via _{1 to} OT _n. Note that the output terminal OT ₁ ~OT _n are connected respectively via a separate printed circuit to the data lines D ₁ to D _n of the display device 20.

Each of the amplifiers AP _{1 to AP n} is a PC-type differential amplifier (op amp) that precharges internally based on the pixel data Q corresponding to the amplifier AP, and has the same internal configuration as each other. Have.

Therefore, an excerpt of the amplifier AP ₁ below describes the internal structure of the amplifier AP ₁ ~AP _n.

FIG. 5 is a circuit diagram showing the internal configuration of the _{amplifier AP 1.} As shown in FIG. 5, the amplifier AP ₁ has an amplification unit including differential circuits DF1 and DF2, a p-channel MOS (Metal-Oxide-Semiconductor) type output transistor R1, and an n-channel MOS type output transistor R2. ..

The first differential circuit DF1 includes n-channel MOS type transistors U1 to U3, and p-channel MOS type transistors U4 and U5. The source terminals of each of the transistors U1 and U2 forming a differential pair are connected to the drain terminal of the transistor U3 as a current source. A bias voltage Vb1 for driving a differential circuit is applied to the gate terminal of the transistor U3, and a ground voltage Vss (for example, 0 volt) is applied to the source terminal thereof. The drain terminal of the transistor U1 is connected to the drain terminal of the transistor U4, the gate terminal of the output transistor R1 and the switch element SW1 via the line Lp1. The drain terminal of the transistor U2 is connected to the gate terminal of the transistor U4 and the drain terminal and the gate terminal of the transistor U5 via the line Lp2, respectively. A power supply voltage Vdd is applied to the source terminals of each of the transistors U4 and U5. The gate terminal of the transistor U1 is connected to the input line LIN, and the gate terminal of the transistor U2 is connected to the output line LOT.

Here, the transistor U1 causes a current corresponding to the _{gradation voltage V 1} supplied via the input line LIN to flow through the line Lp1. Transistor U2 passes a current corresponding to the display driving voltage G ₁ as supplied output voltage via the output line LOT line Lp2. At this time, the transistor U3 as a current source generates a combined current that combines the current flowing through the line Lp1 and the current flowing through the line Lp2 based on the bias voltage Vb1. Therefore, the transistors U1 and U2 pass currents through the lines Lp1 and Lp2, respectively, so that the sum of the current flowing through the line Lp1 and the current flowing through the line Lp2 matches the combined current described above.

Therefore, with such a configuration, the differential circuit DF1 sets the output voltage drive signal PG having a level corresponding to the difference value between the _{gradation voltage V 1} and the display drive voltage G _{1 into the line Lp1 as the first drive line.} Generate. _{The output transistor R1 sends an output current I 1} based on the output voltage drive signal PG to the output line LOT.

The second differential circuit DF2 includes p-channel MOS type transistors M1 to M3, and n-channel MOS type transistors M4 and M5. The source terminals of each of the transistors M1 and M2 forming a differential pair are connected to the drain terminal of the transistor M3 as a current source. A bias voltage Vb2 for driving a differential circuit is applied to the gate terminal of the transistor M3, and a power supply voltage Vdd is applied to the source terminal thereof.

The drain terminal of the transistor M1 is connected to the drain terminal of the transistor M4, the gate terminal of the output transistor R2, and the switch element SW2 via the line Ln1. The drain terminal of the transistor M2 is connected to the gate terminal of the transistor M4 and the drain terminal and the gate terminal of the transistor M5 via the line Ln2, respectively. A ground voltage Vss is applied to the source terminals of the transistors M4 and M5. The gate terminal of the transistor M1 is connected to the input line LIN, and the gate terminal of the transistor M2 is connected to the output line LOT.

Here, the transistor M1 causes a current corresponding to the _{gradation voltage V 1} supplied via the input line LIN to flow through the line Ln1. _{The transistor M2 causes a current corresponding to the display drive voltage G 1} as an output voltage supplied via the output line LOT to flow through the line Ln 2. At this time, the transistor M3 as a current source generates a combined current based on the bias voltage Vb2, which is a combination of the current flowing through the line Ln1 and the current flowing through the line Ln2. Therefore, the transistors M1 and M2 pass currents through the lines Ln1 and Ln2, respectively, so that the sum of the current flowing through the line Ln1 and the current flowing through the line Ln2 matches the combined current described above.

Therefore, with such a configuration, the differential circuit DF2 generates an output voltage drive signal NG having a level corresponding to the difference value between the _{gradation voltage V 1} and the display drive voltage G _{1 on the line Ln 1 as the second drive line.} do. The output voltage drive signal NG is a signal in which the phase of the output voltage drive signal PG described above is inverted.

The output transistor R2 draws the output current I ₂ based on the output voltage drive signal NG from the output line LOT. Therefore, in the output line LOT, _{a display drive voltage G 1} having a voltage value corresponding to the current value obtained by subtracting the output current I _{2 from the output current I 1} transmitted by the output transistor R 1 is generated.

In this way, the amplifier AP ₁ push-pull drives the two output transistors (R1, R2) by two independent differential circuits (DF1, DF2), thereby inputting the gradation voltage (V ₁ ). Is amplified with a gain of 1, and the voltage is generated as the _{display drive voltage (G 1).}

Further, in addition _{to the amplification units (DF1, DF2, R1, R2), the amplifier AP 1} includes an n-channel MOS type transistor PT1 and a p-channel MOS type transistor as a precharge circuit as shown in FIG. An output delay adjusting unit including a PT2, switch elements SS1 and SS2, and a PC (precharge) control unit CNT is provided.

FIG. 6 is a block diagram showing an example of the internal configuration of the PC control unit CNT. 6, increases the detection unit 61, when it detects that the luminance level represented by the pixel data Q ₁ is increased, only for a predetermined time period TC logic level 1, and the other periods of the logic level 0 state Generates a precharge signal PC1 that maintains. The increase detection unit 61 supplies the precharge signal PC1 to the switch element SS1 shown in FIG.
Drop detection unit 62, when the luminance level represented by the pixel data Q ₁ is detected that it has decreased, only during a predetermined time period TC logic level 0, the other period to maintain the state of the logic level 1 pre Generates the charge signal PC2. The drop detection unit 62 supplies the precharge signal PC2 to the switch element SS2 shown in FIG.

When the output delay control signal SWa supplied from the output delay setting unit DST indicates the logic level 0, the switch element SS1 supplies the ground voltage Vss to the gate end of the transistor PT1. On the other hand, when the output delay control signal SWa indicates the logic level 1, the switch element SS1 supplies the precharge signal PC1 to the gate end of the transistor PT1.

The switch element SS2 supplies the power supply voltage Vdd to the gate end of the transistor PT2 when the output delay control signal SWa indicates the logic level 0. On the other hand, when the output delay control signal SWa indicates the logic level 1, the switch element SS2 supplies the precharge signal PC2 to the gate end of the transistor PT2.

A ground voltage Vss is applied to the source end of the transistor PT1 as a precharge circuit, and the drain end is connected to the gate end of the line Lp1 and the output transistor R1.

The transistor PT1 is turned on when the precharge signal PC1 supplied to its own gate end indicates logic level 1, and supplies the ground voltage Vss to the gate end of the output transistor R1. As a result, the transistor PT1 is precharged by sharply reducing the voltage at the gate end of the p-channel type output transistor R1.

On the other hand, when the precharge signal PC1 supplied to its own gate end indicates logic level 0, the transistor PT1 is turned off and the above-mentioned precharge is stopped.

A power supply voltage Vdd is applied to the source end of the transistor PT2 as a precharge circuit, and the drain end is connected to the gate end of the line Ln1 and the output transistor R2.

The transistor PT2 is turned on when the precharge signal PC2 supplied to its own gate end indicates a logic level of 0, and supplies the power supply voltage Vdd to the gate end of the output transistor R2. As a result, the transistor PT2 is precharged by sharply increasing the voltage at the gate end of the n-channel type output transistor R2.

On the other hand, when the precharge signal PC2 supplied to its own gate end indicates logic level 1, the transistor PT2 is turned off and the above-mentioned precharge is stopped.
_{The operation of the amplifier AP 1} having the configuration shown in FIG. 5 will be described below with reference to the time chart of FIG. In FIG. 7, the luminance level represented by the pixel data Q ₁ is, transition from the state of the luminance level Ya, at time t0 at a higher brightness level Yb than the luminance level Ya, then the luminance at time t1 _{The operation of amplifier AP 1} when transitioning to level Ya is shown.

First, while the pixel data Q ₁ representing the luminance level Ya is being supplied, the amplification unit (DF1, DF2, R1, R2) of the _{amplifier AP 1} is a display drive having _{a voltage value V DT1 corresponding to the luminance level Ya.} Outputs voltage G _1.

Then, at time t0, the luminance level represented by the pixel data Q ₁ is a transition from Ya to Yb, the amplification portion of the amplifier AP ₁ is the voltage value V _DT1 display driving voltage G _1, corresponding to the luminance level Yb The voltage value is increased toward _{V DT2.}

At this time, increase the detection unit 61, upon detecting that the luminance level represented by the pixel data Q ₁ is transitioned to a higher brightness level Yb than the luminance level Ya, only during a predetermined time period TC as shown in FIG. 7 logic A single pulse precharge signal PC1 to be level 1 is supplied to the switch element SS1.

Here, when the output delay control signal SWa indicates the logic level 0 corresponding to the output delay time W2, the switch element SS1 supplies the ground voltage Vss to the gate end of the transistor PT1. As a result, the transistor PT1 for precharging is fixed in the off state, and the gate end of the output transistor R1 is not precharged. Therefore, at this time, _{the voltage value of the display drive voltage G 1} gradually increases as shown by the alternate long and short dash line in FIG. 7 only by the operation of the amplification unit (DF1, DF2, R1, R2) immediately after the time point t0. _{The voltage value V DT2} is reached when the output delay time W2 elapses from the time point t0.

On the other hand, when the output delay control signal SWa indicates the logic level 1, the switch element SS1 is turned on. As a result, the precharge signal PC1 shown in FIG. 7 is supplied to the gate end of the transistor PT1 for precharging. Thus, the transistor PT1, as shown in FIG. 7, for a predetermined time period TC in the leading edge of the display driving voltage G _1, precharging of applying a ground voltage Vss to the gate terminal of the output transistor R1. _{According to the precharge, the voltage value of the display drive voltage G 1} is steeper than when the voltage value is increased only by the amplification unit (DF1, DF2, R1, R2) (indicated by the one-point chain line). It increases from the state of the value V _DT1 (shown by a solid line), and reaches the _{voltage value V DT2} when the output delay time W1 shorter than the output delay time W2 described above elapses.

That is, in the case of executing the pre-charge is different from the case of not executing a precharge, from the state of V _DT1 voltage value of the display driving voltage G _1, leading to the state of the high voltage V _DT2 than this The delay time until is shortened.

After that, when the _{luminance level represented by the pixel data Q 1} transitions from Yb to Ya at the time point t1, the amplification unit of the _{amplifier AP 1} sets the voltage value V _{DT 2 of the display drive voltage G 1 to} the voltage corresponding to the luminance level Ya. Decrease towards the value V _DT1.

In this case, drop detection unit 62, upon detecting that the luminance level represented by the pixel data Q ₁ is transitioned to the low luminance level Ya than the luminance level Yb, only during a predetermined time period TC as shown in FIG. 7 logic A single pulse precharge signal PC2 that becomes level 0 is supplied to the switch element SS2.

Here, when the output delay control signal SWa indicates a logic level 0, the switch element SS2 supplies the power supply voltage Vdd to the gate end of the transistor PT2. As a result, the transistor PT2 for precharging is fixed in the off state, and the gate end of the output transistor R2 is not precharged.

Therefore, at this time, _{the voltage value of the display drive voltage G 1} gradually decreases as shown by the alternate long and short dash line in FIG. 7 only by the operation of the amplification unit (DF1, DF2, R1, R2) immediately after the time point t0. _{The voltage value V DT1} is reached when the output delay time W2 elapses from the time point t1.

On the other hand, when the output delay control signal SWa indicates the logic level 1, the switch element SS2 is turned on. As a result, the precharge signal PC2 shown in FIG. 7 is supplied to the gate end of the transistor PT2 for precharging. Thus, the transistor PT2, as shown in FIG. 7, for a predetermined time period TC in the interval falling of the display driving voltage G _1, precharging of applying the power supply voltage Vdd to the gate terminal of the output transistor R2. _{According to the precharge, the voltage value of the display drive voltage G 1} is steeper than when the voltage value is lowered only by the amplification unit (DF1, DF2, R1, R2) (indicated by the one-point chain line). It decreases from the state of the value V _DT2 (shown by a solid line), and reaches the _{voltage value V DT1} when the output delay time W1 shorter than the output delay time W2 described above elapses.

That is, in the case of executing the pre-charge is different from the case of not executing a precharge, the state of the voltage value V _DT2 display driving voltage G _1, a low voltage state of the voltage value V _DT1 than this The delay time to reach it is shortened.

Below, the output delay based on the output delay data MOD, considering the wiring delay in each printed wiring that individually connects _{the output terminals OT 1 to OT n} of the data driver 13 and the data lines D _{1 to} D _{n of the display device 20.} The setting operation of is described.

First, as a form of wiring delay due to each of the printed wirings individually connected to the data lines D _{1 to} D _n , the wiring connected to the _{data lines D 1 arranged at the left end of the screen of the display device 20 is used.} Assume a delay form that is maximum and decreases toward the right end. Here, when the output delays of the amplifiers AP _{1 to AP n} are all the output delay time W2, until the display drive voltages G _{1 to} G _n output from the data driver 13 reach the data lines D _{1 to} D _n. The delay time spent on the data is in the form of a delay as shown by the alternate long and short dash line in FIG.

Therefore, the difference between the maximum delay time and the minimum delay time in the screen of the display device 20 is the delay time difference DL between the delay time _{on the data line D 1} and the delay time on the data line D _{n as shown in FIG.} Therefore, display unevenness corresponding to this delay time difference DL will occur.

Therefore, at this time, the output delay data MOD representing the first delay mode shown in FIG. 4 is supplied to the output delay setting unit DST. Accordingly, the output delay setting unit DST is among the amplifier AP ₁ ~AP _n, the data lines D ₁ to D _r and D _r + 1 amplifier AP ₁ is connected to ~D _k ~AP _r and AP _{r +} The output delay control signals SWa and SWb of the logic level 1 prompting the execution of precharging are supplied _{to 1 to AP k.} Further, the output delay setting unit DST stops the precharge by supplying the output delay control signal SWc of the logic level 0 to the _{remaining amplifier groups AP k + 1 to AP n.}

Therefore, among the amplifier AP ₁ ~AP _n, each of the amplifier AP ₁ ~AP _r and AP _r + 1 ~AP _k is the the output delay time W2 its output delayed by execution of the precharge, the output delay time Reduce to W1. As a result, the delay times in each of the data lines D _{1 to} D _r and D _{r + 1 to} D _{k corresponding to the amplifiers AP 1 to AP r} and AP _{r + 1 to AP k} are shown by the solid line in FIG. As you can see, it gets lower overall.

Therefore, by supplying the output delay data MOD representing the first delay mode to the output delay setting unit DST, the delay time difference in the screen of the display device 20 is larger than the delay time difference DL described above, as shown in FIG. The delay time difference DLX is small. Therefore, as the delay time difference becomes smaller, the brightness difference in the screen also becomes smaller, so that display unevenness can be suppressed.

Next, as a form of wiring delay due to each of the printed wirings individually connected to the data lines D _{1 to} D _n , the wiring connected to the _{data lines D n arranged at the right end of the screen of the display device 20.} Is assumed to be a delay form in which is maximum and decreases toward the left end. Here, when the output delays of the amplifiers AP _{1 to AP n} are all the output delay time W2, until the display drive voltages G _{1 to} G _n output from the data driver 13 reach the data lines D _{1 to} D _n. The delay time spent on the data is in the form of a delay as shown by the alternate long and short dash line in FIG.

Therefore, the difference between the maximum delay time and the minimum delay time in the screen of the display device 20 is the delay time difference DL between the delay time _{on the data line D n} and the delay time on the data line D _{1 as shown in FIG.} Therefore, display unevenness corresponding to this delay time difference DL will occur.

Therefore, at this time, the output delay data MOD representing the second delay mode shown in FIG. 4 is supplied to the output delay setting unit DST. As a result, the output delay setting unit DST has the amplifiers AP _{r + 1 to AP k} connected to the data lines D _{r + 1 to} D _k and D _{k + 1 to} D _{n among the amplifiers AP 1 to AP n.} And AP _{k + 1 to AP n} are made to execute precharging by supplying the output delay control signals SWb and SWc of the logic level 1. Further, the output delay setting unit DST supplies the _{remaining amplifiers AP 1 to AP r} with a logic level 0 output delay control signal SWa indicating that the precharge is stopped.

Therefore, among the amplifier AP ₁ ~AP _n, each of the amplifiers AP _r + 1 ~AP _k and AP _k + 1 ~AP _n from the precharge output delay time its output delayed by execution of W2, the output The delay time is reduced to W1. Thus, the amplifier AP _r + 1 ~AP _k and AP _k + 1 ~AP data lines D corresponding to _{n r} + 1 ~D _k and D _k + 1 to D _n delay time in each of the solid lines in FIG. 9 Overall lower as shown in.

Therefore, by supplying the output delay data MOD representing the second delay mode to the output delay setting unit DST, the delay time difference in the screen of the display device 20 is larger than the delay time difference DL described above, as shown in FIG. The delay time difference DLX is small. Therefore, as the delay time difference becomes smaller, the brightness difference in the screen also becomes smaller, so that display unevenness can be suppressed.

Next, as a form of wiring delay due to each of the printed wirings individually connected to the data lines D _{1 to} D _{n , they are connected to the data lines D 1} and D _{n arranged at both ends of the screen of the display device 20.} Assume a delay form in which the wiring is maximized and becomes smaller toward the center of the screen. Here, when the output delays of the amplifiers AP _{1 to AP n} are all the output delay time W2, until the display drive voltages G _{1 to} G _n output from the data driver 13 reach the data lines D _{1 to} D _n. The delay time spent on the data is in the form of a delay as shown by the alternate long and short dash line in FIG.

Therefore, the difference between the maximum delay time and the minimum delay time in the screen of the display device 20 is the delay time at the data line D _n or D _n and the data line arranged near the center as shown in FIG. For example _{, the delay time difference DL from the delay time at D n / 2} ) will occur, and display unevenness corresponding to this delay time difference DL will occur.

Therefore, at this time, the output delay data MOD representing the third delay mode shown in FIG. 4 is supplied to the output delay setting unit DST. Accordingly, the output delay setting unit DST is among the amplifier AP ₁ ~AP _n, the data lines D ₁ to D _r and D _k + 1 amplifier AP ₁ is connected to ~D _n ~AP _r and AP _{k +} Precharge is executed by supplying the output delay control signals SWa and SWc of the logic level 1 to _{1 to} AP _n. Further, the output delay setting unit DST supplies the _{remaining amplifiers AP r + 1 to AP k} with a logic level 0 output delay control signal SWb indicating that the precharge is stopped.

Therefore, among the amplifier AP ₁ ~AP _n, each of the amplifier AP ₁ ~AP _r and AP _k + 1 ~AP _n, the output delay time its output delay from the output delay time W2 by executing the precharge W1 To reduce. As a result, the delay times in each of the data lines D _{1 to} D _r and D _{k + 1 to} D _{n corresponding to the amplifiers AP 1 to AP r} and AP _{k + 1 to AP n} are shown by the solid line in FIG. As a whole it gets lower.

Therefore, by supplying the output delay data MOD representing the third delay mode to the output delay setting unit DST, the delay time difference in the screen of the display device 20 is larger than the delay time difference DL described above, as shown in FIG. The delay time difference DLX is small. Therefore, as the delay time difference becomes smaller, the brightness difference in the screen also becomes smaller, so that display unevenness can be suppressed.

In the above embodiment, depending on whether or not to execute the pre-charge inside the amplifier AP ₁ ~AP _n each amplifier AP ₁ ~AP _n output delay time although to be set in two stages, pre It is also possible to set the output delay time of _{the amplifiers AP 1 to AP n} in multiple stages of 3 or more stages by another method that does not use the charge.
FIG. 11 is a block diagram showing another example of the internal configuration of the output amplifier unit 133 made in view of this point. In the configuration shown in FIG. 11, the output delay setting unit DSX is used instead of the output delay setting unit DST shown in FIG. 3, and the amplifiers AG _{1 to} AG _n are used _{instead of the amplifiers AP 1 to AP n.} Is.

The output delay setting unit DSX generates output delay control signals SWa, SWb, and SWc corresponding to the delay mode indicated by the output delay data MOD.

The output delay setting unit DSX receives the output delay data MOD supplied via the external terminal of the data driver 13. The output delay data MOD may be stored in the user register built in the data driver 13. At this time, the output delay setting unit DSX takes in the output delay data MOD stored in this user register.

The output delay data MOD is data _{for designating the output delay time of each of the amplifiers AG 1 to} AG _n , and represents, for example, one of the following first to third delay modes.

That is, first, the amplifiers AG _{1 to} AG _{n are the amplifier group CHa composed of the amplifiers AG 1 to} AG _r (r is an integer of 2 or more) responsible for displaying the display in the left region of the screen by the display device 20, and the amplifier group CHa in the central region. It is divided into an amplifier group CHb consisting of amplifiers AG _{r + 1 to} AG _k (k is an integer larger than r) responsible for display drive and an amplifier group CHc consisting of amplifiers _{AG k + 1 to} AG _{n responsible for display drive in the right region.} do.

Here, in the first delay mode, as shown in FIG. 12, the output delay time W1 is specified as the output delay time of the amplifier group CHa and the output delay time is longer than the output delay time W1 as the output delay time of the amplifier group CHb. Specify the time W2. Further, in the first delay mode, an output delay time W3 longer than the output delay time W2 is specified as the output delay time of the amplifier group CHc.

In the second delay mode, as shown in FIG. 12, the output delay time W3 is designated as the output delay time of the amplifier group CHa, and the output delay time W2 is designated as the output delay time of the amplifier group CHb. Further, in the second delay mode, the output delay time W1 is specified as the output delay time of the amplifier group CHc.

Further, in the third delay mode, as shown in FIG. 12, the output delay time W2 is designated as the output delay time of the amplifier groups CHa and CHc, and the output delay time W3 is designated as the output delay time of the amplifier group CHb.

The output delay setting unit DSX generates output delay control signals SWa, SWb and SWc corresponding to the output delay times of each of the amplifier groups CHa, CHb and CHc specified in the output delay data MOD.

For example, when the output delay data MOD represents the first delay mode shown in FIG. 12, the output delay setting unit DSX has an output delay control signal SWa representing the output delay time W1 and an output delay control signal representing the output delay time W2. The output delay control signal SWc representing the SWb and the output delay time W3 is generated. When the output delay data MOD represents the second delay mode, the output delay setting unit DSX represents the output delay control signal SWa representing the output delay time W3, the output delay control signal SWb representing the output delay time W2, and the output. The output delay control signal SWc representing the delay time W1 is generated. When the output delay data MOD represents the third delay mode, the output delay setting unit DSX generates output delay control signals SWa and SWc representing the output delay time W2, and outputs delay control representing the output delay time W3. Generate signal SWb.
Then, the output delay setting unit DSX _{supplies the output delay control signal SWa to each of the amplifiers AG 1 to} AG _r belonging to the amplifier group CHa, and supplies the output delay control signal SWb to the amplifiers AG _{r + 1 to AG belonging to the amplifier group CHb. It} is supplied to each of k, and the output delay control signal SWc is supplied to each of the amplifiers AG _{k + 1 to} AG _n belonging to the amplifier group CHc.

Each of the amplifiers AG _{1 to} AG _{n is provided in association with the gradation voltage V 1 to} V _n and the pixel data Q, respectively. The amplifiers AG _{1 to} AG _n are output terminals OT provided corresponding to the display drive voltages G _{1 to} G _n obtained by individually amplifying the gradation voltages V _{1 to} V _{n with a gain of 1.} Output via _{1 to} OT _n. Note that the output terminal OT ₁ ~OT _n are connected respectively via a separate printed circuit to the data lines D ₁ to D _n of the display device 20.

Each of the amplifiers AG _{1 to} AG _n has the same internal structure as each other. Therefore, an excerpt of the amplifier AG ₁ below describes the internal structure of the amplifier AG ₁ ~AG _n.

FIG. 13 is a circuit diagram showing the internal configuration of the _{amplifier AG 1.} In FIG. 13, the configuration and operation of the amplification unit including the differential circuits DF1 and DF2 and the output transistors R1 and R2 are the same as those shown in FIG. 5, and the description thereof will be omitted.

As shown in FIG. 13, _{in addition to the amplification units (DF1, DF2, R1, R2), the amplifier AG 1} is provided with an n-channel MOS type transistor TX as an output switch and an output delay adjustment unit CND. There is.

Output delay adjusting unit CND is a logic level 1 having when it detects that the luminance level represented by the pixel data Q ₁ is increased or decreased, the output delay time equal to the pulse width represented by the output delay control signal SWa Generates an output delay adjustment signal OPS containing a single pulse of.

That is, when the output delay control signal SWa represents the output delay time W1, the output delay adjusting unit CND has a single pulse FST of logic level 0 having a pulse width equal to the output delay time W1 as shown in FIG. Generates an output delay adjustment signal OPS including. When the output delay control signal SWa represents the output delay time W2, the output delay adjusting unit CND has a single pulse TYPE of logic level 0 having a pulse width equal to the output delay time W2, as shown in FIG. Generates an output delay adjustment signal OPS including. When the output delay control signal SWa represents the output delay time W3, the output delay adjusting unit CND has a single pulse SLW of logic level 0 having a pulse width equal to the output delay time W3, as shown in FIG. Generates an output delay adjustment signal OPS including.

Output delay adjusting unit CND a single pulse FST described above, the output delay adjustment signal OPS containing TYP or SLW, when the luminance level represented by the pixel data Q ₁ is detected that it has increased or decreased, the transistor TX Supply to the gate end of.

The source end of the transistor TX is connected to the output line LOT, and the drain end is connected to the _{output terminal OT 1.} The transistor TX is turned on while the output delay adjustment signal OPS supplied to its gate end represents logic level 1, and the voltage of the output line LOT is set as the display drive voltage G _{1 and} is passed through the output terminal OT _1. And output. On the other hand, while the output delay adjustment signal OPS supplied to its own gate end represents the logic level 0, the transistor TX is turned off and the connection between the _{output line LOT and the output terminal OT 1 is cut off.
The operation of the amplifier AG 1} having the configuration shown in FIG. 13 will be described below with reference to the time chart shown in FIG. In FIG. 14, the luminance level represented by the pixel data Q ₁ is, at time t0, an output delay adjustment that is generated when a transition to a higher brightness level Yb than the luminance level Ya from the state of the luminance level Ya The waveforms of the signal OPS and the display drive voltage G _{1 output from the amplifier AG 1} are shown.

First, while the pixel data Q ₁ representing the luminance level Ya is being supplied, the amplification unit (DF1, DF2, R1, R2) of the _{amplifier AG 1} is a display drive having _{a voltage value V DT1 corresponding to the luminance level Ya.} The voltage G ₁ is output via the output terminal OT _1.

Then, at time t0, the luminance level represented by the pixel data Q ₁ is a transition from Ya to Yb, the amplification portion of the amplifier AG ₁ the voltage of the output line LOT, from the voltage value V _DT1, the brightness level Yb Amplification processing is performed to increase the corresponding voltage value V _DT2.

At this time, the amplifier AG _1, output delay by adjusting signal OPS is supplied to the gate terminal of the transistor TX, pixel data Q output delay time from the time point t0 when the luminance level transitions from Ya to Yb represented by ₁ W1 , W2 or W3, the transistor TX is turned off.

Therefore, the voltage value of the display drive voltage G _{1 is the voltage value V DT1} corresponding to the luminance level Ya to the voltage value V corresponding to the luminance level Yb from the time when the output delay time (W1 to W3) elapses from the time point t0. It will gradually increase toward _DT2.

For example, when the output delay control signal SWa representing the output delay time W1 is supplied to the output delay adjusting unit CND, as shown in FIG. 14, the logic level becomes 0 only between the time point t0 and the output delay time W1. The output delay adjustment signal OPS including the one-pulse FST is supplied to the gate end of the transistor TX. As a result, the transistor TX is turned off from the time point t0 to the output delay time W1, and the connection between the _{output line LOT and the output terminal OT 1 is cut off.} Then, after the output delay time W1 elapses, the transistor TX transitions to the ON state. Therefore, the display drive voltage G ₁ starts increasing from the state of the _{voltage value V DT 1 toward the voltage value V DT 2} at the time point t 1 when the output delay time W1 elapses from the time point t 0, as shown by the solid line in FIG. do.

Further, when the output delay control signal SWa representing the output delay time W2 is supplied to the output delay adjusting unit CND, as shown in FIG. 14, the logic level becomes 0 only between the time point t0 and the output delay time W2. An output delay adjustment signal OPS including a one-pulse TYPE is supplied to the gate end of the transistor TX. As a result, the transistor TX is turned off from the time point t0 to the output delay time W2, and the connection between the _{output line LOT and the output terminal OT 1 is cut off.} Then, after the output delay time W2 elapses, the transistor TX transitions to the ON state. Therefore, the display drive voltage G ₁ increases from the state of the _{voltage value V DT1} toward the _{voltage value V DT2} at the time t2 when the output delay time W2 elapses from the time point t0, as shown by the alternate long and short dash line in FIG. Start.

Further, when the output delay control signal SWa representing the output delay time W3 is supplied to the output delay adjusting unit CND, as shown in FIG. 14, the logic level becomes 0 only between the time point t0 and the output delay time W3. The output delay adjustment signal OPS including the one-pulse SLW is supplied to the gate end of the transistor TX. As a result, the transistor TX is turned off from the time point t0 to the output delay time W3, and the connection between the _{output line LOT and the output terminal OT 1 is cut off.} Then, after the output delay time W3 elapses, the transistor TX transitions to the ON state. Therefore, the display drive voltage G ₁ increases from the state of the _{voltage value V DT1} toward the _{voltage value V DT2} at the time t3 when the output delay time W3 elapses from the time point t0, as shown by the alternate long and short dash line in FIG. To start.

Below, the output delay based on the output delay data MOD, considering the wiring delay in each printed wiring that individually connects _{the output terminals OT 1 to OT n} of the data driver 13 and the data lines D _{1 to} D _{n of the display device 20.} The setting operation of is described.

First, as a form of wiring delay due to each of the printed wirings individually connected to the data lines D _{1 to} D _n , the wiring connected to the _{data lines D 1 arranged at the left end of the screen of the display device 20 is used.} Assume a delay form that is maximum and decreases toward the right end. Here, when the output delays of the amplifiers AP _{1 to AP n} are all the output delay time W2, until the display drive voltages G _{1 to} G _n output from the data driver 13 reach the data lines D _{1 to} D _n. The delay time spent on the data is in the form of a delay as shown by the alternate long and short dash line in FIG.

Therefore, the difference between the maximum delay time and the minimum delay time in the screen of the display device 20 is the delay time difference DL between the delay time _{on the data line D 1} and the delay time on the data line D _{n as shown in FIG.} Therefore, display unevenness corresponding to this delay time difference DL will occur.

Therefore, at this time, the output delay data MOD representing the first delay mode shown in FIG. 12 is supplied to the output delay setting unit DSX. Thus, the output delay setting unit DSX supplies the output delay control signal SWa representative of the output delay time W1, each of AG ₁ ~AG _r belonging to amplifier group CHa which is connected to the data lines D ₁ to D _r .. At this time, the output delay setting unit DSX transmits the output delay control signal SWb representing the output delay time W2 _{to AG r + 1} to AG belonging to the amplifier group CHb connected to the _{data lines D r + 1 to} D _k. Supply to each of _k. Further, the output delay setting unit DSX transmits the output delay control signal SWc representing the output delay time W3 to each of _{AG k + 1 to} AG _n belonging to the amplifier group CH c connected to the _{data lines D k + 1 to} D _n. Supply to.

Therefore, among the amplifiers AG _{1 to} AG _n , the output delay time of the amplifiers AG _{1 to} AG _r is the minimum output delay time W1, and the output delay time of the amplifiers AG _{k + 1 to} AG _n is the maximum output delay time W3. Therefore, the output delay time of the amplifiers AG _{r + 1 to} AG _k is an intermediate output delay time W2. As a result, the delay time in each of the data lines D _{r + 1 to} D _{k corresponding to the amplifiers AG r + 1 to} AG _k does not change as shown by the solid line in FIG. On the other hand, the delay time in each of the data lines D _{1 to} D _{r corresponding to the amplifiers AG 1 to} AG _r is reduced as a whole as shown by the solid line in FIG. On the other hand, the delay time in each of the data lines D _{k + 1 to} D _{n corresponding to the amplifiers AG k + 1 to} AG _n increases as a whole as shown by the solid line in FIG.

Therefore, by supplying the output delay data MOD representing the first delay mode to the output delay setting unit DSX, the delay time difference DLX in the screen of the display device 20 is smaller than the delay time difference DL, as shown in FIG. Become.

Therefore, as the delay time difference becomes smaller, the brightness difference in the screen also becomes smaller, so that display unevenness can be suppressed.

Next, as a form of wiring delay due to each of the printed wirings individually connected to the data lines D _{1 to} D _n , the wiring connected to the _{data lines D n arranged at the right end of the screen of the display device 20.} Is assumed to be a delay form in which is maximum and decreases toward the left end. Here, when the output delays of the amplifiers AP _{1 to AP n} are all the output delay time W2, until the display drive voltages G _{1 to} G _n output from the data driver 13 reach the data lines D _{1 to} D _n. The delay time spent on the data is in the form of a delay as shown by the alternate long and short dash line in FIG.

Therefore, the difference between the maximum delay time and the minimum delay time in the screen of the display device 20 is the delay time difference DL between the delay time _{on the data line D n} and the delay time on the data line D _{1 as shown in FIG.} Therefore, display unevenness corresponding to this delay time difference DL will occur.

Therefore, at this time, the output delay data MOD representing the second delay mode shown in FIG. 12 is supplied to the output delay setting unit DSX. Thus, the output delay setting unit DSX supplies the output delay control signal SWa representative of the output delay time W3, each of AG ₁ ~AG _r belonging to amplifier group CHa which is connected to the data lines D ₁ to D _r .. At this time, the output delay setting unit DSX transmits the output delay control signal SWb representing the output delay time W2 _{to AG r + 1} to AG belonging to the amplifier group CHb connected to the _{data lines D r + 1 to} D _k. Supply to each of _k. Further, the output delay setting unit DSX transmits the output delay control signal SWc representing the output delay time W1 to each of _{AG k + 1 to} AG _n belonging to the amplifier group CH c connected to the _{data lines D k + 1 to} D _n. Supply to.

Therefore, among the amplifiers AG _{1 to} AG _n , the output delay time of the amplifiers AG _{1 to} AG _r is the maximum output delay time W1, and the output delay time of the amplifiers AG _{k + 1 to} AG _n is the minimum output delay time W3. Therefore, the output delay time of the amplifiers AG _{r + 1 to} AG _k is an intermediate output delay time W2. As a result, the delay time in each of the data lines D _{r + 1 to} D _{k corresponding to the amplifiers AG r + 1 to} AG _k does not change as shown by the solid line in FIG. On the other hand, the delay time in each of the data lines D _{1 to} D _{r corresponding to the amplifiers AG 1 to} AG _r increases as a whole as shown by the solid line in FIG. On the other hand, the delay time in each of the data lines D _{k + 1 to} D _{n corresponding to the amplifiers AG k + 1 to} AG _n is reduced as a whole as shown by the solid line in FIG.

Therefore, by supplying the output delay data MOD representing the second delay mode to the output delay setting unit DSX, as shown in FIG. 16, the delay time difference DLX in the screen of the display device 20 is obtained from the delay time difference DL described above. Also becomes smaller.

Therefore, as the delay time difference becomes smaller, the brightness difference in the screen also becomes smaller, so that display unevenness can be suppressed.

Next, as a form of wiring delay due to each of the printed wirings individually connected to the data lines D _{1 to} D _{n , they are connected to the data lines D 1} and D _{n arranged at both ends of the screen of the display device 20.} Assume a delay form in which the wiring is maximized and becomes smaller toward the center of the screen. Here, when the output delays of the amplifiers AP _{1 to AP n} are all the output delay time W2, until the display drive voltages G _{1 to} G _n output from the data driver 13 reach the data lines D _{1 to} D _n. The delay time spent on the data is in the form of a delay as shown by the alternate long and short dash line in FIG.

Therefore, the difference between the maximum delay time and the minimum delay time in the screen of the display device 20 is the delay time at the data line D _n or D _n and the data line arranged near the center as shown in FIG. For example _{, the delay time difference DL from the delay time at D n / 2} ) will occur, and display unevenness corresponding to this delay time difference DL will occur.

Therefore, at this time, the output delay data MOD representing the third delay mode shown in FIG. 12 is supplied to the output delay setting unit DSX. Thus, the output delay setting unit DSX supplies the output delay control signal SWa representative of the output delay time W2, each of AG ₁ ~AG _r belonging to amplifier group CHa which is connected to the data lines D ₁ to D _r .. At this time, the output delay setting unit DSX transmits the output delay control signal SWb representing the output delay time W3 _{to AG r + 1} to AG belonging to the amplifier group CHb connected to the _{data lines D r + 1 to} D _k. Supply to each of _k. Further, the output delay setting unit DSX transmits the output delay control signal SWc representing the output delay time W2 to each of _{AG k + 1 to} AG _n belonging to the amplifier group CH c connected to the _{data lines D k + 1 to} D _n. Supply to.

Therefore, among the amplifiers AG _{1 to} AG _n , the output delay time of the amplifiers AG _{r + 1 to} AG _k is the minimum output delay time W1, and the output delays of the amplifiers AG _{1 to} AG _r and AG _{k + 1 to} AG _n . The time is the output delay time W2. As a result, the delay times for each of the data lines D _{1 to} D _r and D _{k + 1 to} D _{n corresponding to the amplifiers AG 1 to} AG _r and AG _{k + 1 to} AG _n are shown by the solid line in FIG. Does not change. On the other hand, the delay time in each of the data lines D _{r + 1 to} D _{k corresponding to the amplifiers AG r + 1 to} AG _k increases as a whole as shown by the solid line in FIG.

Therefore, by supplying the output delay data MOD representing the third delay mode to the output delay setting unit DSX, as shown in FIG. 17, the delay time difference DLX in the screen of the display device 20 is obtained from the delay time difference DL described above. Also becomes smaller.
Therefore, as the delay time difference becomes smaller, the brightness difference in the screen also becomes smaller, so that display unevenness can be suppressed.

In the above embodiment, the amplifier AP1~APn the (AG ₁ ~AG _n) 3 a group (CHa, CHb, CHc) is divided into, but so as to adjust the output delay time of each amplifier in groups , The output delay time may be adjusted individually for each amplifier.

In short, a plurality of display drive voltages (G _{1 to} G _{n ) obtained by individually amplifying a plurality of gradation voltages (V 1 to} V _n ) representing the brightness level of each pixel are displayed on a plurality of display devices (20). If the display driver supplied to the data line (D _{1 to} D _n ) includes the following output delay setting units (DST, DSX) and multiple amplifiers (AP _{1 to AP n} , AG _{1 to} AG _n ). good. That is, the output delay setting unit receives output delay data (MOD) that specifies the output delay time of each of the plurality of amplifiers, and output delay control signals (SWa to SWc) corresponding to the output delay time of each of the plurality of amplifiers. To generate. Then, each amplifier adjusts the output delay of its own amplification unit based on the output delay control signal and the amplification unit (DF1, DF2, R1, R2) that outputs the voltage obtained by amplifying the gradation voltage as the display drive voltage. It has an output delay adjusting unit (CNT, SS1, SS2, PT1, PT2, CND, TX).

As a result, even if there is a difference in the wiring delay due to the wiring connecting the display driver and each data line of the display device, the display driver is based on the output delay data without changing the internal configuration of the display driver. It is possible to reduce the difference in the delay time required for the display drive voltage sent from the data line to reach each data line. Therefore, according to the present invention, the display on the screen caused by the delay time difference corresponds to various forms of wiring delay associated with the wiring connecting the display driver and the display device without increasing the manufacturing cost. It is possible to suppress unevenness.

13 Data driver 133 Output amplifier section AP _{1 to AP n} Amplifier CNT PC control section DST Output delay setting section PT1, PT2 Transistor SS1, SS2 Switch element

Claims (7)

A display driver that includes a plurality of amplifiers that supply a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness levels of each pixel to a plurality of data lines of a display device.
Output delay data that specifies the time from when the gradation voltage is received for each of the plurality of amplifiers until the voltage value of the display drive voltage reaches the voltage value corresponding to the gradation voltage as the output delay time. Includes an output delay setting unit that receives and generates an output delay control signal corresponding to the output delay time for each of the plurality of amplifiers.
Each of the plurality of amplifiers
An amplification unit that outputs a voltage obtained by amplifying the gradation voltage as the display drive voltage,
Includes an output delay adjusting unit that adjusts the output delay of the amplification unit based on the output delay control signal.
The amplification unit
The output line that transmits the display drive voltage and
A differential circuit that generates an output voltage drive signal having a level corresponding to the difference between the voltage of the output line and the gradation voltage, and
It includes an output transistor that receives the output voltage drive signal at its own gate end and sends a current of a magnitude corresponding to the output voltage drive signal to the output line.
The output delay adjustment unit
A display driver comprising a precharge circuit that adjusts the output delay time depending on whether or not the gate end of the output transistor is precharged based on the output delay control signal. The output delay setting unit
As the output delay data, data is received in which the output delay time of each of the plurality of amplifiers is designated in two stages of a first delay time and a second delay time longer than the first delay time, and each of the plurality of amplifiers receives data. Generates the output delay control signal representing one of the first delay time and the second delay time.
The output delay adjustment unit
When the output delay control signal represents the first delay time, the precharge is executed, while when the output delay control signal represents the second delay time, the precharge is stopped. The display driver according to claim 1. The display driver according to claim 2, wherein the output delay adjusting unit executes the precharge for a predetermined period when the increase or decrease of the luminance level is detected. A display driver that includes a plurality of amplifiers that supply a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness levels of each pixel to a plurality of data lines of a display device.
Each of the plurality of amplifiers receives output delay data in which the time from receiving the gradation voltage to outputting the display drive voltage is designated as an output delay time, and the output delay is received for each of the plurality of amplifiers. Includes an output delay setting unit that generates an output delay control signal corresponding to time.
Each of the plurality of amplifiers
An amplification unit that outputs a voltage obtained by amplifying the gradation voltage as the display drive voltage,
Includes an output delay adjusting unit that adjusts the output delay of the amplification unit based on the output delay control signal.
The amplification unit
The output line that transmits the display drive voltage and
Including output terminal,
The output delay adjusting unit includes an output switch that connects or disconnects the output line and the output terminals, and the output delay time represented by the output delay control signal when an increase or decrease in the luminance level is detected. A display driver characterized in that the output switch is set to the cutoff state only during the period. The plurality of amplifiers include a first amplifier group that drives each of the data lines responsible for displaying the left region of the screen of the display device among the plurality of data lines, and a data line responsible for displaying the central region of the screen. It is divided into a second amplifier group that drives each and a third amplifier group that drives each of the data lines responsible for displaying the right area of the screen.
The output delay setting unit
Upon receiving the output delay data that specifies the output delay time for each of the first to third amplifier groups,
The first to third output delay control signals corresponding to the output delay times corresponding to each of the first to third amplifier groups are generated.
The output delay adjusting unit included in each of the amplifiers belonging to the first amplifier group is based on the first output delay control signal, and the output delay of the amplification unit included in each of the amplifiers belonging to the first amplifier group. Adjust and
The output delay adjusting unit included in each of the amplifiers belonging to the second amplifier group is the output of the amplification unit included in each of the amplifiers belonging to the second amplifier group based on the second output delay control signal. Adjust the delay,
The output delay adjusting unit included in each of the amplifiers belonging to the third amplifier group is the output of the amplification unit included in each of the amplifiers belonging to the third amplifier group based on the third output delay control signal. The display driver according to any one of claims 1 to 4, wherein the delay is adjusted. A semiconductor device in which a display driver including a plurality of amplifiers is formed to supply a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness levels of each pixel to a plurality of data lines of a display device. And
Output delay data that specifies the time from when the gradation voltage is received for each of the plurality of amplifiers until the voltage value of the display drive voltage reaches the voltage value corresponding to the gradation voltage as the output delay time. Includes an output delay setting unit that receives and generates an output delay control signal corresponding to the output delay time for each of the plurality of amplifiers.
Each of the plurality of amplifiers
An amplification unit that outputs a voltage obtained by amplifying the gradation voltage as the display drive voltage,
Includes an output delay adjusting unit that adjusts the output delay of the amplification unit based on the output delay control signal.
The amplification unit
The output line that transmits the display drive voltage and
A differential circuit that generates an output voltage drive signal having a level corresponding to the difference between the voltage of the output line and the gradation voltage, and
It includes an output transistor that receives the output voltage drive signal at its own gate end and sends a current having a magnitude corresponding to the output voltage drive signal to the output line.
The output delay adjustment unit
A semiconductor device comprising a precharge circuit that adjusts the output delay time depending on whether or not the gate end of the output transistor is precharged based on the output delay control signal. A semiconductor device in which a display driver including a plurality of amplifiers is formed to supply a plurality of display drive voltages obtained by individually amplifying a plurality of gradation voltages representing the brightness levels of each pixel to a plurality of data lines of a display device. And
Each of the plurality of amplifiers receives output delay data in which the time from receiving the gradation voltage to outputting the display drive voltage is designated as an output delay time, and the output delay is received for each of the plurality of amplifiers. Includes an output delay setting unit that generates an output delay control signal corresponding to time.
Each of the plurality of amplifiers
An amplification unit that outputs a voltage obtained by amplifying the gradation voltage as the display drive voltage,
Includes an output delay adjusting unit that adjusts the output delay of the amplification unit based on the output delay control signal.
The amplification unit
The output line that transmits the display drive voltage and
Including output terminal,
The output delay adjusting unit includes an output switch that connects or disconnects the output line and the output terminals, and the output delay time represented by the output delay control signal when an increase or decrease in the luminance level is detected. A semiconductor device characterized in that the output switch is set to a cutoff state only during the period.

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