JP6918090B2 - Liquid crystal display device - Google Patents

Description

The present invention relates to a display device, and more particularly to a display device whose display area and outer shape are not rectangular.

In a liquid crystal display device, which is one of the display devices, a TFT substrate in which pixels having pixel electrodes and thin film transistors (TFTs) are formed in a matrix, and an opposing substrate are arranged facing the TFT substrate, and the TFT substrate and the opposing substrate are arranged. The liquid crystal is sandwiched between and. An image is formed by controlling the light transmittance of the liquid crystal molecules for each pixel. Since liquid crystal display devices are flat and lightweight, their applications are expanding in various fields.

Most liquid crystal display devices have a rectangular display area or outer shape, but in display devices used in automobiles, display devices used in various games, etc., there is a requirement for a display device in which the outer shape of the display area or device is not rectangular. Also exists. Patent Document 1 describes problems and countermeasures of the scanning line drive circuit caused by the display device not being rectangular.

Japanese Unexamined Patent Publication No. 2008-292995

If the display area is not rectangular, the layout of peripheral circuits and wiring arranged around the display device will be different from that when the display area is not rectangular. Further, if the display device is not rectangular, a problem that does not occur when the display area is rectangular arises. Hereinafter, the non-rectangular display area is referred to as a deformed display area, and the non-rectangular display panel is referred to as a deformed display panel.

Even in the case of a deformed display panel, high resolution is often required. At high resolution, the number of pixels in the horizontal direction increases, and the number of drain lines that supply video signals to the pixels also increases. As the number of drain lines increases, the number of drain routing lines increases outside the display area, and the area of the wiring area for this purpose increases. In particular, recently, there has been a demand for reducing the width from the edge of the display area to the edge of the display panel, that is, the so-called frame area. For this purpose, it is necessary to reduce the number of drain routing lines.

In order to prevent the number of drain routing lines from increasing, the number of video signal lines supplied from the driver IC is reduced to 1/2 or 1/3 by using a selector circuit as described later, and the routing wires are used. There is a technology to reduce the number of. However, when the selector circuit is used in the irregular display area, interference between the selector circuit and the scanning line or common wiring and the selector circuit (intersection on the layout, or electrical influence due to the intersection or proximity) occurs.

An object of the present invention is to realize a display area in which a frame area can be suppressed even when a deformed display panel having a deformed display area having a selector circuit is used.

The present invention overcomes the above problems, and the main specific means are as follows.

(1) The scanning lines extend in the first direction and are arranged in the second direction, the drain lines extend in the second direction and are arranged in the first direction, and the scanning lines and the drain lines are arranged. A liquid crystal display device in which an opposing substrate is arranged via a liquid crystal display on a TFT substrate in which pixels are formed in an area surrounded by, and the outer shape of the display area is not rectangular, and a video signal is supplied to the outside of the display area. There is a selector having a selector TFT between the display area and the driver, a video signal line exists between the driver and the selector, and there is a video signal line between the selector and the display area. Is Nd / Nv = n, where Nd is the number of drain lines corresponding to the display area and Nv is the number of video signal lines corresponding to the drain lines. n is an integer greater than or equal to 2
Outside the display area, there is a scanning circuit that supplies a scanning signal to the scanning line, and the selector is located between the scanning line and the display area, or between the scanning circuit and the display area. A liquid crystal display device that exists, wherein the selector is covered by ITO, which is a common electrode, and a common bus wiring is arranged outside the selector.

(2) The liquid crystal display device according to (1), wherein the selector control signal line for supplying the gate voltage to the selector TFT is formed of the same layer as the drain line.

It is sectional drawing of the display area of a liquid crystal display device. This is an example of a deformed display panel. It is an equivalent circuit showing the configuration of the selector. It is a schematic diagram which shows the periphery of the display area. It is a top view which shows the layout around the display area up to the state where a drain line is formed. It is a top view which shows the layout around the display area up to the state where a pixel electrode is formed. It is sectional drawing in the selector part. This is another example of a variant display panel. It is a top view which shows the layout when the display area is rectangular.

There are various types of display devices, but one of them, a liquid crystal display device, has a problem of viewing angle characteristics. The viewing angle characteristic is a phenomenon in which the brightness changes or the chromaticity changes when the screen is viewed from the front and when viewed from an oblique direction. As for the viewing angle characteristic, the IPS (In Plane Switching) method in which the liquid crystal molecules are operated by an electric field in the horizontal direction has excellent characteristics. In the following embodiments, the IPS type liquid crystal display device will be described as a premise. The present invention covers the configuration outside the display area, but for the purpose of explaining the layer structure, first, the cross-sectional structure of the display area will be described.

FIG. 1 is a cross-sectional view of an IPS liquid crystal display device. The TFT in FIG. 1 is a so-called top gate type TFT, and LTPS (Low Temperature Poly-Si) is used as the semiconductor used. In FIG. 1, a first base film 101 made of SiN and a _{second base film 102 made of SiO 2} are formed on a glass substrate 100 by CVD (Chemical Vapor Deposition). The role of the first base film 101 and the second base film 102 is to prevent impurities from the glass substrate 100 from contaminating the semiconductor layer 103.

A semiconductor layer 103 is formed on the second base film 102. The semiconductor layer 103 is formed by forming an a-Si film on the second base film 102 by CVD and converting it into a poly-Si film by laser annealing. This poly-Si film is patterned by photolithography.

A gate insulating film 104 is formed on the semiconductor film 103. The gate insulating film 104 is a SiO ₂ film made of TEOS (tetraethoxysilane). This film is also formed by CVD. A gate electrode 105 is formed on the gate electrode 105. The gate electrode 105 also serves as a scanning line. The gate electrode 105 is formed of, for example, a MoW film. When it is necessary to reduce the resistance of the gate electrode 105 or the scanning line 10, an Al alloy is used.

The interlayer insulating film 106 is formed _{of SiO 2} so as to cover the gate electrode 105. This is because the interlayer insulating film 106 insulates the gate wiring 105 and the contact electrode 107. Through holes 120 for connecting the source portion S of the semiconductor layer 103 to the contact electrode 107 are formed in the interlayer insulating film 106 and the gate insulating film 104. Photolithography for forming through holes 120 in the interlayer insulating film 106 and the gate insulating film 104 is performed at the same time.

The contact electrode 107 is formed on the interlayer insulating film 106. The contact electrode 107 is connected to the pixel electrode 112 via a through hole 130. The TFT is connected to the drain wire at a portion (not shown).

The contact electrode 107 and the drain wire are formed in the same layer at the same time. For the contact electrode 107 and the drain wire (hereinafter, represented by the contact electrode 107), for example, an AlSi alloy is used in order to reduce the resistance. Since the AlSi alloy generates hillocks and Al diffuses into other layers, for example, a barrier layer made of MoW (not shown) and a cap layer sandwich AlSi.

The contact electrode 107 is covered with an inorganic passivation film (insulating film) 108 to protect the entire TFT. The inorganic passivation film 108 is formed by CVD in the same manner as the first base film 101. The organic passivation film 109 is formed so as to cover the inorganic passivation film 108. The organic passivation film 109 is made of a photosensitive acrylic resin. The organic passivation film 109 can be formed of a silicone resin, an epoxy resin, a polyimide resin, or the like in addition to the acrylic resin. Since the organic passivation film 109 has a role as a flattening film, it is formed thick. The film thickness of the organic passivation film 109 is 1 to 4 μm, but in most cases it is about 2 μm.

Through holes 130 are formed in the organic passivation film 109 in order to establish continuity between the pixel electrode 112 and the contact electrode 107. After that, ITO (Indium Tin Oxide) to be the common electrode 110 is formed by sputtering, and patterned so as to remove ITO from the through hole 130 and its periphery. The common electrode 110 can be formed in a flat shape in common with each pixel. Since the common electrode is an ITO formed at the beginning, it is sometimes called a first ITO.

After that, SiN to be the capacitive insulating film 111 is formed on the entire surface by CVD. After that, in the through hole 130, a through hole for making the contact electrode 107 and the pixel electrode 112 conductive is formed in the capacitive insulating film 111 and the inorganic passivation film 108.

After that, ITO is formed by sputtering and patterned to form the pixel electrode 112. Since the pixel electrode is the second ITO formed, it is sometimes called the second ITO. The plane of the pixel electrode has a curved stripe shape as shown in FIG. 6, for example. The reason why the pixel electrodes are bent is to make the viewing angle characteristics more uniform. The alignment film material is applied onto the pixel electrode 112 by flexographic printing, inkjet, or the like, and fired to form the alignment film 113. In addition to the rubbing method, a photo-alignment method using polarized ultraviolet rays is used for the alignment treatment of the alignment film 113.

When a voltage is applied between the pixel electrode 112 and the common electrode 110, electric lines of force as shown in FIG. 1 are generated. An image is formed by rotating the liquid crystal molecules 301 by this electric field and controlling the amount of light passing through the liquid crystal layer 300 for each pixel.

In FIG. 1, the opposing substrate 200 is arranged with the liquid crystal layer 300 interposed therebetween. A color filter 201 is formed inside the facing substrate 200. The color filter 201 is formed with red, green, and blue color filters for each pixel, whereby a color image is formed. A black matrix 202 is formed between the color filter 201 and the color filter 201 to improve the contrast of the image. The black matrix 202 also serves as a light-shielding film for the TFT, and prevents photocurrent from flowing through the TFT.

The overcoat film 203 is formed so as to cover the color filter 201 and the black matrix 202. Since the surfaces of the color filter 201 and the black matrix 202 are uneven, the surfaces are flattened by the overcoat film 203. An alignment film 113 for determining the initial orientation of the liquid crystal is formed on the overcoat film. As for the alignment treatment of the alignment film 113, a rubbing method or a photoalignment method is used as in the alignment film 113 on the TFT substrate 100 side.

The above configuration is an example, and for example, the inorganic passivation film 108 in the TFT substrate 100 may not be formed depending on the product type. Further, the process of forming the through hole 130 may also differ depending on the type. The present invention will be described in detail below with reference to examples.

FIG. 2 is an example of a deformed display panel. FIG. 2 shows a race track shape in which both the display area 1000 and the outer shape are straight at the top and bottom and curved at the sides. FIG. 2 is a plan view of the TFT substrate side. In FIG. 2, in the display area 1000, the scanning lines 10 extend in the horizontal direction, the drain lines 20 extend in the vertical direction, and pixels are formed in the area surrounded by the scanning lines 10 and the drain lines 20. There is.

In FIG. 2, the selector 30 and the driver IC 40 are arranged below the display area 1000. The outside of the driver IC 40 is a terminal area 150 for connecting to the flexible wiring board. A video signal is supplied from the driver IC 40 to the drain line 20 of the display area 1000 via the selector 30. The drain line 20 exists for the pixels in the horizontal direction of the display area 1000, but the number of the video signal lead-out lines 21 from the driver IC 40 to the selector 30 is, for example, 1/3 of the drain line. Assuming that the number of drain lines is Nd and the number of video signal lead lines is Nv, Nd / Nv = n and n is an integer of 2 or more.

Scanning circuits 11 for supplying scanning signals to the scanning lines 10 are present on both sides of the display area 1000. In FIG. 2, the selector 30 is arranged adjacent to the display area 1000. Since the display area 1000 has a race track shape, a selector 30 exists between the scanning circuit 11 and the display area 1000 in the area A outside the curved portion on the side of the display area 1000. In this case, wiring interference occurs between the scanning line 10 and the selector 30.

FIG. 9 is a plan view of the display device when the display area 1000 is rectangular. In FIG. 9, the selector 30, the driver IC 40, and the terminal portion 150 are arranged in this order on the lower side of the display area 1000, and the scanning circuits 11 are present on both sides of the display area 1000. In this case, there is no interference between the scanning line 10 extending from the scanning circuit 11 and the selector 30.

The present invention provides a configuration for preventing interference between the scanning line 10 and the selector 30 and reducing the frame area in the deformed display panel. FIG. 3 is an equivalent circuit showing the configuration of the selector 30. The upper side is the display area side, and the lower side is the driver IC side. In FIG. 3, pixels 50 having a TFT 51 and a pixel capacity 52 are arranged in the horizontal direction. A video signal is supplied to each pixel 50 via the drain line 20. Further, the TFT 51 of each pixel 50 is controlled by the scanning line 10.

The selector 30 is arranged to reduce the number of drain leader lines (video signal leader lines) 21 outside the display area, and is arranged adjacent to the outermost side of the display area. Due to the selector in FIG. 3, the number of video signal lead-out lines 21 output from the driver IC is 1/3 of the drain line 20. Therefore, it is possible to save the area for the routing wiring of the video signal lead wire 21.

On the other hand, in order to control the selector 30, the selector control line 31 is required. FIG. 4 is a plan view showing the arrangement of the selector 30 and the pixel 50 in the area A of FIG. In FIG. 4, the set of the three pixels 50 of the red pixel R, the green pixel G, and the blue pixel B is formed in a stepped shape so that the outer end of the display area 1000 is approximated by a curve. The selector 30 corresponding to each pixel set is formed adjacent to the pixel set. Conventionally, a common bus wiring for supplying a common voltage to a common electrode in the display region has been formed adjacent to the outer end portion of the display region 1000, but the present invention differs in that the selector 30 is arranged. There is.

A scanning line is connected to each pixel from a scanning circuit arranged outside in the horizontal direction of FIG. That is, although the selector 30 has a selector TFT, it is necessary to prevent interference between the gate electrode of the selector TFT, that is, the selector control line and the scanning line.

FIG. 5 is a plan view showing a wiring layout near the end of the display area up to the state where the drain line 20 is formed. In the display area of FIG. 5, drain lines 20 bent in a dogleg shape extend in the vertical direction and are arranged in the horizontal direction, and scanning lines 10 extend in the horizontal direction and are arranged in the vertical direction. .. The region surrounded by the drain line 20 and the scanning line 10 is a pixel, and a pixel electrode is formed, but in FIG. 5, the pixel electrode is not yet formed. In FIG. 5, the side on which the drain line 20 is formed is the display area from the dotted line.

A selector TFT 32 is arranged for each drain line 20 adjacent to the outermost pixel. Three selector control lines 31 for sending a gate signal to each selector TFT 32 extend outside the selector TFT 32. In order to prevent interference between the scanning line 10 and the selector control signal line 31, the selector control line 31 is wired in the same layer as the drain line 20, and immediately before connecting to the selector TFT 32, the selector control line 31 and the scanning line 10 are connected through a through hole. I'm switching to the same layer. As a result, the selector 30 can be arranged adjacent to the display area even if the display area is irregular.

A video signal is commonly sent to the three selector TFTs 32 as a set via the video signal lead-out line 21. This video signal is distributed and supplied to the drain line 20 by the signal passing through the selector control line 31. Therefore, in FIG. 5, the number of video signal lead-out lines 21 is one-third of the number of drain lines 20. In the present invention, the selector is provided close to the display area. Therefore, the video signal lead-out line 21 and the scanning line intersect. However, when the selector is provided away from the display area, the number of intersections between the video signal lead-out line and the scanning line can be reduced, but the number of intersections with the drain line increases. According to the configuration of the present invention, the number of intersections between the scanning line and the drain line can be reduced. Further, by providing the selector control line 31 between the video signal lead-out line and the selector, the number of intersections between the selector control line and the video signal lead-out line can be reduced, and the length of the selector control line can be shortened. be able to. Although the selector control line is arranged along the selector in FIG. 5, it can be provided in parallel with the video line leader line. As a result, the length of the selector control line can be further shortened.

By the way, as shown in FIG. 4, the number of pixels in the Y direction handled by each selector differs depending on the X direction. For example, in the portion where the outer shape of the display area 1000 is a straight line, the number of pixels handled by the selector 30 is 320 pixels, and in the portion where the outer shape of the display area is curved, the number of pixels handled by the selector 30 is the smallest. Is 6 pixels.

Then, the resistance and capacitance of the wiring handled by each selector 30 are different, and therefore the magnitude and delay of the signal are different depending on the location. In order to prevent this, in the present invention, the channel width of the selector TFT 32 is changed depending on the location. For example, the channel width of the selector TFT 32 arranged in the straight portion is made larger than the channel width of the selector TFT 32 arranged in the curved portion. Further, the channel width of the selector TFT 32 arranged on the curved portion is also changed depending on the location. As a result, a uniform image can be formed even on a deformed display panel.

FIG. 6 is a plan view in a state where the pixel electrodes 112 are formed in the same region as in FIG. That is, with respect to FIG. 5, the inorganic passivation film, the organic passivation film, the common electrode, the capacitive insulating film, and the pixel electrode are laminated and formed. In FIG. 6, the side on which the drain line 20 is formed is the display area from the dotted line.

In FIG. 6, the common electrode 110, which is a transparent electrode, is formed on the entire surface except for the through hole 130. In the display region, the pixel electrode 112 is formed by ITO in the region surrounded by the drain line 20 and the scanning line 10. On the outside of the display area, dummy pixel electrodes 1121 having the same shape as the pixel electrodes 112 are formed at the same pitch as the pixel electrodes 112 in the display area. As a result, the pixel electrode 112 on the outermost side of the display region can be formed under the same process conditions as the pixel electrode 112 in the other display region. As will be described later, a common voltage can be applied to the dummy pixel electrode 1121.

FIG. 7 is a cross-sectional view corresponding to AA of FIG. 5, and shows a cross-sectional view of the vicinity of the selector TFT 32. The layer structure is the same as the cross-sectional structure in the display area described with reference to FIG. That is, the gate insulating film 104 is formed on the semiconductor layer 103, the gate electrode 105 is formed on the gate insulating film 104, and the interlayer insulating film 106 is formed over the gate electrode 105.

The gate electrode 105 is connected to the selector control line 31, and the source electrode is the video signal line 21. The drain electrode is the drain wire 20. That is, the selector TFT 32 has two source electrodes formed in parallel. An inorganic passivation film 108 is formed so as to cover the drain electrode and the source electrode, and an organic passivation film 109 is formed on the inorganic passivation film 108. On the organic passivation film 109, a common electrode 110 formed of ITO in a plane is formed.

A capacitive insulating film 111 is formed so as to cover the common electrode 110, and a dummy pixel electrode 1121 is formed on the capacitive insulating film 111. That is, in the present invention, the selector TFT 32 is covered with the common electrode 110. The common electrode 110 is formed continuously with the common electrode 110 in the display region. With such a configuration, the selector 30 is shielded by the common electrode 110. Then, a common voltage is supplied to the common electrode 110 from the common wiring (common bus wiring) formed further outside the selector 30.

Conventionally, the common bus wiring is formed adjacent to the display area, but in the configuration of the present invention, the common bus wiring is formed outside the selector 30. With such a configuration, the selector control line 31 can be formed in the same layer as the drain line 20 or the common bus wiring.

If the dummy pixel electrode 1121 shown in FIG. 6 is not desired to be floated, a through hole 140 may be formed in the capacitive insulating film 111 to supply a common voltage to the dummy pixel electrode 1121 as shown on the right side of FIG. You can. The through hole 140 formed in the capacitive insulating film 111 can be formed at the same time as the through hole formed in the capacitive insulating film 111 in the through hole 130 in the display region.

As described above, according to the present invention, even in the case of the deformed display panel, the selector can be formed adjacent to the display area, so that the area of the frame area in the deformed display panel is prevented from increasing. Can be done. Further, the selector can be shielded by the common electrode, and the channel width of the selector TFT can be changed depending on the location, so that a uniform screen can be formed even on a deformed display panel.

The above has described the racetrack-shaped irregular shape display panel as shown in FIG. 2, but the present invention is not limited to this, and for example, the heart-shaped irregular shape display panel as shown in FIG. 8 can also be applied. Almost the same configuration as described in FIG. 2 can be applied to the shape of FIG. That is, the area A in FIG. 8 can have the same configuration as the area A in FIG. However, since the upper part of the display area is not a straight line in FIG. 8, the capacitance of the selector TFT arranged below the display area, that is, the channel width needs to be changed also in the straight line part.

The irregular display area shown in FIGS. 2 and 8 is a combination of a straight line and a curved line, but it can also be used for a display device having a display area in which sides such as a triangle, a pentagon, and a hexagon are formed by a combination of straight lines. The present invention can be applied. Further, although the scanning circuits are present on both sides of the screen in FIGS. 2 and 8, the present invention can be applied even when the scanning circuits are present on one side of the screen. The present invention is not limited to the liquid crystal display device, but has a display area having a shape other than a rectangular shape, and supplies a video signal to the drain line (video signal line) of the display area in a time-divided manner. It can be applied to all display devices such as organic EL type display devices having (switch circuit).

10 ... scanning line, 11 ... scanning circuit, 20 ... drain line, 21 ... video signal line, 30 ... selector, 31 ... selector control signal line, 32 ... selector TFT, 40 ... driver IC, 50 ... pixel, 51 ... pixel TFT, 52 ... pixel capacity, 100 ... TFT substrate, 101 ... first base film, 102 ... second base film, 103 ... semiconductor layer, 104 ... gate insulating film, 105 ... gate electrode, 106 ... interlayer insulating film, 107 ... contact electrode, 108 ... inorganic passivation film, 109 ... organic passivation film, 110 ... common electrode, 111 ... capacitive insulating film, 112 ... pixel electrode, 113 ... alignment film, 120 ... first through hole, 130 ... second through hole , 140 ... through hole, 150 ... terminal area, 200 ... opposed substrate, 201 ... color filter, 202 ... black matrix, 203 ... overcoat film, 300 ... liquid crystal layer, 301 ... liquid crystal molecule, 1121 ... dummy pixel electrode, D ... Drain part, S ... Source part

Claims (8)

A display device having a TFT substrate on which a scanning line, a drain line, and a pixel electrode are formed.
The display device has a non-rectangular display area and a peripheral area surrounding the display area.
The scanning line supplies a scanning signal and is connected to a scanning circuit arranged in the peripheral region along the display region.
The pixel electrode has a first pixel electrode located in the display region and a second pixel electrode located in the peripheral region.
The scanning line has a first portion extending in the extending direction of the drain line in the peripheral region.
The second pixel electrodes are arranged at the same pitch as the first pixel electrodes in a direction perpendicular to the extending direction of the drain line.
The first pixel electrode is surrounded by the scanning line and the drain line in a plan view.
A display device characterized in that the second pixel electrode adjacent to the first pixel electrode is superimposed on the first portion in a plan view. Further, it has a video signal lead wire located in the peripheral area.
The video signal lead-out line is connected to the drain line via a selector, and is connected to the drain line.
The display device according to claim 1, wherein the scanning line and the video signal lead-out line intersect in the peripheral region. The selector has a selector TFT and has a selector TFT.
The display device according to claim 2, wherein the selector control line connected to the gate of the selector TFT is formed in the same layer as the drain line. The display device according to any one of claims 1 to 3, wherein the second pixel electrode is a dummy pixel electrode. The display device according to claim 3, wherein the second pixel electrode is superimposed on the selector control line in a plan view. The display device according to claim 2, wherein the second pixel electrode is superimposed on the video signal leader line in a plan view. The selector control line and the scanning line intersect with each other via an insulating film.
The display device according to claim 3, wherein the selector control line and the video signal lead-out line intersect with each other via the insulating film. The display device according to any one of claims 1 to 7, wherein a common voltage is supplied to the second pixel electrode.

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