JP6920611B2

JP6920611B2 - Semiconductor devices and their manufacturing methods

Info

Publication number: JP6920611B2
Application number: JP2017097211A
Authority: JP
Inventors: 泰紀上村
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2017-05-16
Filing date: 2017-05-16
Publication date: 2021-08-18
Anticipated expiration: 2037-05-16
Also published as: JP2018195664A

Description

本発明は、半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the same.

近年の半導体チップの小型化にともない、半導体チップの接続端子の微細化が進展している。
微細な接続端子を用いた接続方法の１つとして、例えばＣｕ端子などの凸状端子同士を直接接合した実装構造がある。
このような凸状端子同士を接合させる構造では、高さの製造ばらつきによって接続不良や信頼性の低下につながる場合がある。 With the recent miniaturization of semiconductor chips, the miniaturization of connection terminals of semiconductor chips is progressing.
As one of the connection methods using fine connection terminals, there is a mounting structure in which convex terminals such as Cu terminals are directly bonded to each other.
In such a structure in which convex terminals are joined to each other, connection failure and reliability may be lowered due to manufacturing variations in height.

特開２０１７−２８１５６号公報Japanese Unexamined Patent Publication No. 2017-28156 特開２００５−３５３８５７号公報Japanese Unexamined Patent Publication No. 2005-335857 特開平９−１８１１２４号公報Japanese Unexamined Patent Publication No. 9-181124

ところで、例えば図１３（Ａ）、図１３（Ｂ）に示すように、半導体チップ１００及び基板１０１の外周部に設けられる接続端子１０２、１０３の高さを低くし、圧力をかけることによって、すべての接続端子を確実に接合することが考えられる。
しかしながら、この方法では、接続時に半導体チップ１００にかかる応力、特に、半導体チップ１００の外周部よりも内側に設けられる接続端子１０４に集中する応力が大きくなり、信頼性の低下につながる。 By the way, for example, as shown in FIGS. 13 (A) and 13 (B), the heights of the connection terminals 102 and 103 provided on the outer peripheral portions of the semiconductor chip 100 and the substrate 101 are lowered and pressure is applied to all of them. It is conceivable to securely join the connection terminals of.
However, in this method, the stress applied to the semiconductor chip 100 at the time of connection, particularly the stress concentrated on the connection terminal 104 provided inside the outer peripheral portion of the semiconductor chip 100, becomes large, which leads to a decrease in reliability.

そこで、この応力集中を緩和するために、例えば図１４（Ａ）、図１４（Ｂ）に示すように、半導体チップ１００の外周部よりも内側に設けられる接続端子１０４にヤング率の低い材料を用いることが考えられる。
しかしながら、この方法では、ヤング率の低い材料からなる接続端子１０４は、接続時に押しつぶされて側方へ広がってしまうため、接続端子１０４の狭ピッチ化が進むと隣接する接続端子同士が接触し、ショートするおそれがあり、信頼性の低下につながる。 Therefore, in order to alleviate this stress concentration, for example, as shown in FIGS. 14 (A) and 14 (B), a material having a low Young's modulus is applied to the connection terminal 104 provided inside the outer peripheral portion of the semiconductor chip 100. It is conceivable to use it.
However, in this method, the connection terminal 104 made of a material having a low Young's modulus is crushed at the time of connection and spreads laterally. Therefore, as the pitch of the connection terminal 104 becomes narrower, the adjacent connection terminals come into contact with each other. There is a risk of short circuit, which leads to a decrease in reliability.

この場合、例えば予めアンダーフィル等で接続端子同士が接触しないようにすることも考えられるが、アンダーフィルによって固められると接続端子が変形できず、半導体チップ１００にかかる応力を緩和することができない。
本発明は、半導体チップにかかる応力を緩和し、隣接する接続端子同士が接触しないようにして、信頼性を向上させることを目的とする。 In this case, for example, it is conceivable to prevent the connection terminals from contacting each other by underfilling in advance, but if the connection terminals are hardened by underfilling, the connection terminals cannot be deformed and the stress applied to the semiconductor chip 100 cannot be relaxed.
An object of the present invention is to relieve stress applied to a semiconductor chip and prevent adjacent connection terminals from coming into contact with each other to improve reliability.

１つの態様では、半導体装置は、外周部に設けられた第１接続端子と、第１接続端子よりも内側に設けられ、複数のパッドからなるパッド群上に設けられた第２接続端子とを備える半導体チップと、外周部に設けられた第３接続端子と、第３接続端子よりも内側に設けられた第４接続端子とを備える基板とを備え、第１接続端子と第３接続端子が接合され、第２接続端子と第４接続端子が接合され、第２接続端子は、第４接続端子よりもヤング率が小さい材料からなり、第１接続端子が第３接続端子に接触するまで第４接続端子に押し付けられた状態である。 In one embodiment, the semiconductor device comprises a first connection terminal provided on the outer peripheral portion and a second connection terminal provided on the pad group composed of a plurality of pads and provided inside the first connection terminal. a semiconductor chip comprising, a third connection terminal provided on an outer peripheral portion, and a substrate and a fourth connection terminals provided on the inner side of the third connection terminal, a first connection terminal and the third connection terminal It is joined, the second connection terminal and the fourth connection terminal are joined, the second connection terminal is made of a material with a Young's modulus smaller than that of the fourth connection terminal, and the first connection terminal is in contact with the third connection terminal. 4 It is in a state of being pressed against the connection terminal.

１つの態様では、半導体装置の製造方法は、半導体チップの外周部に第１接続端子を形成するとともに、第１接続端子よりも内側に、第１接続端子よりも高さが高く、銅よりもヤング率が小さい材料からなり、第１接続端子よりも断面積が小さい第２接続端子を形成する工程と、基板の外周部に第３接続端子を形成するとともに、第３接続端子よりも内側に第４接続端子を形成する工程と、第１接続端子が第３接続端子に接触するまで第２接続端子を第４接続端子に押し付けた状態で、第１接続端子と第３接続端子を接合し、第２接続端子と第４接続端子を接合する工程とを含む。 In one aspect, the method of manufacturing a semiconductor device is to form a first connection terminal on the outer periphery of a semiconductor chip, and to be inside the first connection terminal, higher than the first connection terminal, and higher than copper. The process of forming a second connection terminal made of a material having a small Young's modulus and having a smaller cross-sectional area than the first connection terminal, and forming a third connection terminal on the outer peripheral portion of the substrate and inside the third connection terminal. In the process of forming the fourth connection terminal, the first connection terminal and the third connection terminal are joined while the second connection terminal is pressed against the fourth connection terminal until the first connection terminal contacts the third connection terminal. , Including a step of joining the second connection terminal and the fourth connection terminal.

１つの側面として、半導体チップにかかる応力を緩和し、隣接する接続端子同士が接触しないようにして、信頼性を向上させることができるという効果を有する。 As one aspect, there is an effect that the stress applied to the semiconductor chip can be relaxed and the adjacent connection terminals do not come into contact with each other to improve the reliability.

（Ａ）、（Ｂ）は、本実施形態にかかる半導体装置の構成を示す模式的断面図である。(A) and (B) are schematic cross-sectional views which show the structure of the semiconductor device which concerns on this Embodiment. （Ａ）、（Ｂ）は、本実施形態にかかる半導体装置の構成を示す模式的断面図である。(A) and (B) are schematic cross-sectional views which show the structure of the semiconductor device which concerns on this Embodiment. 本実施形態にかかる半導体装置の構成を示す模式的断面図である。It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on this Embodiment. 本実施形態にかかる半導体装置の構成を示す模式的断面図である。It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on this Embodiment. （Ａ）〜（Ｆ）は、本実施形態にかかる半導体装置の製造方法を説明するための模式的断面図である。(A) to (F) are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device according to this embodiment. （Ａ）〜（Ｄ）は、本実施形態にかかる半導体装置の製造方法を説明するための模式的断面図である。(A) to (D) are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device according to this embodiment. （Ａ）〜（Ｆ）は、本実施形態にかかる半導体装置の製造方法を説明するための模式的断面図である。(A) to (F) are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device according to this embodiment. （Ａ）〜（Ｄ）は、本実施形態にかかる半導体装置の製造方法を説明するための模式的断面図である。(A) to (D) are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device according to this embodiment. （Ａ）〜（Ｄ）は、本実施形態にかかる半導体装置の製造方法を説明するための模式的断面図である。(A) to (D) are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device according to this embodiment. （Ａ）〜（Ｄ）は、本実施形態にかかる半導体装置の製造方法を説明するための模式的断面図である。(A) to (D) are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device according to this embodiment. 本実施形態にかかる半導体装置の製造方法及び半導体装置を説明するための模式的断面図である。It is a schematic cross-sectional view for demonstrating the manufacturing method of the semiconductor device and the semiconductor device which concerns on this Embodiment. 本実施形態にかかる半導体装置の構成を示す模式的断面図である。It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on this Embodiment. （Ａ）、（Ｂ）は、本発明の課題を説明するための模式的断面図である。(A) and (B) are schematic cross-sectional views for explaining the subject of this invention. （Ａ）、（Ｂ）は、本発明の課題を説明するための模式的断面図である。(A) and (B) are schematic cross-sectional views for explaining the subject of this invention.

以下、図面により、本発明の実施の形態にかかる半導体装置及びその製造方法について、図１〜図１２を参照しながら説明する。
本実施形態にかかる半導体装置は、図１（Ａ）、図２（Ａ）に示すように、外周部に設けられた第１接続端子１と、第１接続端子１よりも内側に設けられ、第１接続端子１よりも高さが高く、銅よりもヤング率が小さい材料からなり、第１接続端子１よりも断面積が小さい第２接続端子２とを備える半導体チップ３である。なお、半導体チップ３を電子部品ともいう。また、端子の断面積とは、半導体チップ３あるいは基板４の主面に平行な面で端子を切った断面積をいう。 Hereinafter, the semiconductor device according to the embodiment of the present invention and the manufacturing method thereof will be described with reference to FIGS. 1 to 12.
As shown in FIGS. 1 (A) and 2 (A), the semiconductor device according to the present embodiment is provided with the first connection terminal 1 provided on the outer peripheral portion and inside the first connection terminal 1. The semiconductor chip 3 is made of a material having a height higher than that of the first connection terminal 1 and a Young's modulus smaller than that of copper, and includes a second connection terminal 2 having a cross-sectional area smaller than that of the first connection terminal 1. The semiconductor chip 3 is also referred to as an electronic component. The cross-sectional area of the terminal means the cross-sectional area of the terminal cut on a surface parallel to the main surface of the semiconductor chip 3 or the substrate 4.

このように、本実施形態の半導体チップ３は、断面積の異なる接続端子（接続部）１、２を有し、断面積の広い接続端子（接続部；第１接続端子）１の高さよりも断面積の狭い接続端子（接続部；第２接続端子）２の高さが高くなっている。
これにより、図１（Ｂ）、図２（Ｂ）に示すように、すべての接続端子１、２が確実に接合されることで、製造ばらつきなどで生じる接続不良や信頼性の低下を抑制することができる。また、接合時に、断面積が小さく、高さが高い接続端子２が優先的に変形することで、半導体チップ３にかかる応力を緩和し、隣接する接続端子同士が接触しないようにして、信頼性を向上させることができる。 As described above, the semiconductor chip 3 of the present embodiment has connection terminals (connection portions) 1 and 2 having different cross-sectional areas, and is higher than the height of the connection terminals (connection portion; first connection terminal) 1 having a wide cross-sectional area. The height of the connection terminal (connection portion; second connection terminal) 2 having a narrow cross-sectional area is high.
As a result, as shown in FIGS. 1 (B) and 2 (B), all the connection terminals 1 and 2 are reliably joined, thereby suppressing connection defects and deterioration of reliability caused by manufacturing variations and the like. be able to. Further, at the time of joining, the connection terminal 2 having a small cross-sectional area and a high height is preferentially deformed to relieve the stress applied to the semiconductor chip 3 and prevent the adjacent connection terminals from coming into contact with each other for reliability. Can be improved.

また、第２接続端子２は、銅よりもヤング率が小さい材料からなるため、半導体チップ３にかかる応力を緩和することが可能となる。
ここで、第１接続端子１は、例えば銅やＮｉなどの金属などによって構成される。また、第２接続端子２は、例えばＳｎ又はＩｎを主成分として含むはんだ（Ｓｎ、Ｉｎ又はこれらの合金）などによって構成される。ここで、Ｓｎ又はＩｎを主成分として含むはんだは、例えばＩｎＳｎはんだ、ＳｎＡｇはんだ、ＳｎＡｇＣｕはんだなどである。特に、ヤング率が低いという点で、Ｉｎを含むものであることが好ましい。これらの材料によって第１接続端子１及び第２接続端子２が構成される場合、第２接続端子２は、第１接続端子２よりもヤング率が小さい材料からなることになる。なお、第１接続端子１は、第２接続端子２と同様に、はんだなどによって構成しても良い。 Further, since the second connection terminal 2 is made of a material having a Young's modulus smaller than that of copper, it is possible to relieve the stress applied to the semiconductor chip 3.
Here, the first connection terminal 1 is made of, for example, a metal such as copper or Ni. Further, the second connection terminal 2 is composed of, for example, solder containing Sn or In as a main component (Sn, In or an alloy thereof) or the like. Here, the solder containing Sn or In as a main component is, for example, InSn solder, SnAg solder, SnAgCu solder, or the like. In particular, it is preferable that it contains In in that the Young's modulus is low. When the first connection terminal 1 and the second connection terminal 2 are composed of these materials, the second connection terminal 2 is made of a material having a Young's modulus smaller than that of the first connection terminal 2. The first connection terminal 1 may be made of solder or the like, like the second connection terminal 2.

ここで、第２接続端子２は、図１（Ａ）に示すように、複数の接続端子２Ａからなる接続端子群によって構成されることが好ましい。
この場合、複数の接続端子２Ａからなる接続端子群によって構成される１つの第２接続端子２は、図１（Ｂ）に示すように、基板（配線基板）４に設けられた１つの接続端子６に接続されることになる。 Here, as shown in FIG. 1A, the second connection terminal 2 is preferably composed of a group of connection terminals including a plurality of connection terminals 2A.
In this case, as shown in FIG. 1B, one second connection terminal 2 composed of a group of connection terminals composed of a plurality of connection terminals 2A is one connection terminal provided on the board (wiring board) 4. It will be connected to 6.

これにより、基板４に設けられた接続端子６に接合した場合に、接合断面積を確保することができ、また、位置合わせの際のマージンを広げることができる。
また、図１（Ａ）に示すように、第２接続端子２を複数備え、複数の第２接続端子２の間隔は、接続端子群に含まれる複数の接続端子２Ａの間隔よりも広いことが好ましい。
特に、図４に示すように、複数の第２接続端子２は、第１接続端子１と第２接続端子２の高さの差の０．６倍よりも長い間隔で設けられており、接続端子群に含まれる複数の接続端子２Ａは、第１接続端子１と第２接続端子２の高さの差の０．６倍よりも短い間隔で設けられていることが好ましい。つまり、断面積の狭い接続端子２（２Ａ）の間隔が、第１接続端子１と第２接続端子２の高さの差の０．６倍よりも短い間隔と０．６倍よりも長い間隔の２種類によって形成されていることが好ましい。 As a result, when the connection terminal 6 is joined to the connection terminal 6 provided on the substrate 4, the joint cross-sectional area can be secured, and the margin at the time of alignment can be widened.
Further, as shown in FIG. 1A, a plurality of second connection terminals 2 are provided, and the distance between the plurality of second connection terminals 2 may be wider than the distance between the plurality of connection terminals 2A included in the connection terminal group. preferable.
In particular, as shown in FIG. 4, the plurality of second connection terminals 2 are provided at intervals longer than 0.6 times the height difference between the first connection terminal 1 and the second connection terminal 2, and are connected. The plurality of connection terminals 2A included in the terminal group are preferably provided at intervals shorter than 0.6 times the height difference between the first connection terminal 1 and the second connection terminal 2. That is, the distance between the connection terminals 2 (2A) having a narrow cross-sectional area is shorter than 0.6 times the height difference between the first connection terminal 1 and the second connection terminal 2 and longer than 0.6 times. It is preferable that it is formed by two types of.

このように、第１接続端子１と第２接続端子２の高さの差をΔｈとした場合、複数の第２接続端子２の間隔を、Δｈの０．６倍よりも大きい間隔にすることによって、端子間で接触しにくくしている。また、第２接続端子２を構成する接続端子群に含まれる複数の接続端子２Ａの間隔を、Δｈの０．６倍以下の間隔にすることによって、良好な接続が得られるようにしている。ここで、０．６倍というのは高さ方向にΔｈ圧縮された場合、横方向に膨らむ倍率であるポアソン比０．３を端子間でとったものである。 As described above, when the difference in height between the first connection terminal 1 and the second connection terminal 2 is Δh, the distance between the plurality of second connection terminals 2 is set to be larger than 0.6 times Δh. This makes it difficult for the terminals to come into contact with each other. Further, a good connection can be obtained by setting the distance between the plurality of connection terminals 2A included in the connection terminal group constituting the second connection terminal 2 to be 0.6 times or less of Δh. Here, 0.6 times means that the Poisson's ratio of 0.3, which is the magnification of swelling in the lateral direction when compressed by Δh in the height direction, is taken between the terminals.

つまり、図１（Ｂ）に示すように、基板４に設けられた接続端子６に接合した場合に、接続端子群を構成する複数の接続端子２Ａ同士が互いに接触することで良好な接続を確保しながら、隣接する第２接続端子２が接触してショートしてしまうのを防止することができる。
なお、図１、図２に示すように、基板４の外周部に設けられる第３接続端子５を、第３接続端子５よりも内側に設けられる第４接続端子６の高さよりも低くしているが、これに限られるものではなく、例えば図３に示すように、基板４の外周部に設けられる第３接続端子５の高さを、第３接続端子５よりも内側に設けられる第４接続端子６の高さと同じにしても良い。 That is, as shown in FIG. 1 (B), when the connection terminals 6 provided on the substrate 4 are joined, the plurality of connection terminals 2A constituting the connection terminal group come into contact with each other to ensure a good connection. On the other hand, it is possible to prevent the adjacent second connection terminals 2 from coming into contact with each other and causing a short circuit.
As shown in FIGS. 1 and 2, the height of the third connection terminal 5 provided on the outer peripheral portion of the substrate 4 is made lower than the height of the fourth connection terminal 6 provided inside the third connection terminal 5. However, the present invention is not limited to this, and for example, as shown in FIG. 3, the height of the third connection terminal 5 provided on the outer peripheral portion of the substrate 4 is set to be inside the third connection terminal 5. It may be the same as the height of the connection terminal 6.

上述のように構成される半導体装置の製造方法は、半導体チップ３の外周部に第１接続端子１を形成するとともに、第１接続端子１よりも内側に、第１接続端子１よりも高さが高く、銅よりもヤング率が小さい材料からなり、第１接続端子１よりも断面積が小さい第２接続端子２を形成する工程を含む（例えば図５〜図７参照）。
また、第２接続端子２を形成する工程において、複数の接続端子２Ａからなる接続端子群によって構成される第２接続端子２を形成するのが好ましい。 In the method for manufacturing a semiconductor device configured as described above, the first connection terminal 1 is formed on the outer peripheral portion of the semiconductor chip 3, and the height is higher than the first connection terminal 1 inside the first connection terminal 1. A step of forming a second connection terminal 2 having a high value and a Young's modulus smaller than that of copper and having a cross-sectional area smaller than that of the first connection terminal 1 is included (see, for example, FIGS. 5 to 7).
Further, in the step of forming the second connection terminal 2, it is preferable to form the second connection terminal 2 composed of a group of connection terminals composed of a plurality of connection terminals 2A.

また、第２接続端子２を形成する工程において、接続端子群に含まれる複数の接続端子２Ａの間隔よりも間隔が広くなるように複数の第２接続端子２を形成することが好ましい。
また、第２接続端子２を形成する工程において、複数の第２接続端子２を、第１接続端子１と第２接続端子２の高さの差の０．６倍よりも長い間隔で形成し、接続端子群に含まれる複数の接続端子２Ａを、第１接続端子１と第２接続端子２の高さの差の０．６倍よりも短い間隔で形成することが好ましい。 Further, in the step of forming the second connection terminal 2, it is preferable to form the plurality of second connection terminals 2 so that the interval is wider than the interval of the plurality of connection terminals 2A included in the connection terminal group.
Further, in the step of forming the second connection terminal 2, a plurality of second connection terminals 2 are formed at intervals longer than 0.6 times the height difference between the first connection terminal 1 and the second connection terminal 2. It is preferable that the plurality of connection terminals 2A included in the connection terminal group are formed at intervals shorter than 0.6 times the height difference between the first connection terminal 1 and the second connection terminal 2.

具体的には、以下のようにして、半導体チップ３に第１接続端子１及び第２接続端子２を形成すれば良い。
ここでは、第２接続端子２として、複数の接続端子２Ａからなる接続端子群によって構成される第２接続端子２を形成する場合を例に挙げて説明する。
つまり、まず、図５（Ａ）に示すように、パッド（電極）を有する半導体チップ３上にレジスト膜７を形成する。 Specifically, the first connection terminal 1 and the second connection terminal 2 may be formed on the semiconductor chip 3 as follows.
Here, a case where a second connection terminal 2 composed of a group of connection terminals composed of a plurality of connection terminals 2A is formed as the second connection terminal 2 will be described as an example.
That is, first, as shown in FIG. 5A, the resist film 7 is formed on the semiconductor chip 3 having the pad (electrode).

次に、図５（Ｂ）に示すように、レジスト膜７をパターニングすることで、第１接続端子１を形成するための開口部８を設ける。ここでは、半導体チップ１の外周部に大きな径（開口径）の開口部８を設ける。
次に、図５（Ｃ）に示すように、開口部８に、めっきによって、例えばＣｕやＮｉなどの金属からなる第１接続端子（金属端子）１を形成する。これにより、半導体チップ３の外周部に大きな径の第１接続端子１が形成される。 Next, as shown in FIG. 5B, the resist film 7 is patterned to provide an opening 8 for forming the first connection terminal 1. Here, an opening 8 having a large diameter (opening diameter) is provided on the outer peripheral portion of the semiconductor chip 1.
Next, as shown in FIG. 5C, a first connection terminal (metal terminal) 1 made of a metal such as Cu or Ni is formed in the opening 8 by plating. As a result, the first connection terminal 1 having a large diameter is formed on the outer peripheral portion of the semiconductor chip 3.

次に、図５（Ｄ）に示すように、レジスト膜９を形成し、パターニングすることで、第２接続端子２を形成するための開口部１０を設ける。ここでは、半導体チップ３の外周部よりも内側に小さな径の複数の開口部１０を設ける。
次に、図５（Ｅ）に示すように、開口部１０に、めっきによって、例えばＳｎ又はＩｎを主成分として含むはんだ（例えばＩｎＳｎはんだ、ＳｎＡｇはんだ、ＳｎＡｇＣｕはんだなど）からなる第２接続端子２を形成する。 Next, as shown in FIG. 5D, the resist film 9 is formed and patterned to provide an opening 10 for forming the second connection terminal 2. Here, a plurality of openings 10 having a small diameter are provided inside the outer peripheral portion of the semiconductor chip 3.
Next, as shown in FIG. 5 (E), the opening 10 is plated with a second connection terminal 2 made of, for example, a solder containing Sn or In as a main component (for example, InSn solder, SnAg solder, SnAgCu solder, etc.). To form.

その後、レジスト膜を除去することで、図５（Ｆ）に示すように、半導体チップ３の外周部に第１接続端子１が形成され、それよりも内側に第２接続端子２が形成される。
つまり、半導体チップ３の外周部に高さが低く、かつ、径が大きい第１接続端子１が形成され、それよりも内側に高さが高く、かつ、径が小さく、銅（又は第１接続端子）よりもヤング率が小さい第２接続端子２が形成される。ここでは、第２接続端子２として、複数の接続端子２Ａからなる接続端子群によって構成される第２接続端子２が形成される。 After that, by removing the resist film, as shown in FIG. 5 (F), the first connection terminal 1 is formed on the outer peripheral portion of the semiconductor chip 3, and the second connection terminal 2 is formed on the inner side thereof. ..
That is, the first connection terminal 1 having a low height and a large diameter is formed on the outer peripheral portion of the semiconductor chip 3, and the height is high and the diameter is small, and copper (or the first connection) is formed inside the first connection terminal 1. The second connection terminal 2 having a Young's modulus smaller than that of the terminal) is formed. Here, as the second connection terminal 2, a second connection terminal 2 composed of a group of connection terminals composed of a plurality of connection terminals 2A is formed.

なお、第１接続端子１を、第２接続端子２と同様に、はんだなどによって構成する場合は、以下のようにして、半導体チップ３に第１接続端子１及び第２接続端子２を形成すれば良い。
つまり、まず、図６（Ａ）に示すように、パッド（電極）を有する半導体チップ３上にレジスト膜１１を形成する。 When the first connection terminal 1 is made of solder or the like like the second connection terminal 2, the first connection terminal 1 and the second connection terminal 2 are formed on the semiconductor chip 3 as follows. It's fine.
That is, first, as shown in FIG. 6A, the resist film 11 is formed on the semiconductor chip 3 having the pad (electrode).

次に、図６（Ｂ）に示すように、レジスト膜１１をパターニングすることで、第１接続端子１及び第２接続端子２を形成するための開口部１２、１３を設ける。ここでは、少なくとも２種類以上の径（開口径）の開口部１２、１３を設ける。つまり、半導体チップ３の外周部に大きな径の開口部１２を設けるとともに、それよりも内側に小さな径の複数の開口部１３を設ける。 Next, as shown in FIG. 6B, the resist film 11 is patterned to provide openings 12 and 13 for forming the first connection terminal 1 and the second connection terminal 2. Here, openings 12 and 13 having at least two or more types of diameters (opening diameters) are provided. That is, an opening 12 having a large diameter is provided on the outer peripheral portion of the semiconductor chip 3, and a plurality of openings 13 having a smaller diameter are provided on the inner side thereof.

次に、図６（Ｃ）に示すように、開口部１２、１３に、めっきによって、例えばＳｎ又はＩｎを主成分として含むはんだ（例えばＩｎＳｎはんだ、ＳｎＡｇはんだ、ＳｎＡｇＣｕはんだなど）からなる第１接続端子１及び第２接続端子２（金属端子）を形成する。
その後、レジスト膜１１を除去することで、図６（Ｄ）に示すように、半導体チップ３の外周部に第１接続端子１が形成され、それよりも内側に第２接続端子２が形成される。 Next, as shown in FIG. 6C, a first connection made of solder containing, for example, Sn or In as a main component (for example, InSn solder, SnAg solder, SnAgCu solder, etc.) is formed in the openings 12 and 13 by plating. The terminal 1 and the second connection terminal 2 (metal terminal) are formed.
After that, by removing the resist film 11, as shown in FIG. 6D, the first connection terminal 1 is formed on the outer peripheral portion of the semiconductor chip 3, and the second connection terminal 2 is formed on the inner side thereof. NS.

つまり、上述のように、開口部１２、１３の開口径を調整することで、めっきを行なう際に、開口径の大きいところでは電流密度が小さくなるため、半導体チップ３の外周部に高さが低く、かつ、径が大きい第１接続端子１が形成され、それよりも内側に高さが高く、かつ、径が小さい第２接続端子２が形成される。ここでは、第２接続端子２として、銅よりもヤング率が小さく、複数の接続端子２Ａからなる接続端子群によって構成される第２接続端子２が形成される。 That is, as described above, by adjusting the opening diameters of the openings 12 and 13, the current density becomes smaller where the opening diameter is large when plating is performed, so that the height is increased at the outer peripheral portion of the semiconductor chip 3. A first connection terminal 1 having a low diameter and a large diameter is formed, and a second connection terminal 2 having a high height and a small diameter is formed inside the first connection terminal 1. Here, as the second connection terminal 2, a second connection terminal 2 having a Young's modulus smaller than that of copper and composed of a group of connection terminals composed of a plurality of connection terminals 2A is formed.

このほか、第１接続端子１を、第２接続端子２と同様に、はんだなどによって構成する場合、以下のようにして、半導体チップ３に第１接続端子１及び第２接続端子２を形成することもできる。
つまり、まず、図７（Ａ）に示すように、パッド（電極）を有する半導体チップ３上にレジスト膜１４を形成する。 In addition, when the first connection terminal 1 is made of solder or the like like the second connection terminal 2, the first connection terminal 1 and the second connection terminal 2 are formed on the semiconductor chip 3 as follows. You can also do it.
That is, first, as shown in FIG. 7A, the resist film 14 is formed on the semiconductor chip 3 having the pad (electrode).

次に、図７（Ｂ）に示すように、レジスト膜１４をパターニングすることで、第１接続端子１及び第２接続端子２の下側部分２Ｘを形成するための開口部１５、１６を設ける。ここでは、半導体チップ３の外周部に大きな径の開口部１５を設けるとともに、それよりも内側に小さな径の複数の開口部１６を設ける。
次に、図７（Ｃ）に示すように、開口部１５、１６に、めっきによって、例えばＳｎ又はＩｎを主成分として含むはんだ（例えばＩｎＳｎはんだ、ＳｎＡｇはんだ、ＳｎＡｇＣｕはんだなど）からなる第１接続端子１及び第２接続端子２の下側部分２Ｘを形成する。 Next, as shown in FIG. 7B, by patterning the resist film 14, openings 15 and 16 for forming the lower portions 2X of the first connection terminal 1 and the second connection terminal 2 are provided. .. Here, an opening 15 having a large diameter is provided on the outer peripheral portion of the semiconductor chip 3, and a plurality of openings 16 having a smaller diameter are provided on the inner side thereof.
Next, as shown in FIG. 7C, a first connection made of solder containing, for example, Sn or In as a main component (for example, InSn solder, SnAg solder, SnAgCu solder, etc.) is formed in the openings 15 and 16 by plating. The lower portion 2X of the terminal 1 and the second connection terminal 2 is formed.

次に、図７（Ｄ）に示すように、レジスト膜１７を形成し、パターニングすることで、第２接続端子２の上側部分２Ｙを形成するための開口部１８を設ける。ここでは、半導体チップ３の外周部よりも内側に小さな径の複数の開口部１８を設ける。
次に、図７（Ｅ）に示すように、開口部１８に、めっきによって、例えばＳｎ又はＩｎを主成分として含むはんだ（例えばＩｎＳｎはんだ、ＳｎＡｇはんだ、ＳｎＡｇＣｕはんだなど）からなる第２接続端子２の上側部分２Ｙを形成する。 Next, as shown in FIG. 7D, the resist film 17 is formed and patterned to provide an opening 18 for forming the upper portion 2Y of the second connection terminal 2. Here, a plurality of openings 18 having a small diameter are provided inside the outer peripheral portion of the semiconductor chip 3.
Next, as shown in FIG. 7 (E), the opening 18 is plated with a second connection terminal 2 made of, for example, a solder containing Sn or In as a main component (for example, InSn solder, SnAg solder, SnAgCu solder, etc.). The upper portion 2Y of the solder is formed.

その後、レジスト膜１４、１７を除去することで、図７（Ｆ）に示すように、半導体チップ３の外周部に第１接続端子１が形成され、それよりも内側に第２接続端子２が形成される。
つまり、半導体チップ３の外周部に高さが低く、かつ、径が大きい第１接続端子１が形成され、それよりも内側に高さが高く、かつ、径が小さい第２接続端子２が形成される。ここでは、第２接続端子２として、銅よりもヤング率が小さく、複数の接続端子２Ａからなる接続端子群によって構成される第２接続端子２が形成される。 After that, by removing the resist films 14 and 17, as shown in FIG. 7 (F), the first connection terminal 1 is formed on the outer peripheral portion of the semiconductor chip 3, and the second connection terminal 2 is formed inside the first connection terminal 1. It is formed.
That is, the first connection terminal 1 having a low height and a large diameter is formed on the outer peripheral portion of the semiconductor chip 3, and the second connection terminal 2 having a high height and a small diameter is formed inside the first connection terminal 1. Will be done. Here, as the second connection terminal 2, a second connection terminal 2 having a Young's modulus smaller than that of copper and composed of a group of connection terminals composed of a plurality of connection terminals 2A is formed.

ところで、本実施形態にかかる半導体装置は、外周部に設けられた第１接続端子１と、第１接続端子１よりも内側に設けられ、複数のパッド２０からなるパッド群上に設けられた第２接続端子２とを備える半導体チップ３と、外周部に設けられた第３接続端子５と、第３接続端子５よりも内側に設けられた第４接続端子６とを備える基板（配線基板）４とを備え、第２接続端子２は、第４接続端子６よりもヤング率が小さい材料からなり、第１接続端子１と第３接続端子５が接合され、第２接続端子２と第４接続端子６が接合されているものである場合もある［例えば図１（Ｂ）、図２（Ｂ）、図１２参照］。 By the way, the semiconductor device according to the present embodiment is provided on the first connection terminal 1 provided on the outer peripheral portion and inside the first connection terminal 1 and on a pad group composed of a plurality of pads 20. A substrate (wiring board) including a semiconductor chip 3 having two connection terminals 2, a third connection terminal 5 provided on the outer periphery, and a fourth connection terminal 6 provided inside the third connection terminal 5. The second connection terminal 2 is made of a material having a Young's modulus smaller than that of the fourth connection terminal 6, the first connection terminal 1 and the third connection terminal 5 are joined, and the second connection terminal 2 and the fourth connection terminal 2 and the fourth connection terminal 2 are joined. In some cases, the connection terminals 6 are joined [see, for example, FIGS. 1 (B), 2 (B), and 12].

これにより、すべての接続端子が確実に接合されることで、製造ばらつきなどで生じる接続不良や信頼性の低下を抑制することができる。また、接合時に、断面積が小さく、高さが高い接続端子２が優先的に変形することで、半導体チップ３にかかる応力を緩和し、隣接する接続端子同士が接触しないようにして、信頼性を向上させることができる。
また、上述したように、第２接続端子２は、銅よりもヤング率が小さい材料からなるため、半導体チップ３にかかる応力を緩和することが可能となる。 As a result, all the connection terminals are reliably joined, and it is possible to suppress connection defects and deterioration of reliability caused by manufacturing variations and the like. Further, at the time of joining, the connection terminal 2 having a small cross-sectional area and a high height is preferentially deformed to relieve the stress applied to the semiconductor chip 3 and prevent the adjacent connection terminals from coming into contact with each other for reliability. Can be improved.
Further, as described above, since the second connection terminal 2 is made of a material having a Young's modulus smaller than that of copper, it is possible to relieve the stress applied to the semiconductor chip 3.

また、第２接続端子２は、第４接続端子６よりもヤング率が小さい。ここで、第４接続端子６は、例えば銅やＮｉなどの金属によって構成される。なお、ここでは、第３接続端子５も、例えば銅やＮｉなどの金属によって構成される。
このように、ヤング率が低い第２接続端子２と、ヤング率が第２接続端子２よりも高い第４接続端子６とが接合されるようにすることで、第２接続端子２に応力が吸収されやすい構造となり、信頼性が高くなる。 Further, the second connection terminal 2 has a Young's modulus smaller than that of the fourth connection terminal 6. Here, the fourth connection terminal 6 is made of a metal such as copper or Ni. Here, the third connection terminal 5 is also made of a metal such as copper or Ni.
In this way, by joining the second connection terminal 2 having a low Young's modulus and the fourth connection terminal 6 having a Young's modulus higher than that of the second connection terminal 2, stress is applied to the second connection terminal 2. The structure is easily absorbed and the reliability is high.

また、上述したように、第１接続端子１を、例えば銅やＮｉなどの金属によって構成することで、接合時に、銅よりもヤング率が小さい材料からなる第２接続端子２が押しつぶされた場合に、確実に位置合わせを行なうことが可能となる。なお、第１接続端子１、第３接続端子５を、位置合わせ用接続端子ともいう。
また、半導体チップ３に、第２接続端子２として、複数の接続端子２Ａからなる接続端子群によって構成される第２接続端子２を形成し、複数の接続端子２Ａからなる接続端子群は、複数のパッド２０からなるパッド群上に設けられるため、半導体チップ３と基板４を接合した半導体装置では、複数のパッド２０からなるパッド群上に設けられた第２接続端子２を備えるものとなる（例えば図１２参照）。 Further, as described above, when the first connection terminal 1 is made of a metal such as copper or Ni, the second connection terminal 2 made of a material having a Young's modulus smaller than that of copper is crushed at the time of joining. In addition, it is possible to reliably align the position. The first connection terminal 1 and the third connection terminal 5 are also referred to as alignment connection terminals.
Further, the semiconductor chip 3 is formed with a second connection terminal 2 composed of a plurality of connection terminals 2A as the second connection terminal 2, and the plurality of connection terminal groups composed of the plurality of connection terminals 2A are plural. Since the semiconductor device is provided on the pad group composed of the pads 20 of the above, the semiconductor device in which the semiconductor chip 3 and the substrate 4 are joined is provided with the second connection terminal 2 provided on the pad group composed of the plurality of pads 20. For example, see FIG. 12).

また、半導体チップ３を、複数の第２接続端子２を備え、複数の第２接続端子２の間隔を、接続端子群に含まれる複数の接続端子２Ａの間隔よりも広くしたものとして、半導体チップ３と基板４を接合した半導体装置では、第２接続端子２を複数備え、複数の第２接続端子２のそれぞれが設けられたパッド群の間隔は、パッド群に含まれる複数のパッド２０の間隔よりも広いものとなる（例えば図１２参照）。 Further, the semiconductor chip 3 is provided with a plurality of second connection terminals 2, and the distance between the plurality of second connection terminals 2 is wider than the distance between the plurality of connection terminals 2A included in the connection terminal group. In the semiconductor device in which the substrate 4 and the substrate 4 are joined, a plurality of second connection terminals 2 are provided, and the distance between the pads group provided with each of the plurality of second connection terminals 2 is the distance between the plurality of pads 20 included in the pad group. (See, for example, FIG. 12).

上述のように構成される半導体装置の製造方法は、上述の半導体装置の製造方法において、さらに、基板４の外周部に第３接続端子５を形成するとともに、第３接続端子５よりも内側に第４接続端子６を形成する工程と、第１接続端子１が第３接続端子５に接触するまで第２接続端子２を第４接続端子６に押し付けた状態で、第１接続端子１と第３接続端子５を接合し、第２接続端子２と第４接続端子６を接合する工程とを含むものとすれば良い。 In the method for manufacturing a semiconductor device configured as described above, in the method for manufacturing a semiconductor device described above, a third connection terminal 5 is further formed on the outer peripheral portion of the substrate 4, and the third connection terminal 5 is formed inside the third connection terminal 5. In the process of forming the fourth connection terminal 6, and in a state where the second connection terminal 2 is pressed against the fourth connection terminal 6 until the first connection terminal 1 contacts the third connection terminal 5, the first connection terminal 1 and the first connection terminal 1 and the first connection terminal 6 are pressed. 3 The step of joining the connection terminals 5 and joining the second connection terminal 2 and the fourth connection terminal 6 may be included.

なお、接合前の基板４において、第４接続端子６は、第３接続端子５よりも高さを高くするのが好ましい。これにより、すべての接続端子が確実に接合されることで、製造ばらつきなどで生じる接続不良や信頼性の低下を抑制することができる。
ここでは、第２接続端子２と第４接続端子６の高さの和は、第１接続端子１と第３接続端子５の高さの和よりも大きくしている。 In the substrate 4 before joining, the height of the fourth connection terminal 6 is preferably higher than that of the third connection terminal 5. As a result, all the connection terminals are reliably joined, and it is possible to suppress connection defects and deterioration of reliability caused by manufacturing variations and the like.
Here, the sum of the heights of the second connection terminal 2 and the fourth connection terminal 6 is larger than the sum of the heights of the first connection terminal 1 and the third connection terminal 5.

具体的には、以下のようにして、基板（配線基板）４に第３接続端子５及び第４接続端子６を形成すれば良い。
ここでは、第３接続端子５と第４接続端子６の高さ及び径が同じ場合を例に挙げて説明する。
つまり、まず、図８（Ａ）に示すように、基板４上にレジスト膜１９を形成する。 Specifically, the third connection terminal 5 and the fourth connection terminal 6 may be formed on the substrate (wiring board) 4 as follows.
Here, a case where the height and diameter of the third connection terminal 5 and the fourth connection terminal 6 are the same will be described as an example.
That is, first, as shown in FIG. 8A, the resist film 19 is formed on the substrate 4.

次に、図８（Ｂ）に示すように、レジスト膜１９をパターニングすることで開口部２１を設ける。
ここでは、基板４の外周部及びそれよりも内側に等しい径の開口部２１を設ける。
次に、図８（Ｃ）に示すように、これらの開口部２１に、めっきによって、例えばＣｕやＮｉなどの金属からなる第３接続端子５及び第４接続端子６（金属端子）を形成する。 Next, as shown in FIG. 8B, the opening 21 is provided by patterning the resist film 19.
Here, an opening 21 having the same diameter is provided on the outer peripheral portion of the substrate 4 and on the inner side thereof.
Next, as shown in FIG. 8C, a third connection terminal 5 and a fourth connection terminal 6 (metal terminal) made of a metal such as Cu or Ni are formed in these openings 21 by plating. ..

その後、レジスト膜１９を除去することで、図８（Ｄ）に示すように、基板４に、同じ高さ及び同じ径の第３接続端子５及び第４接続端子６が形成される。
なお、これに限られるものではなく、基板４の外周部に設けられる第３接続端子５よりも、それよりも内側に設けられる第４接続端子６の高さを高くしても良い。また、基板４の外周部に設けられる第３接続端子５よりも、それよりも内側に設けられる第４接続端子６の径を小さくしても良い。 After that, by removing the resist film 19, as shown in FIG. 8D, the third connection terminal 5 and the fourth connection terminal 6 having the same height and the same diameter are formed on the substrate 4.
The height of the fourth connection terminal 6 provided inside the third connection terminal 5 provided on the outer peripheral portion of the substrate 4 may be made higher than the third connection terminal 5 provided on the outer peripheral portion of the substrate 4. Further, the diameter of the fourth connection terminal 6 provided inside the third connection terminal 5 provided on the outer peripheral portion of the substrate 4 may be smaller than that of the third connection terminal 5.

この場合、以下のようにして、基板４に第３接続端子５及び第４接続端子６を形成すれば良い。
つまり、まず、図９（Ａ）に示すように、基板４上にレジスト膜２２を形成する。
次に、図９（Ｂ）に示すように、レジスト膜２２をパターニングすることで開口部２３、２４を設ける。 In this case, the third connection terminal 5 and the fourth connection terminal 6 may be formed on the substrate 4 as follows.
That is, first, as shown in FIG. 9A, the resist film 22 is formed on the substrate 4.
Next, as shown in FIG. 9B, the openings 23 and 24 are provided by patterning the resist film 22.

ここでは、基板４の外周部に大きい径（開口径）の開口部２３を設け、それよりも内側に小さい径の開口部２４を設ける。
次に、図９（Ｃ）に示すように、これらの開口部２３、２４に、めっきによって、例えばＣｕやＮｉなどの金属からなる第３接続端子５及び第４接続端子６（金属端子）を形成する。 Here, an opening 23 having a large diameter (opening diameter) is provided on the outer peripheral portion of the substrate 4, and an opening 24 having a smaller diameter is provided inside the opening 23.
Next, as shown in FIG. 9C, the third connection terminal 5 and the fourth connection terminal 6 (metal terminal) made of a metal such as Cu or Ni are formed in these openings 23 and 24 by plating. Form.

その後、レジスト膜２２を除去することで、図９（Ｄ）に示すように、基板４に、異なる高さ及び異なる径の第３接続端子５及び第４接続端子６が形成される。
つまり、上述のように、開口部２３、２４の開口径を調整することで、めっきを行なう際に、開口径の大きいところでは電流密度が小さくなるため、基板４の外周部に高さが低く、かつ、径が大きい第３接続端子５が形成され、それよりも内側に高さが高く、かつ、径が小さい第４接続端子６が形成される。 After that, by removing the resist film 22, as shown in FIG. 9D, the third connection terminal 5 and the fourth connection terminal 6 having different heights and different diameters are formed on the substrate 4.
That is, as described above, by adjusting the opening diameters of the openings 23 and 24, when plating is performed, the current density is reduced where the opening diameter is large, so that the height is low on the outer peripheral portion of the substrate 4. A third connection terminal 5 having a large diameter is formed, and a fourth connection terminal 6 having a high height and a small diameter is formed inside the third connection terminal 5.

ところで、第１接続端子１と第３接続端子５を接合し、第２接続端子２と第４接続端子６を接合する工程において、第１接続端子１が第３接続端子５に接触するまで第２接続端子２を第４接続端子６に押し付けた状態で、第２接続端子２を構成する材料の融点よりも低い温度で加熱し、電流を流して、第２接続端子２と第４接続端子６を接合することが好ましい。 By the way, in the process of joining the first connection terminal 1 and the third connection terminal 5 and joining the second connection terminal 2 and the fourth connection terminal 6, the first connection terminal 1 is in contact with the third connection terminal 5. 2 With the connection terminal 2 pressed against the fourth connection terminal 6, the second connection terminal 2 and the fourth connection terminal are heated at a temperature lower than the melting point of the material constituting the second connection terminal 2 and an electric current is passed through them. It is preferable to join 6.

具体的には、以下のようにして接合すれば良い。
つまり、まず、図１０（Ａ）に示すように、上述のようにして第１接続端子１及び第２接続端子２が形成された半導体チップ３と、上述のようにして第３接続端子５及び第４接続端子６が形成された基板４を対向させる。
次に、図１０（Ｂ）に示すように、半導体チップ３の径が小さく、かつ、高さが高い第２接続端子２を基板４の第４接続端子６に接触させ、図１０（Ｃ）に示すように、半導体チップ３の径が大きく、かつ、高さが低い第１接続端子１が第３接続端子５に接触するまで第２接続端子２を第４接続端子６に押し付ける。 Specifically, they may be joined as follows.
That is, first, as shown in FIG. 10A, the semiconductor chip 3 on which the first connection terminal 1 and the second connection terminal 2 are formed as described above, and the third connection terminal 5 and the third connection terminal 5 as described above. The substrate 4 on which the fourth connection terminal 6 is formed faces each other.
Next, as shown in FIG. 10B, the second connection terminal 2 having a small diameter and a high height of the semiconductor chip 3 is brought into contact with the fourth connection terminal 6 of the substrate 4, and FIG. 10C is shown. As shown in the above, the second connection terminal 2 is pressed against the fourth connection terminal 6 until the first connection terminal 1 having a large diameter and a low height of the semiconductor chip 3 comes into contact with the third connection terminal 5.

この状態で、図１０（Ｄ）に示すように、他の接続端子１、５、６よりも低融点である第２接続端子２を構成する材料の融点よりも低い温度で加熱し、端子部に電流を流す。これにより、接触抵抗の高い微細端子部（接続端子群からなる第２接続端子２と第４接続端子６が接合される部分）の接点で発熱し、部分的に溶融し、接合されることになる。
ここで、例えば、第２接続端子２を構成する金属がＩｎＳｎ共晶合金の場合、加熱温度は約１００℃、電流密度は約１５ｋＡ／ｃｍ^２以下とすれば良い。これは、約１５ｋＡ／ｃｍ^２よりも大きい電流が流れると、高融点の接続端子である例えばＣｕからなる他の接続端子１、５、６がエレクトロマイグレーションする可能性が高くなり、接合後の信頼性が低下してしまうおそれがあるからである。 In this state, as shown in FIG. 10D, the terminal portion is heated at a temperature lower than the melting point of the material constituting the second connection terminal 2, which has a melting point lower than that of the other connection terminals 1, 5 and 6. Apply current to. As a result, heat is generated at the contact point of the fine terminal portion having high contact resistance (the portion where the second connection terminal 2 and the fourth connection terminal 6 composed of the connection terminal group are joined), and the heat is partially melted and joined. Become.
Here, for example, when the metal constituting the second connection terminal 2 is an InSn eutectic alloy, the heating temperature may be about 100 ° C. and the current density may be about 15 kA / cm ² or less. This is because when a ^{current larger than about 15 kA / cm 2} flows, there is a high possibility that other connection terminals 1, 5 and 6 made of, for example, Cu, which are high melting point connection terminals, are electromigrated, and reliability after bonding is high. This is because there is a risk that the sex will deteriorate.

なお、第１接続端子１と第３接続端子５は、互いに押し付けられ、圧力を加えられることで、接合される。
ところで、第１接続端子１と第３接続端子５を接合し、第２接続端子２と第４接続端子６を接合する工程において、第１接続端子１が第３接続端子５に接触するまで第２接続端子２を第４接続端子６に押し付けた状態で、第２接続端子２を構成する材料の融点以上の温度で加熱して、第２接続端子２と第４接続端子６を接合することが好ましい。 The first connection terminal 1 and the third connection terminal 5 are joined by being pressed against each other and applying pressure.
By the way, in the process of joining the first connection terminal 1 and the third connection terminal 5 and joining the second connection terminal 2 and the fourth connection terminal 6, the first connection terminal 1 is in contact with the third connection terminal 5. 2 With the connection terminal 2 pressed against the fourth connection terminal 6, the second connection terminal 2 and the fourth connection terminal 6 are joined by heating at a temperature equal to or higher than the melting point of the material constituting the second connection terminal 2. Is preferable.

このように、第２接続端子２を構成する材料の融点以上に加熱し、溶融させることで、より接続性を良好なものにでき、電気抵抗の低い接合部を実現することができる。
また、このようにして第２接続端子２を構成する材料を溶融させて接合する場合、半導体チップ３に、第２接続端子２として、複数の接続端子２Ａからなる接続端子群によって構成される第２接続端子２を形成すると、複数の接続端子２Ａからなる接続端子群は、複数のパッド２０からなるパッド群上に設けられることになるため、半導体チップ３と基板４を接合した半導体装置では、複数のパッド２０からなるパッド群上に設けられた第２接続端子２を備えるものとなる（例えば図１２参照）。 In this way, by heating and melting the material constituting the second connection terminal 2 above the melting point, the connectivity can be improved and a joint portion having low electrical resistance can be realized.
Further, when the materials constituting the second connection terminal 2 are melted and joined in this way, the semiconductor chip 3 is composed of a group of connection terminals composed of a plurality of connection terminals 2A as the second connection terminal 2. When the two connection terminals 2 are formed, the connection terminal group composed of the plurality of connection terminals 2A is provided on the pad group composed of the plurality of pads 20, so that in a semiconductor device in which the semiconductor chip 3 and the substrate 4 are joined, the semiconductor device is used. A second connection terminal 2 provided on a pad group composed of a plurality of pads 20 is provided (see, for example, FIG. 12).

また、半導体チップ３を、複数の第２接続端子２を備え、複数の第２接続端子２の間隔を、接続端子群に含まれる複数の接続端子２Ａの間隔よりも広くしたものとすると、半導体チップ３と基板４を接合した半導体装置では、第２接続端子２を複数備え、複数の第２接続端子２のそれぞれが設けられたパッド群の間隔は、パッド群に含まれる複数のパッド２０の間隔よりも広いものとなる（例えば図１２参照）。 Further, assuming that the semiconductor chip 3 is provided with a plurality of second connection terminals 2 and the distance between the plurality of second connection terminals 2 is wider than the distance between the plurality of connection terminals 2A included in the connection terminal group, the semiconductor The semiconductor device in which the chip 3 and the substrate 4 are joined includes a plurality of second connection terminals 2, and the distance between the pads group provided with each of the plurality of second connection terminals 2 is such that the pads 20 included in the pad group are spaced apart from each other. It will be wider than the interval (see, for example, FIG. 12).

ここで、接合前の第１接続端子１と第２接続端子２の高さの差をΔｈとした場合、複数の第２接続端子２の間隔を、Δｈの０．６倍よりも大きい間隔にすることによって、端子間で接触しにくくなるため、このようにした場合、接合後の複数の第２接続端子２のそれぞれに設けられたパッド群の間隔は、Δｈの０．６倍よりも大きい間隔となる。また、第２接続端子２を構成する接続端子群に含まれる複数の接続端子２Ａの間隔を、Δｈの０．６倍以下の間隔にすることによって、良好な接続が得られるため、このようにした場合、接合後のパッド群に含まれる複数のパッド２０の間隔は、Δｈの０．６倍以下の間隔となる（例えば図１２参照）。 Here, assuming that the difference in height between the first connection terminal 1 and the second connection terminal 2 before joining is Δh, the distance between the plurality of second connection terminals 2 is set to be larger than 0.6 times Δh. By doing so, it becomes difficult for the terminals to come into contact with each other. Therefore, in this case, the distance between the pads provided in each of the plurality of second connection terminals 2 after joining is larger than 0.6 times Δh. It becomes an interval. Further, a good connection can be obtained by setting the interval between the plurality of connection terminals 2A included in the connection terminal group constituting the second connection terminal 2 to be 0.6 times or less of Δh. If so, the interval between the plurality of pads 20 included in the pad group after joining is 0.6 times or less the interval of Δh (see, for example, FIG. 12).

具体的には、以下のようにして接合すれば良い。
つまり、まず、上述のようにして第１接続端子１及び第２接続端子２が形成された半導体チップ３と、上述のようにして第３接続端子５及び第４接続端子６が形成された基板４を対向させる［図１０（Ａ）参照］。
次に、半導体チップ３の径が小さく、かつ、高さが高い第２接続端子２を基板４の第４接続端子６に接触させ［図１０（Ｂ）参照］、半導体チップ３の径が大きく、かつ、高さが低い第１接続端子１が第３接続端子５に接触するまで第２接続端子２を第４接続端子６に押し付ける［図１０（Ｃ）参照］。 Specifically, they may be joined as follows.
That is, first, the semiconductor chip 3 on which the first connection terminal 1 and the second connection terminal 2 are formed as described above, and the substrate on which the third connection terminal 5 and the fourth connection terminal 6 are formed as described above. 4 are opposed to each other [see FIG. 10 (A)].
Next, the second connection terminal 2 having a small diameter and a high height of the semiconductor chip 3 is brought into contact with the fourth connection terminal 6 of the substrate 4 [see FIG. 10B], and the diameter of the semiconductor chip 3 is large. Further, the second connection terminal 2 is pressed against the fourth connection terminal 6 until the first connection terminal 1 having a low height comes into contact with the third connection terminal 5 [see FIG. 10 (C)].

この状態で、図１１に示すように、他の接続端子１、５、６よりも低融点である第２接続端子２を構成する材料の融点以上の温度で加熱し、溶融させて、第２接続端子２と第４接続端子６を接合する。これにより、微細な端子、即ち、第２接続端子２を構成する接続端子群の複数の接続端子２Ａの間に存在する隙間が埋められることになり、より電気抵抗の低い接合部を実現することができる。 In this state, as shown in FIG. 11, the second connection terminal 2 is heated and melted at a temperature equal to or higher than the melting point of the material constituting the second connection terminal 2, which has a lower melting point than the other connection terminals 1, 5 and 6. The connection terminal 2 and the fourth connection terminal 6 are joined. As a result, a fine terminal, that is, a gap existing between a plurality of connection terminals 2A of the connection terminal group constituting the second connection terminal 2, is filled, and a joint portion having a lower electric resistance can be realized. Can be done.

したがって、本実施形態にかかる半導体装置及びその製造方法は、半導体チップ３にかかる応力を緩和し、隣接する接続端子同士が接触しないようにして、信頼性を向上させることができるという効果を有する。
特に、上述のように、高さの高い接続端子２の断面積を、高さの低い接続端子１の断面積よりも小さくし、対向する接続端子以下のヤング率の材料を用いて押し当てられた構造とする（例えば図１、図２参照）。また、端子径の小さい接続端子群を、対向する１つの接続端子に対して接触させ、加圧することによって製造する。これにより、接合時に半導体チップ３にかかる応力を緩和することができ、かつ、隣接する接続端子同士が接触することのない構造を実現することができる（例えば図１、図２参照）。さらに、この構造によって、端子径が小さく、ヤング率が小さい接続端子２が、緩衝材の役割を果たすことになり、製造後も半導体チップ３にかかる応力を緩和することができる。 Therefore, the semiconductor device and the manufacturing method thereof according to the present embodiment have an effect that the stress applied to the semiconductor chip 3 can be relaxed and the adjacent connection terminals do not come into contact with each other to improve the reliability.
In particular, as described above, the cross-sectional area of the high-height connection terminal 2 is made smaller than the cross-sectional area of the low-height connection terminal 1, and the material is pressed using a material having a Young's modulus equal to or lower than that of the opposite connection terminal. (See, for example, FIGS. 1 and 2). Further, it is manufactured by bringing a group of connection terminals having a small terminal diameter into contact with one facing connection terminal and applying pressure. As a result, the stress applied to the semiconductor chip 3 at the time of joining can be relaxed, and a structure in which adjacent connection terminals do not come into contact with each other can be realized (see, for example, FIGS. 1 and 2). Further, according to this structure, the connection terminal 2 having a small terminal diameter and a small Young's modulus serves as a cushioning material, and the stress applied to the semiconductor chip 3 can be relaxed even after manufacturing.

また、上述のような構造によって、製造ばらつきによらず、良好な接続が達成される。また、高精度な高さ合わせを必要としないプロセスで製造可能である。さらに、半導体チップ３側の接続端子２のヤング率が低く、基板４側の接続端子６よりも断面積が小さいため、変形しやすいという特徴を持つことによって、半導体チップ３にかかる応力を緩和することができ、製造後も信頼性の高い接合部を実現することができる。 Further, due to the structure as described above, good connection is achieved regardless of manufacturing variations. In addition, it can be manufactured by a process that does not require highly accurate height adjustment. Further, since the Young's modulus of the connection terminal 2 on the semiconductor chip 3 side is low and the cross-sectional area is smaller than that of the connection terminal 6 on the substrate 4 side, it is easily deformed, thereby relaxing the stress applied to the semiconductor chip 3. It is possible to realize a highly reliable joint even after manufacturing.

なお、本発明は、上述した実施形態に記載した構成に限定されるものではなく、本発明の趣旨を逸脱しない範囲で種々変形することが可能である。
以下、上述の実施形態に関し、更に、付記を開示する。
（付記１）
外周部に設けられた第１接続端子と、
前記第１接続端子よりも内側に設けられ、前記第１接続端子よりも高さが高く、銅よりもヤング率が小さい材料からなり、前記第１接続端子よりも断面積が小さい第２接続端子とを備えることを特徴とする半導体装置。 The present invention is not limited to the configuration described in the above-described embodiment, and can be variously modified without departing from the spirit of the present invention.
Hereinafter, additional notes will be disclosed with respect to the above-described embodiment.
(Appendix 1)
The first connection terminal provided on the outer circumference and
A second connection terminal provided inside the first connection terminal, having a height higher than that of the first connection terminal, having a Young's modulus smaller than that of copper, and having a smaller cross-sectional area than the first connection terminal. A semiconductor device characterized by being provided with.

（付記２）
前記第２接続端子は、複数の接続端子からなる接続端子群によって構成されることを特徴とする、付記１に記載の半導体装置。
（付記３）
前記第２接続端子を複数備え、
前記複数の第２接続端子の間隔は、前記接続端子群に含まれる複数の接続端子の間隔よりも広いことを特徴とする、付記２に記載の半導体装置。 (Appendix 2)
The semiconductor device according to Appendix 1, wherein the second connection terminal is composed of a group of connection terminals including a plurality of connection terminals.
(Appendix 3)
A plurality of the second connection terminals are provided.
The semiconductor device according to Appendix 2, wherein the distance between the plurality of second connection terminals is wider than the distance between the plurality of connection terminals included in the connection terminal group.

（付記４）
前記複数の第２接続端子は、前記第１接続端子と前記第２接続端子の高さの差の０．６倍よりも長い間隔で設けられており、
前記接続端子群に含まれる複数の接続端子は、前記第１接続端子と前記第２接続端子の高さの差の０．６倍よりも短い間隔で設けられていることを特徴とする、付記３に記載の半導体装置。 (Appendix 4)
The plurality of second connection terminals are provided at intervals longer than 0.6 times the height difference between the first connection terminal and the second connection terminal.
A plurality of connection terminals included in the connection terminal group are provided at intervals shorter than 0.6 times the height difference between the first connection terminal and the second connection terminal. 3. The semiconductor device according to 3.

（付記５）
外周部に設けられた第１接続端子と、前記第１接続端子よりも内側に設けられ、複数のパッドからなるパッド群上に設けられた第２接続端子とを備える半導体チップと、
外周部に設けられた第３接続端子と、前記第３接続端子よりも内側に設けられた第４接続端子とを備える基板とを備え、
前記第２接続端子は、前記第４接続端子よりもヤング率が小さい材料からなり、
前記第１接続端子と前記第３接続端子が接合され、前記第２接続端子と前記第４接続端子が接合されていることを特徴とする半導体装置。 (Appendix 5)
A semiconductor chip including a first connection terminal provided on the outer peripheral portion and a second connection terminal provided inside the first connection terminal and provided on a pad group composed of a plurality of pads.
A substrate including a third connection terminal provided on the outer peripheral portion and a fourth connection terminal provided inside the third connection terminal is provided.
The second connection terminal is made of a material having a Young's modulus smaller than that of the fourth connection terminal.
A semiconductor device characterized in that the first connection terminal and the third connection terminal are joined, and the second connection terminal and the fourth connection terminal are joined.

（付記６）
前記第２接続端子を複数備え、
前記複数の第２接続端子のそれぞれが設けられた前記パッド群の間隔は、前記パッド群に含まれる複数のパッドの間隔よりも広いことを特徴とする、付記５に記載の半導体装置。 (Appendix 6)
A plurality of the second connection terminals are provided.
The semiconductor device according to Appendix 5, wherein the distance between the pads provided with each of the plurality of second connection terminals is wider than the distance between the plurality of pads included in the pad group.

（付記７）
半導体チップの外周部に第１接続端子を形成するとともに、前記第１接続端子よりも内側に、前記第１接続端子よりも高さが高く、銅よりもヤング率が小さい材料からなり、前記第１接続端子よりも断面積が小さい第２接続端子を形成する工程を含むことを特徴とする半導体装置の製造方法。 (Appendix 7)
The first connection terminal is formed on the outer peripheral portion of the semiconductor chip, and is made of a material having a height higher than that of the first connection terminal and a Young's modulus smaller than that of copper inside the first connection terminal. A method for manufacturing a semiconductor device, which comprises a step of forming a second connection terminal having a cross-sectional area smaller than that of one connection terminal.

（付記８）
前記第２接続端子を形成する工程において、複数の接続端子からなる接続端子群によって構成される第２接続端子を形成することを特徴とする、付記７に記載の半導体装置の製造方法。
（付記９）
前記第２接続端子を形成する工程において、前記接続端子群に含まれる複数の接続端子の間隔よりも間隔が広くなるように複数の第２接続端子を形成することを特徴とする、付記８に記載の半導体装置の製造方法。 (Appendix 8)
The method for manufacturing a semiconductor device according to Appendix 7, wherein in the step of forming the second connection terminal, a second connection terminal composed of a group of connection terminals composed of a plurality of connection terminals is formed.
(Appendix 9)
In the step of forming the second connection terminal, a plurality of second connection terminals are formed so that the interval is wider than the interval of the plurality of connection terminals included in the connection terminal group. The method for manufacturing a semiconductor device according to the description.

（付記１０）
前記第２接続端子を形成する工程において、
前記複数の第２接続端子を、前記第１接続端子と前記第２接続端子の高さの差の０．６倍よりも長い間隔で形成し、
前記接続端子群に含まれる複数の接続端子を、前記第１接続端子と前記第２接続端子の高さの差の０．６倍よりも短い間隔で形成することを特徴とする、付記９に記載の半導体装置の製造方法。 (Appendix 10)
In the step of forming the second connection terminal,
The plurality of second connection terminals are formed at intervals longer than 0.6 times the height difference between the first connection terminal and the second connection terminal.
A plurality of connection terminals included in the connection terminal group are formed at intervals shorter than 0.6 times the height difference between the first connection terminal and the second connection terminal. The method for manufacturing a semiconductor device according to the description.

（付記１１）
基板の外周部に第３接続端子を形成するとともに、前記第３接続端子よりも内側に第４接続端子を形成する工程と、
前記第１接続端子が前記第３接続端子に接触するまで前記第２接続端子を前記第４接続端子に押し付けた状態で、前記第１接続端子と前記第３接続端子を接合し、前記第２接続端子と前記第４接続端子を接合する工程とを含むことを特徴とする、付記７〜１０のいずれか１項に記載の半導体装置の製造方法。 (Appendix 11)
A step of forming a third connection terminal on the outer peripheral portion of the substrate and forming a fourth connection terminal inside the third connection terminal.
In a state where the second connection terminal is pressed against the fourth connection terminal until the first connection terminal comes into contact with the third connection terminal, the first connection terminal and the third connection terminal are joined to form the second connection terminal. The method for manufacturing a semiconductor device according to any one of Supplementary note 7 to 10, further comprising a step of joining the connection terminal and the fourth connection terminal.

（付記１２）
前記第１接続端子と前記第３接続端子を接合し、前記第２接続端子と前記第４接続端子を接合する工程において、前記第１接続端子が前記第３接続端子に接触するまで前記第２接続端子を前記第４接続端子に押し付けた状態で、前記第２接続端子を構成する材料の融点よりも低い温度で加熱し、電流を流して、前記第２接続端子と前記第４接続端子を接合することを特徴とする、付記１１に記載の半導体装置の製造方法。 (Appendix 12)
In the step of joining the first connection terminal and the third connection terminal and joining the second connection terminal and the fourth connection terminal, the second connection terminal is in contact with the third connection terminal. With the connection terminal pressed against the fourth connection terminal, the second connection terminal and the fourth connection terminal are heated by heating at a temperature lower than the melting point of the material constituting the second connection terminal and passing an electric current. The method for manufacturing a semiconductor device according to Appendix 11, wherein the semiconductor device is joined.

（付記１３）
前記第１接続端子と前記第３接続端子を接合し、前記第２接続端子と前記第４接続端子を接合する工程において、前記第１接続端子が前記第３接続端子に接触するまで前記第２接続端子を前記第４接続端子に押し付けた状態で、前記第２接続端子を構成する材料の融点以上の温度で加熱して、前記第２接続端子と前記第４接続端子を接合することを特徴とする、付記１１に記載の半導体装置の製造方法。 (Appendix 13)
In the step of joining the first connection terminal and the third connection terminal and joining the second connection terminal and the fourth connection terminal, the second connection terminal is in contact with the third connection terminal. The feature is that the second connection terminal and the fourth connection terminal are joined by heating at a temperature equal to or higher than the melting point of the material constituting the second connection terminal in a state where the connection terminal is pressed against the fourth connection terminal. The method for manufacturing a semiconductor device according to Appendix 11.

１第１接続端子
２第２接続端子
２Ａ複数の接続端子
３半導体チップ
４基板（配線基板）
５第３接続端子
６第４接続端子
７レジスト膜
８開口部
９レジスト膜
１０開口部
１１レジスト膜
１２、１３開口部
１４レジスト膜
１５、１６開口部
１７レジスト膜
１８開口部
１９レジスト膜
２０パッド
２１開口部
２２レジスト膜
２３、２４開口部 1 1st connection terminal 2 2nd connection terminal 2A Multiple connection terminals 3 Semiconductor chip 4 Board (wiring board)
5 3rd connection terminal 6 4th connection terminal 7 Resist film 8 Opening 9 Resist film 10 Opening 11 Resist film 12, 13 Opening 14 Resist film 15, 16 Opening 17 Resist film 18 Opening 19 Resist film 20 Pad 21 Opening 22 Resist film 23, 24 Opening

Claims

A first connecting terminal provided on the outer peripheral portion, provided on the inner side of the said first connecting terminal, a semiconductor chip and a second connection terminal provided on the pad group including a plurality of pads,
A substrate including a third connection terminal provided on the outer peripheral portion and a fourth connection terminal provided inside the third connection terminal is provided.
The first connection terminal and the third connection terminal are joined, and the second connection terminal and the fourth connection terminal are joined.
The second connection terminal is made of a material having a Young's modulus smaller than that of the fourth connection terminal, and is in a state of being pressed against the fourth connection terminal until the first connection terminal contacts the third connection terminal. A semiconductor device characterized by.

A plurality of the second connection terminals are provided.
Wherein the plurality of intervals of said pads, each provided in the second connection terminal is characterized by wider than the interval of a plurality of pads included in the pad group, a semiconductor equipment according to claim 1.

The first connection terminal is formed on the outer peripheral portion of the semiconductor chip, and is made of a material having a height higher than that of the first connection terminal and a Young's modulus smaller than that of copper inside the first connection terminal. The process of forming a second connection terminal whose cross-sectional area is smaller than that of one connection terminal,
A step of forming a third connection terminal on the outer peripheral portion of the substrate and forming a fourth connection terminal inside the third connection terminal.
In a state where the second connection terminal is pressed against the fourth connection terminal until the first connection terminal comes into contact with the third connection terminal, the first connection terminal and the third connection terminal are joined to form the second connection terminal. A method for manufacturing a semiconductor device, which comprises a step of joining a connection terminal and the fourth connection terminal.