JP6930113B2 - Semiconductor devices and manufacturing methods for semiconductor devices - Google Patents

Description

The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

Silicon carbide (SiC) is expected as a next-generation semiconductor material to replace silicon (Si). A semiconductor device using silicon carbide as a semiconductor material (hereinafter referred to as a silicon carbide semiconductor device) has a resistance of several hundredths of that of a conventional semiconductor device using silicon as a semiconductor material. There are various advantages such as being able to reduce the amount of data and being able to be used in an environment of a higher temperature (200 ° C. or higher). This is due to the characteristics of the material itself that the band gap of silicon carbide is about three times larger than that of silicon, and the dielectric breakdown electric field strength is nearly an order of magnitude larger than that of silicon.

As silicon carbide semiconductor devices, Schottky barrier diodes (SBDs), vertical MOSFETs with planar gate structures and trench gate structures (Metal Oxide Semiconductor Field Effect Transistors), and insulated gate type field effect transistors have been used so far. IGBTs (Insulated Gate Bipolar Transistors: Insulated Gate Bipolar Transistors) have been commercialized.

In a wide bandgap semiconductor bipolar device such as SiC, or even in a unipolar device, when performing bipolar operation in which a small number of carriers are generated during operation, high energy is generated during hole / electron recombination due to the wide bandgap. do. Such recombination occurs in the vicinity of the basal dislocation BPD (Basal Plane Dislocation), and when high energy is applied, defects and dislocations become stacking defects and expand, resulting in an increase in on-resistance. Deterioration phenomenon has been observed.

FIG. 11 is a cross-sectional view showing the configuration of a conventional silicon carbide semiconductor device. ^{In the PiN diode shown in FIG. 11, the n-} type conversion layer 9, the n ^- type drift layer 2, and aluminum (Al) are formed by epitaxial growth on the front surface of the n-type silicon carbide substrate 1. It is constructed by using an epitaxial substrate formed by sequentially laminating p-type regions 3 to which is added. A front electrode 7 is provided on the surface of the p-type region 3, and a back electrode 8 is provided on the back surface of the n-type silicon carbide substrate 1. Further, an n-type buffer layer (not shown) may be provided between the n ^- type conversion layer 9 and the n ^{-type drift layer 2.}

The n ^- type conversion layer 9 affects the electrical characteristics of the basal dislocation BPD existing at the interface between the substrate and the epi layer (hereinafter, the layer formed by epitaxial growth on the n-type silicon carbide substrate 1 is abbreviated as the epi layer). It converts to a small number of through-blade dislocations such as TED (Threading Edge Dislocation) at a very high rate (for example, 99%). Conventionally, deterioration has been prevented by ^{the n-type conversion layer 9.}

Japanese Unexamined Patent Publication No. 2009-88223

However, when the current density during operation is high, ^{high energy is given to the basal dislocation BPD at the interface of the n-type buffer layer / n-} type conversion layer 9 or in the substrate, resulting in defects. Expansion can occur. Therefore, there is a problem that it is not possible to completely prevent the on-resistance characteristics from deteriorating.

Further, in a bipolar device, if the injection of a small number of carriers is large, a large current flows until the accumulated carriers are discharged / extinguished when the conduction operation is started to the off operation, and the switching loss due to a long switching period becomes large. ..

An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device, which does not deteriorate the on-resistance characteristics and has a small switching loss, in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has a first conductive type semiconductor substrate and an impurity concentration higher than that of the semiconductor substrate provided on the semiconductor substrate. The second semiconductor layer includes a low first conductive type first semiconductor layer and a second conductive type second semiconductor layer of the first semiconductor layer provided on the opposite side of the semiconductor substrate. Creates an impurity level deeper than that of aluminum in silicon carbide, contains an impurity that becomes a second conductive type, and is the first semiconductor of the third semiconductor layer and the third semiconductor layer in contact with the first semiconductor layer. It is composed of a fourth semiconductor layer provided on the opposite side of the layer and having a higher impurity concentration than the third semiconductor layer and having a concentration of 1 × 10 ²⁰ / cm ³ or more, and the fourth semiconductor layer is made of aluminum impurities. , impurities of the third semiconductor layer is made a deep impurity level than aluminum in silicon carbide, characterized by comprising the boron impurity serving as a second conductivity type.

The semiconductor device according to the present invention, in the invention described above, the fourth semiconductor layer, prior Symbol selectively provided on the surface opposite to the first semiconductor layer, an impurity than said second semiconductor layer It is a second conductive type first semiconductor region having a high concentration.

Further, in the above-described invention, the semiconductor device according to the present invention has a first conductive type fifth semiconductor layer having a higher impurity concentration than the first semiconductor layer between the semiconductor substrate and the first semiconductor layer. It is characterized by being prepared.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the fourth semiconductor layer has a thickness of 100 nm or less.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first semiconductor region has an area ratio of 50% or less with respect to the third semiconductor layer.
Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the third semiconductor layer has an impurity concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ / cm ³ .

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention is a first conductive type semiconductor substrate having a lower impurity concentration than the semiconductor substrate. The first step of forming the first semiconductor layer and the second step of forming the second conductive type second semiconductor layer on the opposite side of the first semiconductor layer with respect to the semiconductor substrate. In the second step, the impurity concentration of the third semiconductor layer in contact with the first semiconductor layer and the third semiconductor layer are higher than those of the third semiconductor layer provided on the opposite side of the first semiconductor layer. The second semiconductor layer is formed of a fourth semiconductor layer of 1 × 10 ²⁰ / cm ³ or more, the fourth semiconductor layer is formed using impurities of aluminum, and the impurities of the third semiconductor layer are carbonized. It is characterized in that an impurity level deeper than that of aluminum is formed in silicon and formed by using an impurity of boron which becomes a second conductive type.

According to the above-described invention, the silicon carbide semiconductor device includes a p-type region (second conductive type second semiconductor layer) doped with an impurity (for example, boron (B)) that forms an impurity level deeper than Al. As a result, even with the same current density as the conventional structure, ^{the hole density reaching the inside of the n-} type conversion layer is reduced, and the amount of hole-electron recombination in the vicinity of the BPD is reduced, thereby preventing the deterioration of the characteristics during operation. Further, even with the same current density, ^{the carriers existing in the n-} type drift layer can be reduced, and the switching loss can be reduced.

Further, the silicon carbide semiconductor device according to the present invention can reduce the amount of minority carriers without reducing the total amount of impurities in the p-type region, and therefore does not change from the depletion layer width and potential distribution in the conventional structure during reverse bias operation. Does not decrease.

Further, the silicon carbide semiconductor device according to the present invention forms a deep level by including Al, which is a conventional impurity, in combination with an impurity that creates an impurity level deeper than Al in the p-type region. It is possible to play a complementary role in the activation rate of impurities which is too low at ultra-low temperature and the slow response which is difficult to ionize in a short time.

According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, the on-resistance characteristics are not deteriorated and the switching loss is small.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the other structure of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 3). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 2. It is sectional drawing which shows the other structure of the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. It is a table which shows the minority carrier amount at the semiconductor substrate interface in the conventional silicon carbide semiconductor device, the silicon carbide semiconductor device according to the first embodiment, and the silicon carbide semiconductor device according to the fourth embodiment. It is sectional drawing which shows the structure of the conventional silicon carbide semiconductor device.

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electron or hole is a large number of carriers in the layer or region marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
As the semiconductor device according to the present invention, a silicon carbide PiN diode will be described as an example. FIG. 1 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment.

As shown in FIG. 1, the silicon carbide semiconductor device, the n-type (first conductivity type semiconductor substrate) silicon carbide substrate 1 of the front surface, n ^- -type transform layer 9, n ^- -type drift layer (first It is configured by using a silicon carbide substrate formed by sequentially laminating 1 conductive type first semiconductor layer) 2 and p-type region (second conductive type second semiconductor layer) 3 + 10.

The n-type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with n-type impurities. The n ^- type conversion layer 9 is a layer that converts the basal plane dislocation BPD into a through-blade dislocation TED that has lower impurities than the n-type silicon carbide substrate 1 and has less influence on the electrical characteristics. The n ^- type drift layer 2 is a drift layer that serves as a pressure-resistant holding layer doped with n-type impurities.

The p-type region 3 + 10 is ^{a region for injecting a small number of carriers into the n-} type drift layer 2, and is most conventionally used in a high impurity concentration layer (p-type region 3) in which Al is doped as a p-type impurity. This is a region doped with impurities (for example, boron (B)) that form an impurity level deeper than Al. The region where Al and B are doped as p-type impurities is referred to as p-type region 3 + 10, the region where Al is doped as p-type impurities is referred to as p-type region 3, and B is doped as p-type impurities. The region is referred to as a p-type region 10.

The impurity level of Al is about 0.18 eV, but in the case of B, it is said that a deeper level of 0.3 eV or more is formed. Since B has a deep level, holes are less likely to be excited than Al having the same concentration when the environmental temperature is the same. Therefore, by doping B, the ^{minority carriers injected into the n-} type drift layer 2 can be reduced. With this structure, even with the same current density as the conventional structure, ^{the hole density reaching the inside of the n-} type conversion layer 9 is reduced, and the amount of hole-electron recombination in the vicinity of the BPD is reduced, thereby preventing characteristic deterioration during operation. .. Further, even with the same current density, ^{the carriers existing in the n-} type drift layer 2 can be reduced, and the switching loss can be reduced.

Further, a surface electrode 7 is provided on the surface of the p-type region 3 + 10. Further, a back surface electrode 8 is provided on the back surface of the n-type silicon carbide substrate 1.

Here, FIG. 2 is a cross-sectional view showing another configuration of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 2, the p-type region 3 + 10 is a p-type region 10 doped with an impurity (for example, B) that forms an impurity level deeper than Al without doping Al. Even with this structure, the same effect as in FIG. 1 can be obtained.

(Manufacturing method of silicon carbide semiconductor device according to the first embodiment)
The method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described by taking as an example a case where a PiN diode using silicon carbide as a semiconductor material is manufactured (manufactured). 3 to 5 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment.

First, an n-type silicon carbide substrate 1 made of n-type silicon carbide and having an impurity concentration of 1 × 10 ¹⁹ / cm ^{3 is prepared.} Next, by epitaxial growth on the first main surface (front surface) of the n-type silicon carbide substrate 1, for example, ^{an n-} type conversion ^{having an impurity concentration of 1 × 10 18} / cm ³ or more and a thickness of 1 μm or more is performed. Form layer 9. The state up to this point is shown in FIG.

Then, n ^- by epitaxial growth on the type conversion layer 9, eg, n impurity concentration becomes 1 × 10 ¹⁴ / cm ³ of about or more breakdown voltage holding layer ^- -type drift layer 2. The concentration and thickness of the n ^- type drift layer 2 vary depending on the withstand voltage class. For example, in the case of an element with a withstand voltage of 1200 V, ^{the concentration is about 1 × 10 15} / cm ³ or more and the thickness is about 10 μm or more. The state up to this point is shown in FIG.

Next, a high-concentration p-type region 3 + 10 is formed on ^{the n-type drift layer 2 by epitaxial growth or ion implantation.} At that time, B is used in addition to Al as the p-type impurity, or only B is used (see FIG. 2). For example, B is used for about 10% to 100% of the total amount of impurities in the p-type region 3 + 10. The impurity concentration of the p-type region 3 + 10 is ^{1 × 10 16} / cm ^{3 or more, which is sufficiently higher than the concentration of the n-} type drift layer 2, and the thickness of the p-type region 3 + 10 may be about 0.1 to several μm. Here, Al and B may be mixed in the same region, divided in a laminated shape in the depth direction, or additionally mixed in a part of the area when viewed from above. Further, as shown in FIG. 2, the p-type region 10 may be formed by using only B. Note that if the impurity concentration in the p-type region 3 + 10 is not sufficiently higher than the impurity concentration in the n ^- type drift layer 2, if the thickness of the p-type region 3 + 10 is thin, the withstand voltage will decrease due to punch-through to the surface electrode. Is. The state up to this point is shown in FIG.

Next, if the p-type region 3 + 10 is formed by epitaxial growth, the p-type region 3 + 10 is removed by etching a part of the outer peripheral portion in order to form a low-concentration p-type region (not shown) in the peripheral portion. Then, a peripheral withstand voltage structure that relaxes the electric field strength in the lateral direction is formed, and then the front electrode 7 and the back surface electrode 8 are formed, respectively. As a result, the PiN diode shown in FIGS. 1 and 2 is completed.

As described above, according to the first embodiment, the silicon carbide semiconductor device includes a p-type region doped with an impurity (for example, boron (B)) that forms an impurity level deeper than Al. As a result, even with the same current density as the conventional structure, ^{the hole density reaching the inside of the n-} type conversion layer is reduced, and the amount of hole-electron recombination in the vicinity of the BPD is reduced, thereby preventing the deterioration of the characteristics during operation. Further, even with the same current density, ^{the carriers existing in the n-} type drift layer can be reduced, and the switching loss can be reduced.

Further, since the silicon carbide semiconductor device according to the first embodiment can reduce the minority carrier amount without reducing the total amount of impurities in the p-type region, it does not change from the depletion layer width and the potential distribution in the conventional structure during the reverse bias operation. , The pressure resistance does not decrease.

Further, the silicon carbide semiconductor device according to the first embodiment has a deep level by including Al, which is a conventional impurity, in combination with an impurity that creates an impurity level deeper than Al in the p-type region. It is possible to play a complementary role in the activation rate of the forming impurities at an ultra-low temperature, which is too low, and the slow response, which is difficult to ionize in a short time.

(Embodiment 2)
FIG. 6 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second embodiment. FIG. 7 is a cross-sectional view showing another configuration of the silicon carbide semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that it has two layers, a p-type region 3 and a p-type region 10, and a PiN having a low concentration in the p-type region. It was a diode.

In a PiN diode having a conventional structure, in order to reduce the on-voltage (on-resistance) during operation and to reduce the contact resistance with the surface electrode 7, a high impurity concentration ^{of 1 × 10 19} / cm ^{3 or more is particularly high near the surface.} Is often used. On the other hand, in the second embodiment of the present invention, p on the lower side (n-type silicon carbide substrate 1 side) than the electrode surface in contact with the surface electrode 7 (for example, in the range of about 100 nm from the surface in contact with the surface electrode 7). The mold region is 1 × 10 ¹⁹ / cm ³ or less and the impurity concentration is equal to or less than the impurity concentration of the buffer layer (for example, 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁹ / cm ³ or more, more preferably 1 × 10 ^17). / Cm ³ to 1 x 10 ¹⁸ / cm ³ ). At that time, as the p-type impurity, an impurity (for example, B) that makes an impurity level deeper than Al is used in addition to Al, or only an impurity that makes an impurity level deeper than Al (for example, B) is used. For example, B is used for about 10% to 100% (for example, 90% to 100%) of the total amount of impurities in the p-type region.

For example, as shown in FIG. 6, the p-type region (fourth semiconductor layer) on the polar surface in contact with the surface electrode 7 is defined as the p-type region 3 using Al as an impurity, and the p-type region below the polar surface. The (third semiconductor layer) may be a p-type region 10 using B as an impurity. In this case, the impurity concentration of the p-type region 10 is lower than the impurity concentration of the p-type region 3, and is reduced to a concentration equal to or less than the impurity concentration of the buffer layer. On the contrary, as shown in FIG. 7, the p-type region on the electrode surface in contact with the surface electrode 7 is defined as the p-type region 10 using B as an impurity, and the p-type region below the electrode surface is Al as an impurity. May be used as the p-type region 3 using. In this case, the impurity concentration in the p-type region 3 is reduced to a concentration lower than the impurity concentration in the p-type region 10 and equal to or less than the impurity concentration in the buffer layer. Since other structures are the same as those in the first embodiment, the description thereof will be omitted.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 2)
Next, a method of manufacturing the semiconductor device according to the second embodiment will be described. ^{First, the n-} type conversion layer 9 and the n ^- type drift layer 2 are formed on the surface of the n-type silicon carbide substrate 1 in the same manner as in the first embodiment (see FIGS. 3 and 4). Next, in the case of FIG. 6, a p-type region 10 using B as a p-type impurity is formed on the ^{n-type drift layer 2 by epitaxial growth or ion implantation.} Next, a p-type region 3 using Al as a p-type impurity is formed on the p-type region 10 by epitaxial growth or ion implantation. In the case of FIG. 7, the p-type region 3 is formed first, and then the p-type region 10 is formed. After that, the front electrode 7 and the back electrode 8 are formed, respectively. As a result, the PiN diode shown in FIGS. 6 and 7 is completed.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, the second embodiment has a low injection structure in which the concentration of the p-type region is reduced. Since the minority carriers at the same current density can be suppressed to 70% or less by this low injection structure, the operating current range without characteristic deterioration can be increased by 1.5 times to 2 times or more.

(Embodiment 3)
FIG. 8 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment in that the PiN has a low injection structure having a p-type region 3 having a high impurity concentration in a part of the p-type region 10 having a low concentration. It was a diode.

In addition to Al, impurities (for example, B) that form an impurity level deeper than Al are used as p-type impurities, or only impurities that form an impurity level deeper than Al (for example, B) are used. For example, B is used for about 10% to 100% (for example, 90% to 100%) of the total amount of impurities in the p-type region 10. In the third embodiment of the present invention, a part of the p-type region 10 in contact with the surface electrode 7 (for example, 50% or less in area ratio) is concentrated in a high concentration (for example, about 1 × 10 ²⁰ / cm ³ or more). And. The rest is reduced to ^{a concentration equal to or less than the impurity concentration of the n-} type conversion layer 9 (for example, about 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁸ / cm ^3). Since other structures are the same as those in the first embodiment, the description thereof will be omitted.

(Manufacturing method of silicon carbide semiconductor device according to the third embodiment)
Next, a method of manufacturing the semiconductor device according to the third embodiment will be described. ^{First, the n-} type conversion layer 9 and the n ^- type drift layer 2 are formed on the surface of the n-type silicon carbide substrate 1 in the same manner as in the first embodiment (see FIGS. 3 and 4). Next, a p-type region 10 using B as a p-type impurity is formed on ^{the n-type drift layer 2 by epitaxial growth or ion implantation.} Next, the p-type region 3 using Al as the p-type impurity is selectively formed on the surface layer of the p-type region 10 by ion implantation. After that, the front electrode 7 and the back electrode 8 are formed, respectively. This completes the PiN diode shown in FIG.

As described above, according to the third embodiment, the same effect as that of the first embodiment can be obtained. Further, in the second embodiment, the same effect as that in the second embodiment can be obtained by having a low injection structure in which the p-type region is reduced in concentration.

(Embodiment 4)
FIG. 9 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the first embodiment in that a high-concentration n-type buffer layer (first conductive type first) that promotes recombination on the ^{n-type conversion layer 9 is present.} It is a PiN diode provided with 5 semiconductor layers) 4. The n-type buffer layer 4 is, for example, a buffer layer having an impurity concentration of 1 × 10 ¹⁸ / cm ³ or more and a thickness of 1 μm or more. Since other structures are the same as those in the first embodiment, the description thereof will be omitted.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 4)
Next, a method of manufacturing the semiconductor device according to the fourth embodiment will be described. ^{First, the n-} type conversion layer 9 is formed on the surface of the n-type silicon carbide substrate 1 as in the first embodiment (see FIG. 3). Next, the n-type buffer layer 4 is formed on ^{the n-type conversion layer 9 by epitaxial growth.} After that, as in the first embodiment, the steps of forming the front surface electrode 7 and the back surface electrode 8 are performed from the step of forming the ^{n-type drift layer 2.} This completes the PiN diode shown in FIG.

As described above, according to the fourth embodiment, the same effect as that of the first embodiment can be obtained. Further, in the fourth embodiment, since the low injection structure is provided as in the second embodiment, the same effect as that of the second embodiment can be obtained. Further, in the fourth embodiment, since the minority carriers at the same current density can be suppressed to 70% or less due to the low injection structure, the thickness of the high-concentration buffer layer can be reduced to minimize the deterioration of resistance during unipolar operation. Can be suppressed to. Further, since the thickness of the high-concentration buffer layer can be reduced to 70% or less due to the low injection structure, the device manufacturing cost can be suppressed.

FIG. 10 is a table showing the amount of minority carriers at the semiconductor substrate interface in the conventional silicon carbide semiconductor device, the silicon carbide semiconductor device according to the first embodiment, and the silicon carbide semiconductor device according to the fourth embodiment. In FIG. 10, the conventional structure PiN diode and the PiN diode of the first embodiment when the current density is energized at 25 ° C. and 100 A / cm ² and the conventional structure PiN diode having a buffer structure and the PiN diode of the fourth embodiment are shown. , The simulation result of the minority carrier (hole in this case) density value near the substrate / epi layer is shown.

As shown in FIG. 10, the minority carrier density values of the conventional structure PiN diode and the PiN diode of the first embodiment are 2.24 × 10 ¹⁶ / cm ³ and 1.75 × 10 ¹⁶ / cm ³ , respectively. Become. The minority carrier density values of the conventional structure PiN diode having a buffer structure and the PiN diode of the fourth embodiment are 9.29 × 10 ¹⁴ / cm ³ and 6.40 × 10 ¹⁴ / cm ³ , respectively. .. As described above, by using the structure of the present invention, the density of minority carriers (holes in this case) in the vicinity of the substrate / epi layer can be reduced to about 70 to 80% of the conventional one.

An application example of the present invention is a PiN diode on an n-type substrate, but a similar device having a different polarity (for example, a NiP diode on a p-type substrate) can also be applied. The same applies to the built-in PN diode in a unipolar device such as a MOSFET. It can also be applied to IGBTs, thyristors and the like.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set in various ways according to the required specifications and the like. Further, in each of the above-described embodiments, the first conductive type is set to n type and the second conductive type is set to p type. However, in the present invention, the first conductive type is set to p type and the second conductive type is set to n type. It holds in.

As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for the bipolar semiconductor device having a high withstand voltage.

1 n-type silicon carbide substrate 2 n ^- type drift layer 3 p-type region 4 n-type buffer layer 7 front electrode 8 back electrode 9 n ^- type conversion layer 10 p-type region

Claims (7)

The first conductive type semiconductor substrate and
A first conductive type first semiconductor layer provided on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate,
A second conductive type second semiconductor layer provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate,
With
The second semiconductor layer has an impurity level deeper than that of aluminum in silicon carbide, contains an impurity that becomes a second conductive type, and is in contact with the first semiconductor layer. A fourth semiconductor layer provided on the opposite side of the first semiconductor layer and having a higher impurity concentration than the third semiconductor layer and having a concentration of 1 × 10 ²⁰ / cm ³ or more.
The fourth semiconductor layer is made of aluminum impurities, the impurity of the third semiconductor layer is made a deep impurity level than aluminum in silicon carbide, and characterized in that it consists of boron impurity serving as a second conductivity type Semiconductor device. The fourth semiconductor layer is
Selectively provided on the surface opposite to the first semiconductor layer, to claim 1, wherein the impurity concentration than the second semiconductor layer is a high first semiconductor region of a second conductivity type The semiconductor device described. The semiconductor according to claim 1 or 2, wherein a first conductive type fifth semiconductor layer having a higher impurity concentration than the first semiconductor layer is provided between the semiconductor substrate and the first semiconductor layer. Device. The semiconductor device according to claim 1, wherein the fourth semiconductor layer has a thickness of 100 nm or less. The semiconductor device according to claim 2 , wherein the first semiconductor region has an area ratio of 50% or less with respect to the third semiconductor layer. The semiconductor device according to any one of claims 1 to 5, wherein the third semiconductor layer has an impurity concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ / cm ^3. A first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate on the first conductive type semiconductor substrate.
The second step of forming the second conductive type second semiconductor layer on the opposite side of the first semiconductor layer with respect to the semiconductor substrate,
Including
In the second step,
A third semiconductor layer in contact with the first semiconductor layer and
A fourth semiconductor layer of the third semiconductor layer, which is provided on the opposite side of the first semiconductor layer and has an impurity concentration higher than that of the third semiconductor layer and is 1 × 10 ²⁰ / cm ³ or more. Form two semiconductor layers,
The fourth semiconductor layer is formed by using impurities of aluminum, and the impurities of the third semiconductor layer form an impurity level deeper than that of aluminum in silicon carbide, and the impurities of boron which becomes the second conductive type are used. A method for manufacturing a semiconductor device, which comprises forming.

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