JP6930393B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

A semiconductor device having a super junction (SJ) structure in which a first conductive type drift region and a second conductive type drift region are alternately arranged and a pn junction is periodically formed is said to have high withstand voltage and low on-resistance. Has characteristics. In a semiconductor device having an SJ structure, for example, a current flows in a drift region where the concentration of n-type impurities is high, and the on-resistance can be reduced. On the other hand, at the time of reverse bias, the drift region is depleted by the depletion layer extending from the pn junction, and high withstand voltage is ensured.

A structure is disclosed in which a drift region is arranged perpendicular to the main surface of the substrate along the side surface of the groove formed on the main surface of the substrate (see Patent Document 1). With this structure, it is possible to suppress an increase in on-resistance per unit area due to an increase in the area of the drift region.

Japanese Unexamined Patent Publication No. 08-181313

In order to obtain a high withstand voltage in the SJ structure, it is necessary to completely deplete the drift region in the off state. Therefore, the ratio of the total amount of p-type impurities in the p-type drift region to the total amount of n-type impurities in the n-type drift region is set to around 1. Generally, the product of the film thickness of the p-type drift region and the p-type impurity concentration is made equal to the product of the film thickness of the n-type drift region and the n-type impurity concentration.

However, when the p-type drift region and the n-type drift region are overlapped in the surface normal direction of the side surface of the groove, the film thickness and the impurity concentration are different between the p-type drift region and the n-type drift region. It is difficult to equalize the products. For example, if the total amount of impurities in the p-type drift region and the n-type drift region is to be equalized on the side surface of the groove, the p-type drift region and the n-type drift region are located at the corner where the side surface and the bottom surface of the groove are in contact with each other. The thickness of is different. That is, the film thickness of the p-type drift region formed earlier by ion implantation is thicker than that of the n-type drift region formed later. Therefore, it has been difficult to obtain a high withstand voltage in a semiconductor device having an SJ structure in which a drift region is formed on the side surface of the groove.

The present invention has been made in view of the above problems, and an object of the present invention is a semiconductor device having a super junction structure in which a drift region is formed on a side surface of a groove and a method for manufacturing a semiconductor device and a semiconductor device capable of obtaining a high withstand voltage. Is to provide.

In the semiconductor device according to one aspect of the present invention, the first conductive type first drift region and the second conductive type second drift region are alternately arranged along the side surface of the groove formed on the main surface of the substrate. The semiconductor layer and the first main electrode and the second main electrode, which are arranged via the semiconductor layer and are the respective ends of the current path of the main current flowing through the semiconductor layer in the direction perpendicular to the main surface of the substrate, are formed. The gist is to prepare.

The method for manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a groove on the main surface of the substrate, a first drift region of the first conductive type and a second of the second conductive type along the side surface of the groove. The process of forming the semiconductor layers in which the drift regions are alternately arranged, and the first main electrode and the second main electrode, which are the respective ends of the current paths of the main current flowing through the semiconductor layers in the direction perpendicular to the main surface of the substrate. The gist of the present invention is a method for manufacturing a semiconductor device, which includes a step of forming main electrodes so as to face each other via a semiconductor layer.

According to the present invention, it is possible to provide a semiconductor device having a super junction structure in which a drift region is formed on a side surface of the groove and a method for manufacturing the semiconductor device and a semiconductor device capable of obtaining a high withstand voltage.

It is a schematic perspective view which shows the structure of the semiconductor device which concerns on 1st Embodiment of this invention. It is a schematic diagram for demonstrating the spread of the depletion layer of the semiconductor device which concerns on 1st Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 1). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 2). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 3). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 4). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 5). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 6). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention (the 7). It is a schematic perspective view which shows the structure of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 1). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 2). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 3). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 4). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 5). It is a perspective view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention (the 6). It is a schematic perspective view which shows the structure of the semiconductor device which concerns on 1st modification of 2nd Embodiment of this invention. It is a schematic perspective view which shows the structure of the semiconductor device which concerns on 2nd modification of 2nd Embodiment of this invention. It is a schematic diagram which shows the calculation result of the electric field distribution of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a schematic perspective view which shows the structure of the semiconductor device which concerns on 3rd modification of 2nd Embodiment of this invention. It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on 3rd modification of 2nd Embodiment of this invention. It is a schematic perspective view which shows the structure of the semiconductor device which concerns on 4th modification of 2nd Embodiment of this invention. It is a schematic perspective view which shows the structure of the semiconductor device which concerns on 3rd Embodiment of this invention. It is a circuit diagram which shows the half-bridge part of the full-bridge circuit configured by using the semiconductor device which concerns on 3rd Embodiment of this invention. It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on other embodiment of this invention.

An embodiment will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, and the like include parts that are different from the actual ones. In addition, there are parts in which the relations and ratios of the dimensions of the drawings are different from each other.

(First Embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention has a semiconductor layer 20 formed in contact with a substrate 10 and one side surface of a groove 100 formed on a main surface of the substrate 10. Be prepared. In the semiconductor layer 20, a plurality of first conductive type first drift regions 21 and a plurality of second conductive type second drift regions 22 alternate along a direction (longitudinal direction) in which the groove 100 extends parallel to the main surface. It is a configuration arranged in. The semiconductor layer 20 is not in contact with the side surface of the groove 100 facing the side surface with which the semiconductor layer 20 is in contact.

As described above, the semiconductor device shown in FIG. 1 has an SJ structure in which a plurality of pn junctions are arranged along the longitudinal direction of the groove 100. That is, the first drift region 21 and the second drift region 22 are depleted by the depletion layer extending from the pn junction at the time of reverse bias, and a high withstand voltage can be obtained.

The first conductive type and the second conductive type are opposite conductive types to each other. That is, if the first conductive type is n type, the second conductive type is p type, and if the first conductive type is p type, the second conductive type is n type. Hereinafter, the case where the first conductive type is the n type and the second conductive type is the p type will be described exemplarily.

For the substrate 10, for example, a silicon carbide (SiC) substrate having an insulating property is used. Here, the “insulating” substrate means that the resistivity of the substrate is several kΩ · cm or more. There are several polymorphs (polymorphs of crystals) in SiC, but the case where a typical 4H SiC substrate is used as the substrate 10 will be described below.

The semiconductor device shown in FIG. 1 further includes a first main electrode 31 and a second main electrode 32 arranged so as to face the first main electrode 31 via the semiconductor layer 20. The first main electrode 31 is arranged on the main surface of the substrate 10 outside the groove 100, and the second main electrode 32 is arranged on the bottom surface of the groove 100. The second drift region 22 is electrically connected to the first main electrode 31. As a result, an appropriate potential difference is generated between the first drift region 21 and the second drift region 22 in the off state, and the first drift region 21 and the second drift region 22 are likely to be depleted.

Further, a first conductive type third drift region 23 is formed in the semiconductor layer 20 at a joint portion with the second main electrode 32 on the bottom surface of the groove 100. Although the electric field tends to concentrate on the corners of the groove 100, the concentration of the electric field is relaxed by the third drift region 23, and the withstand voltage of the semiconductor device is improved. The third drift region 23 may be formed as needed.

The first main electrode 31 is one end of the current path of the main current flowing through the semiconductor layer 20 in the on state. The second main electrode 32 is the other end of the current path. In the semiconductor device shown in FIG. 1, the first main electrode 31 is formed with an energy barrier between the first main electrode 31 and the first drift region 21, and the second main electrode 32 is ohmicly connected to the first drift region 21. ing. That is, the semiconductor device shown in FIG. 1 is a diode in which a main current flows between the first main electrode 31 and the second main electrode 32. Hereinafter, the first embodiment will be described with the first main electrode 31 as the anode electrode and the second main electrode 32 as the anode electrode.

Schottky between the anode electrode 31 and the first drift region 21 such as a metal such as nickel (Ni) material or platinum (Pt) material having a high work function, or a silicon film doped with a high concentration of p-type impurities. Use a material that forms a junction or pn junction. On the other hand, for the cathode electrode 32, a material having an ohmic connection with the first drift region 21, such as a metal having a low work function such as titanium (Ti) or a silicon film doped with a high concentration of n-type impurities, is used.

The basic operation of the semiconductor device shown in FIG. 1 will be described below.

In the on operation, the energy barrier between the anode electrode 31 and the first drift region 21 is lowered by applying a low voltage (forward voltage) to the cathode electrode 32 with the anode electrode 31 as a reference potential. Therefore, electrons flow from the first drift region 21 to the anode electrode 31, and a current (forward current) flows from the anode electrode 31 to the cathode electrode 32.

In the off operation, the energy barrier between the anode electrode 31 and the first drift region 21 is increased by applying a high voltage (reverse voltage) to the cathode electrode 32 with the anode electrode 31 as a reference potential. Therefore, electrons do not flow from the first drift region 21 to the anode electrode 31. At this time, the depletion layer spreads from the anode electrode 31 to the inside of the first drift region 21.

Further, as shown by an arrow in FIG. 2, the depletion layer 200 extends from the interface between the first drift region 21 and the second drift region 22. When the reverse voltage increases to a certain extent, both the first drift region 21 and the second drift region 22 are completely depleted (pinch-off state).

When the first drift region 21 and the second drift region 22 are in the pinch-off state, the electric field distribution of the SJ structure becomes a uniform rectangular distribution, and the maximum electric field applied to the semiconductor device is greatly reduced. As a result, the withstand voltage of the semiconductor device is improved.

In the semiconductor device shown in FIG. 1, the anode electrode 31 is arranged outside the groove 100, the cathode electrode 32 is arranged on the bottom surface of the groove 100, and the first drift region 21 and the second drift region 22 are arranged on the side surface of the groove 100. Is placed. Therefore, the distance between the anode electrode 31 and the cathode electrode 32 is extended without increasing the horizontal distance between the anode electrode 31 and the cathode electrode 32 from the main surface of the substrate 10 (hereinafter referred to as “horizontal distance”). be able to. Therefore, the maximum electric field applied to the semiconductor device can be lowered by widening the width of the depletion layer extending from the anode electrode 31 to the cathode electrode 32 in the off operation without increasing the chip area. As a result, the withstand voltage of the semiconductor device shown in FIG. 1 can be increased without increasing the on-resistance per unit chip area.

Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 3 to 9. The method for manufacturing a semiconductor device described below is an example, and can be realized by various other manufacturing methods including this modification.

First, a groove 100 is formed on the main surface of the substrate 10, which is a non-doped silicon carbide insulating semiconductor. In order to form the groove 100 by the etching method, the mask material 111 is formed on the main surface of the substrate 10 (see FIG. 3). A silicon oxide film can be used as the mask material 111, and a thermal CVD method or a plasma CVD method can be used as the deposition method. Next, the photoresist material is patterned on the mask material 111 (not shown). As a patterning method, a general photolithography technique is used. The mask material 111 is etched using the patterned photoresist material as a mask. As the etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching is used. Next, the photoresist material is removed with oxygen plasma, sulfuric acid, or the like. Using the mask material 111 thus formed as an etching mask, the substrate 10 is selectively etched by dry etching to form the groove 100 as shown in FIG.

Next, in the semiconductor layer 20 in contact with one side surface of the groove 100, the first conductive type first drift region 21 and the second conductive type second drift region 22 are alternately arranged along the longitudinal direction of the groove 100. Form so as to.

That is, as shown in FIG. 4, the first drift region 21 is formed on the upper surface of the substrate 10 and one side surface of the groove 100 by ion implantation. Diagonal ion injection is performed to form the first drift region 21 on the side surface of the groove 100. After that, as shown in FIG. 5, the mask material 112 covering the first drift region 21 is formed by using a photolithography technique in the same manner as the mask material 111. Then, using the mask material 112 as a mask, the second drift region 22 is selectively formed on the substrate 10 by ion implantation.

After that, as shown in FIG. 6, the mask material 113 is formed on the substrate 10 so that the region forming the third drift region 23 is exposed. Then, the third drift region 23 is formed on the substrate 10 by ion implantation using the mask material 113 as a mask.

In the ion implantation in the steps up to this point, for example, nitrogen (N) is used as the n-type impurity, and aluminum (Al) or boron (B) is used as the p-type impurity. By implanting ions while the temperature of the substrate 10 is heated to about 600 ° C., it is possible to suppress the occurrence of crystal defects in the ion-implanted region. Then, the ion-implanted impurities are activated by heat treatment. For example, heat treatment at about 1700 ° C. is performed in an argon atmosphere or a nitrogen atmosphere.

The impurity concentrations in the first drift region 21 and the third drift region 23 are preferably about ^{1E15 / cm 3 to} 1E19 / cm ^3. The impurity concentration in the second drift region 22 is preferably about ^{1E15 / cm 3 to} 1E / cm ^3.

By the way, in order to completely deplete the SJ structure in the off state and obtain a high withstand voltage, the ratio of the total amount of p-type impurities in the p-type drift region to the total amount of n-type impurities in the n-type drift region is 1. Must be set in the vicinity. Therefore, the concentration Nd of the n-type impurity in the first drift region 21, the concentration Na of the p-type impurity in the second drift region 22, the width Wn of the first drift region 21, and the width Wp of the second drift region 22 are the following equations. High withstand voltage can be obtained by satisfying (1):

Na × Wp = Nd × Wn ・ ・ ・ (1)

The width Wn and the width Wp are the widths in the direction in which the first drift region 21 and the second drift region 22 are repeatedly arranged.

Next, the anode electrode 31, which is one end of the current path of the main current flowing through the first drift region 21 in the depth direction of the groove 100 in the on state, faces the anode electrode 31 via the semiconductor layer 20. The cathode electrode 32, which is the other end of the current path, is formed. Therefore, a groove for arranging the anode electrode 31 and the cathode electrode 32 is formed at the end of the semiconductor layer 20. That is, as shown in FIG. 7, the mask material 114 is patterned so that the regions forming the anode electrode 31 and the cathode electrode 32 are exposed, and the end portion of the semiconductor layer 20 is etched by dry etching using the mask material 114 as a mask. Remove.

After removing the mask material 114, the photoresist material 121 is applied to the upper surfaces of the substrate 10 and the semiconductor layer 20. Then, the photoresist material 121 is patterned to expose the substrate 10 in the region forming the anode electrode 31 outside the groove 100. Then, as shown in FIG. 8, the anode electrode 31 is formed. For example, for the anode electrode 31, a metal such as a Ni material or a Pt material having a high work function and forming a Schottky junction with the first drift region 21 is used. An electron beam (EB) vapor deposition method, a sputtering method, or the like is used to form the anode electrode 31. Then, by lift-off to remove the photoresist material 121, unnecessary metal (not shown) formed on the upper surface of the photoresist material 121 is removed.

Next, as shown in FIG. 9, the photoresist material 122 is patterned to form the cathode electrode 32 on the bottom surface of the groove 100. For the cathode electrode 32, a metal such as a Ti material having a low work function and ohmic contact with the first drift region 21 is used. After that, the photoresist material 122 is removed for lift-off to remove an unnecessary metal film (not shown) formed on the upper surface of the photoresist material 122. As a result, the semiconductor device shown in FIG. 1 is completed.

In the above, an example in which the first drift region 21 and the second drift region 22 are formed by ion implantation into the substrate 10 has been described. However, the first drift region 21 and the second drift region 22 may be formed on the substrate 10 by epitaxial growth on the substrate 10. By forming the first drift region 21 and the second drift region 22 by ion implantation, the manufacturing cost can be reduced as compared with the case where the first drift region 21 and the second drift region 22 are formed by epitaxial growth. On the other hand, by forming by epitaxial growth, the first drift region 21 and the second drift region 22 can be formed thicker, and the effect of reducing the on-resistance per unit area can be obtained.

In the semiconductor device shown in FIG. 1, an SJ structure is formed by repeating the first drift region 21 and the second drift region 22 along the longitudinal direction of the groove 100. Therefore, unlike the case where different conductive type drift regions are arranged in the film thickness direction, it is necessary to increase the pressure resistance of the SJ structure represented by the equation (1) even at the corners where the side surfaces and the bottom surfaces of the groove 100 intersect. The conditions can be met. That is, the total amount of p-type impurities and the total amount of n-type impurities can be equalized. Therefore, the entire SJ structure is depleted by the depletion layer extending from the pn junction during reverse bias. Therefore, the electric fields applied from the second drift region 22 to the first drift region 21 in the off state in the direction perpendicular to the interface between the second drift region 22 and the first drift region 21 are equal throughout the SJ structure. As a result, the electric field relaxation effect can be uniformly obtained in the entire SJ structure.

As described above, in the off state where the main current is cut off in the current path, the first drift region 21 and the first drift region 21 and the first drift region 21 are formed by the depletion layer extending from the pn junction formed at the boundary between the first drift region 21 and the second drift region 22. 2 At least a part of the drift region 22 is depleted. Even if all of the first drift region 21 and the second drift region 22 are not depleted, a certain pressure resistance can be obtained even if a part of the first drift region 21 and the second drift region 22 are depleted.

In FIG. 1, in order to form the first drift region 21 and the second drift region 22 on the side surface of the groove 100, the anode electrode 31 is arranged on the main surface of the substrate 10 outside the groove 100, and the cathode electrode 32 is the groove 100. An example of being placed on the bottom surface of is shown. However, it goes without saying that the anode electrode 31 may be arranged on the bottom surface of the groove 100 and the cathode electrode 32 may be arranged on the bottom surface of the groove 100.

The second drift region 22 preferably extends to the bottom of the groove 100. When the first drift region 21 is formed on the side surface of the groove 100, electric field concentration occurs at the bottom of the groove 100 when a high voltage is applied in the off state. At this time, when the second drift region 22 extends to the position of the bottom of the groove 100, the electric field at the bottom of the groove 100 is relaxed by the depletion layer extending from the second drift region 22, and the withstand voltage of the semiconductor device is improved. can get.

(Second Embodiment)
As shown in FIG. 10, the semiconductor device according to the second embodiment of the present invention further includes a control electrode 33 between the first main electrode 31 and the second main electrode 32. The control electrode 33 is arranged between the first main electrode 31 and the second main electrode 32 in the vicinity of the current path flowing in the first drift region 21, and controls the main current flowing in the current path. That is, the semiconductor device shown in FIG. 10 is different from the semiconductor device shown in FIG. 1 in that it includes a control electrode 33 and operates as a transistor. In the semiconductor device shown in FIG. 10, the first main electrode 31 and the second main electrode 32 are ohmic-connected to the first drift region 21. Other configurations are the same as those of the first embodiment shown in FIG.

Hereinafter, the second embodiment will be described with the first main electrode 31 as the source electrode, the second main electrode 32 as the drain electrode, and the control electrode 33 as the gate electrode. As shown in FIG. 10, the source electrode 31 and the gate electrode 33 are arranged on the main surface of the substrate 10 outside the groove 100, and the drain electrode 32 is arranged on the bottom surface of the groove 100.

In the semiconductor device shown in FIG. 10, a high-concentration first conductive type is arranged so as to face the well region 24 with the second conductive type well region 24 and the first drift region 21 and the second drift region 22 interposed therebetween. The drain region 26 is arranged so as to extend in the longitudinal direction of the groove 100. The well region 24 connects to one end of the first drift region 21 outside the groove 100. The drain region 26 is connected to the drain electrode 32 at the bottom surface of the groove 100 and is connected to the other end of the first drift region 21. Further, a high-concentration first conductive type source region 25 is arranged between the well region 24 and the source electrode 31. The source region 25 is arranged for ohmic connection between the source electrode 31 and the semiconductor layer 20, and the drain region 26 is arranged for ohmic connection between the drain electrode 32 and the semiconductor layer 20. The second drift region 22 and the well region 24 are set to the same potential as the source electrode 31.

As shown in FIG. 10, the gate electrode 33 surrounded by the gate insulating film 40 is arranged so as to penetrate the well region 24 from the source region 25 to the region reaching the first drift region 21 and the second drift region 22. Has been done. Therefore, one end of the second drift region 22 is in contact with the gate insulating film 40, and the other end is in contact with the drain region 26.

In the semiconductor device shown in FIG. 10, a channel region is formed in the well region 24 in contact with the gate insulating film 40 during the ON operation. The basic operation of the semiconductor device shown in FIG. 1 will be described below.

In the on operation, the semiconductor device functions as a transistor by controlling the potential of the gate electrode 33 in a state where a positive potential is applied to the drain electrode 32 with reference to the potential of the source electrode 31. That is, by setting the voltage between the gate electrode 33 and the source electrode 31 to be equal to or higher than a predetermined threshold voltage, an inversion layer is formed in the channel region of the well region 24 on the side surface of the gate electrode 33. As a result, the semiconductor device is turned on, and the main current flows between the drain electrode 32 and the source electrode 31. In this way, the first drift region 21 is electrically connected to the first main electrode 31 via the inversion layer formed in the on state.

On the other hand, in the off operation, the voltage between the gate electrode 33 and the source electrode 31 is set to be equal to or lower than a predetermined threshold voltage. As a result, the inversion layer disappears and the main current is cut off.

In the off state, the depletion layer spreads from the pn junction between the well region 24 and the first drift region 21 toward the drain electrode 32, but at this time, the depletion layer also spreads from the interface between the first drift region 21 and the second drift region 22. Spreads. When the reverse voltage increases to a certain extent, both the first drift region 21 and the second drift region 22 are completely depleted (pinch-off state).

When the first drift region 21 and the second drift region 22 are in the pinch-off state, the electric field distribution of the SJ structure becomes a uniform rectangular distribution, and the maximum electric field applied to the semiconductor device is greatly reduced. As a result, the withstand voltage of the semiconductor device is improved. The second drift region 22 is electrically connected to the source electrode 31 via the well region 24 and the source region 25. Therefore, in the off state, an appropriate potential difference is generated between the first drift region 21 and the second drift region 22, and the first drift region 21 and the second drift region 22 are likely to be depleted.

Further, by extending the length of the first drift region 21 and the second drift region 22 along the current path, the maximum electric field is lowered as compared with the case where the same reverse voltage is applied without extending the length. do. As a result, the withstand voltage of the semiconductor device can be increased. In the semiconductor device shown in FIG. 10, since the first drift region 21 can be extended in the direction perpendicular to the main surface of the substrate 10, the chip area does not increase even if the first drift region 21 is extended. Therefore, it is possible to increase the withstand voltage without increasing the on-resistance per unit chip area.

By using a SiC substrate for the substrate 10, the insulating property of the substrate 10 can be increased and the thermal conductivity can be increased. Therefore, the back surface of the substrate 10 can be directly attached to the cooling mechanism to efficiently cool the semiconductor device. According to this structure, since the SiC substrate has a high thermal conductivity, heat generated by the main current can be efficiently dissipated when the semiconductor device is in the ON state. Since SiC is a wide bandgap semiconductor and has a small number of intrinsic carriers, it is easy to realize high insulation properties, and it is possible to realize a semiconductor device having a high withstand voltage.

Hereinafter, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. The method for manufacturing a semiconductor device described below is an example, and can be realized by various other manufacturing methods including this modification.

A groove 100 is formed in the substrate 10 and a first drift region 21 and a second drift region 22 are formed in the substrate 10 in the same manner as in the method described with reference to FIGS. 3 to 5 in the first embodiment. That is, the semiconductor layer 20 in contact with one side surface of the groove 100 is formed so that the first drift region 21 and the second drift region 22 are alternately arranged along the longitudinal direction of the groove 100.

Next, as shown in FIG. 11, the mask material 115 formed on the substrate 10 is patterned so that the region forming the well region 24 is exposed. Then, the well region 24 is formed by ion implantation using the mask material 115 as a mask. As a method of patterning the mask material 115, a general photolithography technique can be used. That is, the mask material 115 is etched using the photoresist material (not shown) patterned by the photolithography technique as a mask. As the etching method, dry etching such as wet etching using hydrofluoric acid or reactive ion etching is used.

After removing the mask material 115, the mask material 116 patterned so that the region forming the source region 25 and the drain region 26 is exposed is used as a mask, and the source region 25 and the drain region 26 are implanted by ion implantation as shown in FIG. To form.

In the ion implantation step up to this point, nitrogen can be used as the n-type impurity and aluminum or boron can be used as the p-type impurity, as in the first embodiment. Impurity concentration 1E15 / cm ³ ~1E19 / cm ³ about the first drift region 21, the impurity concentration of the second drift region 22 is approximately 1E15 / cm ³ ~1E / cm ³ are preferred. Then, the concentration Nd of the n-type impurity in the first drift region 21, the concentration Na of the p-type impurity in the second drift region 22, the width Wn of the first drift region 21, and the second drift region so as to satisfy the equation (1). The width Wp of 22 is set.

The impurity concentration in the well region 24 is preferably about ^{1E15 / cm 3 to} 1E19 / cm ^3. The impurity concentrations in the source region 25 and the drain region 26 are preferably about ^{1E18 / cm 3 to} 1E21 / cm ^3.

Next, as shown in FIG. 13, the mask material 117 formed on the substrate 10 is patterned so as to have a groove for forming the gate insulating film 40. Then, the gate groove 400 is formed as shown in FIG. 14 by etching with the mask material 117 as a mask. As the etching method, for example, dry etching such as reactive ion etching is used.

After that, the inner wall surface of the gate groove 400 is oxidized to form the gate insulating film 40. The gate insulating film 40 may be formed by either a thermal oxidation method or a deposition method. As an example, in the case of the thermal oxidation method, the substrate 10 is heated to a temperature of about 1100 ° C. in an oxygen atmosphere. After forming the gate insulating film 40, in order to reduce interface states at the interface between the well region 24 and the gate insulating film 40, go nitrogen, argon, annealing at about 1000 ° C. in an atmosphere such as N ₂ O May be good. Thermal oxidation in a straight NO or N ₂ O atmosphere is also possible. In that case, the temperature is preferably 1100 ° C to 1400 ° C. The thickness of the gate insulating film 40 is about several tens of nm.

Next, as shown in FIG. 15, the gate groove 400 is embedded to form the gate electrode 33. The material of the gate electrode 33 is generally a polysilicon film, and here, a case where the polysilicon film is used for the gate electrode 33 will be described. As a method for depositing the polysilicon film, a reduced pressure CVD method or the like can be used. Further, after the polysilicon film is deposited, it _{is annealed in phosphorus oxychloride POCl 3} at 950 ° C. to form a first conductive type polysilicon film, and the gate electrode 33 is made conductive. Next, the polysilicon of the gate electrode 33 is etched and flattened. The etching method may be isotropic etching or anisotropic selective etching. As a result of etching, the polysilicon film has a structure embedded inside the gate groove 400.

Next, the source electrode 31 and the drain electrode 32 are formed. That is, by patterning using a mask material (not shown), the region forming the source electrode 31 of the source region 25 and the region forming the drain electrode 32 of the drain region 26 are etched. After that, the newly formed photoresist material 123 is patterned so that the regions forming the source electrode 31 and the drain electrode 32 are exposed, and the source electrode 31 and the drain electrode 32 are formed as shown in FIG.

After that, the photoresist material 123 is removed for lift-off to remove an unnecessary metal film (not shown) formed on the upper surface of the photoresist material 123. As a result, the semiconductor device shown in FIG. 10 is completed.

<First modification>
In the semiconductor device according to the first modification of the second embodiment of the present invention shown in FIG. 17, the source electrode 31 and the drain electrode 32 are arranged outside the groove 100 with the groove 100 interposed therebetween. That is, it differs from the semiconductor device shown in FIG. 10 in that the drain electrode 32 is arranged outside the groove instead of the bottom surface of the groove 100. That is, the first drift region 21 and the second drift region 22 are continuously formed on the inner wall surface of the groove 100 from one side surface of the groove 100 to the other side surface through the bottom surface of the groove 100.

According to the semiconductor device shown in FIG. 17, the source electrode 31 and the drain electrode 32 are formed outside the groove 100 with the groove 100 interposed therebetween, so that the electrode is formed on the bottom surface of the groove 100 as compared with the case where the electrode is formed on the bottom surface of the groove 100. Electrodes can be formed by a simple process. Further, since the side surfaces on both sides of the groove 100 are used as drift regions, high withstand voltage can be obtained even if the horizontal distance between the source electrode 31 and the drain electrode 32 is short.

Although FIG. 17 shows an example in which the source electrode 31 and the drain electrode 32 are arranged outside the groove 100, both the anode electrode 31 and the cathode electrode 32 are also used in the semiconductor device according to the first embodiment. It may be arranged outside the groove 100. As a result, a high withstand voltage can be obtained even if the horizontal distance between the anode electrode 31 and the cathode electrode 32 is short.

<Second modification>
In the semiconductor device according to the second modification of the second embodiment of the present invention shown in FIG. 18, the second conductive type electric field relaxation region 27 is arranged at the corner of the bottom of the groove 100. It is different from the semiconductor device shown in 10. In the semiconductor device shown in FIG. 18, the first drift region 21 does not reach the bottom surface of the groove 100, and the end portion of the first drift region 21 is connected to the electric field relaxation region 27 in the vicinity of the bottom surface of the groove 100. ..

As described above, when the first drift region 21 and the second drift region 22 are in the pinch-off state, the maximum electric field is greatly reduced and the withstand voltage of the semiconductor device is improved. However, since the first drift region 21 is bent at the corner where the side surface and the bottom surface of the groove 100 intersect, the electric field may be concentrated on the corner and lead to dielectric breakdown.

FIG. 19 shows the calculation result of the electric field distribution when a voltage of 600 V is applied to the drain electrode 32 when the first drift region 21 is bent. As shown in FIG. 19, the corner portion P where the side surface and the bottom surface of the groove 100 intersect is a region where the electric field is concentrated, which is displayed in a dark color in the calculation result.

According to the semiconductor device shown in FIG. 18, by arranging the second conductive type electric field relaxation region 27 at the corner of the groove 100 where the electric field concentration occurs, the depletion layer is formed from the electric field relaxation region 27 to the first drift region 21. Spreads. Therefore, the effect of relaxing the electric field concentration at the corner of the groove 100 can be obtained.

<Third modification example>
In the semiconductor device according to the third modification of the second embodiment of the present invention shown in FIG. 20, the interlayer insulating film 50 is arranged on the upper surface of the first drift region 21, and the first drift passes through the interlayer insulating film 50. An electric field relaxation electrode 60 is arranged above the region 21 along the first drift region 21. As shown in FIGS. 20 and 21, the electric field relaxation electrode 60 is electrically connected to the source electrode 31. In addition, in order to make the drawing easy to understand, the interlayer insulating film 50 is shown only by the outline in FIG. 20.

As described above, since the first drift region 21 is bent at the corner of the groove 100, when a high voltage is applied to the drain electrode 32 in the off state, an electric field is generated at the corner of the first drift region 21. Concentrate and lead to dielectric breakdown. In the semiconductor device shown in FIG. 20, an electric field relaxation electrode 60 having the same potential as the source electrode 31 is arranged along the first drift region 21 via the interlayer insulating film 50. Therefore, the electric field relaxation electrode 60 functions as a field plate, and the electric field concentrated at the corner of the groove 100 is dispersed at the end of the electric field relaxation electrode 60. As a result, the peak of the electric field concentrated in the first drift region 21 is dispersed, and the maximum value of the peak of the electric field strength decreases. As a result, the withstand voltage of the semiconductor device can be improved.

<Fourth modification>
In the semiconductor device according to the fourth modification of the second embodiment of the present invention shown in FIG. 22, the source electrode 31 is arranged above the gate electrode 33 along the surface normal direction of the main surface of the substrate 10. ing. That is, the well region 24, the source region 25, and the source electrode 31 are sequentially arranged on the end faces of the first drift region 21 and the second drift region 22 along the surface normal direction of the main surface of the substrate 10. The gate electrode 33 is exposed on the side surface of the groove 100 perpendicular to the upper surface of the substrate 10.

In the semiconductor device shown in FIG. 22, the source electrode 31, the well region 24, and the gate electrode 33 are arranged so as to be perpendicular to the main surface of the substrate 10, so that the active region from the source electrode 31 to the gate electrode 33 is located. The area becomes smaller. Therefore, the effect of reducing the on-resistance per unit area can be obtained.

(Third Embodiment)
In the semiconductor device according to the third embodiment of the present invention, as shown in FIG. 23, a plurality of semiconductor elements having the same configuration as the semiconductor device according to the second embodiment are integrated on the same substrate 10. .. That is, in the semiconductor device shown in FIG. 23, the first semiconductor element 1 and the second semiconductor element 2 are formed on the insulating substrate 10.

As shown in FIG. 23, the first drift region 21 and the second drift region 22 alternately arranged along the longitudinal direction of the groove 100 are formed from one upper surface of the substrate 10 sandwiching the groove 100 to the bottom surface of the groove 100. It is formed over the other upper surface of the substrate 10 via.

Both the first semiconductor element 1 and the second semiconductor element 2 have a transistor structure having a source electrode 31, a drain electrode 32, and a gate electrode 33. As shown in FIG. 23, the drain electrode 32 of the first semiconductor element 1 and the source electrode 31 of the second semiconductor element 2 are also used.

The source electrode 31 and the gate electrode 33 of the first semiconductor element 1 are arranged outside the groove 100, and the drain electrode 32 is arranged on the bottom surface of the groove 100. On the other hand, the source electrode 31 and the gate electrode 33 of the second semiconductor element 2 are arranged on the bottom surface of the groove 100, and the drain electrode 32 is arranged outside the groove 100.

According to the semiconductor device having the first semiconductor element 1 and the second semiconductor element 2, for example, the half-bridge portion of the full bridge circuit used in the DC / DC converter shown in FIG. 24 can be integrated. That is, the first semiconductor element 1 is formed as a lower arm element connected between the N terminal and the U terminal, and the second semiconductor element is formed as an upper arm element connected between the U terminal and the P terminal.

In this case, the N terminal is arranged so as to connect to the source electrode 31 of the first semiconductor element 1. The U terminal is arranged so as to be in contact with the drain electrode 32 of the first semiconductor element 1 and the source electrode 31 of the second semiconductor element 2. Then, the P terminal is arranged so as to be in contact with the drain electrode 32 of the second semiconductor element 2.

According to the semiconductor device according to the third embodiment, by integrating a plurality of semiconductor elements on the same substrate 10, the effects such as reduction of wiring inductance and reduction of chip cost can be obtained. Others are substantially the same as those of the second embodiment, and duplicate description is omitted.

(Other embodiments)
As mentioned above, the invention has been described by embodiment, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure.

For example, although the example in which the SiC substrate is used for the substrate 10 has been described above, the substrate 10 is not limited to the SiC substrate, and the substrate 10 made of a semiconductor material having a wide bandgap may be used. Semiconductor materials with a wide bandgap include GaN, diamond, ZnO, AlGaN, and the like.

Further, although the example of using the first conductive type polysilicon film for the gate electrode 33 has been described, the second conductive type polysilicon film may be used. Further, another semiconductor material may be used for the gate electrode 33, or another conductive material such as a metal material may be used. For example, second conductive type polysilicon carbide, SiGe, Al and the like can be used as the material of the gate electrode 33.

Although an example of using a silicon oxide film for the gate insulating film 40 has been described, a silicon nitride film may be used for the gate insulating film 40. Alternatively, a laminate of a silicon oxide film and a silicon nitride film may be used for the gate insulating film 40. When a silicon nitride film is used for the gate insulating film 40, isotropic etching can be performed by cleaning with thermal phosphoric acid at 160 ° C.

Further, as shown in FIG. 25, it is preferable that the second drift region 22 is formed from the main surface of the substrate 10 to a position deeper than the first drift region 21. That is, the film thickness of the second drift region 22 is made thicker than the film thickness of the first drift region 21. Since the second drift region 22 is formed deeper than the first drift region 21, the distance between the end of the first main electrode 31 where the electric field is normally concentrated and the second drift region 22 is shortened. By shortening this distance, the depletion layer extending from the second drift region 22 relaxes the electric field concentration at the end of the first main electrode 31.

Further, by using an insulating substrate for the substrate 10, an electric field concentrated on the first main electrode 31 when the semiconductor device is off is arranged on the side surface of the groove 100 via the substrate 10 for a second drift. The region 22 provides a mitigating effect. Further, it becomes possible to form electrically separated elements on the same semiconductor chip.

As described above, it goes without saying that the present invention includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

The semiconductor device and the method for manufacturing a semiconductor device of the present invention can be used in the electronic equipment industry including a manufacturing industry for manufacturing a semiconductor device having an SJ structure.

10 ... Substrate 20 ... Semiconductor layer 21 ... First drift region 22 ... Second drift region 23 ... Third drift region 24 ... Well region 25 ... Source region 26 ... Drain region 27 ... Electric field relaxation region 31 ... First main electrode 32 ... Second main electrode 33 ... Control electrode 40 ... Gate insulating film 60 ... Electric field relaxation electrode

Claims (17)

With the board
The first drift region and the second conductive of the first conductive type are formed in contact with one side surface of the groove formed on the main surface of the substrate and along the direction in which the groove extends in parallel with the main surface of the substrate. A semiconductor layer in which the second drift region of the mold is alternately arranged, and
In the ON state, the first main electrode, which is one end of the current path of the main current flowing through the semiconductor layer in the direction perpendicular to the main surface of the substrate,
A semiconductor device comprising a second main electrode, which is the other end of the current path, arranged so as to face the first main electrode via the semiconductor layer. The semiconductor device according to claim 1, wherein the substrate has an insulating property. The semiconductor device according to claim 1 or 2, wherein the second drift region is electrically connected to the first main electrode. In the off state where the main current is cut off in the current path, the first drift region and the second drift region are formed by the depletion layer extending from the pn junction formed at the boundary between the first drift region and the second drift region. The semiconductor device according to any one of claims 1 to 3, wherein at least a part of the above is depleted. The semiconductor device according to any one of claims 1 to 4, wherein the first drift region is electrically connected to the first main electrode in the on state. Any one of claims 1 to 5, wherein one of the first main electrode and the second main electrode is arranged outside the groove, and the other is arranged on the bottom surface of the groove. The semiconductor device described in 1. The semiconductor device according to any one of claims 1 to 5, wherein the first main electrode and the second main electrode are respectively arranged outside the groove with the groove in between. .. The invention according to any one of claims 1 to 7, further comprising a second conductive type electric field relaxation region connected to the end of the first drift region and arranged at a corner of the bottom of the groove. The semiconductor device described. An insulating film arranged on the upper surface of the first drift region and
An electric field relaxation electrode arranged above the first drift region via the insulating film along the first drift region and electrically connected to the first main electrode is further provided. The semiconductor device according to any one of claims 1 to 8. The semiconductor device according to any one of claims 1 to 9, wherein the second drift region extends to the bottom of the groove. The claim is characterized in that the film thickness of the second drift region is thicker than that of the first drift region, and the second drift region is formed from the main surface of the substrate to a position deeper than the first drift region. Item 2. The semiconductor device according to any one of Items 1 to 10. The first main electrode is formed with an energy barrier between the first main electrode and the first drift region.
The second main electrode is ohmic-connected to the first drift region.
The semiconductor device according to any one of claims 1 to 11, wherein the semiconductor device operates as a diode having the first main electrode as an anode electrode and the second main electrode as a cathode electrode. Further, a control electrode arranged between the first main electrode and the second main electrode is provided.
Claim 1 is characterized in that the first main electrode and the second main electrode are ohmicly connected to the first drift region and operate as a transistor that controls the main current flowing through the current path by the control electrode. The semiconductor device according to any one of items 11 to 11. The semiconductor device according to claim 13, wherein the first main electrode is arranged above the control electrode along the surface normal direction of the main surface of the substrate. The process of forming a groove on the main surface of the substrate and
In the semiconductor layer in contact with one side surface of the groove, the first conductive type first drift region and the second conductive type second drift region alternate along the direction in which the groove extends in parallel with the main surface of the substrate. And the process of forming so that it is arranged in
A step of forming a first main electrode which is one end of a current path of a main current flowing through the semiconductor layer in a direction perpendicular to the main surface of the substrate 10.
A method for manufacturing a semiconductor device, which comprises a step of forming a second main electrode which is the other end of the current path so as to face the first main electrode via the semiconductor layer. The method for manufacturing a semiconductor device according to claim 15, wherein the first drift region and the second drift region are formed by ion implantation into the substrate. The method for manufacturing a semiconductor device according to claim 15, wherein the first drift region and the second drift region are formed by epitaxial growth on the substrate.

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