JPH0671085B2 - Vertical field effect transistor - Google Patents
Vertical field effect transistorInfo
- Publication number
- JPH0671085B2 JPH0671085B2 JP21821087A JP21821087A JPH0671085B2 JP H0671085 B2 JPH0671085 B2 JP H0671085B2 JP 21821087 A JP21821087 A JP 21821087A JP 21821087 A JP21821087 A JP 21821087A JP H0671085 B2 JPH0671085 B2 JP H0671085B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- source
- effect transistor
- field effect
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005669 field effect Effects 0.000 title claims description 7
- 230000002457 bidirectional effect Effects 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、縦形電界効果トランジスタに関する。The present invention relates to a vertical field effect transistor.
最近の電界効果トランジスタ（以下FETと云う）の高電
圧応用の普及に伴い、縦形FETの入力サージ電圧に対す
る静電圧破壊耐量の向上が重要となってきた。With the recent spread of high-voltage applications of field-effect transistors (hereinafter referred to as FETs), it has become important to improve the withstand voltage breakdown capability of vertical FETs against input surge voltage.
第２図（ａ）〜（ｃ）は従来の縦形FETの製造方法を説
明するための工程順に示した半導体チップの断面斜視図
である。2A to 2C are cross-sectional perspective views of a semiconductor chip, which are shown in the order of steps for explaining a conventional method of manufacturing a vertical FET.
第２図（ａ）に示すように、n-形シリコンシリコン基板
11の表面の一部を電圧保護素子形成領域17とする。As shown in FIG. 2 (a), n - form silicon silicon substrate
A part of the surface of 11 is defined as a voltage protection element forming region 17.
第２図（ｂ）に示すように、シリコン基板11の表面にシ
リコン酸化膜13と多結晶シリコン膜14よりなる積層体15
を形成する。As shown in FIG. 2 (b), a laminated body 15 composed of a silicon oxide film 13 and a polycrystalline silicon film 14 is formed on the surface of the silicon substrate 11.
To form.
次に、第２図（ｃ）に示すように、多結晶シリコン膜14
に選択的にホウ素を拡散してｐ層16ｂを設けてから、ホ
トリソグラフィ技術で窓を開けリンを拡散してn+層1
6ａ,16ｃを形成する。Next, as shown in FIG. 2 (c), the polycrystalline silicon film 14
Then, boron is selectively diffused into the p-type layer 16b to form a p-layer 16b, and then a photolithography technique is used to open a window and diffuse phosphorus to form the n + layer 1.
6 a and 16 c are formed.
この双方向ダイオード16のn+層16ａ及び16ｃはそれぞれ
FET領域のゲート及びソースと電気的に接続されてい
る。The n + layers 16 a and 16 c of this bidirectional diode 16 are respectively
It is electrically connected to the gate and source of the FET region.
この双方向ダイオード16の動作抵抗Ｒはpn+接合長ｌに
比例する。The operating resistance R of this bidirectional diode 16 is proportional to pn + junction length l.
第３図は従来の縦形FETの一例の等価回路図である。FIG. 3 is an equivalent circuit diagram of an example of a conventional vertical FET.
双方向ダイオード16は動作抵抗Ｒと逆直列の定電圧ダイ
オード二個を有し、FETのゲートＧとソースＳ間に接続
され、ゲート・ソース間に印加されるサージ電圧を吸収
してFET静電破壊耐量ＶＢを向上している。The bidirectional diode 16 has two constant voltage diodes in anti-series with the operating resistor R, is connected between the gate G and the source S of the FET, absorbs the surge voltage applied between the gate and the source, and absorbs the FET electrostatic. The breaking resistance V B is improved.
第４図は双方向ダイオードの動作抵抗とFETの静電圧破
壊耐量の特性図である。FIG. 4 is a characteristic diagram of the operating resistance of the bidirectional diode and the electrostatic breakdown strength of the FET.
一般に、双方向ダイオード16の動作抵抗の値Ｒが大きい
と、サージ電圧吸収能力が低下するために、保護できる
FET静電圧破壊耐量ＶＢが小さくなる傾向にある。In general, when the value R of the operating resistance of the bidirectional diode 16 is large, the surge voltage absorbing ability is lowered, so that the bidirectional diode 16 can be protected.
The FET static voltage breakdown capability V B tends to decrease.
上述した従来の縦形電界効果トランジスタは、双方向ダ
イオードが平面の横方向に形成されており、接合部面積
が小さく、従って動作抵抗が大きいので、FET静電圧破
壊耐量が小さいという問題があった。In the conventional vertical field effect transistor described above, the bidirectional diode is formed in the horizontal direction of the plane, the junction area is small, and therefore the operating resistance is large, so that there is a problem that the FET static voltage breakdown resistance is small.
本発明の目的は、静電圧破壊耐量の大きい縦形電界効果
トランジスタを提供することにある。An object of the present invention is to provide a vertical field effect transistor having a large withstand voltage breakdown capability.
本発明の電界効果トランジスタは、 （Ａ） 半絶縁性基板の表面の一部にソース及びゲート
を有し、該ソース及びゲートと対応する前記半絶縁性基
板の裏面にドレインを有する縦形FET領域、 （Ｂ） 前記半絶縁性基板の他の表面に設けられた少な
くとも１つ溝部を有する電圧保護素子形成領域、 （Ｃ） 前記電圧保護素子形成領域の表面に形成された
絶縁膜と多結晶シリコン膜よりなる積層体、 （Ｄ） 前記多結晶シリコン膜の平面に前記溝部に交っ
て設けられた一導電形の半導体層を逆導電形の半導体層
が挾み、かつ前記逆導電形の半導体層の両端が前記ソー
ス及びゲートにそれぞれ電気的に接続する双方向ダイオ
ード、 を含んで構成されている。The field effect transistor of the present invention comprises: (A) a vertical FET region having a source and a gate on a part of the front surface of a semi-insulating substrate, and a drain on the back surface of the semi-insulating substrate corresponding to the source and the gate. (B) A voltage protection element formation region having at least one groove provided on the other surface of the semi-insulating substrate, (C) An insulating film and a polycrystalline silicon film formed on the surface of the voltage protection element formation region (D) A semiconductor layer of opposite conductivity type sandwiches a semiconductor layer of one conductivity type provided on the plane of the polycrystalline silicon film so as to intersect with the groove, and the semiconductor layer of opposite conductivity type. Both ends of the bidirectional diode are electrically connected to the source and the gate, respectively.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明の製造方法の一実施例を
説明するための工程順に示した半導体チップの断面斜視
図である。1 (a) to 1 (c) are cross-sectional perspective views of a semiconductor chip shown in the order of steps for explaining one embodiment of the manufacturing method of the present invention.
電圧保護素子形成領域７が複数の溝部２を有する点が異
る以外は、第２図（ａ）〜（ｃ）の製造工程と同様であ
る。The manufacturing process is the same as that in FIGS. 2A to 2C except that the voltage protection element forming region 7 has a plurality of groove portions 2.
第１図（ａ）に示すように、n-形シリコン基板１の表面
にRIE法で深さｄの溝部２を３本形成する。As shown in FIG. 1A, three groove portions 2 having a depth d are formed on the surface of the n − type silicon substrate 1 by the RIE method.
次に、第１図（ｂ）に示すように、表面にシリコン酸化
３と多結晶シリコン膜４よりなる積層体５を形成する。Next, as shown in FIG. 1B, a laminated body 5 composed of silicon oxide 3 and a polycrystalline silicon film 4 is formed on the surface.
最後に、第１図（ｃ）に示すように、従来と同じ方法
で、溝部２と接合部が交わる方向にn+pn+の双方向ダイ
オード６を形成する。Finally, as shown in FIG. 1C, the n + pn + bidirectional diode 6 is formed in the direction in which the groove 2 and the junction intersect with each other by the same method as in the conventional method.
この場合のpn+接合部の実効長Ｌは三つの溝部２の深さ
ｄの約６倍分だけ従来よりも長くなる。In this case, the effective length L of the pn + junction becomes longer than that of the conventional one by about 6 times the depth d of the three grooves 2.
従って、双方向ダイオードの動作抵抗ｒは、従来の約l/
（ｌ＋6d）まで小さくすることができ、第４図の特性図
に示すように、FET静電圧破壊耐量Ｖ′Ｂに向上でき
る。Therefore, the operating resistance r of the bidirectional diode is about 1 /
It can be reduced to (1 + 6d), and as shown in the characteristic diagram of FIG. 4, it is possible to improve the FET static voltage breakdown withstand voltage V ′ B.
以上説明したように本発明は、電圧保護素子形成領域に
少くとも一つの溝部を双方向ダイオードのpn接合部と交
って形成して動作抵抗を低減することにより、縦形電界
効果トランジスタの静電圧破壊耐量を向上させることが
できる効果がある。As described above, according to the present invention, at least one groove is formed in the voltage protection element formation region so as to intersect with the pn junction of the bidirectional diode to reduce the operating resistance. There is an effect that the breakdown resistance can be improved.
第１図（ａ）〜（ｃ）は本発明の製造方法の一実施例を
説明するための工程順に示した半導体チップの断面斜視
図、第２図（ａ）〜（ｃ）は従来の縦形FETの製造方法
を説明するための工程順に示した半導体チップの断面斜
視図、第３図は従来の縦形FETの一例の等価回路図、第
４図は双方向ダイオードの内部抵抗とFETの静電圧破壊
耐量の特性図である。 １……n-形シリコン基板、２……溝部、３……シリコン
酸化膜、４……多結晶シリコン膜、５……積層体、６…
…双方向ダイオード、6a,6c……n+層、6b……ｐ層、７
……電圧保護素子形成領域。1 (a) to 1 (c) are cross-sectional perspective views of a semiconductor chip shown in the order of steps for explaining an embodiment of the manufacturing method of the present invention, and FIGS. 2 (a) to 2 (c) are conventional vertical shapes. FIG. 3 is a cross-sectional perspective view of a semiconductor chip, which is shown in the order of steps for explaining a method for manufacturing a FET, FIG. 3 is an equivalent circuit diagram of an example of a conventional vertical FET, and FIG. FIG. 4 is a characteristic diagram of breakdown resistance. 1 ...... n - form a silicon substrate, 2 ...... groove 3 ...... silicon oxide film, 4 ...... polycrystalline silicon film, 5 ...... laminate 6 ...
… Bidirectional diode, 6a, 6c …… n + layer, 6b …… p layer, 7
...... Voltage protection element formation area.
Claims (1)
ス及びゲートを有し、該ソース及びゲートと対応する前
記半絶縁性基板の裏面にドレインを有する縦形FET領
域、 （Ｂ） 前記半絶縁性基板の他の表面に設けられた少な
くとも１つ溝部を有する電圧保護素子形成領域、 （Ｃ） 前記電圧保護素子形成領域の表面に形成された
絶縁膜と多結晶シリコン膜よりなる積層体、 （Ｄ） 前記多結晶シリコン膜の平面に前記溝部に交っ
て設けられた一導電形の半導体層を逆導電形の半導体層
が挾み、かつ前記逆導電形の半導体層の両端が前記ソー
ス及びゲートにそれぞれ電気的に接続する双方向ダイオ
ード、 を含むことを特徴とする縦形電界効果トランジスタ。1. A vertical FET region having a source and a gate on a part of a front surface of a semi-insulating substrate, and a drain on a back surface of the semi-insulating substrate corresponding to the source and the gate. A voltage protection element forming region having at least one groove portion provided on the other surface of the semi-insulating substrate; and (C) a stack of an insulating film and a polycrystalline silicon film formed on the surface of the voltage protection element forming region. (D) A semiconductor layer of opposite conductivity type sandwiches a semiconductor layer of one conductivity type provided on the plane of the polycrystalline silicon film so as to intersect with the groove portion, and both ends of the semiconductor layer of opposite conductivity type are A vertical field effect transistor, comprising: a bidirectional diode electrically connected to the source and the gate, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21821087A JPH0671085B2 (en) | 1987-08-31 | 1987-08-31 | Vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21821087A JPH0671085B2 (en) | 1987-08-31 | 1987-08-31 | Vertical field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6459958A JPS6459958A (en) | 1989-03-07 |
| JPH0671085B2 true JPH0671085B2 (en) | 1994-09-07 |
Family
ID=16716347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21821087A Expired - Fee Related JPH0671085B2 (en) | 1987-08-31 | 1987-08-31 | Vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671085B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002141507A (en) * | 2000-10-31 | 2002-05-17 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP5394141B2 (en) * | 2009-06-24 | 2014-01-22 | 株式会社東芝 | Semiconductor device |
| JP6930393B2 (en) * | 2017-11-24 | 2021-09-01 | 日産自動車株式会社 | Semiconductor devices and their manufacturing methods |
-
1987
- 1987-08-31 JP JP21821087A patent/JPH0671085B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6459958A (en) | 1989-03-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |