JP6967962B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device having a rewiring layer and a method for manufacturing the same.

For example, Patent Document 1 describes a silicon substrate, a terminal pad on the silicon substrate, a connection wiring connected to the terminal pad by rewiring of WL-CSP, and a mold resin (sealing resin) for sealing the connection wiring. Discloses a semiconductor device comprising a bump on a mold resin and a copper post formed in the mold resin that connects the connection wiring and the bump.

Japanese Unexamined Patent Publication No. 2007-134552

In a semiconductor device as described above, for example, a resin (underfill agent) is injected between the wiring board and the semiconductor device in a state where a bump as an external terminal is connected to a land such as a wiring board. Then, by thermosetting the underfill agent, the mounting of the semiconductor device is completed.
However, due to the resin stress and thermal history due to the underfill agent at the time of mounting, stress may be applied between the rewiring layer (connection wiring) and the mold resin in the semiconductor device. Therefore, it is preferable that the adhesion of the mold resin to the rewiring layer is relatively high.

Therefore, one embodiment of the present invention provides a semiconductor device capable of improving the adhesion of the sealing resin to the rewiring layer and a method for manufacturing the same.

A semiconductor device according to an embodiment of the present invention includes a semiconductor layer having a first surface on which a pad is formed, an insulating base layer formed so as to cover the first surface of the semiconductor layer, and a lower layer thereof. A rewiring layer formed on the ground layer and extending from the pad in a direction along the first surface of the semiconductor layer, a sealing resin formed so as to cover the rewiring layer, and the semiconductor of the sealing resin. An external terminal arranged on a first surface opposite to the surface on the layer side and electrically connected to the rewiring layer is included, and the underlayer is rewired from the edge of the rewiring layer. A recess extending in a direction along the first surface of the semiconductor layer is formed in the lower region of the layer, and a part of the sealing resin enters the lower region of the rewiring layer via the recess.

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes a step of forming an insulating base layer so as to cover the first surface of a semiconductor layer having a first surface on which a pad is formed, and the semiconductor. By forming a rewiring layer extending from the pad along the first surface of the layer and isotropically removing the base layer exposed from the rewiring layer, the base layer is covered with the base layer. forming a recess extending from the edge of the re-wiring layer in a direction along the first surface of the semiconductor layer to the lower region of the rewiring layer, so as to cover the redistribution layer, and through the recess The step of forming the sealing resin so as to enter the lower region of the rewiring layer and the first surface of the sealing resin opposite to the surface of the semiconductor layer side are electrically connected to the rewiring layer. It includes a step of forming an external terminal so as to be.

FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a bottom view of the semiconductor device of FIG. 1, which is partially seen through. FIG. 3A is an enlarged view of the portion surrounded by the alternate long and short dash line IIIA in FIG. FIG. 3B is an enlarged view of the portion surrounded by the alternate long and short dash line IIIB in FIG. FIG. 4 is a schematic cross-sectional view of the semiconductor device according to the embodiment of the present invention. FIG. 5 is an enlarged view of the portion surrounded by the alternate long and short dash line V in FIG. FIG. 6 is a drawing of an SEM image of a main part of the semiconductor device according to the embodiment of the present invention. FIG. 7 is an enlarged view of a main part of FIG. FIG. 8A is a diagram showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8B is a diagram showing the next step of FIG. 8A. FIG. 8C is a diagram showing the next step of FIG. 8B. FIG. 8D is a diagram showing the next step of FIG. 8C. FIG. 8E is a diagram showing the next step of FIG. 8D. FIG. 8F is a diagram showing the next step of FIG. 8E. FIG. 8G is a diagram showing the next step of FIG. 8F. FIG. 8H is a diagram showing the next step of FIG. 8G. FIG. 8I is a diagram showing the next step of FIG. 8H. FIG. 8J is a diagram showing the next step of FIG. 8I. FIG. 8K is a diagram showing the next step of FIG. 8J. FIG. 8L is a diagram showing the next step of FIG. 8K. FIG. 8M is a diagram showing the next step of FIG. 8L. FIG. 8N is a diagram showing the next step of FIG. 8M. FIG. 8O is a diagram showing the next step of FIG. 8N. FIG. 8P is a diagram showing the next step of FIG. 8O. FIG. 8Q is a diagram showing the next step of FIG. 8P. FIG. 9 is a schematic perspective view of the semiconductor device according to another embodiment of the present invention. FIG. 10 is a cross-sectional view showing a main part of the semiconductor device of FIG. FIG. 11 is a schematic cross-sectional view of the semiconductor device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic perspective view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 2 is a bottom view of the semiconductor device 1 of FIG. 1, which is partially seen through. More specifically, the sealing resin 5 is shown through. 3A and 3B are enlarged views of the portion surrounded by the two-dot chain lines IIIA and IIIB in FIG. 2, respectively. FIG. 4 is a schematic cross-sectional view of the semiconductor device 1 according to the embodiment of the present invention. Note that FIG. 4 schematically shows a configuration necessary for explaining this embodiment, and does not show a cross section of the semiconductor device 1 shown in FIGS. 1 and 2 at a specific position. FIG. 5 is an enlarged view of the portion surrounded by the alternate long and short dash line V in FIG. FIG. 6 is a drawing of an SEM image of a main part of the semiconductor device 1 according to the embodiment of the present invention. FIG. 7 is an enlarged view of a main part of FIG. Although the structures of FIGS. 6 and 7 do not completely match the structures shown in FIGS. 1 to 5, they are common in that they have the features of the present invention.

The semiconductor device 1 is a semiconductor device to which WL-CSP (Wafer Level Chip Size Package) is applied as a package format. The size of the semiconductor device 1 may be, for example, a length L = 0.3 mm to 10 mm, a width W = 0.3 mm to 10 mm, and a height H = 0.1 mm to 2 mm.
The semiconductor device 1 includes a semiconductor layer 2, a base layer 3, a rewiring layer 4, a sealing resin 5, and an external terminal 7.

As the semiconductor layer 2, for example, various semiconductor materials such as a Si substrate and a SiC substrate can be applied. The semiconductor layer 2 is formed, for example, in the shape of a square plate having a thickness of 50 μm to 1000 μm, and has a first surface 8, four second surfaces 9 extending from each of the four sides of the first surface 8, and a first surface. It has a third surface 10 on the opposite side of the surface 8. In other words, the first surface 8 may be referred to as the front surface of the semiconductor layer 2, the second surface 9 may be referred to as the side surface of the semiconductor layer 2, and the third surface 10 may be referred to as the back surface of the semiconductor layer 2.

In this embodiment, since the WL-CSP is applied to the semiconductor device 1, the second surface 9 which is the side surface of the semiconductor layer 2 is exposed as the package end surface. On the other hand, the protective layer 11 is formed on the third surface 10 which is the back surface of the semiconductor layer 2.
The protective layer 11 may cover the entire surface of the third surface 10 of the semiconductor layer 2 as in this embodiment, or may cover a part of the third surface 10 so as to selectively expose it. .. As the protective layer 11, for example, an insulating material such as an epoxy resin can be applied. The thickness of the protective layer 11 is, for example, 5 μm to 100 μm.

The element 12 is formed on the first surface 8 of the semiconductor layer 2. The element 12 may include, for example, an active element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) or a diode, and a passive element such as a resistor or a capacitor.
Further, an insulating layer 13 is formed on the first surface 8 of the semiconductor layer 2 so as to cover the element 12. The insulating layer 13 may cover the entire surface of the first surface 8 of the semiconductor layer 2 as in this embodiment, or may cover a part of the first surface 8 so as to selectively expose it. ..

The insulating layer 13 may be formed as a single layer structure or a multilayer structure on the first surface 8 of the semiconductor layer 2. When the insulating layer 13 having a multilayer structure is applied, the insulating layer 13 is configured as a multilayer wiring structure by providing wiring electrically connected to the element 12 between the insulating layers 13 adjacent to each other in the stacking direction. May be good.
Further, as the insulating layer 13, for example, _{an insulating material such as silicon oxide (SiO 2} ) or silicon nitride (SiN) can be applied.

A wiring 14 electrically connected to the element 12 is formed on the insulating layer 13. As the wiring 14, for example, wiring (Al wiring or the like) made of a material different from that of the rewiring layer 4 can be applied.
A surface protective layer 15 is formed so as to cover the wiring 14. As the surface protective layer 15, for example, _{an insulating material such as silicon oxide (SiO 2} ) or silicon nitride (SiN) can be applied.

The surface protective layer 15 is formed with a square pad opening 16 that exposes a part of the wiring 14 as a pad 17. In this embodiment, a plurality of pads 17 exposed from the pad openings 16 are formed.
As shown in FIG. 2, a large number of the plurality of pads 17 are provided on the first surface 8 of the semiconductor layer 2, and may be arranged regularly or irregularly. .. For example, as in the first pad group 18 of FIG. 2, a plurality of pads 17 may be regularly arranged linearly at equal intervals from each other, or as in the second pad group 19, a plurality of pads 17 may be arranged in a straight line. The pads 17 may be regularly arranged so as to bend at equal intervals from each other. Further, as in the third pad group 20 of FIG. 2, a plurality of pads 17 may be irregularly arranged at different intervals from each other.

The base layer 3 is formed so as to cover the surface protective layer 15. As the base layer 3, for example, a resin material such as a polyimide resin can be applied. The thickness of the base layer 3 is 3 μm to 20 μm.
As shown in FIG. 5, the base layer 3 selectively covers the peripheral edge portion of the pad opening 16 so as to secure the exposure of the pad 17. That is, a part of the base layer 3 enters the pad opening 16 and covers the side surface of the pad opening 16.

The rewiring layer 4 is formed from the pad 17 on the base layer 3 along the first surface 8 of the semiconductor layer 2. The rewiring layer 4 has various shapes as a planar shape (bottom shape). For example, as shown in FIG. 2, the rewiring layer 4 has a first rewiring layer 21 connected to one of the plurality of pads 17, and a second rewiring layer commonly connected to the plurality of pads 17. The wiring layer 22 may be included.

With reference to FIGS. 2 and 3A, in this embodiment, the first rewiring layer 21 is located in the area directly above the pad 17 so as to cover the pad 17 and is connected to the pad 17 via the pad opening 16. The first contact portion 23, the first land portion 24 arranged in the region directly below the external terminal 7, which is a region separated from the region directly above the pad 17 in the direction along the first surface 8, and the first contact portion 23. Includes a first wiring portion 25 extending from the surface to the first land portion 24 along the first surface 8 of the semiconductor layer 2.

In this embodiment, one external terminal 7 is electrically connected to the first rewiring layer 21, so that one pad 17 and one external terminal 7 are electrically connected one-to-one. There is. Each pad 17 may be arranged adjacent to the corresponding external terminal 7, as shown in FIG. 3A. Further, as shown in FIG. 2 (excluding the pattern of FIG. 3A), each pad 17 sandwiches another external terminal 7 electrically separated from the pad 17 between the pad 17 and the corresponding external terminal 7. , May be located apart. When the pads 17 corresponding to each other and the external terminal 7 are separated from each other, the first wiring portion 25 may extend so as to pass through a region between other adjacent external terminals 7.

Further, for example, as shown in FIG. 3A, the first contact portion 23 may have a rectangular shape larger than the pad 17 in a plan view (bottom view). The first land portion 24 may have a polygonal shape larger than that of the external terminal 7 in a plan view (bottom view). The first wiring portion 25 may be linear in a plan view (bottom view).
On the other hand, with reference to FIGS. 2 and 3B, in this embodiment, the second rewiring layer 22 is arranged in a region directly above the pad 17 so as to collectively cover the plurality of pads 17, and is arranged via the pad opening 16. The second contact portion 26 connected to the plurality of pads 17 and the second land located in the region directly below the external terminal 7 in the region separated from the region directly above the pads 17 in the direction along the first surface 8. A portion 27 and a second wiring portion 28 extending from the second contact portion 26 to the second land portion 27 along the first surface 8 of the semiconductor layer 2 are included.

In this embodiment, as shown in FIG. 3B, the plurality of pads 17 and the plurality of external terminals 7 are collectively connected to the second rewiring layer 22 by electrically connecting the plurality of external terminals 7. Is electrically connected.
When a plurality of external terminals 7 are electrically connected to the second rewiring layer 22, the second land portion 27 directly under one external terminal 7 and the second land portion 27 directly under another external terminal 7 are connected. May be connected by a connecting portion 29 having a width narrower than those of the second land portion 27. Further, the plurality of external terminals 7 electrically connected to one second rewiring layer 22 may be positioned adjacent to each other in the external terminals 7 arranged in a matrix pattern.

On the other hand, as shown in FIG. 2, one external terminal 7 may be electrically connected to the second rewiring layer 22 electrically connected to the plurality of pads 17.
Further, as shown in FIG. 3B, for example, with respect to the second rewiring layer 22, the second contact portion 26, the second land portion 27, and the second wiring portion 28 have different shapes in a plan view (bottom view). However, it may have a polygonal shape as a whole.

Next, the cross-sectional shape of the rewiring layer 4 will be described with reference to FIGS. 4 and 5. This cross-sectional shape has a configuration common to the first rewiring layer 21 and the second rewiring layer 22, and the first rewiring layer 21 and the second rewiring layer 22 are distinguished for the sake of clarity in the drawings. I will explain without.
First, as shown in FIG. 4, the rewiring layer 4 is formed on the first layer 30 and the first layer 30 in which one surface and the other surface on the opposite side are formed along the inner surface of the pad opening 16. The second layer 31 is partially embedded in the pad opening 16. The first layer 30 is arranged below the external terminal 7 (solder terminal) and is for electrically connecting the external terminal 7 to the pad 17, and may be referred to as, for example, UBM (Under Bump Metal). .. Further, the second layer 31 may be referred to as a plating layer based on the method (described later) for forming on the first layer 30.

As shown in FIG. 5, the first layer 30 further includes a lower layer 32 on the side close to the pad 17, and an upper layer 33 on the lower layer 32 made of a conductive material different from the lower layer 32, and the lower layer 32 is the upper layer 33. It has an edge 35 that recedes to the lower region of the upper layer 33 with respect to the edge 34 of the above layer 33.
Further, as the material of the rewiring layer 4, for example, the lower layer 32 and the upper layer 33 of the first layer 30 are made of different materials from each other, and the second layer 31 is made of the same material as the upper layer 33 of the first layer 30. You may. More specifically, the lower layer 32 of the first layer 30 may be made of Ti, the upper layer 33 of the first layer 30 may be made of Cu, and the second layer 31 may be made of Cu. In this case, since the upper layer 33 and the second layer 31 of the first layer 30 are both made of Cu, these interfaces do not have to be clearly formed as shown in FIG. That is, the upper layer 33 of the first layer 30 and the second layer 31 may be integrated in the middle of manufacturing the semiconductor device 1. Further, the thickness (height) of the rewiring layer 4 may be 5 μm to 15 μm.

Then, in this semiconductor device 1, a recess 6 is formed in the base layer 3. For example, as shown in FIG. 5, the recess 6 is formed in a portion of the base layer 3 exposed from the rewiring layer 4, and is a surface (for example, a lower surface) on the first surface 8 side of the semiconductor layer 2 of the rewiring layer 4. It is formed so as to have a bottom surface 43 closer to the first surface 8 of the semiconductor layer 2 than 42.
As shown in FIGS. 3A and 3B, the recess 6 is formed on the outer side of each rewiring layer 4, and is exposed from the rewiring layer 4 in a plan view. In the embodiment, the concealing portion 61 is formed so as to extend from the edge 34) to the lower region of the rewiring layer 4 in the direction along the first surface 8 of the semiconductor layer 2 and is covered and hidden by the rewiring layer 4 in a plan view. including.

As shown in FIG. 7, the bottom surface 43 of the exposed portion 60 has a roughened uneven structure 62.
As shown by the broken line in FIGS. 3A and 3B, the concealing portion 61 is formed in the lower region of the rewiring layer 4 continuously around the entire peripheral edge of each rewiring layer 4. That is, the concealing portion 61 is independently formed in each rewiring layer 4 and has the same contour as the rewiring layer 4 in a plan view. Further, as shown in FIGS. 5 to 7, each concealing portion 61 has a curved surface 63 that is curved so as to bulge to the first surface 8 of the semiconductor layer 2. In addition, in FIG. 7, the insulating layer 13 is shown as a multi-layer wiring structure including a plurality of laminated wiring layers 64 and vias 65 connecting these wiring layers 64.

Further, in this embodiment, as shown in FIG. 4, the recess 6 is formed in the entire portion of the base layer 3 exposed from the rewiring layer 4, and is formed so as to straddle between the adjacent rewiring layers 4. Has been done. That is, the concealment portion 61 of one rewiring layer 4 (for example, the rewiring layer 4 on the left side of the paper in FIG. 4) and another rewiring layer 4 (for example, the rewiring layer 4 on the right side of the paper in FIG. 4) are concealed. The portion 61 is continuous with the common exposed portion 60.

The sealing resin 5 is formed on the first surface 8 side of the semiconductor layer 2 so as to cover the rewiring layer 4. The sealing resin 5 is formed in the shape of a square plate having a thickness of, for example, 10 μm to 200 μm, and has a first surface 36 on the side opposite to the surface on the semiconductor layer 2 side and four sides of the first surface 36, respectively. It has four second surfaces 37 extending from. In other words, the first surface 36 may be referred to as the surface of the sealing resin 5, and the second surface 37 may be referred to as the side surface of the sealing resin 5.

In this embodiment, since the WL-CSP is applied to the semiconductor device 1, as shown in FIG. 1, the second surface 37, which is the side surface of the sealing resin 5, is exposed as the package end surface. The second surface 37 of the sealing resin 5 is formed on the same plane as the second surface 9 of the semiconductor layer 2. Further, the first surface 36 of the sealing resin 5 is a surface on which the external terminal 7 is arranged in the semiconductor device 1, and is exposed as a mounting surface of the package.

Further, as the sealing resin 5, various resins can be applied, and for example, an epoxy resin can be applied. Further, as shown in FIGS. 5 and 7, the sealing resin 5 enters the concealing portion 61 of the recess 6 of the base layer 3 from the end edge 34 of the rewiring layer 4 to the lower region of the rewiring layer 4. It has a first portion 66 that protrudes and is sandwiched between the rewiring layer 4 and the base layer 3.
An external terminal 7 is arranged on the first surface 36 of the sealing resin 5. As shown in FIG. 2, the external terminals 7 are arranged in a matrix pattern in a plan view (bottom view). In this embodiment, they are arranged in a 10 × 10 pattern. Further, as the material of the external terminal 7, for example, solder, Au / Ni, or the like can be applied, and in this embodiment, the external terminal 7 is composed of a spherical solder terminal (solder bump).

In this embodiment, each external terminal 7 is electrically connected to the rewiring layer 4 via the intermediate conductive material 39.
The intermediate conductive material 39 is provided so as to penetrate the sealing resin 5 in the thickness direction so as to reach the rewiring layer 4 from the first surface 36 of the sealing resin 5. The intermediate conductive material 39 is formed, for example, in a columnar shape (cylindrical column) extending vertically from the rewiring layer 4 (first land portion 24 and second land portion 27), and is referred to as a post based on its morphology. May be good.

The thickness (height) of the intermediate conductive material 39 may be thicker than the thickness of the rewiring layer 4, for example, 90 μm to 110 μm. Each of the external terminals 7 is joined to the end surface 40 of the intermediate conductive material 39 exposed on the first surface 36 of the sealing resin 5.
In this embodiment, as shown in FIGS. 4 and 5, a recess 45 formed by a step formed on the second surface 9 of the semiconductor layer 2 is formed on the first surface 8 side of the semiconductor layer 2. The recess 45 is formed over the entire outer circumference of the semiconductor layer 2.

The recess 45 is formed from the surface of the base layer 3 opposite to the semiconductor layer 2 side toward the semiconductor layer 2. The recess 45 is formed so as to straddle the base layer 3 and the semiconductor layer 2, and is formed at a first wall surface 46 inclined with respect to the second surface 9 of the semiconductor layer 2 and a second end portion of the first wall surface 46 on the semiconductor layer 2 side. It has a second wall surface 47 which is formed in series with one wall surface 46 and is inclined at an angle different from that of the first wall surface 46. The first wall surface 46 and the second wall surface 47 intersect at an angle exceeding 90 °, for example.

Then, the sealing resin 5 enters the recess 45, and the second surface 37 of the portion 48 of the sealing resin 5 that has entered the recess 45 is exposed as the package end surface as shown in FIG. The second surface 37 of the portion 48 of the sealing resin 5 is formed on the same plane as the second surface 9 of the semiconductor layer 2, and the package end surface is sealed with the second surface 9 of the semiconductor layer 2 over the entire circumference thereof. A boundary 49 with the second surface 37 of the stop resin 5 is formed.

8A to 8Q are diagrams showing a part of the manufacturing method of the semiconductor device 1 according to the embodiment of the present invention in the order of processes.
In order to manufacture the semiconductor device 1, for example, a wafer-shaped semiconductor layer 2 (for example, a thickness of 200 μm to 1000 μm) is prepared, and the element 12 is formed on the semiconductor layer 2. After the element 12, the insulating layer 13 covering the element 12 is formed, and the wiring 14 is formed on the insulating layer 13.

Next, a surface protective layer 15 is formed on the insulating layer 13 so as to cover the wiring 14, a pad opening 16 is formed by patterning the surface protective layer 15, and a part of the wiring 14 is exposed as a pad 17. ..
Next, for example, the base layer 3 is formed on the surface protective layer 15 by a spin coating method, a spray coating method, or the like. After that, by patterning the base layer 3, the pad 17 covered with the base layer 3 is exposed. The base layer 3 remains in the pad opening 16 in a state of covering the side surface of the pad opening 16.

Next, as shown in FIG. 8B, for example, by sputtering, the first layer 30 of the rewiring layer 4 is formed on the base layer 3. Although not shown in FIG. 8B, the first layer 30 may be formed by laminating the lower layer 32 and the upper layer 33 (see FIG. 5) in this order.
Next, as shown in FIG. 8C, a mask material such as a photoresist is applied onto the first layer 30, and the mask material is patterned to form a mask 51. The mask 51 has an opening 52 having the same pattern as the pattern of the rewiring layer 4.

Next, as shown in FIG. 8D, for example, by a plating method, the second layer 31 of the rewiring layer 4 grows from the portion of the first layer 30 exposed from the opening 52 of the mask 51. As a result, the rewiring layer 4 composed of the first layer 30 and the second layer 31 is formed. At this stage, the first layer 30 in contact with each second layer 31 is connected to each other via a portion covered with the mask 51 (a portion below the mask 51).

Next, as shown in FIG. 8E, the mask 51 is removed.
Next, as shown in FIG. 8F, a mask 53 is formed on the rewiring layer 4 by applying (laminating) a mask material such as a dry film.
Next, as shown in FIG. 8G, by patterning the mask 53, an opening 54 having the same pattern as that of the intermediate conductive material 39 is formed in the mask 53.

Next, as shown in FIG. 8H, for example, by a plating method, the intermediate conductive material 39 grows from the portion of the rewiring layer 4 (second layer 31) exposed from the opening 54 of the mask 53. As a result, the intermediate conductive material 39 extending vertically from the rewiring layer 4 is formed.
Next, as shown in FIG. 8I, the mask 53 is removed.
Next, as shown in FIG. 8J, for example, a portion of the first layer 30 of the rewiring layer 4 exposed from the second layer 31 is removed by wet etching. As a result, the base layer 3 is exposed between the adjacent rewiring layers 4. At this time, since the lower layer 32 (for example, Ti) of the first layer 30 is made of a different material from the second layer 31 and the intermediate conductive material 39 (for example, Cu), after the upper layer 33 of the first layer 30 is removed, The lower layer 32 can be selectively removed. Further, the lower layer 32 may be overetched in order to prevent a short circuit between the adjacent rewiring layers 4, and by this over etching, the edge 35 of the lower layer 32 becomes the end of the upper layer 33, as shown in FIG. It may recede to the lower region of the upper layer 33 with respect to the edge 34.

Next, as shown in FIG. 8K, for example, a cutter such as a dicing blade is inserted from the first surface 8 side of the semiconductor layer 2 to the middle portion of the semiconductor layer 2 in the thickness direction, so that the base layer 3 to the semiconductor layer 2 are inserted. A groove 55 is formed that reaches the middle portion in the thickness direction of the (half cut). At this time, the tip shape of the cutter may be selected so that the groove 55 has the first wall surface 46 and the second wall surface 47 having different inclination angles as shown in FIG. The groove 55 is partitioned by a first wall surface 46 and a second wall surface 47 facing each other, and a tip portion 56 formed by intersecting the second wall surfaces 47 is formed at the bottom thereof.

Next, as shown in FIG. 8L, the base layer 3 exposed from the rewiring layer 4 is isotropically etched, for example, by an ashing process. As a result, the recess 6 having the above-mentioned shape is formed.
Next, as shown in FIG. 8M, the sealing resin 5 is formed so as to cover the rewiring layer 4. The sealing resin 5 is formed to have a thickness that completely hides the intermediate conductive material 39. At this time, the sealing resin 5 also enters the concealing portion 61 and the groove 55 of the recess 6.

Next, as shown in FIG. 8N, the sealing resin 5 is thinned from the first surface 36 side of the sealing resin 5, for example, by grinding, polishing, or the like. This thinning continues until the end face 40 of the intermediate conductive material 39 is exposed. As a result, the end surface 40 of the intermediate conductive material 39 is exposed from the first surface 36 of the sealing resin 5.
Next, as shown in FIG. 8O, the semiconductor layer 2 is thinned from the third surface 10 side by, for example, grinding, polishing, or the like. As a result, the thickness of the semiconductor layer 2 becomes, for example, 50 μm to 1000 μm. After that, for example, the protective layer 11 is formed by applying the resin material of the protective layer 11 to the third surface 10 of the semiconductor layer 2 by a spin coating method, a spray coating method, or the like.

Next, as shown in FIG. 8P, the external terminal 7 (for example, a solder bump) is bonded to the end face 40 of the intermediate conductive material 39 exposed from the sealing resin 5, and the reflow treatment is performed at a temperature of, for example, 180 ° C to 270 ° C. Is done.
Next, as shown in FIG. 8Q, the wafer-shaped semiconductor layer 2 is cut into each semiconductor device 1 (chip) by, for example, a cutter having a width narrower than that of the cutter when the groove 55 is formed. At this time, the sealing resin 5 remaining in the groove 55 is exposed as the side surface of the package of the semiconductor device 1. Through the above steps, the above-mentioned semiconductor device 1 can be obtained.

As described above, according to the semiconductor device 1, the recess 6 is formed in the base layer 3, and a part of the sealing resin 5 (first portion 66) is formed in the lower region of the rewiring layer 4 through the recess 6. It's getting in. Therefore, even if a stress is applied between the rewiring layer 4 and the sealing resin 5 due to the resin stress due to the underfill agent or the thermal history at the time of mounting the semiconductor device 1, in the direction along the first surface 8 of the semiconductor layer 2. The contact surface between the sealing resin 5 and the base layer 3 is increased, and the adhesion of the sealing resin 5 can be improved, so that the influence of the stress can be suppressed. Further, since the uneven structure 62 is formed on the exposed portion 60 of the base layer 3, it is possible to suppress the influence of stress in the direction along the first surface 8 of the semiconductor layer 2.

On the other hand, in the direction intersecting the first surface 8 of the semiconductor layer 2, the adhesion of the sealing resin 5 is improved by the anchor effect of the first portion 66 of the sealing resin 5 that has entered the lower region of the rewiring layer 4. To let. As a result, the influence of stress in the direction intersecting the first surface 8 of the semiconductor layer 2 can be suppressed.
Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.

For example, in the above-described embodiment, the recess 45 is formed on the first surface 8 side of the semiconductor layer 2, but the recess 45 may not be formed as shown in FIGS. 9 and 10, for example. In this case, in addition to the semiconductor layer 2 and the sealing resin 5, the base layer 3, the surface protective layer 15, and the insulating layer 13 may be exposed as the package side surface of the semiconductor device 1. In such a form, for example, when the wafer-shaped semiconductor layer 2 is cut in the process of FIG. 8Q, the wafer-shaped semiconductor layer 2 is formed by a cutter having a wider width than the cutter when the groove 55 is formed. It may be separated into the semiconductor device 1 (chip).

Further, in the above-described embodiment, the rewiring layer 4 and the external terminal 7 are connected via the intermediate conductive material 39. For example, as shown in FIG. 11, the external terminal 7 is directly rewired. It may be connected to layer 4. In this case, an opening 59 may be formed that penetrates the sealing resin 5 and exposes a part of the rewiring layer 4, and the external terminal 7 is connected to the rewiring layer 4 in the opening 59. May be good.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor device 2 Semiconductor layer 3 Underlayer 4 Rewiring layer 5 Encapsulating resin 6 Recess 7 External terminal 8 (Semiconductor layer) 1st surface 9 (Semiconductor layer) 2nd surface 10 (Semiconductor layer) 3rd surface 14 Wiring 17 Pad 21 1st rewiring layer 22 2nd rewiring layer 30 1st layer 31 2nd layer 32 Lower layer 33 Upper layer 34 (Upper layer) Edge edge 35 (Lower layer) Edge edge 36 (Encapsulating resin) 1st surface 37 (Encapsulating resin) ) 2nd surface 39 Intermediate conductive material 40 (Intermediate conductive material) End surface 42 (Rewiring layer) Bottom surface 43 (Concave) Bottom surface 45 Recessed 46 1st wall surface 47 2nd wall surface 48 (Encapsulating resin) Part inside the recess 60 (Concave) ) Exposed part 61 (Concave part) Concealed part 62 Concavo-convex structure

Claims (18)

A semiconductor layer having a first surface on which a pad is formed,
An insulating base layer formed so as to cover the first surface of the semiconductor layer, and
A rewiring layer formed on the base layer and extending from the pad in a direction along the first surface of the semiconductor layer.
A sealing resin formed so as to cover the rewiring layer, and
An external terminal arranged on a first surface of the sealing resin opposite to the surface of the sealing resin on the semiconductor layer side and electrically connected to the rewiring layer is included.
The base layer is formed with a recess extending from the edge of the rewiring layer to the lower region of the rewiring layer in a direction along the first surface of the semiconductor layer.
A semiconductor device in which a part of the sealing resin has entered the lower region of the rewiring layer through the recess. A plurality of the rewiring layers are formed on the base layer.
The semiconductor device according to claim 1, wherein the recess is formed so as to straddle between adjacent rewiring layers. The semiconductor device according to claim 1 or 2, wherein the peripheral edge of the recess includes a curved surface curved so as to bulge toward the semiconductor layer. The semiconductor device according to any one of claims 1 to 3, wherein the recess is continuously formed in the lower region of the rewiring layer so as to be continuous with the entire periphery of the peripheral edge of the rewiring layer. The semiconductor device according to any one of claims 1 to 4, wherein the bottom surface of the recess is roughened. Further included is an intermediate conductive material provided through the sealing resin so as to reach the rewiring layer from the first surface of the sealing resin and electrically connecting the rewiring layer and the external terminal. , The semiconductor device according to any one of claims 1 to 5. The base layer has an opening that exposes the pad.
The rewiring layer is formed on a first layer in which one surface and the other surface on the opposite side are formed along the inner surface of the opening, and a part thereof is embedded in the opening. Including the second layer
The first layer includes a lower layer on the side close to the pad and an upper layer on the lower layer made of a conductive material different from the lower layer.
The semiconductor device according to any one of claims 1 to 6, wherein the lower layer has an edge recessed to a lower region of the upper layer with respect to the edge of the upper layer. The lower layer of the first layer is made of Ti, and the upper layer of the first layer is made of Cu.
The semiconductor device according to claim 7, wherein the second layer is made of Cu. A recess formed by a step formed on the second surface of the semiconductor layer intersecting the first surface is formed on the first surface side of the semiconductor layer.
The semiconductor device according to any one of claims 1 to 8, wherein the sealing resin is contained in the recess. Claims 1 to 8, wherein the base layer is exposed on the second surface side of the semiconductor layer so as to be continuous with the second surface of the semiconductor layer intersecting the first surface of the semiconductor layer. The semiconductor device according to any one of the above. A plurality of the pads are arranged on the semiconductor layer.
The rewiring layer includes a first rewiring layer connected to one of the pads.
The semiconductor device according to any one of claims 1 to 10, wherein one of the external terminals is electrically connected to the first rewiring layer. A plurality of the pads are arranged on the semiconductor layer.
The semiconductor device according to any one of claims 1 to 11, wherein the rewiring layer includes a second rewiring layer commonly connected to the plurality of pads. The semiconductor device according to claim 12, wherein one of the external terminals is electrically connected to the second rewiring layer. The semiconductor device according to claim 12 or 13, wherein a plurality of the external terminals are electrically connected to the second rewiring layer. The semiconductor device according to any one of claims 1 to 14, wherein the external terminal includes a solder terminal. The semiconductor device according to any one of claims 1 to 15, which is a WL-CSP. A step of forming an insulating base layer so as to cover the first surface of the semiconductor layer having the first surface on which the pad is formed, and
A step of forming a rewiring layer extending from the pad along the first surface of the semiconductor layer, and a step of forming the rewiring layer.
By isotropically removing the underlying layer exposed from the rewiring layer, the underlying layer is provided on the first surface of the semiconductor layer from the edge of the rewiring layer to the lower region of the rewiring layer. The process of forming a recess extending along the line and
Forming said to cover the redistribution layer and the sealing resin so as to enter the lower region of the rewiring layer through the recess,
A method for manufacturing a semiconductor device, comprising a step of forming an external terminal on a first surface of the sealing resin opposite to the surface on the semiconductor layer side so as to be electrically connected to the rewiring layer. The method for manufacturing a semiconductor device according to claim 17, wherein the step of isotropically removing the base layer includes a step of ashing the base layer.

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