JP6985574B2 - Wafer underbump metallization plating layer structure and its manufacturing method - Google Patents

Description

The present invention relates to a technical area of an integrated circuit package, and more particularly to a wafer underbump metallized plating layer structure and a method for manufacturing the same.

As the demand for high-performance and high-integration of chips increases, the wiring of chips and packages becomes thinner and thinner, satisfying more I / O connections and improving the calculation efficiency of chips. In particular, the RDL (rewiring) process of the fou-out process, which has appeared in recent years, has reached a line width of 2/2 μm.

Traditionally, the advanced package is the down package chip process, the typical process is the CSP (Chip Scale Package) package, and by the driving process, the electrodes inside the chip are dispersed by the RDL method, and the balls are further planted. .. This encapsulation process saves a lot of space compared to traditional striking packages and reduces the chip size to a very small size. However, there is a problem that the width of the wiring is wide and the number of connection points is small.

A fan-shaped process was born to reduce the area occupied by the chip or to increase the computational efficiency of the chip. The connection points inside the chip are significantly increased and do not occupy more area, so that the wire width and the distance between the wires in the encapsulation process are smaller. The origin of these wires comes from the electrodes of the chip, and the rewiring process disperses the wires to form pads at the ends, or to plant or bind balls to connect to the outside.

Since copper has excellent conductivity, most of the material of the wiring body is copper, but copper has a drawback that it is easily oxidized and difficult to bond. For this reason, in the traditional process, after the production of copper wire is completed, chemical plating or nickel plating is performed to prevent the oxidation of copper and enhance its weldability and bondability. However, wiring is getting thinner, spacing is getting smaller, and the chemical gold plating process faces major challenges. The reason is that chemical gold plating is easy to penetrate, two independent wires are short-circuited, and plating leakage is likely to occur in independent pads. The electroplating process does not cause plating leaks, but it is necessary for all wiring to be connected and to have an energizing function in the plating process to realize the function and meet the needs of the plating layer of the independent pad. I can't.

In response to the existing shortage of the above techniques, the present invention provides a wafer underbump metallized plating layer structure and a method for manufacturing the same. The plating layer obtained by the electroless tin alloy plating technique according to the present invention becomes an electroless substitution plating layer, which eliminates the need for energization and allows only a substitution reaction instead of the conventional electroless autocatalytic reaction. Under bump metalization according to the present invention (UB)
M: Under Bump Metal) and rewiring (RDL: Redistributi)
onLayer) has good bondability and semi-attachability.

In order to realize the above object, the present invention is a method for manufacturing a plating layer for wafer underbump metallization.
The base material is silicon or a silicon carbide semiconductor, a conductive line region and a non-conductive region are provided on the surface of the base material, and a wafer bump having an inverted shape in which the conductive line region on the surface of the base material is recessed downward is formed. It ’s a method,
Step 1: Forming a metal electrode, the electrode inside the wafer is exposed by etching the wafer base material, and the metal electrode is formed at the bottom of the protruding portion of the wafer bump.
Step 2: Forming a passivation layer, forming silica on the surface of the wafer by performing a passivation treatment on the surface of the wafer bump to form a passivation layer.
Step 3: By forming a barrier layer, the surface of the passivation layer formed on the wafer bump is subjected to titanium plating, tungsten plating, or tantalum plating in a vacuum to form the barrier layer, and the barrier layer is constructed. , Being able to prevent ion diffusion between copper and wafer,
Step 4: The conductive copper seed layer is formed, and the surface of the barrier layer formed on the wafer bump is copper-plated in vacuum to form the conductive copper seed layer, thereby having good conductivity. To be ready for subsequent copper plating,
Step 5: The surface of the conductive copper seed layer formed on the wafer bump is coated, exposed, and developed to form a pattern, and the metal wiring portion is exposed.
Step 6: Forming a copper-plated layer, that is, copper-plating a metal wiring portion to form a copper-plated layer.
Step 7: Desmear treatment to remove the photoresist of the metal wiring portion in the conductive copper seed layer.
Step 8: In the etching process, the conductive copper seed layer is removed by etching, and then the barrier layer is removed by etching.
Step 9: Forming a chemically (non-electrolytic) tin alloy plating layer, the copper wiring in the copper plating layer is subjected to a non-electrolytic tin plating treatment to form a non-electrolytic tin alloy plating layer.
Step 10: An insulating layer is installed over the entire wiring and the pad position of the ball mount or bonding is exposed, and Step 11: Ball mounting or bonding is performed at the exposed pad position to realize interconnection with the external wiring. To do,
Provided is a method for manufacturing a plating layer for wafer underbump metallization, which comprises the above.

Preferably, the electroless tin plating layer in the electroless tin alloy plating layer is a substitution type plating layer, and the electroless tin plating solution uses water as a solvent and has a solute of 5 to 30 g / L of tin ions.
Contains 0-130 g / L thiourea, 10-100 g / L methylsulfonic acid, complexing agent.
A tin or tin-silver alloy plating layer is formed by adding 1 to 10 ppm of silver ions and immersing the base material to be plated with copper-containing wiring in a non-electrolytic tin plating solution under the condition of 60 to 80 ° C. Therefore, the immersion time is 10 to 20 minutes.
The potential of copper ions in an acidic solution is 0.52V, but the solution contains thiourea and Cu
^{The 2+} plating can be reduced to -0.5V and the ^{Sn 2+ potential is -0.136V.}
Since the tin potential is corrected (calibrated) with respect to copper, the following reaction:
2Cu + Sn ²⁺ → 2Cu ⁺ + Sn
By being able to occur
Tin deposition occurs due to the substitution reaction between tin ions and copper, and since the tin plating layer is not formed from tin ions in places without copper, it is possible to prevent the penetration plating phenomenon in places other than copper wiring.

Preferably, the thickness of the barrier layer is 0.1 to 0.5 μm, the thickness of the copper plating layer is 1 to 20 μm, and the thickness of the electroless tin alloy layer is 0.5 to 1.5 μm. Become. The insulating layer is made of resin.

In order to realize the above object, the present invention is a wafer underbump metallized plating layer structure obtained by a method for manufacturing a wafer underbump metallized plating layer.
The structure is formed on a wafer base material, in which a conductive line region and a non-conductive region are provided on the surface of the base material, and all of the conductive line regions on the surface of the base material are recessed downward. Includes wafer bumps from
A metal electrode is formed at the bottom of the protruding portion of the wafer bump, and the wafer bump includes a passage layer, a barrier layer, a conductive copper seed layer, a copper plating layer, and an electrolytic tin alloy plating layer in this order from the bottom. An insulating layer is installed on the entire substrate, the pad position of the ball mount or bonding is exposed on the electrolytic-free tin alloy plating layer, and the ball mount or bonding is performed on the exposed pad position to interconnect with the external wiring. Form,
Provided is a wafer underbump metallized plating layer structure.

An advantageous effect of the present invention is a wafer underbump metallized plating layer structure and a method for manufacturing the same, as compared with conventional techniques. Specifically, it has the following advantageous effects.

1) In the present technical plan, the surface of the base material on which the conductive line region is installed is recessed downward to form an inverted wafer bump on the surface of the base material on which the conductive line region is installed, and the wafer bump is formed. On the other hand, the passivation, the barrier, the conductive seed, the copper plating, the electroless tin alloy plating and the like are sequentially performed, and the electroless tin alloy plating layer is installed on the wafer base material. As a result, the plating layer obtained by the electroless tin alloy plating technique according to the present invention becomes an electroless substitution plating layer, no energization is required, and only a substitution reaction is required instead of the conventional electroless autocatalytic reaction.

2) The portion to be processed in the wafer base material is designed as a wafer bump having an inverted shape, and then the metalized plating layer treatment is performed on the wafer bump. As a result, when the bumps are treated with an electroless tin alloy plating layer, underbump metallization and rewiring can be obtained. Under Bump Metalation according to the present invention (UBM: Under Bump Metal)
And rewiring (RDL: Redistribution Layer) have both good bondability and semi-attachability.

3) Since electroless tin alloy plating is the replacement plating layer, there is no risk of penetration plating or skip plating, so it is not affected by the wiring design, and the wiring width and spacing in the electroless Ni-Au plating technology used in the past are not affected. It is possible to overcome the limitation of wiring conductivity in electrolytic Ni-Au plating technology.

4) An insulating layer is installed over the entire wiring, and then the pad position of the ball mount or bonding is exposed, and then tin ball mounting or bonding is performed at the pad-pin position. This enables interconnection with external wiring. According to it, the present invention realizes interconnection with the outside without energizing.

It is a figure which shows the plating layer structure of the wafer under bump metalization of this invention. It is a figure which shows the step of the process of the plating layer structure of the wafer underbump metallization of this invention. It is a figure which shows the quality risk which a conventional chemical nickel gold process poses. It is a figure which shows the penetration example of the conventional chemical nickel gold process. It is a figure which shows the example after electroless tin plating of the plating layer structure of the wafer under bump metalization of this invention. It is sectional drawing of electroless tin plating of this invention.

[Explanation of code]
Base material 11
Metal electrode 12
Passivation layer 13
Barrier layer 14
Conductive copper seed layer 15
Copper electroplating layer 16
Chemical (electroless) tin alloy plating layer 17
Tin ball 18
Insulation layer 19

In order to explain the present invention more clearly, the present invention will be described in detail below together with the drawings.
As shown in FIGS. 1 and 2, the present invention is a method for manufacturing a plating layer for wafer underbump metallization.
The base material 11 is a silicon or silicon carbide semiconductor, a conductive line region and a non-conductive region are provided on the surface of the base material, and a wafer bump having an inverted shape in which the conductive line region on the surface of the base material is recessed downward is formed. Specifically, as shown in FIG. 2,
Step 1: By forming the metal electrode 12, the electrode inside the wafer is exposed by etching the wafer base material, and the metal electrode 12 is formed at the bottom of the protruding portion of the wafer bump.
Step 2: A passivation layer 13 is formed, and silica is formed on the surface of the wafer by performing a passivation treatment on the surface of the wafer bump to form a passivation layer. The passivation material is an organic material such as PI. Resin can be used,
Step 3: The barrier layer 14 is formed, and the surface of the passivation layer formed on the wafer bump is subjected to titanium plating, tungsten plating, or tantalum plating in a vacuum to form the barrier layer, and the barrier layer is constructed. This makes it possible to prevent ion diffusion between the copper and the wafer.
Step 4: The conductive copper seed layer 15 is formed, and the surface of the barrier layer formed on the wafer bump is copper-plated in vacuum to form the conductive copper seed layer, thereby having good conductivity. , To be ready for subsequent copper plating,
Step 5: The surface of the conductive copper seed layer formed on the wafer bump is coated, exposed, and developed to form a pattern, and the metal wiring portion is exposed.
Step 6: Forming the copper electroplating layer 16 by plating the metal wiring portion with copper to form the copper plating layer.
Step 7: Desmear treatment to remove the photoresist of the metal wiring portion in the conductive copper seed layer.
Step 8: In the etching process, the conductive copper seed layer is removed by etching, and then the barrier layer is removed by etching.
Step 9: Forming a chemical (non-electrolytic) tin alloy plating layer 17, and forming a non-electrolytic tin alloy plating layer by performing a non-electrolytic tin plating treatment on copper wiring in the copper plating layer.
Step 10: The insulating layer 19 is installed on the entire wiring and the pad position of the ball mount or bonding is exposed, and Step 11: The tin ball 18 is mounted or bonded to the exposed pad position to mutually with the external wiring. To realize the connection,
It is a method for manufacturing a plating layer of a wafer underbump metallization, which comprises the above.

Based on the above steps, the present invention is a wafer underbump metallized plating layer structure, which is formed on a wafer base material, and has a conductive line region and a non-conductive region on the surface of the base material. Is installed, and the entire conductive line region on the surface of the base material contains a wafer bump having an inverted shape recessed downward, and a metal electrode 12 is formed at the bottom of a protruding portion of the wafer bump. In order from the bottom, the passivation layer 13, the barrier layer 14,
A conductive copper seed layer 15, a copper plating layer 16 and an electroless tin alloy plating layer 17 are provided.
External wiring is performed by installing the insulating layer 19 on the entire wafer substrate, exposing the pad position of the ball mount or bonding to the electroless tin alloy plating layer, and mounting or bonding the ball 18 to the exposed pad position. Form an interconnection with.

In this embodiment, the thickness of the barrier layer is 0.1 to 0.5 μm. The barrier layer is one of titanium, tungsten, tantalum and alloys. The seed layer of conductive copper is a copper layer,
The thickness of the copper plating layer is 1 to 20 μm. The electroless tin alloy layer includes electroless tin, electroless tin silver and electroless tin copper layer. The thickness of the electroless tin alloy layer is 0.5 to 1.5 μm.

The electroless tin plating layer in the electroless tin alloy plating layer is a displacement type plating layer, and the electroless tin plating solution uses water as a solvent and has a solute of 5 to 30 g / L tin ions (source is sulphate or methylsulfonic acid). (Tin), 70-130 g / L thiourea, 10-100 g / L methylsulfonic acid, complexing agent (citrate, etc.), 1-10 ppm silver ion (source: silver methylsulfonate, silver acetate, etc.) ) Is added, and the base material to be plated with copper-containing wiring is immersed in a tin-free tin plating solution under the condition of 60 to 80 ° C. to form a tin or tin-silver alloy plating layer. The time is 10 to 20 minutes.

The potential of copper ions in an acidic solution is 0.52V, but the solution contains thiourea and Cu
^{The 2+} plating can be reduced to -0.5V and the ^{Sn 2+ potential is -0.136V.}
Since the tin potential for copper will be corrected, the following reaction:
2Cu + Sn ²⁺ → 2Cu ⁺ + Sn
By being able to occur
Tin deposition occurs due to the substitution reaction between tin ions and copper, and since the tin plating layer is not formed from tin ions in places without copper, it is possible to prevent the penetration plating phenomenon in places other than copper wiring.

In inverse proportion, the conventional method employs electroless Ni-Au plating technology, which may cause shots between wirings. This will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic diagram showing a situation in which a short circuit is likely to occur between wirings when the wiring width is small. That is,
Although it is an independent wiring from the beginning, contact may occur due to an autocatalytic reaction that is difficult to control in chemical tin (electroless Ni-Au) plating. In the present invention, the line spacing is 9
We conducted an actual test of electroless Ni-Au plating for wiring of about μm, but found that Ni-Au deposition occurred in many parts between the wirings, and that they were interconnected between independent wirings and could not operate. (Shown in FIG. 4).

In the present invention, the electroless tin alloy plating serves as a substitution plating layer, and only the substitution reaction occurs in the copper wiring portion. Therefore, there is no penetration plating or skip plating of the electroless tin alloy plating, and there is no nickel corrosion. It is not affected by the independent pad design.

Further, in order to prove the practical effect of the present invention, electroless tin alloy plating having a wiring width of 3 μm and a wiring interval of 5 μm was tested. The test sample comprises a finer wiring design than the electroless Ni-Au plating example described above. According to the result of the test, it was found that there was no osmotic plating phenomenon (shown in FIG. 5). Further, as a result of testing the FIB (Focused Ion Beam) flakes after electroless tin plating, it was found that there were no abnormalities such as voids in the plating layer.

Each of the above steps may optionally include one or more auxiliary steps such as washing with water, wetting, pre-soaking or drying. FIG. 5 shows the wiring after electroless tin plating according to the present invention, and there was no penetration plating. After flaking and analyzing with FIB, it was found that there were no voids between the tin alloy and the copper layer (shown in FIG. 6). According to each experiment, it was proved in the present invention that interconnection with the outside is possible without energization.

Since electroless tin alloy plating is a replacement plating layer, there is no risk of penetration plating or skip plating, and it is not affected by the wiring design, and the wiring width and spacing in the electroless Ni-Au plating technology used conventionally It is possible to overcome the limitation of wiring conductivity in electrolytic Ni-Au plating technology. The plating layer by the electroless tin alloy plating technique becomes an electroless substitution plating layer, does not require energization, and does not require a conventional electroless autocatalytic reaction, but only a substitution reaction.

The above disclosure is limited to an embodiment of a sample of the inventor of the present invention, the present invention is not limited thereto, and changes that can be considered by engineers in any field are the scope of protection of the present invention. Should be included in.

Claims (1)

Wafer underbump This is a method for manufacturing a metallized plating layer.
The base material is silicon or a silicon carbide semiconductor, a conductive line region and a non-conductive region are provided on the surface of the base material, and a wafer bump having an inverted shape in which the conductive line region on the surface of the base material is recessed downward is formed. It ’s a method,
Step 1: Forming a metal electrode, the electrode inside the wafer is exposed by etching the wafer base material, and the metal electrode is formed at the bottom of the protruding portion of the wafer bump.
Step 2: Forming a passivation layer, forming silica on the surface of the wafer by performing a passivation treatment on the surface of the wafer bump to form a passivation layer.
Step 3: By forming a barrier layer, the surface of the passivation layer formed on the wafer bump is subjected to titanium plating, tungsten plating, or tantalum plating in a vacuum to form the barrier layer, and the barrier layer is constructed. , Being able to prevent ion diffusion between copper and wafer,
Step 4: The conductive copper seed layer is formed, and the surface of the barrier layer formed on the wafer bump is copper-plated in vacuum to form the conductive copper seed layer, thereby having good conductivity. To be ready for subsequent copper plating,
Step 5: The surface of the conductive copper seed layer formed on the wafer bump is coated, exposed, and developed to form a pattern, and the metal wiring portion is exposed.
Step 6: Forming a copper-plated layer, that is, copper-plating a metal wiring portion to form a copper-plated layer.
Step 7: Desmear treatment to remove the photoresist of the metal wiring portion in the conductive copper seed layer.
Step 8: In the etching process, the conductive copper seed layer is removed by etching, and then the barrier layer is removed by etching.
Step 9: Forming a non-electrolytic tin alloy plating layer, the copper wiring in the copper plating layer is subjected to a non-electrolytic tin plating treatment to form a non-electrolytic tin alloy plating layer.
Step 10: An insulating layer is installed over the entire wiring and the pad position of the ball mount or bonding is exposed, and Step 11: Ball mounting or bonding is performed at the exposed pad position to realize interconnection with the external wiring. To do,
Only including,
The electroless tin plating layer in the electroless tin alloy plating layer is a substitution type plating layer, and is electroless.
The detinned tin plating solution uses water as a solvent and has a solute of 5 to 30 g / L tin ion, 70 to 130 g.
Contains / L thiourea, 10-100 g / L methylsulfonic acid, complexing agent, 1-10 pp
Add m silver ions and electroless the base material to be plated with copper-containing wiring under the conditions of 60 to 80 ° C.
Forming a tin or tin-silver alloy plating layer by immersing it in a tin plating solution.
Therefore, the immersion time is 10 to 20 minutes.
The potential of copper ions in an acidic solution is 0.52V, but the solution contains thiourea and Cu
^{The 2+} plating can be reduced to -0.5V and the ^{Sn 2+ potential is -0.136V.}
Since the tin potential for copper will be corrected, the following reaction:
2Cu + Sn ²⁺ → 2Cu ⁺ + Sn
By being able to occur
Tin deposition is caused by the substitution reaction between tin ions and copper, and in copper-free areas, tinio
Since the tin plating layer is not formed from the copper wiring, there is no osmotic plating phenomenon in places other than copper wiring.
Sea urchin
A method for manufacturing a plated layer of wafer underbump metallization, which is characterized by this.

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