JP7020009B2 - Wiring board with through wiring and its manufacturing method - Google Patents

Description

The present disclosure relates to a wiring board and a method for manufacturing the same. For example, the present invention relates to a wiring board having through wiring and a method for manufacturing the same.

Semiconductor devices (semiconductor chips) manufactured using semiconductor substrates such as silicon are mounted on almost all electronic devices and provide various functions to the electronic devices. The semiconductor device is formed by laminating various patterned insulating films and conductive films on a semiconductor substrate. The semiconductor device is provided with terminals for inputting power supplies and signals necessary for operation, and is mounted on the main board. At this time, a wiring board (hereinafter, also referred to as an interposer) is provided between the semiconductor device and the main board. The interposer has a substrate and a through wiring (through electrode) penetrating the substrate, and the terminal of the semiconductor device and the wiring on the main substrate are electrically connected by the through wiring.

As the interposer substrate, a silicon substrate, a glass substrate, or the like is used. For example, Patent Documents 1 and 2 disclose an interposer manufactured by using a glass substrate, a glass-epoxy composite substrate, or the like, and on which a passive element such as a capacitive element, an inductor, or a resistance element is mounted.

Japanese Unexamined Patent Publication No. 2005-26670 Japanese Unexamined Patent Publication No. 2004-047667

One of the problems of the present disclosure is to provide an interposer on which a passive element such as a capacitive element is mounted and a method for manufacturing the interposer. For example, one of the problems is to provide an interposer on which a capacitance element having a significantly suppressed capacitance variation is mounted and a method for manufacturing the interposer. Alternatively, one of the problems is to provide a semiconductor module using the above interposer.

One of the embodiments of the present disclosure is a wiring board. This wiring board has a substrate having a through hole, and further has a through wiring that continuously covers a side wall of the through hole, a first surface of the substrate, and a second surface located opposite to the first surface. The thickness of the through wiring on the first surface is smaller than the thickness of the through wiring on the second surface.

One of the embodiments of the present disclosure is a wiring board. This wiring board includes a substrate having a through hole, a side wall of the through hole, a first surface of the substrate, and a through wiring that continuously covers a second surface located on the opposite side of the first surface, and a first surface. It has the first wiring above. The thickness of the first wiring is smaller than the thickness of the through wiring on the second surface.

One of the embodiments of the present disclosure is a method for manufacturing a wiring board. In this manufacturing method, a through hole is formed in the substrate, and a through wire that continuously covers the side wall of the through hole, the first surface of the substrate, and the second surface located on the opposite side of the first surface is formed by electrolytic plating. And to flatten the through wiring on the first surface.

FIG. 6 is a schematic cross-sectional view of a wiring board according to an embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view of a wiring board according to an embodiment of the present disclosure. The sectional schematic diagram which shows the manufacturing method of the wiring board of one Embodiment of this disclosure. The sectional schematic diagram which shows the manufacturing method of the wiring board of one Embodiment of this disclosure. A perspective view and a cross-sectional view showing a method of manufacturing a wiring board according to an embodiment of the present disclosure. The sectional schematic diagram which shows the manufacturing method of the wiring board of one Embodiment of this disclosure. The sectional schematic diagram which shows the manufacturing method of the wiring board of one Embodiment of this disclosure. FIG. 3 is a schematic cross-sectional view of a conventional wiring board and a wiring board according to an embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view of a wiring board according to an embodiment of the present disclosure. The sectional schematic diagram which shows the manufacturing method of the wiring board of one Embodiment of this disclosure. The sectional schematic diagram which shows the manufacturing method of the wiring board of one Embodiment of this disclosure. The sectional schematic diagram which shows the manufacturing method of the wiring board of one Embodiment of this disclosure. Schematic diagram of a cross section of the semiconductor module according to the embodiment of the present disclosure. Schematic diagram of a cross section of the semiconductor module according to the embodiment of the present disclosure. Schematic diagram of a cross section of the semiconductor module according to the embodiment of the present disclosure.

Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings and the like. However, the present disclosure can be carried out in various embodiments without departing from the gist thereof, and is not construed as being limited to the description contents of the embodiments exemplified below.

The drawings may schematically represent the width, thickness, shape, etc. of each part as compared to the actual embodiment in order to clarify the explanation, but this is merely an example and the interpretation of the present disclosure is limited. It's not something to do. In this specification and each figure, elements having the same functions as those described with respect to the above-mentioned figures may be designated by the same reference numerals to omit duplicate explanations.

In the present specification and the scope of patent claims, when expressing an aspect of arranging another structure on one structure, when the term "above" is simply used, the structure shall be used unless otherwise specified. It includes both the case where another structure is placed directly above the structure so as to be in contact with each other and the case where another structure is placed above one structure via another structure.

When a single film is processed to form a plurality of films, or when a plurality of films are simultaneously formed in the same process, the plurality of films may have different functions and roles. However, these multiple films are derived from films formed as the same layer in the same process, and these multiple films have the same structure and the same material, except when a part of these films is selectively processed. Has. Therefore, in the present specification and claims, these multiple films are defined as existing in the same layer.

In the present specification, when a plurality of components are referred to separately, a hyphen and a natural number are used after the reference numeral. When describing the whole component or an arbitrarily selected component without distinguishing each of the plurality of components, only the reference numeral is used.

(First Embodiment)
The structure and manufacturing method of the wiring board 100, which is one of the embodiments of the present disclosure, will be described with reference to the drawings.

1. 1. A schematic cross-sectional view of the structural wiring board 100 is shown in FIG. 1 (A). The wiring board 100 is sandwiched between a semiconductor device and a main board, for example, and can function as an interposer for electrically connecting these.

Specifically, the wiring board 100 has a board 102, and the board 102 is provided with a through hole 104 that penetrates the board 102. The wiring board 100 further includes a side wall of the through hole and a through wiring 110 that continuously covers the upper surface and the lower surface (hereinafter, referred to as the first surface and the second surface, respectively) of the substrate 102. In FIG. 1, the through wiring 110 does not completely close the through hole 104, but the through wiring 110 may be provided so as to completely close the through hole 104.

In addition to the through wiring 110, various wirings and insulating films can be provided on the wiring board 100, and passive elements such as capacitive elements can be formed by these wirings. For example, in the example shown in FIG. 1A, the wiring board 100 has a first wiring 112 on the substrate 102, an insulating film 106-1 on a part of the through wiring 110, and an insulation on the first wiring 112. A second wiring 114-1 located on the film 106-2 and the insulating film 106-1 and overlapping the through wiring 110, and a second wiring 114-1 located on the insulating film 106-2 and overlapping the first wiring 112. Has wiring 114-2. The capacitive element 150 is formed by a part of the through wiring 110, the insulating film 106-1, and the second wiring 114-1, and by the first wiring 112, the insulating film 106-1, and the second wiring 114-2. Capacitive element 152 is formed. In the present embodiment, the number of capacitive elements is not limited, and for example, the through wiring 110 may not contribute to the formation of the capacitance, and three or more capacitive elements may be provided.

An enlarged view of the capacitive element 152 is shown in FIG. 1 (B). Although the details will be described later, the through wiring 110 and the first wiring 112 can be formed by electrolytic plating. Moreover, these may be formed by the same process. In this case, as shown in FIGS. 1A and 1B, a metal layer (hereinafter referred to as a seed layer) 124 is formed between the substrate 102 and the first wiring 112 and between the substrate 102 and the through wiring 110. It may have been done.

As schematically shown in FIG. 1B, the roughness of the upper surface of the first wiring 112 (that is, the surface facing the substrate 102 and in contact with the insulating film 106-1) is smaller than the roughness of the side surface. .. That is, in the first wiring 112, the flatness of the upper surface is higher than that of the side surface. For example, the center line average roughness Ra of the upper surface of the first wiring 112 can be 0.02 nm or more and 60 nm or less. Ra on the upper surface of the first wiring 112 is smaller than Ra on the side surface.

The through wiring 110 has a similar relationship. That is, the roughness of the surface of the through wiring 110 on the first surface (the surface far from the substrate 102) is smaller than the roughness of the surface of the through wiring 110 on the second surface (the surface far from the substrate 102). The average roughness Ra of the center line on the surface of the through wiring 110 on the first surface is smaller than that on the second surface, and can be 0.02 nm or more and 60 nm or less.

Similarly, the roughness of the upper surface of the first wiring 112 is smaller than the roughness of the surface of the through wiring 110 on the second surface. The upper surface of the first wiring 112 and the surface of the through wiring 110 on the first surface can have the same degree of roughness.

The thickness of the through wiring 110 on the first surface is different from the thickness of the through wiring 110 on the second surface. Further, the former may be smaller than the latter. Similarly, the thickness of the first wiring 112 is different from the thickness of the through wiring 110 on the second surface, and the former may be smaller than the latter. The thickness of the through wiring 110 on the first surface and the thickness of the first wiring 112 may be the same.

Further, from a macroscopic point of view, the surface of the through wiring 110 on the first surface and the upper surface of the first wiring 112 have smaller undulations than the surface of the through wiring 110 on the second surface. Specifically, as shown in a schematic enlarged view (FIG. 2) of the first wiring 112, the ratio of the minimum thickness h ₁ to the maximum thickness h ₂ of the first wiring 112 (h ₁ / h ₂ ). Is large compared to the ratio of the minimum thickness to the maximum thickness of the through wiring 110 on the second surface. Similarly, the ratio of the minimum thickness to the maximum thickness of the through wiring 110 on the first surface is large compared to the ratio of the minimum thickness to the maximum thickness of the through wiring 110 on the second surface. The ratio of the minimum thickness to the maximum thickness of the first wiring 112 and the ratio of the minimum thickness to the maximum thickness of the through wiring 110 on the first surface may be substantially the same as each other, and may be 0.85 or more and 1 or less. Can be.

Referring to FIG. 1A, the wiring board 100 is further located on the board 102, the first protective film 116 covering the end of the second wiring 114 and the end of the through wiring 110, and the board 102. It may have a second protective film 118 that is located underneath and covers the end of the through wiring 110. The through wiring 110 exposed from the second protective film 118 can be electrically connected to the main board provided under the wiring board 100.

A third wiring 120-1 and 120-2 are provided on the second wiring 114-1 and 114-2, respectively. The third wiring 120-1 is electrically connected to the second wiring 114-1, and the third wiring 120-2 is electrically connected to the second wiring 114-2. Further, a third protective film 122 that covers these ends may be provided on the third wiring 120 as an arbitrary configuration. The third wiring 120 is used to electrically connect the semiconductor device and the wiring board 100.

2. 2. Manufacturing Method A manufacturing method of the wiring board 100 having the above-mentioned structure will be described with reference to FIGS. 3 (A) to 6 (B).

First, a through hole 104 is formed in the substrate 102 (FIG. 3A). The material contained in the substrate 102 is not limited, and examples thereof include organic materials such as glass, silicon, gallium arsenide, gallium nitride, ceramics, and resin, or composite materials of glass and organic materials. Examples of the resin include epoxy resin, polyimide resin, polyester resin and the like. When the glass substrate is used as the substrate 102, the through hole 104 may be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sandblasting or ultrasonic drilling. The number and size of the through holes 104 can be arbitrarily determined according to the design of the wiring board 100.

Next, the seed layer 124 is formed on the surface of the substrate 102 (FIG. 3A). The seed layer 124 is formed for forming the through wiring 110 and the first wiring 112 by electroplating, and includes metals such as titanium, nickel, chromium, and copper, or alloys thereof. The seed layer 124 can be formed by a sputtering method, a chemical vapor deposition (CVD) method, electroless plating, a vapor deposition method, or the like.

Next, the resist 130 for protecting the region where the through wiring 110 and the first wiring 112 are not formed is formed on the first surface and the second surface. The resist 130 may be formed by curing a liquid resist, but since the substrate 102 has through holes 104, a film-like resist is attached to the first and second surfaces, and then light is applied. It can be efficiently formed by irradiation and development. After that, the seed layer 124 is fed to perform electrolytic plating to form the through wiring 110 and the first wiring 112 on the seed layer 124 not covered with the resist 130 (that is, in the opening of the resist 130) (FIG. 3). (C)). The through wiring 110 and the first wiring 112 can include metals such as titanium, aluminum, copper, nickel, tungsten, molybdenum, gold, silver, iron, and chromium, and alloys thereof. Further, the through wiring 110 and the first wiring 112 may have a laminated structure of different metal films, and may be, for example, laminated metal films containing copper, nickel, and gold, respectively.

After that, the resist 130 is removed, and the seed layer 124 exposed from the through wiring 110 and the first wiring 112 is removed by etching. At this time, the seed layer 124 can be efficiently removed by using an etchant containing an acid such as sulfuric acid, but at the same time, a part of the surface of the through wiring 110 and the first wiring 112 elutes. As a result, as schematically shown in FIG. 4B, fine irregularities are generated on the surface. Further, in the formation of the metal film by electrolytic plating, it is not always possible to construct a flat structure over the entire upper surface, and the growth of the metal film is slow in the vicinity of the resist 130. As a result, as shown in FIG. 4B, it is easy to give a shape in which the end portion of the upper surface is inclined.

Therefore, in the present disclosure, the surface of the through wiring 110 and the first wiring 112 located on the first surface is flattened (FIG. 4A). The flattening treatment can be performed by using, for example, physical polishing with a diamond bite or chemical mechanical polishing (CMP) using a polishing liquid in which an abrasive is dispersed.

In the case of physical polishing, for example, as shown in FIG. 5A, a mother substrate 162 on which a plurality of wiring boards 100 are formed is installed on a stage 160 having a rectangular or square upper surface. While rotating the spindle 164 equipped with the diamond bite 166, the stage 160 and the spindle 164 are relatively moved, and one surface of the mother substrate 162 is polished. By this operation, as shown in FIG. 5B, the surfaces of the through wiring 110 and the first wiring 112 on the substrate 102 are scraped, and a flat surface can be obtained. The flattening treatment may be performed in a state where the resist 130 is formed.

By the flattening process, as shown in FIG. 4C, the upper surfaces of the through wiring 110 and the first wiring 112 on the substrate 102 are flattened, and a surface having a small center line average roughness Ra is obtained. At the same time, a flat surface with small undulations is obtained over the entire upper surface of the through wiring 110 and the first wiring 112, and the thickness of the through wiring 110 and the first wiring 112 is reduced (FIG. 4A). When the through wiring 110 located on the second surface is not flattened, as described above, the through wiring 110 and the first wiring 112 on the first surface are compared with the through wiring 110 on the second surface. , Thickness, surface roughness, and surface undulations are reduced.

Next, the insulating films 106-1 and 106-2 are formed so as to cover the locations where the capacitive elements 150 and 152 are formed, that is, a part of the through wiring 110 and the first wiring 112, respectively (FIG. 6A). ). Since the insulating film 106 functions as a dielectric film, it is preferable to use a material having a high dielectric constant. Typically, silicon-containing inorganic compounds such as silicon oxide, silicon nitride, silicon oxide, silicon carbide, silicon nitride carbide, carbon-added silicon oxide, aluminum-containing inorganic compounds such as aluminum oxide and aluminum nitride, or hafnium silicate and oxidation. Examples thereof include hafnium-containing inorganic compounds such as hafnium and hafniumaluminate, and transition metal oxides such as yttrium oxide and zirconium oxide. The insulating film 106 is formed by using a CVD method or a sputtering method.

Subsequently, as shown in FIG. 6B, the second wirings 114-1 and 114-2 that function as electrodes of the capacitive elements 150 and 152 are formed so as to overlap the through wiring 110 and the first wiring 112, respectively. .. Typically, the second wiring 114 is formed by using a CVD method, a sputtering method, a vapor deposition method, or the like. The second wiring 114 includes metals such as copper, aluminum, titanium, molybdenum, and tungsten, and alloys thereof. The second wiring 114 may have a laminated structure. In this case, for example, a laminated structure in which a metal having a high conductivity such as aluminum or copper is sandwiched between a metal having a high melting point such as titanium or molybdenum can be adopted.

After that, the first protective film 116 and the second protective film 118 are formed on the first surface and the second surface, respectively (FIG. 6 (C)). The first protective film 116 and the second protective film 118 can also be formed by using a film-like resist. The first protective film 116 is provided with an opening for exposing the second wirings 114-1 and 114-2, and the second protective film 118 is for connecting the main board and the through wiring 110. An opening is provided.

Subsequently, the third wirings 120-1 and 120-2 electrically connected to the second wirings 114-1 and 114-2 are formed on the second wirings 114-1 and 114-2, respectively. (FIG. 7 (A)). The third wiring 120 can also be formed in the same manner as the second wiring 114, and includes the metal that can be used in the second wiring 114. The capacitive elements 150 and 152 are electrically connected to other wirings and elements in the wiring board 100 or semiconductor devices via the third wiring 120.

Next, the third protective film 122 is formed on the first protective film 116 and the third wiring 120 (FIG. 7 (B)). The third protective film 122 can be formed by the same method as that of the first protective film 116. The third protective film 122 is formed with an opening for exposing the third wirings 120-1 and 120-2.

As described above, in the wiring board manufacturing method of the present disclosure, after forming the through wiring 110 and the first wiring 112, a flattening process is performed on these. On the other hand, when the capacitive element is formed without the flattening process, as shown in FIG. 8A, the through wiring 110 or the first wiring 112 having a large surface roughness and uneven surface is formed. An insulating film 106 is formed on the insulating film 106. Since the thickness of the insulating film 106 is about several tens to several hundreds of nanometers, when a voltage is applied to the capacitive elements 150 and 152, the electric field is concentrated on the convex portion 140 on the surface of the through wiring 110 and the first wiring 112. Happens. As a result, dielectric breakdown easily occurs around this portion, and the capacitive elements 150 and 152 are destroyed.

On the other hand, by performing the above-mentioned flattening process, the surface roughness of the through wiring 110 and the first wiring 112 on the first surface becomes smaller. Therefore, the local electric field concentration is suppressed, and the withstand voltage of the capacitive elements 150 and 152 increases. As a result, the reliability of the wiring board 100 can be improved.

Since the insulating film 106 has a small thickness, the surface shape of the through wiring 110 and the first wiring 112 is reflected in the surface shape of the insulating film 106. Therefore, when the surface of the through wiring 110 or the first wiring 112 is greatly uneven, the area where the second wiring 114 overlaps the insulating film 106 (effective area) and the area where the second wiring 114 and the insulating film 106 are in contact (the area where the second wiring 114 and the insulating film 106 are in contact). The difference in contact area) becomes large, and the capacitance variation of the capacitive elements 150 and 152 becomes large.

On the other hand, in the method for manufacturing the wiring board 100 of the present disclosure, since the through wiring 110 and the first wiring 112 are flattened, the roughness of their surfaces is reduced and the undulations are reduced. As a result, the difference between the effective area and the contact area becomes small, and it is possible to provide the wiring board 100 having a small variation in capacitance with respect to the design value. Therefore, the wiring board 100 of the present disclosure exhibits excellent characteristics as an interposer including a circuit sensitive to capacitance variation, for example, a filter circuit.

As described above, when the through wiring 110 and the first wiring 112 are formed by electrolytic plating, a flat structure is not always constructed over the entire upper surface, and both ends of the upper surface tend to be inclined. Therefore, the area of the flat surface required for forming the capacitive elements 150 and 152 is reduced, and the margin L for forming the second wiring 114 is reduced (FIG. 8A).

On the other hand, in the method for manufacturing the wiring board 100 of the present disclosure, since the through wiring 110 and the first wiring 112 are flattened, a flat surface having a large area is formed on the surface of the through wiring 110 and the first wiring 112. It can be secured above (Fig. 8 (B)). Therefore, a large margin L can be obtained, and not only the yield of the wiring board 100 can be improved, but also the degree of freedom in designing the wiring board 100 can be increased.

(Second Embodiment)
The structure of the wiring board is not limited to the structure described in the first embodiment, and the structure described in the present embodiment can also be adopted. For example, as in the wiring board 108 shown in FIG. 9A, the thickness of the through wiring 110 may be the same or substantially the same on the first surface and the second surface of the substrate 102. Further, as in the wiring board 109 shown in FIG. 9B, the through wiring 110 may be provided so as to fill the through hole 104 and function as a so-called through electrode. When the through wiring 110 is formed so as to have the same thickness on the first surface and the second surface, the stress caused by the difference in the coefficient of thermal expansion between the substrate 102 and the through wiring 110 is evenly applied to the top and bottom of the substrate 102. Therefore, it is possible to prevent the substrate 102 from being deformed (warped).

The wiring board 108 can be manufactured, for example, by the following method. First, as shown in FIGS. 3A and 3B, a seed layer 124 is formed on the surface of the substrate 102, and a resist 130 is formed in a region where the through wiring 110 and the first wiring 112 are not formed. After that, power is supplied to the seed layer 124 to perform electrolytic plating, and the through wiring 110 and the first wiring 112 are formed on the seed layer 124. The through wiring 110 and the first wiring 112 at this time are formed so as to be larger than their final thickness (FIG. 10A). After that, the resist 130 is removed, and the seed layer 124 exposed from the through wiring 110 and the first wiring 112 is removed by etching.

After that, the through wiring 110 is flattened on both the first surface and the second surface. For example, the through wiring 110 on the second surface is flattened by the method described in the first embodiment. As a result, the thickness of the through wiring 110 is reduced on the second surface (FIG. 10 (B)). Next, as in the first embodiment, the through wiring 110 and the first wiring 112 are flattened on the first surface (FIG. 10 (C)). The flattening process is performed so that the thickness of the through wiring 110 is substantially the same on the first surface and the second surface. Although not shown, the flattening process may be performed first on the through wiring 110 located on the first surface. Since the subsequent process is the same as that of the first embodiment, the description thereof will be omitted.

Reflecting the manufacturing method described above, on the first surface and the second surface, Ra on the upper surface (that is, the main surface not in contact with the substrate) of the through wiring 110 and the first wiring 112 is higher than Ra on these side surfaces, respectively. small. Further, the Ra on the surface of the through wiring 110 on the first surface and the second surface is the same as or substantially the same as each other, but is smaller than the Ra on the surface of the through wiring 110 inside the through hole 104.

Alternatively, the through wiring 110 and the first wiring 112 are electroplated so that the thickness of the through wiring 110 and the first wiring 112 located on the first surface is larger than the thickness of the through wiring 110 located on the second surface. It may be formed in one step. This can be done, for example, by installing the substrate 102 so that the distances from the electrodes used in electrolytic plating to the first surface and the second surface are different from each other and performing electrolytic plating, or the seed layers 124 on the first surface and the second surface. It is achieved by feeding different current values to different power sources. By this method, the form of FIG. 10 (B) can be obtained directly from the form of FIG. 3 (B). In this case, it is not always necessary to perform the flattening process on the second surface. Therefore, as in the case of the first embodiment, the upper surface of the first wiring 112 has a smaller Ra and a higher flatness than the side surface of the first wiring 112 and the surface of the through wiring 110 on the second surface. The surface of the through wiring 110 on the first surface has a smaller Ra and a higher flatness than that on the second surface.

The wiring board 109 can be manufactured by, for example, the following method. First, as shown in FIG. 3A, a seed layer 124 is formed on the surface of the substrate 102, and then electrolytic plating is performed by supplying power to the seed layer 124. Electroplating is performed so that the through hole 104 is filled with the metal or alloy described in the first embodiment. As a result, a metal film 113 that fills the through hole 104 and covers the first surface and the second surface is formed (FIG. 11 (A)). Then, by polishing such as CMP to remove the metal film 113 on the first surface and the second surface, the through electrode 111 can be obtained (FIG. 11 (B)). The method for forming the through silicon via 111 is not limited to this, and various methods can be applied.

After that, as in the production of the wiring board 108, the resist 130 is formed (FIG. 11 (C)), the first wiring 112, and the wirings 115-1 and 115-2 electrically connected to the through electrode 111 are formed (the first wiring 112). FIG. 12A), and the first wiring 112 and the wiring 115 are polished (FIGS. 12B and 12C). Through silicon via 111 and wirings 115-1 and 115-2 form through wiring 110. Therefore, Ra on the upper surface of the through wiring 110 and the first wiring 112 is smaller than Ra on these side surfaces.

Although not shown, in the form of FIG. 11C, as in the case of manufacturing the wiring board 108, the wirings 115-1, 115-2, and the wirings 115-1, 115-2, so as to be larger than the thickness of the wiring 115-2 formed on the second surface. The wiring 112 of 1 may be directly formed by electrolytic plating. In this case, since it is not necessary to perform flattening processing on the second surface, the upper surface of the through wiring 110 or the first wiring 112 has a smaller Ra than the side surface and the surface of the through wiring 110 on the second surface. , High flatness.

Since the wiring boards 108 and 109 are also flattened with respect to the through wiring 110 and the first wiring 112, it is possible to provide a wiring board having a capacity having a small variation with respect to the design value. Therefore, the wiring boards 108 and 109 of the present embodiment also have a high degree of freedom in design and exhibit excellent characteristics as an interposer including a circuit sensitive to capacitance variation, for example, a filter circuit.

(Third Embodiment)
In this embodiment, the semiconductor module using the wiring board 100 described in the first or second embodiment will be described.

The semiconductor module 170 shown in FIG. 13 has a main substrate 172 and a plurality of wiring boards 100-1, 100-2, 100-3 laminated on the main substrate 172. The number of wiring boards 100 is not limited, and is determined according to the performance required for the semiconductor module 170. Various semiconductor chips (memory devices, central arithmetic units) and semiconductor elements (microelectromechanical systems (MEMS), etc.) (not shown) are connected to the main substrate 172. As described in the first embodiment, the wiring board 100 has a through wiring 110 and a third wiring 120, which function as terminals in the semiconductor module 170. The through wiring 110 of the wiring board 100-1 in the lowermost layer is electrically connected to the terminal 176 provided on the main board 172 via the bump 174. Further, the laminated wiring boards 100-1, 100-2, and 100-3 are also electrically connected to each other by the bump 174. Bump 174 includes metals such as indium, copper and gold, or alloys such as solder.

Like the semiconductor module 180 shown in FIG. 14, the laminated wiring boards 100 may be different in size and shape from each other, and the number of the wiring boards 100 laminated on the main substrate 172 may also be different. In the example shown in FIG. 14, two wiring boards 100-4 and 100-5 are laminated in a part of the area, and three wiring boards 100-1, 100-2 and 100-3 are laminated in a part of the area. Has been done.

The semiconductor module 200 shown in FIG. 15 has a structure in which a plurality of semiconductor chips (or semiconductor elements) 204-1 and 204-2 are laminated on a main substrate 202 via a wiring substrate 100. Terminals 208 and 210 are formed on the semiconductor chips 204-1 and 204-2, respectively, and these are electrically connected to the through wiring 110 and the third wiring 120 of the wiring board 100 via the bump 206. As a result, the semiconductor chips 204-1 and 204-2 are electrically connected to each other. Further, the semiconductor chip 186 and the main board 202 may be electrically connected by the wire wiring 212.

Each of the above-described embodiments as the embodiments of the present disclosure can be appropriately combined and implemented as long as they do not contradict each other. In addition, those skilled in the art who have appropriately added, deleted, or changed the design of components based on each embodiment are also included in the scope of the present disclosure as long as the gist of the present disclosure is provided.

In addition, even if the effects are different from the effects brought about by each of the above-described embodiments, those that are clear from the description of the present specification or those that can be easily predicted by those skilled in the art are of course. It is understood to be brought about by this disclosure.

100: Wiring board, 102: Board, 104: Through hole, 106: Insulation film, 108: Wiring board, 109: Wiring board, 110: Through wiring, 111: Through electrode, 112: First wiring, 113: Metal film , 114: 2nd wiring, 115: wiring, 116: 1st protective film, 118: 2nd protective film, 120: 3rd wiring, 122: 3rd protective film, 124: seed layer, 130: Resist, 140: Convex, 150: Capacitive element, 152: Capacitive element, 160: Stage, 162: Mother substrate, 164: Spindle, 166: Diamond bite, 170: Semiconductor module, 172: Main substrate, 174: Bump, 176 : Terminal, 180: Semiconductor module, 186: Semiconductor chip, 200: Semiconductor module, 202: Main board, 204: Semiconductor chip, 206: Bump, 208: Terminal, 210: Terminal, 212: Wire wiring

Claims (28)

A substrate with a through hole and
It has a side wall of the through hole, a first surface of the substrate, and a through wiring that continuously covers a second surface opposite to the first surface.
The thickness of the through wiring on the first surface is smaller than the thickness of the through wiring on the second surface.
A wiring board in which the average roughness of the center line of the through wiring on the first surface is smaller than the average roughness of the center line of the through wiring on the second surface . The wiring board according to claim 1, wherein the ratio of the minimum thickness to the maximum thickness of the through wiring on the first surface is smaller than the ratio of the minimum thickness to the maximum thickness of the through wiring on the second surface. .. The wiring board according to claim 1, wherein the ratio of the minimum thickness to the maximum thickness of the through wiring on the first surface is 0.85 or more and 1 or less. Further having a first wiring on the first surface,
The wiring board according to claim 1, wherein the thickness of the first wiring is smaller than the thickness of the through wiring on the second surface. According to claim 4 , the average roughness of the center line of the first wiring and the average roughness of the center line of the through wiring on the first surface are smaller than the average roughness of the center line of the through wiring on the second surface. The wiring board described. The ratio of the minimum thickness to the maximum thickness of the first wiring and the ratio of the minimum thickness to the maximum thickness of the through wiring on the first surface are the ratio of the minimum thickness to the maximum thickness of the through wiring on the second surface. The wiring board according to claim 4 , which is smaller than the minimum thickness ratio. According to claim 4 , the ratio of the minimum thickness to the maximum thickness of the first wiring and the ratio of the minimum thickness to the maximum thickness of the through wiring on the first surface are 0.85 or more and 1 or less. The wiring board described. The wiring board according to claim 4 , wherein the through wiring and the first wiring have the same composition. The wiring board according to claim 4 , further comprising a seed layer between the substrate and the through wiring, and between the substrate and the first wiring. With the through wiring and the insulating film on the first wiring,
The wiring board according to claim 4 , which is located on the insulating film and has the through wiring and the second wiring overlapping with the first wiring. The wiring board according to claim 10 , further comprising a third wiring located on the second wiring and electrically connected to the second wiring. The wiring board according to claim 1, wherein the substrate includes a material selected from glass, ceramics, silicon, and an organic material. A substrate with a through hole and
It has a side wall of the through hole, a first surface of the substrate, and a through wiring that continuously covers a second surface opposite to the first surface.
The thickness of the through wiring on the first surface is substantially the same as the thickness of the through wiring on the second surface.
On the first surface, the average roughness of the center line on the upper surface of the through wiring is smaller than the average roughness of the center line on the side surface of the through wiring.
The through wiring is a wiring board exposed in the internal space of the through hole . The wiring board according to claim 13 , wherein on the second surface, the average roughness of the center line on the upper surface of the through wiring is smaller than the average roughness of the center line on the side surface of the through wiring. 13. The average roughness of the center line of the upper surface of the through wiring on the first surface and the second surface is smaller than the average roughness of the center line of the upper surface of the through wiring inside the through hole . The wiring board described. The wiring board according to claim 13 , wherein the center line average roughness of the through wiring on the first surface is substantially the same as the center line average roughness of the through wiring on the second surface. A substrate with a through hole and
It has a side wall of the through hole, a first surface of the substrate, and a through wiring that continuously covers a second surface opposite to the first surface.
The thickness of the through wiring on the first surface is substantially the same as the thickness of the through wiring on the second surface.
On the first surface, the average roughness of the center line on the upper surface of the through wiring is smaller than the average roughness of the center line on the side surface of the through wiring.
A wiring board in which the average roughness of the center line of the through wiring on the first surface is smaller than the average roughness of the center line of the through wiring on the second surface. The wiring board according to claim 13 , wherein the through hole is filled with the through wiring. The insulating film on the through wiring and
The wiring board according to claim 13 , which is located on the insulating film and has a second wiring that overlaps with the through wiring. 19. The wiring board of claim 19 , further comprising a third wiring that is located on the second wiring and is electrically connected to the second wiring. The wiring board according to claim 13 , wherein the substrate includes a material selected from glass, ceramics, silicon, and an organic material. Forming through holes in the substrate,
Forming a through wire that continuously covers the side wall of the through hole, the first surface of the substrate, and the second surface located on the opposite side of the first surface by electrolytic plating .
Flattening the through wiring on the first surface, as well as
A method for producing a wiring board, which comprises forming an insulating film in contact with the through wiring on the first surface in a state where the through wiring is exposed in the internal space of the through hole . Forming through holes in the substrate,
By electroplating, a through wire that continuously covers the side wall of the through hole, the first surface of the substrate, and the second surface located on the opposite side of the first surface is formed by electroplating.
Including flattening the through wiring on the first surface,
The flattening is a method for manufacturing a wiring board , wherein the thickness of the through wiring on the first surface is smaller than the thickness on the second surface. 22. The manufacturing method according to claim 22 , further comprising flattening the through wiring on the second surface. A claim that the flattening of the through wiring on the first surface and the second surface is performed so that the thickness of the through wiring on the first surface and the thickness on the second surface are substantially the same. 24. The production method according to 24. Forming through holes in the substrate,
By electroplating, a through wire that continuously covers the side wall of the through hole, the first surface of the substrate, and the second surface located on the opposite side of the first surface is formed by electroplating.
Including flattening the through wiring on the first surface,
A method for manufacturing a wiring board , wherein the through wiring is formed by the electrolytic plating so that the thickness on the first surface is larger than the thickness on the second surface. Forming through holes in the substrate,
Through electrolytic plating is used to form through wiring that continuously covers the side wall of the through hole, the first surface of the substrate, and the second surface located on the opposite side of the first surface, and at the same time, the first surface is placed on the first surface. Forming the wiring, as well as
A method for manufacturing a wiring board, which comprises flattening the through wiring on the first surface and at the same time flattening the first wiring . Forming through holes in the substrate,
By electroplating, a through wire that continuously covers the side wall of the through hole, the first surface of the substrate, and the second surface located on the opposite side of the first surface is formed by electroplating.
Including flattening the through wiring on the first surface,
The flattening is a method for manufacturing a wiring board , which is performed using a diamond bite.

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