JP7035002B2 - Clock regeneration circuit, waveform observation device, clock regeneration method and waveform observation method - Google Patents

Description

The present invention relates to a clock reproduction circuit, a waveform observation device, a clock reproduction method and a waveform observation method having a function of reproducing a clock signal used for observing the waveform of the input signal from the input signal.

For example, as a measurement system used in an inspection stage of an optical device (or an optical module) such as an optical transceiver or an optical interface, a system configuration using a sampling oscilloscope 60 is known as shown in FIG.

In FIG. 7, the device under test (DUT) 70 is, for example, an optical transceiver, and is used by being mounted (connected) to the evaluation board 70A. In the system configuration shown in FIG. 7, the signal generator (PPG) 65 sends a data signal to the DUT 70 and also sends a clock signal to the sampling oscilloscope 60. The DUT 70 inputs a data signal from the PPG 65 and outputs the data signal as an optical signal to the sampling oscilloscope 60. In the sampling oscilloscope 60, the trigger generation unit 62 generates a trigger signal based on the clock signal input from the PPG 65, and the sampler 61 samples the data signal at the sampling timing corresponding to the trigger signal to observe the waveform. There is.

In the above system configuration, the data signal transmitted by the DUT 70 may not be synchronized with the clock signal of the PPG 65. To give a specific example, PPG65 (host side) and DUT70 (reception side) were synchronized up to 100GHz until now, but in recent years, 400GHz (PAM4 signal) has been handled, and the host side and reception side have come to handle. There was a situation where the clock was not synchronized with the clock, and clock recovery was required.

As a conventional clock reproduction device having a clock recovery function, when the phase comparator detects the phase difference between the input signal and the reproduction clock signal, the reproduction clock is oscillated by the digitally controlled oscillator by one of the two correction values having different resolutions. Patent Document 1 proposes a closed-loop control technique for matching the phase of a reproduction clock signal with the phase of an input signal by shifting the phase of the above (see paragraphs 0008 to 0011, FIG. 1).

Japanese Unexamined Patent Publication No. 11-20528

By the way, in the inspection stage of an optical device (see FIG. 7), it is general that many kinds of optical devices that pass signals having different transmission rate standards are used as waveform observation targets (DUT70).

Therefore, it is desired that the clock recovery circuit used together with the sampling oscilloscope 60 can reproduce (replace) the DUT 70s having different transmission rates and reproduce the clock signal corresponding to the transmission rate of the input signal from the DUT 70. ing.

Further, at the production site of an optical device, from the viewpoint of improving productivity, it is required to shorten the waveform observation time per optical device by the sampling oscilloscope 60 as much as possible.

In response to the above-mentioned requirements, the conventional clock reproduction circuit described in Patent Document 1 is premised on inputting a signal having a known transmission rate and reproducing a clock signal having a frequency corresponding to that rate, and the transmission rate. Exchanges different DUT 70s, selectively inputs signals with different transmission rates individually output by the exchanged DUT 70, and reproduces a clock signal having a frequency corresponding to the transmission rate of the signal each time. I couldn't.

On the other hand, as a conventional clock reproduction circuit that inputs a signal whose standard rate is unknown (a signal having an arbitrary standard rate) and enables reproduction of a clock signal having a frequency matching the standard rate of the input signal, For example, a phase comparison in which a voltage control oscillator that outputs a clock signal having an oscillation frequency corresponding to an input voltage, a phase difference signal between the input signal and the clock signal is detected, and the voltage corresponding to the phase difference signal is input to the VCO. A PLL (Phase-Locked Loop) having a device is provided, and a control voltage (phase correction value) is comprehensively and sequentially set from within a predetermined voltage range until the PLL is locked, and the set phase correction value is set. In some cases, the clock signal is synchronized with the input signal by repeating the operation of sequentially shifting the phase of the clock signal input to the phase comparator.

However, in this conventional clock recovery circuit, not only a signal having an arbitrary transmission rate but also a signal having a known transmission rate, every time the signal is input, the control voltage has the same fluctuation pattern. It was necessary to repeatedly carry out the sweep control of the PLL, and the lock time of the PLL had to be long.

Therefore, in the conventional clock reproduction circuit, it takes time to observe the waveform of each object to be measured such as an optical device that outputs an input signal, and as a result, the production throughput of the object to be measured has to be reduced. I didn't.

The present invention has been made to solve such a conventional problem, and is capable of shortening the lock time for input of a signal having a known transmission rate and shortening the waveform observation time. It is an object of the present invention to provide a circuit, a waveform observation device, a clock reproduction method, and a waveform observation method.

In order to solve the above problems, the clock reproduction circuit according to claim 1 of the present invention includes a voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, an input signal, and the clock signal. The PLL circuit unit (3e) is provided with a phase comparison means (3c) that outputs a voltage corresponding to the phase difference signal of the above as the input voltage to the voltage control oscillator, and the phase is locked so that the PLL circuit unit is locked. A clock reproduction circuit that performs phase shift control of the clock signal input to the comparison means to synchronize the clock signal with the input signal, and the input signal has the transmission rate corresponding to the transmission rate. The storage means (6a) for storing the locked voltage of the PLL circuit unit, the transmission rate input means (9) for inputting the transmission rate in association with the input signal, and the transmission rate are associated with the input signal. In this case, it has a phase correction control means (5e) that executes the phase shift control using the locked voltage stored in the storage means corresponding to the transmission rate.

With this configuration, the clock reproduction circuit according to claim 1 of the present invention is locked when the clock signal is reproduced from the input signal according to the standard of the transmission rate and corresponds to the transmission rate associated with the input signal by the user. By starting the phase shift of the clock signal that reads the voltage from the storage means and inputs it to the phase comparison means, the speed until the lock of the PLL circuit section is compared with the method of comprehensively scanning the control voltage used for the phase shift. Is expected to improve.

Further, in the clock reproduction circuit according to claim 2 of the present invention, the storage means further stores the standard of the transmission rate corresponding to the transmission rate, and the transmission rate input means accepts the selection of the standard. Therefore, the transmission rate corresponding to the selected standard may be input.

With this configuration, the clock recovery circuit according to claim 2 of the present invention can input the transmission rate only by the user selecting a standard, and can improve the operability of the user.

Further, in the clock recovery circuit according to claim 3 of the present invention, the storage means may be configured to store a plurality of different locked voltage according to the same transmission rate. With this configuration, the clock reproduction circuit according to claim 3 is, for example, at the time of inputting a signal to be measured from a device such as an error rate measuring device capable of selectively outputting a plurality of signals of arbitrary transmission rates. It will be useful for shortening the lock time.

Further, in the clock reproduction circuit according to claim 4 of the present invention, the input signal is an NRZ signal having a PRBS pattern and a PAM signal, and the storage means is used for the transmission rate of the NRZ signal and the PAM signal. It is also possible to have a configuration in which the corresponding locked voltage is stored.

With this configuration, the clock regeneration circuit according to claim 4 receives a NRZ signal having a PRBS pattern and a PAM signal as input signals after inputting a transmission rate, thereby shortening the lock time for the input signal. be able to.

Further, in the clock reproduction circuit according to claim 5 of the present invention, the storage means has a transmission rate of at least 100 GbE, 200 GbE, 400 GbE, or an arbitrary transmission rate within a transmission rate range of 25.5 Gbaud to 28.2 Gbaud. It may be configured to store the corresponding locked voltage.

With this configuration, the clock recovery circuit according to claim 5 can shorten the lock time for an input signal having a transmission rate of 100 GbE, 200 GbE, and 400 GbE, and an arbitrary transmission rate within 25.5 Gbaud to 28.2 Gbaud. Will be.

Further, the clock reproduction circuit according to claim 6 of the present invention counts the number of the clock signals output by the voltage control oscillator, and the count value of the number of the clock signals by the counting is associated with the input signal. The configuration may further include a lock determination means (5e1) for determining that the PLL circuit unit is locked when the expected number of clocks corresponding to the input standard is reached.

With this configuration, the clock regeneration circuit according to claim 6 can detect the lock of the PLL circuit unit 3e in a short time and accurately, and can quickly shift to the waveform observation after the lock.

Further, the waveform observation device according to claim 7 of the present invention responds to a voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, and a phase difference signal between the input signal and the clock signal. The PLL circuit unit (3e) having a phase comparison means (3c) that outputs the input voltage to the voltage control oscillator, and inputs the voltage to the phase comparison means so that the PLL circuit unit locks. The clock reproduction circuit includes a clock reproduction circuit (3) that performs phase shift control of the clock signal to synchronize the clock signal with the input signal, and uses the measured signal output by the object to be measured (50) as the input signal. A waveform observation device that observes the waveform of the signal to be measured based on the clock signal reproduced by the clock reproduction circuit, when the signal to be measured has the transmission rate corresponding to the transmission rate. The storage means (6a) for storing the locked voltage of the PLL circuit unit, the transmission rate input means (9) for inputting the transmission rate in association with the signal to be measured, and the transmission rate are associated with the input signal. If so, it is characterized by having a phase correction control means (5e) that executes the phase shift control using the locked voltage stored in the storage means corresponding to the transmission rate.

With this configuration, the waveform observation device according to claim 7 of the present invention is associated with the measured signal by the user when the clock signal is reproduced from the measured signal in accordance with the transmission rate standard in the clock reproduction circuit. By using the lock voltage corresponding to the transmission rate (selectively input), the speed to lock of the PLL circuit section can be shortened as compared with the method of comprehensively scanning the control voltage used for the phase shift. Can be done. As a result, the waveform observation time for each object to be measured that outputs the signal to be measured can be shortened.

Further, the clock reproduction method according to claim 8 of the present invention corresponds to a voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, and a phase difference signal between the input signal and the clock signal. The phase shift control of the clock signal input to the phase comparison means is controlled so that the PLL circuit unit (3e) having the phase comparison means (3c) that outputs the input voltage to the voltage control oscillator is locked. A storage step for storing the locked voltage of the PLL circuit unit when the input signal has the transmission rate, which is a clock reproduction method for synchronizing the clock signal with the input signal. (S1), a transmission rate input step (S2) for inputting a transmission rate in association with the input signal, and when the transmission rate is associated with the input signal, in the storage step corresponding to the transmission rate. It has a configuration including a phase correction control step (S5) for executing the phase shift control using the stored locked voltage.

With this configuration, the clock reproduction method according to claim 8 of the present invention, when reproducing a clock signal from an input signal according to a transmission rate standard, is locked when the clock signal corresponds to the transmission rate associated with the input signal by the user. By starting the phase shift of the clock signal that reads the voltage from the storage means and inputs it to the phase comparator, the speed until the lock of the PLL circuit section is compared with the method of comprehensively scanning the control voltage used for the phase shift. Is expected to improve.

Further, the waveform observation method according to claim 9 of the present invention corresponds to a voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, and a phase difference signal between the input signal and the clock signal. Phase shift control of the clock signal input to the phase comparison means is performed so that the PLL circuit unit (3e) having the phase comparison means (3c) that outputs the voltage as the input voltage to the voltage control oscillator is locked. The clock reproduction method for synchronizing the clock signal with the input signal is used, and the measured signal output by the object to be measured (50) is used as the input signal, and the clock signal is reproduced based on the clock signal. It is a waveform observation method for observing the waveform of a signal to be measured, and the clock reproduction method stores the locked voltage of the PLL circuit unit when the signal to be measured has the transmission rate corresponding to the transmission rate. Storage step (S1) to be input, a transmission rate input step (S2) for inputting a transmission rate in association with the signal to be measured, and when the transmission rate is associated with the input signal to be measured, the transmission rate is set to the transmission rate. Correspondingly, it has a configuration including a phase correction control step (S5) for executing the phase shift control using the locked voltage stored in the storage step.

With this configuration, the waveform observation method according to claim 8 of the present invention locks the transmission rate associated with the input signal by the user when the clock signal is reproduced from the measured signal according to the transmission rate standard. By using the hour voltage, the speed to lock the PLL circuit unit can be shortened as compared with the method of comprehensively scanning the control voltage used for the phase shift. This makes it possible to shorten the waveform observation time for each object to be measured that outputs the signal to be measured.

The present invention can provide a clock reproduction circuit, a waveform observation device, a clock reproduction method and a waveform observation method capable of shortening the lock time for an input of a signal having a known transmission rate and shortening the waveform observation time. can.

It is an overall block diagram of the sampling oscilloscope which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the clock recovery circuit of the sampling oscilloscope which concerns on one Embodiment of this invention. It is a figure explaining the lock time shortening effect by the 2nd sweep control of the phase correction value in the clock recovery circuit of the sampling oscilloscope which concerns on one Embodiment of this invention. It is a block diagram which shows the functional structure of the control part of the sampling oscilloscope which concerns on one Embodiment of this invention. It is a table diagram which shows an example of the phase correction control table mounted on the sampling oscilloscope which concerns on one Embodiment of this invention. It is a flowchart which shows the clock reproduction processing operation of the sampling oscilloscope which concerns on one Embodiment of this invention. It is a figure which shows the structure of the conventional sampling oscilloscope for observing the waveform of an optical device.

Hereinafter, embodiments of a clock regeneration circuit, a waveform observation device, a clock regeneration method, and a waveform observation method according to the present invention will be described with reference to the drawings.

First, the configuration of the sampling oscilloscope 1 according to the embodiment of the present invention will be described with reference to FIGS. 1 to 5. The sampling oscilloscope 1 is an example of the waveform observation device according to the present invention, and has a configuration including a clock recovery circuit 3 as a clock reproduction circuit according to the present invention.

As shown in FIG. 1, the sampling oscilloscope 1 according to the present embodiment has a photoelectric converter (O / E) 2, a clock recovery circuit 3, a waveform observation unit 4, a control unit 5, a storage unit 6, an operation unit 7, and a display. The part 8 is provided.

The sampling oscilloscope 1 connects a DUT 50, inputs a data signal output by the DUT 50, generates a clock signal synchronized with the data signal from the input data signal, and observes the data signal based on the generated clock signal. Is to do.

As the DUT 50, various optical devices such as an optical transceiver having a function of passing an optical signal are used. There are many types of DUT50 that can transfer optical signals having one of a plurality of transmission rates to which each standard is assigned (standard rate: transmission rate to which the standard is assigned). Be prepared. The sampling oscilloscope 1 selectively connects various types of DUTs 50 capable of passing optical signals of each standard rate, and observes the optical signal (measured signal) output by the DUT50. ing.

In the configuration of the sampling oscilloscope 1 shown in FIG. 1, the O / E2 includes, for example, a photodiode as a photodetector, and converts an optical signal output by the DUT 50 as a signal to be measured (data signal) into an electric signal. .. O / E2 is necessary when the specification of the DUT 50 is to output an optical signal based on the input of an electric signal, and the DUT 50 is a specification to output an electric signal based on the input of the optical signal. If it is, it is not necessary.

The clock recovery (CR) circuit 3 inputs a data signal (Data) converted into an electric signal by O / E2, and reproduces and outputs a clock signal (Clock) synchronized with the data signal. As shown in FIG. 2, for example, the clock recovery circuit 3 includes a voltage controlled oscillator (VCO) 3a, a phase shifter (PS) 3b, a phase detector (PD) 3c, and a low pass filter. It has a low-pass filter (LPF) 3d.

The VCO3a outputs a signal having an oscillation frequency corresponding to the input voltage. In the present embodiment, the VCO3a inputs a voltage corresponding to a phase error signal between the phase of the data signal input from the DUT 50 and the clock signal output by the VCO3a from the phase comparator 3c via the LPF3d, and inputs the input voltage. The clock signal having the oscillation frequency corresponding to the above is output again.

The phase shift circuit 3b has a terminal 3b1 for inputting an external control voltage, and a clock from the VCO 3a based on a DC control voltage (DC input) input as a phase correction value from the control unit 5 to the terminal 3b1. The phase of the signal is shifted, and the phase-shifted clock signal is input to the phase comparator 3c.

The phase comparator 3c compares the phase of the data signal input from the DUT 50 via the O / E2 with the phase of the clock signal output from the phase shift circuit 3b after the phase shift, and outputs both phase error signals. ..

The LPF3d filters the phase error signal output by the phase comparator 3c so as to pass through and smooth only frequencies below the specified frequency, and outputs the phase error signal as the input voltage to the VCO3a. The VCO3a is adapted to re-output a clock signal having a frequency corresponding to the input voltage from the LPF3d.

In this way, the clock recovery circuit 3 detects the phase difference signal between the VCO3a that outputs the clock signal having the oscillation frequency corresponding to the input voltage and the input data signal and the clock signal output by the VCO3a, and the phase difference. It includes a PLL circuit unit 3e having a phase comparator 3c that outputs a voltage corresponding to a signal as an input voltage to the VCO3a, and an LPF3d that generates a voltage corresponding to the phase difference signal. Then, in this clock recovery circuit 3, the phase shift circuit 3b shifts the phase of the clock signal input to the phase comparator 3c according to the control voltage (DC input value) so that the PLL circuit unit 3e locks. Therefore, the clock signal is synchronized with the input data signal.

The control unit 5 controls the phase shift of the clock signal in the phase shift circuit 3b. In this control, the control unit 5 controls the sweep control of the phase correction value (DC input value) input from the terminal 3b1 to the phase shift circuit 3b when the data signal is input to the clock recovery circuit 3. Repeat until the lock of 3e is detected. More specifically, when the data signal is input, the control unit 5 sets the DC input value to the preset sweep voltage range V0 to V1 (for example, 5V range), for example, as shown in FIG. Until the circuit unit 3e is locked, the control for sequentially varying and setting the predetermined voltage width V11 (for example, 0.1 V) is repeatedly performed by the same routine each time. The setting of the sequential fluctuation of the DC input value by the sweep control here corresponds to the "comprehensive setting of the phase correction value" performed in the existing device, and is the first in the following description in the present embodiment. Sometimes called sweep control. In the present embodiment, the first sweep control is performed when the standard rate is not input in relation to the data signal input from the DUT 50, or when the data signal whose transmission rate is out of the standard is input. It has become.

In the present embodiment, the standard rate is input in relation to the data signal input from the DUT 50 for the sweep control of the DC input value, and the phase correction value related to the standard rate is stored in the phase correction control table 6a described later. If so, there is a function to directly set the phase correction value (input DC value) corresponding to the standard rate in the phase shift circuit 3b by using the phase correction control table 6a, regardless of the comprehensive setting described above. is doing. In the following, this sweep control may be referred to as a second sweep control. Here, the DC input value (phase correction value) corresponding to the standard rate is a state in which there is no phase difference between the data signal and the clock signal when the data signal having the standard rate is input, that is, the PLL circuit unit 3e. Corresponds to the control voltage value that can establish the locked state of.

In order to realize the second sweep control, the phase correction control table 6a (see FIG. 5) is stored in the storage unit 6 of the sampling oscilloscope 1. The detailed configuration of the phase correction control table 6a will be described in detail later.

The waveform observation unit 4 inputs a data signal output by the O / E2 and a clock signal output by the clock recovery circuit 3 (output when the PLL circuit unit 3e is locked), and observes the data signal based on the clock signal. It has a signal processing function.

In the present embodiment, the waveform observation unit 4 has a trigger generation unit 41, a sampler 42, and a signal waveform processing unit 43. The trigger generation unit 41 generates a strobe signal used as a sampling timing for operating the sampler 42 based on the clock signal output by the clock recovery circuit 3. The sampler 42 performs switching operation at, for example, several hundred kHz with the strobe signal generated by the trigger generation unit 41 as the sampling timing, and samples the measured signal (input data signal) converted into an electric signal by O / E2. .. The signal waveform processing unit 43 performs processing for detecting the waveform of the input data signal based on the sample data from the sampler 42.

The control unit 5 controls the operation of the entire sampling oscilloscope 1, such as operation control related to clock recovery processing in the clock recovery circuit 3 and operation control related to data signal sampling processing in the waveform observation unit 4.

As shown in FIG. 4, the control unit 5 includes a CPU 5a and an external interface (I / F) unit 5f. The CPU 5a realizes each functional unit such as a setting control unit 5b, a measurement control unit 5c, a display control unit 5d, and a phase correction control unit 5e by executing a program stored in the storage unit 6, for example.

The setting control unit 5b performs various setting processes such as setting of simulation parameters for measurement (waveform observation) of the DUT 50.

The measurement control unit 5c controls each unit related to the measurement (observation) of the measured signal, such as the detection processing of the waveform of the measured signal based on the sample data in the signal waveform processing unit 43.

The display control unit 5d performs display control for displaying the waveform of the measured signal on the display unit 8 based on the detection processing of the waveform of the measured signal by the signal waveform processing unit 43. The display control unit 5d also controls the display unit 8 to display an input screen used for selectively inputting a desired transmission rate.

The phase correction control unit 5e sets a DC input value for the phase shift circuit 3b through the terminal 3b1, and controls to shift the phase of the clock signal output from the VCO 3a based on the set input DC value. It is something to do. As described above, the phase correction control unit 5e has a configuration in which the first sweep control and the second control can be applied to the sweep of the control voltage (DC input value) related to the control of the phase shift. .. The phase correction control unit 5e is provided with a lock determination unit 5e1 for determining that the PLL circuit unit 3e is locked.

The external I / F unit 5f has an interface function when accessing an external device via the network 10. In the present embodiment, the network 10 is connected between the sampling oscilloscope 1 and the external control device 11 (see FIG. 1). It also provides an interface function for sending and receiving signals via.

In the present embodiment, the sampling oscilloscope 1 may have a system configuration in which the sampling oscilloscope 1 is operated by a command from an external control device 11 via the network 10 in addition to the operation controlled by the control unit 5 of the own device. The system operation in this case can be realized by providing the control unit (not shown) of the control device 11 with a function unit equivalent to that of the control unit 5.

The storage unit 6 includes a phase correction control unit 5e in addition to a program necessary for the CPU 5a to realize each functional unit such as a setting control unit 5b, a measurement control unit 5c, a display control unit 5d, and a phase correction control unit 5e. The phase correction control table 6a used when performing the sweep control (second sweep control) of the DC input value at the time of the clock reproduction processing is stored.

As shown in FIG. 5, for example, the phase correction control table 6a corresponds to the transmission rate standards A1, A2, A3, A4, ... Of the signal to be measured that can be output by the DUT 50, and the transmission rate Tr1. It has data contents in which Tr2, Tr3, Tr4, ... And phase correction values V21, V22, V23, V24, ... Are stored. Here, the phase correction values (DC input values) V21, V22, V23, V24, ... Are, for example, 0.1V (volt), 0.2V, 0.3V, 0.4V, ..., respectively. It has become.

In the phase correction control table 6a, the signal types to which the standards A1, A2, A3, A4, ... Are assigned include NRZ (Non Return to Zero) signals having different signal patterns, and PAM (Pulse Amplitude Modulation: Pulse-). Amplitude Modulation) 4 and PAM8 and the like. Regarding the above signal pattern, for evaluation of the NRZ signal, for example, PRBS7 (pattern length: 2 ⁷ -1), PRBS 9 (pattern length: 2 ⁹ -1), PRBS 10 (pattern length: 2 ¹⁰ -1), PRBS 11 Pseudo-random (PRBS (Pseudo Random Binary Sequence: PRBS) patterns such as (pattern length: 2 ¹¹ -1), PRBS 15 (pattern length: 2 ¹⁵ -1), PRBS 20 (pattern length: 2 ²⁰ -1), etc. can be mentioned. Further, for PAM evaluation, there are patterns such as PRBS13Q, PRQS10, and SSPR.

Further, in the phase correction control table 6a, the transmission rates Tr1, Tr2, Tr3, Tr4, ... Corresponding to each of the above standards are, for example, 100 GbE (Gigabit Ethernet: Gigabit Ethernet) which is a standard of Ethernet (registered trademark). , 200 GBe, 400 GBe and the like. Further, as another standard rate, for example, an arbitrary transmission rate within the transmission rate range of 25.5 Gbad to 28.2 Gbaud can be mentioned.

Further, in the phase correction control table 6a, the phase correction values V21, V22, V23, V24, ... Are the clocks output from the data signal and VCO3a when the data signal of each standard rate described above is input. This corresponds to the DC input value (locked voltage) when the phase difference of the signal disappears, that is, when the PLL circuit unit 3e is locked. These locked voltages can be obtained by a mock measurement test conducted in advance following actual waveform observation. That is, in the simulated measurement test, while the simulated data signals of each standard rate are sequentially input to the clock recovery circuit 3, the first sweep control regarding the DC input value is performed for each standard rate, and each of them is the PLL circuit unit 3e. Gets the DC input value when locked. Then, the acquired DC input value is saved, and in the table setting mode described later, the saved DC input value is registered in association with each standard to create the phase correction control table 6a (see FIG. 5). Can be set (generated).

The phase correction control table 6a may have data contents in which one or more locked voltages (phase correction values) are registered for the same standard rate. The phase correction control table 6a of this type uses, for example, a device such as an error rate measuring device or a mobile wireless communication device capable of outputting signals of a plurality of arbitrary transmission rates as the DUT 50, and is used from the device. It is useful for shortening the lock time when observing the waveform of a signal that is selectively output.

As described above, the phase correction control table 6a is a data signal (measured signal) of the standard for each data signal (NRZ signal, PAM4 signal, PAM8 signal, etc.) input from the DUT 50 to the clock recovery circuit 3. The locked voltage when is input is registered. When the voltage range related to the first sweep control described above is V0 to V1 (see FIG. 3), the locked voltages V21, V22, V23, V24, ... Registered in the phase correction control table 6a are It is a voltage value within the voltage range of V0 to V1.

The operation unit 7 is composed of an operation panel such as a switch or a button. The operation panel may have a touch panel function. The operation unit 7 is necessary for instructing the start and stop of the clock regeneration process performed before the waveform observation of the DUT 50, instructing the start and stop of the waveform observation of the DUT 50 after that, and performing a desired display on the display unit 8. The configuration is such that various settings necessary for waveform measurement of the DUT 50, including settings of various information, can be selectively executed. In the present embodiment, the operation unit 7 receives a selection operation for selecting a desired standard from a plurality of standards displayed on the input screen while the above-mentioned input screen is displayed on the display unit 8, and the operation unit 7 receives the selection operation. The configuration is such that the transmission rate corresponding to the selected standard can be input by the selection operation. As described above, the operation unit 7 constitutes the transmission rate input means 9 (see FIG. 4) together with the display unit 8 and the display control unit 5d.

The display unit 8 is composed of a display such as a liquid crystal panel, and displays various information related to the waveform measurement of the DUT 50 including the clock recovery process. In the present embodiment, the display unit 8 displays the input screen constituting the transmission rate input means 9 described above under the control of the display control unit 5d.

Next, the operation of the sampling oscilloscope 1 having the above-described configuration will be described. The sampling oscilloscope 1 has a table setting mode, a phase correction control mode, and a waveform observation mode. In the table setting mode, the display control unit 5d displays a UI screen for setting the standard and transmission rate of the signal to be measured on the display unit 8, and on the UI screen, for example, an input operation on the operation unit 7 or the like. Therefore, the phase correction control table 6a can be set using the DC input value acquired and held in the simulated measurement test described above.

In the phase correction control mode, first, before inputting the data signal (measured signal) for waveform observation from the DUT 50, the display control unit 5d displays an input screen for inputting the transmission rate of the measured signal on the display unit 8. Is displayed. By selecting a desired standard on the input screen by a predetermined selection operation on the operation unit 7, the user can input the transmission rate corresponding to the selected standard in association with the signal to be measured. ..

Further, in the phase correction control mode, after selecting the standard rate described above, the user performs a phase correction start operation, for example, in the operation unit 7, so that the data signal (measured signal) from the DUT 50 to be observed in the waveform is input. Then, the above-mentioned second sweep control using the locked voltage stored in the phase correction control table 6a corresponding to the input transmission rate is started.

By this second sweep control, the clock recovery circuit 3 can reproduce the clock signal synchronized with the input data signal (symbol synchronization) in a short time, and the lock time can be shortened. In the symbol synchronization, in the sampling oscilloscope 1, the data signal input from the DUT 50 is processed by the signal waveform processing unit 43 of the waveform observation unit 4, and the waveform at the most open moment of the eye pattern can be displayed on the display unit 8. Synchronized state.

As the reproduction time of the clock signal in the phase correction control mode is shortened, it becomes possible to quickly shift to the waveform observation mode after the phase correction control mode. In the waveform observation mode, the waveform observation unit 4 performs signal processing using a clock signal that synchronizes the data signal input from the DUT 50 with the data signal, and displays the waveform of the processed signal on the display unit 8. Will be.

Hereinafter, the clock recovery processing operation of the sampling oscilloscope 1 according to the present embodiment will be described with reference to the flowchart shown in FIG. In this clock recovery process, first, the table setting mode is set, and the setting control unit 5b sets the phase correction control table 6a used for the sweep control of the DC input value according to the operation input from the operation unit 7 by the method described above. Set (step S1).

After that, when the phase correction control mode is set, the phase correction control unit 5e performs a process of receiving the transmission rate input by the transmission rate input means 9 and the phase correction control start operation from the operation unit 7 (step S2). ..

When the input of the transmission rate is accepted and the phase correction control start operation is further accepted, the phase correction control unit 5e starts taking in the input signal (measured signal) from the DUT 50 (step S3).

Subsequently, the phase correction control unit 5e checks whether or not the transmission rate is associated with the input signal. Specifically, the phase correction control unit 5e determines whether or not the transmission rate input in step S2 is a standard rate stored in the phase correction control table 6a (step S4).

Here, when it is determined that the input transmission rate is the standard rate (YES in step S4), the phase correction control unit 5e stores in the phase correction control table 6a corresponding to the input standard rate. The phase correction value (locked voltage) is read out and set in the phase shift circuit 3b, and the above-mentioned second sweep control is performed (step S5).

In the second sweep control, the phase correction control unit 5e shifts the phase of the clock signal output from the VCO 3a from the lock voltage set as the DC input value as the base point, and causes the phase shift circuit 3b to input the phase. The phase shift circuit 3b is controlled. After performing the second sweep control in step S5, the phase correction control unit 5e shifts to step S7.

On the other hand, when it is determined that the input transmission rate is not the standard rate (the input signal is an arbitrary transmission rate) (NO in step S4), the phase correction control unit 5e uses the first sweep described above. Control is carried out (step S6).

In this first sweep control, the phase correction control unit 5e performs a sweep control for comprehensively and sequentially setting each phase correction value of the voltage width V11 in the voltage range V0 to V1 described above with respect to the phase shift circuit 3b. Then, the shift circuit 3b is controlled so that the phase of the clock signal output from the VCO 3a is sequentially shifted based on the set phase correction value and input to the phase comparator 3c. After performing the first sweep control in step S6, the phase correction control unit 5e shifts to step S7.

In step S7, the phase correction control unit 5e determines whether or not the PLL circuit unit 3e is locked by the second sweep control in step S5 or the first sweep control in step S6. I do.

In order to enable determination as to whether or not the clock is locked, the storage unit 6 contains clock signals corresponding to the transmission rates (standard rates) registered in the phase correction control table 6a in addition to the phase correction control table 6a. The number (number within a predetermined period) is stored in advance as an expected value. The expected value depends on the transmission rate of the data signal.

In step S6, the lock determination unit 5e1 of the phase correction control unit 5e captures and counts the clock signal output from the VCO3a as the lock confirmation clock signal, and the count value of the lock confirmation clock signal within a predetermined period is expected. If the values match, it is determined that the lock has been established, and if they do not match, it is determined that the lock has not been established.

When it is determined that the PLL circuit unit 3e is not locked based on the count value of the lock confirmation clock signal (NO in step S7), the phase correction control unit 5e continues the lock confirmation process.

During this period, if it is determined that the PLL circuit unit 3e is locked (YES in step S7), the phase correction control unit 5e fixes the phase correction value of the phase shift circuit 3b to the value at the time when the lock is confirmed (step). S8), control is performed so that the output of the VCO3a at this time is output from the clock recovery circuit 3 as a clock signal synchronized with the data signal input in step S2 (step S8).

After the lock is confirmed in step S7, the sampling oscilloscope 1 shifts to the waveform observation mode by the user's waveform observation mode setting operation, and the waveform observation unit 4 uses the clock signal supplied from the clock recovery circuit 3 to use the clock signal. The waveform observation process (step S11) of the data signal branched in the previous stage of the clock recovery circuit 3 can be executed.

According to the series of clock regeneration processes shown in FIG. 6, when the transmission rate is not input in association with the data signal (measured signal) input from the DUT 50, the first sweep control is performed in step S6. .. In the first sweep control, for example, as shown in FIG. 3, control is performed in which the DC input value is comprehensively set by varying it for each voltage width V11 within the voltage range V0 to V1, for example. It tends to take a long time (for example, t1) to find the hourly voltage value.

On the other hand, when the transmission rate is input in association with the measured signal input from the DUT 50, the second sweep control is performed in step S5. In the second sweep control, the locked voltage corresponding to the selected transmission rate is set directly from the phase correction control table 6a to the phase shift circuit 3b, so that the DC input values related to the first sweep control are comprehensively set. No need for setting control.

Here, for example, assuming that the locked voltage of the PLL circuit unit 3e when a signal to be measured of a certain standard, which is acquired by a simulated measurement test, is V21 in FIG. 3, this signal to be measured is used. In the clock recovery reproduction process shown in FIG. 6 when input from the DUT 50, the locked voltage V21 is directly set in the phase shift circuit 3b from the phase correction control table 6a in step S5. At this time, the time t2 until the PLL circuit unit 3e locks is ideally 0 (zero), which is significantly larger than the time until the locked voltage value is found by the first sweep control (for example, t1). Will be shortened to.

In the above embodiment, an example is given in which the transmission rate of the signal to be measured is input by inputting (selecting) a standard by using the data structure shown in FIG. 5 for the configuration of the phase correction control table 6a. The present invention is not limited to this, and may be configured to directly input the transmission rate of the signal to be measured.

Further, in the above embodiment, the control unit 5 of the sampling oscilloscope 1 is provided with a control function for setting a phase correction value stored in association with the standard or transmission rate according to the input standard or transmission rate. Although an example is given, the present invention is not limited to this, and the control function may be mounted on an external control device 11 and the phase correction control of the sampling oscilloscope 1 may be performed from the control device 11 via the network 10.

Further, in the above embodiment, the configuration in which the sampling oscilloscope 1 includes the clock recovery circuit 3 is exemplified, but the configuration may be such that the clock recovery circuit 3 is arranged outside the sampling oscilloscope 1.

Further, in the above embodiment, an example of mainly processing a signal from an optical device has been mainly described, but the present invention has been made from various devices or modules capable of transmitting a signal to be measured, such as an error rate measuring device. It is possible to input the signal of the above and perform clock reproduction processing and waveform observation processing from the input signal.

As described above, the clock recovery circuit 3 according to the present embodiment inputs a VCO3a that outputs a clock signal having an oscillation frequency corresponding to the input voltage and a voltage corresponding to the phase difference signal between the input signal and the clock signal. A PLL circuit unit 3e having a phase comparator 3c to output to the VCO 3a is provided, and a control is performed to shift the phase of the clock signal input to the phase comparator 3c so that the PLL circuit unit 3e is locked to obtain a clock signal. A phase correction control table 6a that synchronizes with the input signal and stores the locked voltage (phase correction value) of the PLL circuit unit 3e when the input signal has the transmission rate corresponding to the transmission rate. When the transmission rate input means 9 for inputting the transmission rate in association with the input signal and the transmission rate are associated with the input signal, the locked voltage stored in the phase correction control table 6a corresponding to the transmission rate is used. It has a phase correction control unit 5e that executes phase shift control of a clock signal input to the phase comparator 3c.

With this configuration, the clock recovery circuit 3 according to the present embodiment is associated with the input signal by the user when the clock signal is reproduced from the input signal according to the standard of the transmission rate (the transmission rate is associated). That is, the control voltage used for the phase shift is started by reading the locked lock voltage corresponding to the selectively input transmission rate from the phase correction control table 6a and starting the phase shift of the clock signal input to the phase comparator 3c. It is expected that the speed up to the lock of the PLL circuit unit 3e will be improved as compared with the method of comprehensively scanning. Further, according to this configuration, it is possible to suppress the storage capacity of information related to the control voltage used for the phase shift and reduce the cost of the circuit configuration.

Further, in the clock recovery circuit 3 according to the present embodiment, the phase correction control table 6a further stores the standard of the transmission rate corresponding to the transmission rate, and the transmission rate input means 9 accepts the selection of the standard. The configuration is such that the transmission rate corresponding to the selected standard is input. With this configuration, the clock recovery circuit 3 according to the present embodiment can input the transmission rate only by the user selecting a standard, and can improve the operability of the user.

Further, in the clock recovery circuit 3 according to the present embodiment, the phase correction control table 6a may be configured to store a plurality of different locked lock voltages corresponding to the same transmission rate. With this configuration, in the clock recovery circuit 3, for example, the lock time at the time of inputting a signal to be measured from a device such as an error rate measuring device capable of selectively outputting a plurality of signals of an arbitrary transmission rate can be shortened. It will be useful.

Further, in the clock recovery circuit 3 according to the present embodiment, the input signals are an NRZ signal having a PRBS pattern and a PAM signal, and the phase correction control table 6a is a lock corresponding to the transmission rate of the NRZ signal and the PAM signal. It has a configuration that stores the hour voltage.

With this configuration, the clock recovery circuit 3 according to the present embodiment receives the NRZ signal having the PRBS pattern and the PAM signal as the input signal after inputting the transmission rate, thereby shortening the lock time for the input signal. can do.

Further, in the clock recovery circuit 3 according to the present embodiment, the phase correction control table 6a has a transmission rate of at least 100 GbE, 200 GbE, and 400 GbE, or an arbitrary transmission rate within a transmission rate range of 25.5 Gbaud to 28.2 Gbaud. Each stores the corresponding locked voltage.

With this configuration, the clock recovery circuit 3 according to the present embodiment can shorten the lock time for an input signal having a transmission rate of 100 GbE, 200 GbE, or 400 GbE, and an arbitrary transmission rate within 25.5 Gbaud to 28.2 Gbaud. It will be possible.

Further, in the clock recovery circuit 3 according to the present embodiment, the control unit 5 and the phase correction control unit 5e count the number of clock signals output by the VCO 3a, and the counted values are input in association with the input signal. It has a lock determination unit 5e1 that determines that the PLL circuit unit 3e has locked when the expected value clock number corresponding to the transmission rate (standard) is reached. With this configuration, the clock recovery circuit 3 according to the present embodiment can detect the lock of the PLL circuit unit 3e in a short time and accurately, and can quickly shift to the waveform observation after the lock.

Further, the sampling oscilloscope 1 according to the present embodiment includes the clock recovery circuit 3 having the above-described configuration, and the waveform of the DUT 50 is based on the clock signal reproduced by the clock recovery circuit 3 with the measured signal output by the DUT 50 as an input signal. The clock recovery circuit 3 is used for observation, and the clock recovery circuit 3 includes a phase correction control table 6a for storing the locked voltage of the PLL circuit unit 3e when the DUT 50 has the transmission rate, and the DUT 50. When the transmission rate input means 9 for inputting the transmission rate in association with the transmission rate and the transmission rate are associated with the input signal, the phase is used by using the locked voltage stored in the phase correction control table 6a corresponding to the transmission rate. It is configured to include a phase correction control unit 5e that executes shift control.

With this configuration, the sampling oscilloscope 1 according to the present embodiment is used by the user when the clock signal is reproduced from the measured signal (with which the transmission rate is associated) in accordance with the transmission rate standard in the clock recovery circuit 3. The PLL circuit unit 3e is compared with the method of comprehensively scanning the control voltage used for the phase shift by using the lock voltage associated with the input signal, that is, corresponding to the selectively input transmission rate. The speed to lock can be reduced. This makes it possible to shorten the waveform observation time per DUT 50 that outputs the signal to be measured and improve the production throughput of the DUT 50. Further, according to this configuration, it is possible to suppress the storage capacity of information related to the control voltage used for the phase shift and reduce the cost of the circuit configuration.

Further, in the clock reproduction method according to the present embodiment, a VCO3a that outputs a clock signal having an oscillation frequency corresponding to an input voltage and a voltage corresponding to a phase difference signal between the input signal and the clock signal are output to the VCO3a as an input voltage. This is a clock reproduction method in which the phase shift control of the clock signal input to the phase comparator 3c is performed to synchronize the clock signal with the input signal so that the PLL circuit unit 3e having the phase comparator 3c is locked. A storage step (S1) for storing the locked voltage of the PLL circuit unit 3e when the input signal has the transmission rate corresponding to the rate, and a transmission rate input step (S2) for inputting the transmission rate in association with the input signal. ), And when a transmission rate is associated with the input signal, a phase correction control step (S5) that executes phase shift control using the locked lock voltage stored in the storage step corresponding to the transmission rate. It is a configuration including.

With this configuration, in the clock reproduction method according to the present embodiment, when the clock signal is reproduced from the input signal according to the transmission rate standard, the locked voltage corresponding to the selected transmission rate is obtained from the phase correction control table 6a. By starting the phase shift of the clock signal read out and input to the phase comparator 3c, the speed up to the lock of the PLL circuit unit 3e is improved as compared with the method of comprehensively scanning the control voltage used for the phase shift. You can expect it.

Further, in the waveform observation method according to the present embodiment, the VCO3a that outputs a clock signal having an oscillation frequency corresponding to the input voltage and the voltage corresponding to the phase difference signal between the input signal and the clock signal are used as input voltages in the VCO3a. A clock reproduction method is used in which the phase shift control of the clock signal input to the phase comparator 3c is performed so that the PLL circuit unit 3e having the phase comparator 3c to output is locked, and the clock signal is synchronized with the input signal. This is a method of observing the waveform of the measured signal based on the clock signal reproduced by the above clock reproduction method using the measured signal output by the clock as an input signal, and the clock reproduction method corresponds to the transmission rate and is measured. A storage step (S1) for storing the locked voltage of the PLL circuit unit 3e when the signal has the transmission rate, a transmission rate input step (S2) for inputting the transmission rate in association with the signal to be measured, and a subject to be input. When a transmission rate is associated with the measurement signal, a phase correction control step (S5) that executes phase shift control using the locked lock voltage stored in the storage step corresponding to the transmission rate input to the transmission rate. ) And.

With this configuration, the waveform observation method according to the present embodiment uses the locked voltage corresponding to the selected transmission rate when reproducing the clock signal from the measured signal according to the transmission rate standard, thereby performing the phase. Compared with the method of comprehensively scanning the control voltage used for the shift, the speed to lock the PLL circuit unit 3e can be shortened. This makes it possible to shorten the waveform observation time per DUT 50 that outputs the signal to be measured and improve the production throughput of the DUT 50. Further, according to this configuration, it is possible to suppress the storage capacity of information related to the control voltage used for the phase shift and reduce the cost of the circuit configuration.

As described above, the clock reproduction circuit, the waveform observation device, the clock reproduction method, and the waveform observation method according to the present invention shorten the lock time for the input of a signal having a known transmission rate, and also shorten the waveform observation time. The clock reproduction circuit and waveform used to input only the waveform observation signal from the object to be measured, reproduce the clock signal from the input signal, and observe the waveform of the input signal. It is useful for observation equipment, clock reproduction methods, and waveform observation methods in general.

1 Sampling oscilloscope (waveform observation device)
3 Clock recovery circuit (clock regeneration circuit)
3a Voltage Controlled Oscillator (VCO)
3b phase shift circuit 3c phase detector (PD) (phase comparison means)
3e PLL (Phase-Locked Loop) circuit unit 5 control unit 5e phase correction control unit (phase correction control means)
5e1 lock determination unit (lock determination means)
6a Phase correction control table (storage means)
9 Transmission rate input means 50 Object to be measured (DUT)

Claims (9)

A voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, and a phase that outputs a voltage corresponding to a phase difference signal between the input signal and the clock signal to the voltage control oscillator as the input voltage. The PLL circuit unit (3e) having the comparison means (3c) is provided, and the phase shift control of the clock signal input to the phase comparison means is performed so that the PLL circuit unit is locked, and the clock signal is input. It is a clock reproduction circuit that synchronizes with a signal.
A storage means (6a) for storing the locked voltage of the PLL circuit unit when the input signal has the transmission rate corresponding to the transmission rate, and
A transmission rate input means (9) for inputting a transmission rate in association with the input signal, and
When the transmission rate is associated with the input signal, the phase correction control means (5e) that executes the phase shift control using the locked voltage stored in the storage means corresponding to the transmission rate. When,
A clock recovery circuit characterized by having. The storage means further stores the standard of the transmission rate corresponding to the transmission rate.
The clock recovery circuit according to claim 1, wherein the transmission rate input means accepts a selection of the standard and inputs the transmission rate corresponding to the selected standard. The clock recovery circuit according to claim 1 or 2, wherein the storage means stores a plurality of different locked voltage corresponding to the same transmission rate. The input signal is an NRZ signal having a PRBS pattern and a PAM signal.
The clock regeneration circuit according to any one of claims 1 to 3, wherein the storage means stores the locked voltage corresponding to the transmission rate of the NRZ signal and the PAM signal. The storage means is characterized in that it stores the locked voltage corresponding to at least 100 GbE, 200 GbE, 400 GbE transmission rates, or any transmission rate within the transmission rate range of 25.5 Gbaud to 28.2 Gbaud. The clock regeneration circuit according to any one of claims 1 to 4. The number of the clock signals output by the voltage controlled oscillator is counted, and the count value of the number of the clock signals by the counting becomes the expected value clock number corresponding to the standard input in association with the input signal. The clock reproduction circuit according to any one of claims 1 to 4, further comprising a lock determination means (5e1) for determining that the PLL circuit unit is locked. A voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, and a phase that outputs a voltage corresponding to a phase difference signal between the input signal and the clock signal to the voltage control oscillator as the input voltage. The PLL circuit unit (3e) having the comparison means (3c) is provided, and the phase shift control of the clock signal input to the phase comparison means is performed so that the PLL circuit unit is locked, and the clock signal is input. The measured signal includes the clock reproduction circuit (3) synchronized with the signal, and the measured signal output by the object to be measured (50) is used as the input signal, and the measured signal is reproduced based on the clock signal reproduced by the clock reproduction circuit. It is a waveform observation device that observes waveforms.
The clock recovery circuit is
A storage means (6a) for storing the locked voltage of the PLL circuit unit when the signal to be measured has the transmission rate corresponding to the transmission rate, and
A transmission rate input means (9) for inputting a transmission rate in association with the signal to be measured, and a transmission rate input means (9).
When the transmission rate is associated with the input signal, the phase correction control means (5e) that executes the phase shift control using the locked voltage stored in the storage means corresponding to the transmission rate. When,
A waveform observation device characterized by having. A voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, and a phase that outputs a voltage corresponding to a phase difference signal between the input signal and the clock signal to the voltage control oscillator as the input voltage. A clock reproduction method for synchronizing the clock signal with the input signal by performing phase shift control of the clock signal input to the phase comparison means so that the PLL circuit unit (3e) having the comparison means (3c) is locked. And,
A storage step (S1) for storing the locked voltage of the PLL circuit unit when the input signal has the transmission rate corresponding to the transmission rate,
A transmission rate input step (S2) for inputting a transmission rate in association with the input signal, and
When the transmission rate is associated with the input signal, the phase correction control step (S5) for executing the phase shift control using the locked voltage stored in the storage step corresponding to the transmission rate. When,
A clock recovery method characterized by including. A voltage control oscillator (3a) that outputs a clock signal having an oscillation frequency corresponding to an input voltage, and a phase that outputs a voltage corresponding to a phase difference signal between the input signal and the clock signal to the voltage control oscillator as the input voltage. A clock reproduction method for synchronizing the clock signal with the input signal by performing phase shift control of the clock signal input to the phase comparison means so that the PLL circuit unit (3e) having the comparison means (3c) is locked. Is a waveform observation method for observing the waveform of the measured signal based on the clock signal reproduced by the clock reproduction method using the measured signal output by the object to be measured (50) as the input signal. ,
The clock recovery method is
A storage step (S1) for storing the locked voltage of the PLL circuit unit when the signal to be measured has the transmission rate corresponding to the transmission rate,
A transmission rate input step (S2) for inputting a transmission rate in association with the signal to be measured, and a transmission rate input step (S2).
When the transmission rate is associated with the input signal to be measured, the phase correction control step for executing the phase shift control using the locked voltage stored in the storage step corresponding to the transmission rate. (S5) and
A waveform observation method characterized by including.

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