JP7045052B2 - Semiconductor mounting method - Google Patents
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- JP7045052B2 JP7045052B2 JP2018016426A JP2018016426A JP7045052B2 JP 7045052 B2 JP7045052 B2 JP 7045052B2 JP 2018016426 A JP2018016426 A JP 2018016426A JP 2018016426 A JP2018016426 A JP 2018016426A JP 7045052 B2 JP7045052 B2 JP 7045052B2
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
- H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
- H10W72/01336—Manufacture or treatment of die-attach connectors using blanket deposition in solid form, e.g. by using a powder or by laminating a foil
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07232—Compression bonding, e.g. thermocompression bonding
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/221—Structures or relative sizes
- H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本発明は、フィルム状半導体封止材を用いた半導体実装方法に関する。 The present invention relates to a semiconductor mounting method using a film-shaped semiconductor encapsulant.
半導体チップと基板との間の狭ギャップ化の要請に対応するため、フィルム状半導体封止材を用いた半導体実装方法が提案されている。 In order to meet the demand for narrowing the gap between the semiconductor chip and the substrate, a semiconductor mounting method using a film-shaped semiconductor encapsulant has been proposed.
フィルム状半導体封止材を用いた半導体実装方法は以下の手順で実施される。
(1)回路面に電極をする半導体ウエハに対し、一方の面にフィルム状半導体封止材をラミネートする。
(2)半導体ウエハをダイシングして個片化する。
(3)個片化した半導体ウエハ(半導体チップ)のフィルム状半導体封止材がラミネートされた側の面を、フリップチップボンダー等を用いて、基板に対し加熱圧接(Thermal Compression Bonding:TCB)する。
The semiconductor mounting method using the film-shaped semiconductor encapsulant is carried out by the following procedure.
(1) A film-shaped semiconductor encapsulant is laminated on one surface of a semiconductor wafer having electrodes on the circuit surface.
(2) The semiconductor wafer is diced and separated into individual pieces.
(3) The surface of the fragmented semiconductor wafer (semiconductor chip) on which the film-shaped semiconductor encapsulant is laminated is thermocompression bonded (TCB) to the substrate using a flip chip bonder or the like. ..
フィルム状半導体封止材を用いた半導体実装においては、良好な接合性とボイドなどの欠陥がない封止状態が求められる。これら不具合のない封止状態を達成するためのフィルム状半導体封止材組成や実装方法が提案されており、ボイド欠陥を無くすため、TCBの実施後、加圧雰囲気下にてフィルム状半導体封止材を硬化させる手法も検討されている(特許文献1参照)。 In semiconductor mounting using a film-shaped semiconductor encapsulant, good bondability and a sealed state without defects such as voids are required. Film-shaped semiconductor encapsulant compositions and mounting methods have been proposed to achieve these defect-free encapsulation states. In order to eliminate void defects, film-like semiconductor encapsulation is performed under a pressurized atmosphere after TCB. A method of curing the material is also being studied (see Patent Document 1).
TCBの実施後、加圧雰囲気下にてフィルム状半導体封止材を硬化させる手法は、ボイド欠陥なく硬化させるために効果的であるが、硬化前のボイド体積が大きすぎると十分な効果を得ることができないことが明らかになった。
このような不具合発生を防止するために、加圧雰囲気下での硬化の効果をより確実にし、不具合を発生させない半導体実装方法を提供することを課題とする。
The method of curing the film-like semiconductor encapsulant under a pressurized atmosphere after the TCB is performed is effective for curing without void defects, but a sufficient effect is obtained if the void volume before curing is too large. It became clear that it could not be done.
In order to prevent such defects from occurring, it is an object of the present invention to provide a semiconductor mounting method that more reliably cures under a pressurized atmosphere and does not cause defects.
本願発明は、フィルム状半導体封止材を、はんだを含む突起電極が形成された半導体チップ上へラミネートした後、基板に対しフィルム状半導体封止材を加熱圧接し、その後、前記フィルム状半導体封止材を加熱硬化させて半導体チップを前記基板へ実装する半導体装置の実装方法において、
前記フィルム状半導体封止材の厚みが、前記突起電極の高さの0.8倍以上1.3倍以下であり、
前記半導体チップにラミネートされた前記半導体封止材面の最高高さと、最低高さとの差が2.2μm以下であり
ラミネーション圧力が0.1MPa以上0.8MPa以下であり、
前記加熱硬化が0.4MPa以上の加圧雰囲気下で実施される半導体装置の実装方法(1)を提供する。
In the present invention, the film-shaped semiconductor encapsulant is laminated on a semiconductor chip on which a protruding electrode containing solder is formed, the film-shaped semiconductor encapsulant is heat-pressed against the substrate, and then the film-shaped semiconductor encapsulant is sealed. In a method of mounting a semiconductor device in which a stop material is heat-cured and a semiconductor chip is mounted on the substrate.
The thickness of the film-shaped semiconductor encapsulant is 0.8 times or more and 1.3 times or less the height of the protruding electrode.
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor chip is 2.2 μm or less, and the lamination pressure is 0.1 MPa or more and 0.8 MPa or less.
Provided is a method (1) for mounting a semiconductor device in which the heat curing is carried out in a pressurized atmosphere of 0.4 MPa or more.
また、本願発明は、フィルム状半導体封止材を、はんだを含む突起電極が形成された半導体ウエハ上へラミネートし、基板に対し前記フィルム状半導体封止材を加熱圧接し、その後、前記フィルム状半導体封止材を加熱硬化させて半導体チップを前記基板へ実装する半導体装置の実装方法において、
前記フィルム状半導体封止材がラミネートされた半導体ウエハを個片化する工程、
個片化された半導体チップを基板電極と位置合わせをする工程、
位置合わせされた半導体チップと、基板とを加熱しながら圧接する工程、および
圧接後に圧力雰囲気下にてフィルム状半導体封止材を加熱硬化する工程を有し、
前記フィルム状半導体封止材の厚みが、前記突起電極の高さの0.8倍以上1.3倍以下であり、
前記半導体ウエハにラミネートされ、その後、個片化された前記半導体封止材面の最高高さと最低高さとの差が2.2μm以下であり、
ラミネーション圧力が0.1MPa以上0.8MPa以下であり、
前記加熱硬化が0.4MPa以上の加圧雰囲気下で実施される半導体装置の実装方法
(2)を提供する。
Further, in the present invention, the film-shaped semiconductor encapsulant is laminated on a semiconductor wafer on which a protruding electrode containing solder is formed, the film-shaped semiconductor encapsulant is heat-pressed against a substrate, and then the film-shaped semiconductor encapsulant is heat-pressed. In a method for mounting a semiconductor device in which a semiconductor encapsulant is heat-cured and a semiconductor chip is mounted on the substrate.
The process of individualizing a semiconductor wafer laminated with the film-shaped semiconductor encapsulant.
The process of aligning the individualized semiconductor chip with the substrate electrode,
It has a step of pressure-welding the aligned semiconductor chip and the substrate while heating, and a step of heat-curing the film-shaped semiconductor encapsulant under a pressure atmosphere after the pressure welding.
The thickness of the film-shaped semiconductor encapsulant is 0.8 times or more and 1.3 times or less the height of the protruding electrode.
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor wafer and then separated into pieces is 2.2 μm or less.
The lamination pressure is 0.1 MPa or more and 0.8 MPa or less.
Provided is a method (2) for mounting a semiconductor device in which the heat curing is carried out in a pressurized atmosphere of 0.4 MPa or more.
また、本願発明は、フィルム状半導体封止材を、はんだを含む突起電極が形成された半導体ウエハ上へラミネートし、基板に対し前記フィルム状半導体封止材を加熱圧接し、その後、前記フィルム状半導体封止材を加熱硬化させて半導体チップを前記基板へ実装する半導体装置の実装方法において、
前記フィルム状半導体封止材がラミネートされた半導体ウエハの厚みを研磨によって薄くする工程、
前記フィルム状半導体封止材がラミネートされた半導体ウエハを個片化する工程、
個片化された半導体チップを基板電極と位置合わせをする工程、
位置合わせされた半導体チップと、基板とを加熱しながら圧接する工程、および、
圧接後に圧力雰囲気下にてフィルム状半導体封止材を加熱硬化する工程を有し、
前記フィルム状半導体封止材の厚みが、前記突起電極の高さの0.8倍以上1.3倍以下であり、
前記半導体ウエハにラミネートされ、その後、個片化された前記半導体封止材面の最高高さと最低高さとの差が2.2μm以下であり、
ラミネーション圧力が0.1MPa以上0.8MPa以下であり、
前記加熱硬化が0.4MPa以上の加圧雰囲気下で実施される半導体装置の実装方法(3)を提供する。
Further, in the present invention, the film-shaped semiconductor encapsulant is laminated on a semiconductor wafer on which a protruding electrode containing solder is formed, the film-shaped semiconductor encapsulant is heat-pressed against a substrate, and then the film-shaped semiconductor encapsulant is heat-pressed. In a method for mounting a semiconductor device in which a semiconductor encapsulant is heat-cured and a semiconductor chip is mounted on the substrate.
A step of reducing the thickness of a semiconductor wafer on which the film-shaped semiconductor encapsulant is laminated by polishing.
The process of individualizing a semiconductor wafer laminated with the film-shaped semiconductor encapsulant.
The process of aligning the individualized semiconductor chip with the substrate electrode,
The process of pressure-welding the aligned semiconductor chip and the substrate while heating, and
It has a step of heating and curing the film-like semiconductor encapsulant under a pressure atmosphere after pressure welding.
The thickness of the film-shaped semiconductor encapsulant is 0.8 times or more and 1.3 times or less the height of the protruding electrode.
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor wafer and then separated into pieces is 2.2 μm or less.
The lamination pressure is 0.1 MPa or more and 0.8 MPa or less.
Provided is a method (3) for mounting a semiconductor device in which the heat curing is carried out in a pressurized atmosphere of 0.4 MPa or more.
本発明の半導体実装方法(1)~(3)において、前記突起電極が半導体チップ面上、若しくは半導体ウエハ面上に銅層、はんだ層の順に積層された構造を有することが好ましい。 In the semiconductor mounting methods (1) to (3) of the present invention, it is preferable that the protruding electrodes have a structure in which a copper layer and a solder layer are laminated in this order on a semiconductor chip surface or a semiconductor wafer surface.
本発明の半導体実装方法(1)~(3)において、前記突起電極の高さが5μm以上50μm以下であることが好ましい。 In the semiconductor mounting methods (1) to (3) of the present invention, the height of the protruding electrode is preferably 5 μm or more and 50 μm or less.
本発明の半導体実装方法(1)~(3)によれば、ボイド欠陥等の不具合を防止し、確実な接続を達成できる。 According to the semiconductor mounting methods (1) to (3) of the present invention, defects such as void defects can be prevented and a reliable connection can be achieved.
以下、本発明について詳細に説明する。 Hereinafter, the present invention will be described in detail.
本発明の半導体装置の実装方法(1)では、フィルム状半導体封止材を、はんだを含む突起電極が形成された半導体チップ上へラミネートした後、基板に対しフィルム状半導体封止材を加熱圧接し、その後、フィルム状半導体封止材を加熱硬化させて半導体チップを基板へ実装する。
本発明の半導体装置の実装方法(1)では、以下に示す条件(A)~(D)を満たすことが求められる。
In the method (1) for mounting a semiconductor device of the present invention, a film-shaped semiconductor encapsulant is laminated on a semiconductor chip on which a protruding electrode containing solder is formed, and then the film-shaped semiconductor encapsulant is heat-pressed against a substrate. Then, the film-shaped semiconductor encapsulant is heat-cured to mount the semiconductor chip on the substrate.
In the mounting method (1) of the semiconductor device of the present invention, it is required to satisfy the following conditions (A) to (D).
条件(A)
フィルム状半導体封止材の厚みを、突起電極の高さの0.8倍以上1.3倍以下とする。
条件(A)により、フィルム状半導体封止材の過供給と不足を防止する。フィルム状半導体封止材の厚みが、突起電極の高さの0.8倍未満だと、フィルム状半導体封止材が不足するため、ボイド欠陥やデラミネーションといった実装不良が生じる。フィルム状半導体封止材の厚みが、突起電極の高さの1.3倍超だと、フィルム状半導体封止材が過供給となるため、フィルム状半導体封止材の半導体チップ上への這い上がりを生じ実装不良となる。
フィルム状半導体封止材の厚みは、突起電極の高さの0.9倍以上1.25倍以下が好ましい。
Condition (A)
The thickness of the film-shaped semiconductor encapsulant shall be 0.8 times or more and 1.3 times or less the height of the protruding electrode.
The condition (A) prevents oversupply and shortage of the film-shaped semiconductor encapsulant. If the thickness of the film-shaped semiconductor encapsulant is less than 0.8 times the height of the protruding electrode, the film-shaped semiconductor encapsulant is insufficient, and mounting defects such as void defects and delamination occur. If the thickness of the film-shaped semiconductor encapsulant is more than 1.3 times the height of the protruding electrode, the film-shaped semiconductor encapsulant will be oversupplied, and the film-shaped semiconductor encapsulant will crawl onto the semiconductor chip. It will rise and the mounting will be defective.
The thickness of the film-shaped semiconductor encapsulant is preferably 0.9 times or more and 1.25 times or less the height of the protruding electrode.
条件(B)
半導体チップにラミネートされた半導体封止材面の最高高さと、最低高さとの差を2.2μm以下とする。
条件(B)により、フィルム状半導体封止材と、基板とが接触する際に発生するボイド体積を小さくすることができ、ボイド欠陥による実装不良を防止できる。半導体チップにラミネートされた半導体封止材面の最高高さと、最低高さとの差が2.2μm超だと、フィルム状半導体封止材と、基板とが接触する際に発生するボイド体積が大きくなり、ボイド欠陥による実装不良を生じる。
半導体チップにラミネートされた半導体封止材面の最高高さと、最低高さとの差は2μm以下がより好ましい。
Condition (B)
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor chip shall be 2.2 μm or less.
According to the condition (B), the void volume generated when the film-shaped semiconductor encapsulant and the substrate come into contact with each other can be reduced, and mounting defects due to void defects can be prevented. If the difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor chip is more than 2.2 μm, the void volume generated when the film-like semiconductor encapsulant and the substrate come into contact with each other is large. This causes mounting defects due to void defects.
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor chip is more preferably 2 μm or less.
条件(C)
フィルム状半導体封止材を半導体チップ上へラミネートする際のラミネーション圧力を0.1MPa以上0.8MPa以下とする。
条件(C)により、フィルム状半導体封止材と、基板とが接触する際に発生するボイド体積を小さくすることができ、ボイド欠陥による実装不良を防止できる。ラミネーション圧力が0.8MPa超だと、フィルム状半導体封止材が薄化し、半導体チップにラミネートされた半導体封止材面の最高高さと最低高さとの差が大きくなり、ボイドが生じ、実装不良となる。また、突起電極にダメージを生じるおそれがある。ラミネーション圧力が0.1MPa未満だと、過小圧力によるフィルム状半導体封止材の貼りつき不良が発生し、接続不良やボイド欠陥による実装不良を生じる。
Condition (C)
The lamination pressure when laminating the film-shaped semiconductor encapsulant on the semiconductor chip is 0.1 MPa or more and 0.8 MPa or less.
Depending on the condition (C), the void volume generated when the film-shaped semiconductor encapsulant and the substrate come into contact with each other can be reduced, and mounting defects due to void defects can be prevented. When the lamination pressure exceeds 0.8 MPa, the film-shaped semiconductor encapsulant becomes thin, the difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor chip becomes large, voids occur, and mounting defects occur. Will be. In addition, the protruding electrode may be damaged. If the lamination pressure is less than 0.1 MPa, poor adhesion of the film-shaped semiconductor encapsulant occurs due to underpressure, and poor connection or mounting failure due to void defects occurs.
条件(D)
フィルム状半導体封止材の加熱硬化を、0.4MPa以上の加圧雰囲気下で実施する。
条件(D)により、ボイドの発生や膨張を抑制しながらフィルム状半導体封止材の硬化を進行させることができ、ボイド欠陥による実装不良を防止できる。フィルム状半導体封止材の加熱硬化を0.4MPa未満の雰囲気下で実施した場合、ボイドの発生や膨張を抑制することができず、ボイド欠陥による実装不良を生じる。
Condition (D)
The film-shaped semiconductor encapsulant is heat-cured in a pressurized atmosphere of 0.4 MPa or more.
According to the condition (D), the curing of the film-shaped semiconductor encapsulant can be promoted while suppressing the generation and expansion of voids, and mounting defects due to void defects can be prevented. When the film-shaped semiconductor encapsulant is heat-cured in an atmosphere of less than 0.4 MPa, the generation and expansion of voids cannot be suppressed, and mounting defects due to void defects occur.
本発明の半導体装置の実装方法(2)では、フィルム状半導体封止材を、はんだを含む突起電極が形成された半導体ウエハ上へラミネートした後、基板に対しフィルム状半導体封止材を加熱圧接し、その後、フィルム状半導体封止材を加熱硬化させて半導体チップを基板へ実装する。
本発明の半導体装置の実装方法(2)は、下記工程(a)~(d)を有する。
(a)フィルム状半導体封止材がラミネートされた半導体ウエハを個片化する工程
(b)個片化された半導体チップを基板電極と位置合わせをする工程
(c)位置合わせされた半導体チップと基板とを加熱しながら圧接する工程
(d)圧接後に圧力雰囲気下にてフィルム状半導体封止材を加熱硬化する工程
In the method (2) for mounting a semiconductor device of the present invention, a film-shaped semiconductor encapsulant is laminated on a semiconductor wafer on which a protruding electrode containing solder is formed, and then the film-shaped semiconductor encapsulant is heat-pressed against a substrate. Then, the film-shaped semiconductor encapsulant is heat-cured to mount the semiconductor chip on the substrate.
The method (2) for mounting a semiconductor device of the present invention includes the following steps (a) to (d).
(A) Step of individualizing a semiconductor wafer laminated with a film-like semiconductor encapsulant (b) Step of aligning the fragmented semiconductor chip with a substrate electrode (c) With the aligned semiconductor chip Step of pressure contacting with the substrate while heating (d) Step of heating and curing the film-shaped semiconductor encapsulant in a pressure atmosphere after pressure welding
フィルム状半導体封止材をラミネートする対象が半導体ウエハであるのに対し、基板上に実装する対象は半導体チップである。
そのため、工程(a)において、ダイシングにより、半導体ウエハを個片化して、フィルム状半導体封止材がラミネートされた半導体チップを得る。
次に、工程(b)により、半導体チップ上、および、基板上に形成された位置合わせの基準マークを可視光用のカメラ等で認識しながら、個片化された半導体チップを、基板電極と位置合わせする。
次に、工程(c)により、個片化された半導体チップを、フリップチップボンダー等を用いて、基板に対し加熱圧接(TCB)する。ここで、半導体チップの基板へのマウントと、突起電極と基板電極との接続を同時に実施してもよいし、半導体チップを基板へマウントした後、突起電極と基板電極とを接続してもよい。前者の場合、はんだ溶融温度以上に加熱した状態でTCBを実施する。後者の場合、フィルム状半導体封止材の軟化温度以上に加熱した状態で、半導体チップを基板上の所定の位置にマウントし、さらに、はんだ溶融温度以上に加熱して、突起電極と基板電極とを接続する。また、後者の場合、半導体チップを個々にはんだ溶融温度以上に加熱して突起電極と基板電極とを接続してもよいし、半導体チップ複数個を同時に加熱して突起電極と基板電極を接続してもよい。
次に、工程(d)により、圧力雰囲気下にてフィルム状半導体封止材を加熱硬化させて、半導体チップを基板に実装する。
While the target for laminating the film-shaped semiconductor encapsulant is a semiconductor wafer, the target for mounting on the substrate is a semiconductor chip.
Therefore, in the step (a), the semiconductor wafer is individualized by dicing to obtain a semiconductor chip on which the film-shaped semiconductor encapsulant is laminated.
Next, in step (b), while recognizing the alignment reference marks formed on the semiconductor chip and the substrate with a camera for visible light or the like, the individualized semiconductor chip is used as a substrate electrode. Align.
Next, in the step (c), the fragmented semiconductor chip is heat-pressed (TCB) with respect to the substrate using a flip chip bonder or the like. Here, the mounting of the semiconductor chip on the substrate and the connection between the projection electrode and the substrate electrode may be carried out at the same time, or the projection electrode and the substrate electrode may be connected after the semiconductor chip is mounted on the substrate. .. In the former case, TCB is carried out in a state of being heated to a temperature higher than the solder melting temperature. In the latter case, the semiconductor chip is mounted at a predetermined position on the substrate while being heated to the softening temperature or higher of the film-shaped semiconductor encapsulant, and further heated to the solder melting temperature or higher to form the protruding electrode and the substrate electrode. To connect. Further, in the latter case, the semiconductor chips may be individually heated to a temperature higher than the solder melting temperature to connect the protrusion electrodes and the substrate electrodes, or a plurality of semiconductor chips may be heated simultaneously to connect the protrusion electrodes and the substrate electrodes. You may.
Next, in step (d), the film-shaped semiconductor encapsulant is heat-cured under a pressure atmosphere, and the semiconductor chip is mounted on the substrate.
本発明の半導体装置の実装方法(2)においても、上述した条件(A)~(D)を満たすことが求められる。本発明の半導体装置の実装方法(2)における留意点を以下に示す。
半導体ウエハは、上記工程(a)により、個片化して半導体チップとするため、個片化後の半導体チップの個数に応じた複数の突起電極を有している。これら複数の突起電極について、条件(A)を満たすことが求められる。
一方、条件(B)については、上記工程(a)の実施後、すなわち、個片化された半導体チップが満たすことが求められる。
Also in the mounting method (2) of the semiconductor device of the present invention, it is required to satisfy the above-mentioned conditions (A) to (D). The points to be noted in the mounting method (2) of the semiconductor device of the present invention are shown below.
Since the semiconductor wafer is fragmented into semiconductor chips by the above step (a), it has a plurality of protruding electrodes according to the number of semiconductor chips after fragmentation. It is required that the condition (A) is satisfied for these plurality of protruding electrodes.
On the other hand, the condition (B) is required to be satisfied after the above step (a) is performed, that is, the semiconductor chip is separated into individual pieces.
本発明の半導体装置の実装方法(3)は、フィルム状半導体封止材を、はんだを含む突起電極が形成された半導体ウエハ上へラミネートした後、基板に対しフィルム状半導体封止材を加熱圧接し、その後、フィルム状半導体封止材を加熱硬化させて半導体チップを基板へ実装する点は、本発明の半導体装置の実装方法(2)と同様である。したがって、 本発明の半導体装置の実装方法(3)は、上記工程(a)~(d)を有する。但し、本発明の半導体装置の実装方法(3)では、上記工程(a)の前に実施する以下の工程(e)を有する。
(e)フィルム状半導体封止材がラミネートされた半導体ウエハの厚みを研磨によって薄くする工程
工程(e)は、いわゆるバックグラインド工程である。
In the method (3) for mounting a semiconductor device of the present invention, a film-shaped semiconductor encapsulant is laminated on a semiconductor wafer on which a protruding electrode containing solder is formed, and then the film-shaped semiconductor encapsulant is heat-pressed against a substrate. After that, the film-shaped semiconductor encapsulant is heat-cured to mount the semiconductor chip on the substrate, which is the same as the mounting method (2) of the semiconductor device of the present invention. Therefore, the method (3) for mounting the semiconductor device of the present invention includes the above steps (a) to (d). However, the semiconductor device mounting method (3) of the present invention includes the following step (e) to be carried out before the step (a).
(E) The step step (e) of reducing the thickness of the semiconductor wafer on which the film-shaped semiconductor encapsulant is laminated by polishing is a so-called backgrinding step.
本発明の半導体装置の実装方法(3)においても、上述した条件(A)~(D)を満たすことが求められる。本発明の半導体装置の実装方法(3)における留意点は、本発明の半導体装置の実装方法(2)における留意点と同様である。 Also in the mounting method (3) of the semiconductor device of the present invention, it is required to satisfy the above-mentioned conditions (A) to (D). The points to be noted in the semiconductor device mounting method (3) of the present invention are the same as the points to be noted in the semiconductor device mounting method (2) of the present invention.
本発明の半導体装置の実装方法(1)~(3)についてさらに記載する。 The mounting methods (1) to (3) of the semiconductor device of the present invention will be further described.
本発明の半導体装置の実装方法(1)で使用する半導体チップは、少なくとも1つの突起電極を有している。突起電極の個数は、半導体チップを実装する基板の基板電極の個数と一致する。
本発明の半導体装置の実装方法(2),(3)で使用する半導体ウエハは、個片化後の半導体チップの個数に応じた複数の突起電極を有している。
これらの突起電極は、はんだ、金、銅などで単独または複合された構造で構成されることがあるが、半導体チップ面上、若しくは半導体ウエハ面上に銅層、はんだ層の順に積層された構造を有することが好ましい。
また、これらの突起電極の高さが5μm以上50μm以下であることが好ましい。
なお、半導体チップ若しくは半導体ウエハは、特に限定されず、シリコンチップ若しくはシリコンウエハでもよく、化合物半導体チップもしくは化合物半導体ウエハでもよい。
The semiconductor chip used in the mounting method (1) of the semiconductor device of the present invention has at least one protruding electrode. The number of protruding electrodes matches the number of substrate electrodes on the substrate on which the semiconductor chip is mounted.
The semiconductor wafer used in the mounting methods (2) and (3) of the semiconductor device of the present invention has a plurality of protruding electrodes according to the number of semiconductor chips after individualization.
These protruding electrodes may be composed of a single or composite structure of solder, gold, copper, etc., but have a structure in which a copper layer and a solder layer are laminated in this order on a semiconductor chip surface or a semiconductor wafer surface. It is preferable to have.
Further, it is preferable that the height of these protruding electrodes is 5 μm or more and 50 μm or less.
The semiconductor chip or semiconductor wafer is not particularly limited, and may be a silicon chip or a silicon wafer, or may be a compound semiconductor chip or a compound semiconductor wafer.
本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、以下に示す条件を満たすことが好ましい。 The film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention preferably satisfies the following conditions.
本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、可視光に対する透過性を備えていることが好ましい。具体的には、波長550nmの光の透過率が15%以上であることが好ましい。
波長550nmの光の透過率が15%以上であれば、半導体チップ上、若しくは半導体ウエハ上、あるいは、基板上に位置合わせの基準マークが形成されている場合に、フィルム状半導体封止材を通してこれらの基準マークを可視光用のカメラ等で認識できるためである。
The film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention preferably has transparency to visible light. Specifically, it is preferable that the transmittance of light having a wavelength of 550 nm is 15% or more.
When the transmittance of light having a wavelength of 550 nm is 15% or more, when the alignment reference mark is formed on the semiconductor chip, the semiconductor wafer, or the substrate, these are passed through the film-like semiconductor encapsulant. This is because the reference mark of can be recognized by a camera for visible light or the like.
また、本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、半導体チップを基板に対し加熱圧接(TCB)する際にボイドが発生しないことが好ましい。例えば、半導体チップを基板に対し加熱圧接(TCB)する際は230℃以上に加熱するため、フィルム状半導体封止材を構成する樹脂材料の熱分解等に起因する樹脂発泡によりボイドが発生するおそれがある。そのため、本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、230℃以上で樹脂発泡を起こさない材料を選択することが好ましい。 Further, it is preferable that the film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention does not generate voids when the semiconductor chip is heat-pressed (TCB) with respect to the substrate. For example, when a semiconductor chip is heat-pressed (TCB) with respect to a substrate, it is heated to 230 ° C. or higher, so that voids may occur due to resin foaming caused by thermal decomposition of the resin material constituting the film-shaped semiconductor encapsulant. There is. Therefore, as the film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention, it is preferable to select a material that does not cause resin foaming at 230 ° C. or higher.
また、本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、熱硬化性成分とその硬化剤を含んでいることが望ましい。この熱硬化性成分としては、例えば、エポキシ樹脂、ビスマレイミド樹脂、ポリアミド樹脂、ポリイミド樹脂、トリアジン樹脂、シアノアクリレート樹脂、不飽和ポリエステル樹脂、メラミン樹脂、尿素樹脂、ベンゾオキサジン樹脂、ポリウレタン樹脂、ポリイソシアネート樹脂、フラン樹脂、レゾルシノール樹脂、キシレン樹脂、ベンゾグアナミン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、ポリビニルブチラール樹脂、シロキサン変性エポキシ樹脂、シロキサン変性ポリアミドイミド樹脂、アクリレート樹脂、アクリル樹脂などが挙げられる。この中でも特に好ましいのは、耐熱性の観点から、エポキシ樹脂、ベンゾオキサジン樹脂、シロキサン変性エポキシ樹脂、シロキサン変性ポリアミドイミド樹脂である。これらは単独または二種以上の混合物として使用することができる。例えば、フィルム状半導体封止材が、熱硬化性成分として、ポリイミド樹脂とエポキシ樹脂との混合物を含むようにしてもよい。 Further, it is desirable that the film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention contains a thermosetting component and a curing agent thereof. Examples of the thermosetting component include epoxy resin, bismaleimide resin, polyamide resin, polyimide resin, triazine resin, cyanoacrylate resin, unsaturated polyester resin, melamine resin, urea resin, benzoxazine resin, polyurethane resin, and polyisocyanate. Examples thereof include resins, furan resins, resorcinol resins, xylene resins, benzoguanamine resins, diallyl phthalate resins, silicone resins, polyvinyl butyral resins, siloxane-modified epoxy resins, siloxane-modified polyamideimide resins, acrylate resins, and acrylic resins. Of these, epoxy resin, benzoxazine resin, siloxane-modified epoxy resin, and siloxane-modified polyamide-imide resin are particularly preferable from the viewpoint of heat resistance. These can be used alone or as a mixture of two or more. For example, the film-shaped semiconductor encapsulant may contain a mixture of a polyimide resin and an epoxy resin as a thermosetting component.
フィルム状半導体封止材に含まれる硬化剤としては、例えば、脂肪族アミン、脂環式アミン、芳香族ポリアミン、第3級アミンといったアミン系硬化剤、脂肪族酸無水物、脂環式酸無水物、芳香族酸無水物、といった酸無水物系硬化剤、ノボラックフェノール樹脂といったフェノール系硬化剤、ジシアンジアミド、有機酸ジヒドラジド、三フッ化ホウ素アミン錯体、イミダゾール類、ポリアミド、有機過酸化物、等が挙げられる。これらは単独または二種以上の混合物として使用することができる。 Examples of the curing agent contained in the film-shaped semiconductor encapsulant include amine-based curing agents such as aliphatic amines, alicyclic amines, aromatic polyamines, and tertiary amines, aliphatic acid anhydrides, and alicyclic acid anhydrides. Acid anhydride-based curing agents such as products and aromatic acid anhydrides, phenol-based curing agents such as novolak phenol resin, dicyandiamide, organic acid dihydrazide, boron trifluoride amine complex, imidazoles, polyamide, organic peroxide, etc. Can be mentioned. These can be used alone or as a mixture of two or more.
また、本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、上記した熱硬化性成分以外の高分子樹脂を含んでいてもよい。高分子樹脂としては、例えば、ポリエステル樹脂、ポリエーテル樹脂、ポリアミド樹脂、ポリアミドイミド樹脂、ポリイミド樹脂、ポリアクリレート樹脂、ポリビニルブチラール樹脂、ポリウレタン樹脂、フェノキシ樹脂、ポリアクリレート樹脂、ポリブタジエン、アクリロニトリルブタジエン共重合体、アクリロニトリルブタジエンゴムスチレン樹脂、スチレンブタジエン共重合体、アクリル酸共重合体などが挙げられる。これらは、単独または二種以上を併用して使用することができる。これらの中でも、耐熱性及びフィルム形成性の観点から、ポリイミド樹脂やフェノキシ樹脂が好ましい。 Further, the film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention may contain a polymer resin other than the above-mentioned thermosetting component. Examples of the polymer resin include polyester resin, polyether resin, polyamide resin, polyamideimide resin, polyimide resin, polyacrylate resin, polyvinyl butyral resin, polyurethane resin, phenoxy resin, polyacrylate resin, polybutadiene, and acrylonitrile butadiene copolymer. , Acrylonitrile butadiene rubber styrene resin, styrene butadiene copolymer, acrylic acid copolymer and the like. These can be used alone or in combination of two or more. Among these, polyimide resin and phenoxy resin are preferable from the viewpoint of heat resistance and film formability.
また、本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、低熱膨張化のために無機フィラーを含んでいてもよい。この場合、波長550nmの透過率が15%以上になるように、フィラー種、粒径、配合量などを設定する。 Further, the film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention may contain an inorganic filler for low thermal expansion. In this case, the filler type, particle size, blending amount, etc. are set so that the transmittance at a wavelength of 550 nm is 15% or more.
さらに、また、本発明の半導体装置の実装方法(1)~(3)で使用するフィルム状半導体封止材は、硬化促進剤、フラックス剤、シランカップリング剤、チタンカップリング剤、酸化防止剤、レベリング剤、イオントラップ剤などの添加剤や、エラストマー成分を配合してもよい。これらは単独で用いてもよいし、2種以上を組み合わせてもよい。配合量については、各添加剤の効果が発現するように調整すればよい。 Furthermore, the film-shaped semiconductor encapsulant used in the mounting methods (1) to (3) of the semiconductor device of the present invention is a curing accelerator, a flux agent, a silane coupling agent, a titanium coupling agent, and an antioxidant. , Additives such as leveling agents and ion trapping agents, and elastomer components may be blended. These may be used alone or in combination of two or more. The blending amount may be adjusted so that the effect of each additive is exhibited.
本発明の半導体装置の実装方法(1)~(3)において、フィルム状半導体封止材を半導体チップ上、若しくは、半導体ウエハ上にラミネートする際は、公知のラミネート装置を使用できる。使用するラミネート装置は特に限定されず、たとえば、ロールラミネーター、真空ラミネーターを用いることができる。 In the mounting methods (1) to (3) of the semiconductor device of the present invention, a known laminating device can be used when laminating a film-shaped semiconductor encapsulant on a semiconductor chip or a semiconductor wafer. The laminating device to be used is not particularly limited, and for example, a roll laminator or a vacuum laminator can be used.
本発明の半導体装置の実装方法(1)~(3)において、フィルム状半導体封止材を半導体チップ上、若しくは、半導体ウエハ上にラミネートする際のラミネーション温度、およびラミネーション時間は、使用するフィルム状半導体封止材に応じて適宜選択することができる。 In the mounting methods (1) to (3) of the semiconductor device of the present invention, the lamination temperature and the lamination time when laminating the film-shaped semiconductor encapsulant on the semiconductor chip or the semiconductor wafer are the film-like to be used. It can be appropriately selected depending on the semiconductor encapsulant.
本発明の半導体装置の実装方法(1)~(3)において、基板に対し半導体チップを加熱圧接(TCB)する際の条件は特に限定されず、使用するフィルム状半導体封止材やはんだに応じて適宜選択すればよい。 In the mounting methods (1) to (3) of the semiconductor device of the present invention, the conditions for heat-pressing (TCB) the semiconductor chip to the substrate are not particularly limited, depending on the film-shaped semiconductor encapsulant and solder used. It may be selected as appropriate.
本発明の半導体装置の実装方法(1)~(3)において、圧力雰囲気下でフィルム状半導体封止材を加熱硬化する際の加熱温度、および加熱時間は特に限定されず、使用するフィルム状半導体封止材に応じて適宜選択すればよい。 In the mounting methods (1) to (3) of the semiconductor device of the present invention, the heating temperature and the heating time when the film-shaped semiconductor encapsulant is heat-cured under a pressure atmosphere are not particularly limited, and the film-shaped semiconductor used is not particularly limited. It may be appropriately selected according to the sealing material.
本発明の半導体装置の実装方法(2),(3)における工程(a)は、一般的なダイシング装置を使用し、乾式又は湿式ダイシングを行うことによって達成できる。 The step (a) in the mounting method (2) and (3) of the semiconductor device of the present invention can be achieved by using a general dicing device and performing dry or wet dicing.
本発明の半導体装置の実装方法(3)における工程(e)は、一般的なバックグラインダーにより達成できる。 The step (e) in the mounting method (3) of the semiconductor device of the present invention can be achieved by a general back grinder.
本発明の半導体装置の実装方法(1)~(3)では、密着性、濡れ性等の改善のため、加熱圧接(TCB)実施前の基板に対し、プラズマ処理等の表面処理を施してもよい。 In the mounting methods (1) to (3) of the semiconductor device of the present invention, even if the substrate before heat pressure welding (TCB) is subjected to surface treatment such as plasma treatment in order to improve adhesion, wettability, etc. good.
本発明の半導体装置の実装方法(1)~(3)では、外部からの衝撃や、水分侵入からの保護のため、半導体チップを実装した部位を、公知のモールド半導体封止材で封止してもよい。モールド半導体封止材の硬化は、フィルム状半導体封止材の硬化と同時に実施してもよく、フィルム状半導体封止材の硬化後に実施してもよい。 In the mounting methods (1) to (3) of the semiconductor device of the present invention, the portion where the semiconductor chip is mounted is sealed with a known molded semiconductor encapsulant in order to protect from external impact and moisture intrusion. You may. The curing of the molded semiconductor encapsulant may be carried out at the same time as the curing of the film-shaped semiconductor encapsulant, or may be carried out after the curing of the film-shaped semiconductor encapsulant.
以下、実施例により、本発明を詳細に説明するが、本発明はこれらに限定されるものではない。 Hereinafter, the present invention will be described in detail with reference to Examples, but the present invention is not limited thereto.
(実施例1~11、比較例1~4)
7.3mm□の半導体チップが16個連なった半導体ウエハを準備した。各半導体チップ面上には、銅層、はんだ層(Sn-Agはんだ)の順に積層された構造の突起電極が設けられている。半導体ウエハの突起電極が設けられた面上に、下記表に示す組成のフィルム状半導体封止材を4cm□にカットして載置し、真空加圧式ラミネーター(MVLP-500/600、株式会社名機製作所)を用いて、下記表に記載した条件で半導体ウエハ上にフィルム状半導体封止材をラミネートした。
熱硬化性成分
NC3000:ビフェニルアラルキル型エポキシ樹脂、日本化薬株式会社製
YDPN-638:フェノールノボラック型エポキシ樹脂、新日鉄住金化学株式会社製
EXA830-CRP:ビスフェノールF型液状エポキシ樹脂、DIC株式会社製
EXA850-CRP:ビスフェノールA型エポキシ樹脂、DIC株式会社製
硬化剤
EH105:アミン系硬化剤、株式会社ADEKA製
KA-1180:フェノール樹脂系硬化剤、DIC株式会社製
硬化促進剤
2PHZ:イミダゾール系硬化促進剤、四国化成工業株式会社製
無機フィラー
Sciqas(0.1μm):シリカフィラー、平均粒径0.1μm、堺化学工業株式会社製
高分子樹脂
jER4250:ビスフェノールA/ビスフェノールF共重合型フェノキシ樹脂、三菱化学株式会社製
FX316:ビスフェノールA型フェノキシ樹脂、新日鉄住金化学株式会社製
フラックス剤
8-キノリノール:シグマアルドリッチジャパン合同会社製
エラストマー
XER-32C:ブタジエン・アクリロニトリル・メタクリル酸共重合体、JSR株式会社製
シランカップリング剤
KBM573:信越化学株式会社製
(Examples 1 to 11, Comparative Examples 1 to 4)
A semiconductor wafer in which 16 semiconductor chips of 7.3 mm □ were connected was prepared. On each semiconductor chip surface, a protruding electrode having a structure in which a copper layer and a solder layer (Sn—Ag solder) are laminated in this order is provided. A film-shaped semiconductor encapsulant having the composition shown in the table below was cut into 4 cm □ and placed on the surface of the semiconductor wafer provided with the protruding electrodes, and placed on it. A film-shaped semiconductor encapsulant was laminated on a semiconductor wafer under the conditions shown in the table below using Kikai Seisakusho).
Thermosetting ingredient
NC3000: Biphenyl aralkyl type epoxy resin, YDPN-638 manufactured by Nippon Kayaku Co., Ltd., EXA830-CRP: Bisphenol F type liquid epoxy resin manufactured by Nippon Steel & Sumitomo Metal Chemical Co., Ltd., EXA850-CRP: Bisphenol manufactured by DIC Co., Ltd. A type epoxy resin, manufactured by DIC Co., Ltd.
Hardener
EH105: Amine-based curing agent, ADEKA Corporation KA-1180: Phenol resin-based curing agent, manufactured by DIC Corporation
Curing accelerator
2PHZ: Imidazole-based curing accelerator, manufactured by Shikoku Chemicals Corporation
Inorganic filler
Sciqas (0.1 μm): silica filler, average particle size 0.1 μm, manufactured by Sakai Chemical Industry Co., Ltd.
Polymer resin
jER4250: Bisphenol A / Bisphenol F copolymer type phenoxy resin, Mitsubishi Chemical Corporation FX316: Bisphenol A type phenoxy resin, manufactured by Nippon Steel & Sumitomo Metal Corporation
Flux agent
8-Kinolinol: Made by Sigma-Aldrich Japan GK
Elastomer
XER-32C: Butadiene / Acrylonitrile / Methacrylic acid copolymer, manufactured by JSR Corporation
Silane coupling agent
KBM573: Made by Shin-Etsu Chemical Co., Ltd.
なお、切断前のフィルム状半導体封止材の厚みを以下の手順で測定し、ラミネート後の半導体封止材面の最高高さと最低高さとの差を以下の手順で測定した。
フィルム状半導体封止材の厚み
基材フィルム(PETフィルム)上へ形成されたフィルム状半導体封止材を、基材フィルム表面を基準高さとし、表面粗さ・形状測定機(東京精密社製、SURFCOM1500SD2)を用い測定し厚みを求めた。
ラミネート後の半導体封止材面の最高高さと最低高さとの差
半導体チップ(7.3mm□)上にラミネートされたフィルム状半導体封止材上をコンフォーカル顕微鏡(レーザーテック社製、OPTELICS H1200)にてスキャンし、凹凸を測定し、フィルム表面高さを基準とし、その基準高さから最も高いところを最高高さとし、最も低いところを最低高さとして、両者の高さの差を求めた。
実施例10については、半導体ウエハの裏面側を大きさが異なる研磨砥粒(粗(#320)、仕上げ(#2000))を用いてバックグラインドした。
次に、フィルム状半導体封止材をラミネートした半導体ウエハは、東京精密製ダイシングマシン(型番:A-WD-100A)を使用し、ダイシングラインに沿って、速度:20mm/sec、ブレード回転数:30000rpmの条件でダイシングを行い所定のサイズ(7.3mm×7.3mm)へ個片化しテスト用チップとした。
その後、フリップチップボンダー(パナソニックファクトリーソリューションズ株式会社製、商品名FCB3)を用いて、テスト用チップとシリコン基板とを加熱圧接(TCB)した。なお、実施例9は、以下の手順(b)で加熱圧接(TCB)を実施し、残りの実施例、比較例は以下の手順(a)で加熱圧接(TCB)を実施した。
手順(a)
80℃に加熱したテスト用チップをシリコン基板へ接触させた後、その状態で260℃まで温度を上昇させテスト用チップの突起電極と基板電極を接続した。
手順(b)
80℃に加熱したテスト用チップをシリコン基板上へマウントした。その後、300℃に加熱したフリップチップボンダーの加熱ヘッドを搭載されたテストチップ上から加圧し、テストチップの突起電極と基板電極を接続した。
次に、所定の圧力雰囲気下でフィルム状半導体封止材を加熱硬化させた。実施例1~7、9、10、および、比較例2~4は、0.7MPaの圧力雰囲気下、175℃で2時間加熱硬化させた。実施例8は、0.4MPaの圧力雰囲気下、175℃で2時間加熱硬化させた。実施例11は、0.7MPaの圧力雰囲気下、185℃で4時間加熱硬化させた。比較例1は、0.3MPaの圧力雰囲気下、175℃で2時間加熱硬化させた。
上記の手順をN=5で実施し、以下の評価を実施した。
視認性:フリップチップボンダーにて位置合わせ工程中、N=5の全てで認識エラーが発生しなかった場合は○とし、1試験片でも認識エラーが発生した場合を×とした。
這い上がり: 作製した試験片を目視で観察した。N=5の全てでフィルム状半導体封止材の這い上がりが観察されなかった場合を○とし、1試験片でも這い上がりが観察された場合を×とした。
ボイド: 作製した試験片を超音波探傷装置(Scanning Acoustic Tomography、SAT)を用いて反射法にて観察した。N=5の全てで画像上、ボイド/デラミネーションの陰影が観察されなかった場合を○とし、1試験片でも陰影が観察された場合を×とした。
接続:作製した試験片のうち、1試験片を抜き出し、研磨にて接続断面を削りだした断面にてペリフェラル部を1列断面観察した。テスト用チップのはんだと、BottomチップのPadとの界面のはんだ濡れがあるか走査型電子顕微鏡にて確認し、はんだ濡れが確認された場合を○とし、はんだ濡れが確認されなかった場合を×とした。
The thickness of the film-shaped semiconductor encapsulant before cutting was measured by the following procedure, and the difference between the maximum height and the minimum height of the semiconductor encapsulant surface after laminating was measured by the following procedure.
Thickness of film-shaped semiconductor encapsulant
The film-like semiconductor encapsulant formed on the base film (PET film) is measured using a surface roughness / shape measuring machine (SURFCOM1500SD2, manufactured by Tokyo Seimitsu Co., Ltd.) with the surface of the base film as the reference height, and the thickness is measured. I asked.
Difference between the maximum height and the minimum height of the semiconductor encapsulant surface after laminating
The film-like semiconductor encapsulant laminated on the semiconductor chip (7.3 mm □) is scanned with a confocal microscope (Lasertec, OPTELICS H1200), unevenness is measured, and the film surface height is used as a reference. From the standard height, the highest point was set as the highest height, and the lowest point was set as the lowest height, and the difference between the two heights was calculated.
In Example 10, the back surface side of the semiconductor wafer was back grinded using abrasive grains (coarse (# 320), finish (# 2000)) of different sizes.
Next, for the semiconductor wafer laminated with the film-shaped semiconductor encapsulant, a dicing machine manufactured by Tokyo Seimitsu Co., Ltd. (model number: A-WD-100A) was used, and the speed was 20 mm / sec and the blade rotation speed was: along the dicing line. Dicing was performed under the condition of 30,000 rpm, and the chips were separated into predetermined sizes (7.3 mm × 7.3 mm) and used as test chips.
Then, a flip chip bonder (manufactured by Panasonic Factory Solutions Co., Ltd., trade name FCB3) was used to heat-press weld (TCB) the test chip and the silicon substrate. In Example 9, heat pressure welding (TCB) was carried out in the following procedure (b), and in the remaining Examples and Comparative Examples, heat pressure welding (TCB) was carried out in the following procedure (a).
Procedure (a)
After the test chip heated to 80 ° C. was brought into contact with the silicon substrate, the temperature was raised to 260 ° C. in that state to connect the protruding electrode of the test chip and the substrate electrode.
Procedure (b)
The test chip heated to 80 ° C. was mounted on a silicon substrate. Then, the heating head of the flip chip bonder heated to 300 ° C. was pressurized from above the mounted test chip, and the protrusion electrode of the test chip and the substrate electrode were connected.
Next, the film-shaped semiconductor encapsulant was heat-cured under a predetermined pressure atmosphere. Examples 1 to 7, 9, 10 and Comparative Examples 2 to 4 were heat-cured at 175 ° C. for 2 hours under a pressure atmosphere of 0.7 MPa. Example 8 was heat-cured at 175 ° C. for 2 hours under a pressure atmosphere of 0.4 MPa. Example 11 was heat-cured at 185 ° C. for 4 hours under a pressure atmosphere of 0.7 MPa. Comparative Example 1 was heat-cured at 175 ° C. for 2 hours under a pressure atmosphere of 0.3 MPa.
The above procedure was carried out at N = 5, and the following evaluation was carried out.
Visibility: During the alignment process with the flip-chip bonder, if no recognition error occurred at all of N = 5, it was evaluated as ◯, and if a recognition error occurred even with one test piece, it was evaluated as x.
Crawling up: The prepared test piece was visually observed. The case where the film-like semiconductor encapsulant was not observed to crawl up in all of N = 5 was evaluated as ◯, and the case where the film-like semiconductor encapsulant was observed to crawl up was evaluated as x.
Void: The prepared test piece was observed by a reflection method using an ultrasonic flaw detector (Scanning Acoustic Tomography, SAT). The case where no shadow / delamination shadow was observed on the image in all of N = 5 was marked with ◯, and the case where shadow was observed even with one test piece was marked with x.
Connection: Of the prepared test pieces, one test piece was taken out, and the peripheral portion was observed in a row in a cross section obtained by cutting out the connection cross section by polishing. Check with a scanning electron microscope whether there is solder wetting at the interface between the solder of the test chip and the pad of the Bottom chip. And said.
実施例1~11は、実装性(視認性、這い上がり、ボイド、接続)が良好であった。なお、実施例2,3は、実施例1に対し、フィルム状半導体封止材の厚み、半導体ウエハの突起電極の高さ、および、ラミネーション圧力を変えた実施例である。実施例4は、実施例2に対し、フィルム状半導体封止材の厚み、および、ラミネーション圧力を変えた実施例である。実施例5は、実施例4に対し、フィルム状半導体封止材の厚みを変えた実施例である。実施例6,7は、実施例5に対し、ラミネーション圧力を変えた実施例である。実施例8は、実施例5に対し、フィルム状半導体封止材の硬化時の圧力条件を変えた実施例である。実施例9は、実施例5に対し、加熱圧接(TCB)の手順を、手順(a)から手順(b)に変えた実施例である。実施例10は、実施例5に対し、ラミネーションと、ダイシングとの間にバックグラインドを実施した実施例である。実施例11は、実施例5に対し、フィルム状半導体封止材の組成を、組成Aから組成Bに変更し、該フィルム状半導体封止材の硬化条件(温度、加熱時間)を変えた実施例である。
比較例1は、0.4MPa未満(0.3MPa)の加圧雰囲気下でフィルム状半導体封止材を硬化させた例であり、実装性(ボイド)が×であった。比較例2は、ラミネーション圧力が0.8MPa超(0.9MPa)で、半導体封止材面の最高高さと、最低高さとの差が2.2μm超(2.3μm)の例であり、実装性(ボイド)が×であった。比較例3は、フィルム状半導体封止材の厚みが突起電極の高さの0.8倍未満(0.75)で、半導体封止材面の最高高さと、最低高さとの差が2.2μm超(2.3μm)の例であり、実装性(ボイド)が×であった。比較例4は、フィルム状半導体封止材の厚みが突起電極の高さの1.3倍超(1.40)の例であり、実装性(這い上がり)が×であった。そのため、実装性(ボイド、接続)の評価は実施しなかった。
Examples 1 to 11 had good mountability (visibility, creeping up, voids, connection). It should be noted that Examples 2 and 3 are examples in which the thickness of the film-shaped semiconductor encapsulant, the height of the projection electrode of the semiconductor wafer, and the lamination pressure are changed from those of Example 1. Example 4 is an example in which the thickness of the film-shaped semiconductor encapsulant and the lamination pressure are changed with respect to Example 2. Example 5 is an example in which the thickness of the film-shaped semiconductor encapsulant is changed from that of Example 4. Examples 6 and 7 are examples in which the lamination pressure is changed with respect to Example 5. Example 8 is an example in which the pressure conditions at the time of curing of the film-shaped semiconductor encapsulant are changed from those of Example 5. Example 9 is an example in which the procedure of heat pressure welding (TCB) is changed from the procedure (a) to the procedure (b) with respect to the fifth embodiment. Example 10 is an example in which backgrinding is performed between lamination and dicing with respect to Example 5. In Example 11, the composition of the film-shaped semiconductor encapsulant was changed from composition A to composition B, and the curing conditions (temperature, heating time) of the film-shaped semiconductor encapsulant were changed with respect to Example 5. This is an example.
Comparative Example 1 was an example in which the film-shaped semiconductor encapsulant was cured in a pressurized atmosphere of less than 0.4 MPa (0.3 MPa), and the mountability (void) was x. Comparative Example 2 is an example in which the lamination pressure is more than 0.8 MPa (0.9 MPa) and the difference between the maximum height and the minimum height of the semiconductor encapsulant surface is more than 2.2 μm (2.3 μm). The sex (void) was x. In Comparative Example 3, the thickness of the film-shaped semiconductor encapsulant is less than 0.8 times the height of the protruding electrode (0.75), and the difference between the maximum height and the minimum height of the semiconductor encapsulant surface is 2. It was an example of more than 2 μm (2.3 μm), and the mountability (void) was ×. Comparative Example 4 was an example in which the thickness of the film-shaped semiconductor encapsulant was more than 1.3 times the height of the protruding electrode (1.40), and the mountability (crawling up) was ×. Therefore, the mountability (void, connection) was not evaluated.
Claims (5)
前記フィルム状半導体封止材の厚みが、前記突起電極の高さの0.8倍以上1.3倍以下であり、
前記半導体チップにラミネートされた前記半導体封止材面の最高高さと、最低高さとの差が2.2μm以下であり、
ラミネーション圧力が0.1MPa以上0.8MPa以下であり、
前記加熱硬化が0.4MPa以上の加圧雰囲気下で実施される半導体装置の実装方法。 After laminating the film-shaped semiconductor encapsulant on the semiconductor chip on which the protruding electrode containing solder is formed, the film-shaped semiconductor encapsulant is heat-pressed against the substrate to connect the protruding electrode and the substrate electrode . Then, in the mounting method of the semiconductor device in which the film-shaped semiconductor encapsulant is heat-cured and the semiconductor chip is mounted on the substrate.
The thickness of the film-shaped semiconductor encapsulant is 0.8 times or more and 1.3 times or less the height of the protruding electrode.
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor chip is 2.2 μm or less.
The lamination pressure is 0.1 MPa or more and 0.8 MPa or less.
A method for mounting a semiconductor device, wherein the heat curing is carried out in a pressurized atmosphere of 0.4 MPa or more.
前記フィルム状半導体封止材がラミネートされた半導体ウエハを個片化する工程、
個片化された半導体チップを前記基板電極と位置合わせをする工程、
位置合わせされた半導体チップと、基板とを加熱しながら圧接する工程、および
圧接後に圧力雰囲気下にてフィルム状半導体封止材を加熱硬化する工程を有し、
前記フィルム状半導体封止材の厚みが、前記突起電極の高さの0.8倍以上1.3倍以下であり、
前記半導体ウエハにラミネートされ、その後、個片化された前記半導体封止材面の最高高さと最低高さとの差が2.2μm以下であり、
ラミネーション圧力が0.1MPa以上0.8MPa以下であり、
前記加熱硬化が0.4MPa以上の加圧雰囲気下で実施される半導体装置の実装方法。 The film-shaped semiconductor encapsulant is laminated on a semiconductor wafer on which a protruding electrode containing solder is formed, and the film-shaped semiconductor encapsulant is heat-pressed against the substrate to connect the protruding electrode and the substrate electrode . Then, in the mounting method of the semiconductor device in which the film-shaped semiconductor encapsulant is heat-cured and the semiconductor chip is mounted on the substrate.
The process of individualizing a semiconductor wafer laminated with the film-shaped semiconductor encapsulant.
A process of aligning an individualized semiconductor chip with the substrate electrode,
It has a step of pressure-welding the aligned semiconductor chip and the substrate while heating, and a step of heat-curing the film-shaped semiconductor encapsulant under a pressure atmosphere after the pressure welding.
The thickness of the film-shaped semiconductor encapsulant is 0.8 times or more and 1.3 times or less the height of the protruding electrode.
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor wafer and then separated into pieces is 2.2 μm or less.
The lamination pressure is 0.1 MPa or more and 0.8 MPa or less.
A method for mounting a semiconductor device, wherein the heat curing is carried out in a pressurized atmosphere of 0.4 MPa or more.
前記フィルム状半導体封止材がラミネートされた半導体ウエハの厚みを研磨によって薄くする工程、
前記フィルム状半導体封止材がラミネートされた半導体ウエハを個片化する工程、
個片化された半導体チップを前記基板電極と位置合わせをする工程、
位置合わせされた半導体チップと、基板とを加熱しながら圧接する工程、および、
圧接後に圧力雰囲気下にてフィルム状半導体封止材を加熱硬化する工程を有し、
前記フィルム状半導体封止材の厚みが、前記突起電極の高さの0.8倍以上1.3倍以下であり、
前記半導体ウエハにラミネートされ、その後、個片化された前記半導体封止材面の最高高さと最低高さとの差が2.2μm以下であり、
ラミネーション圧力が0.1MPa以上0.8MPa以下であり、
前記加熱硬化が0.4MPa以上の加圧雰囲気下で実施される半導体装置の実装方法。 The film-shaped semiconductor encapsulant is laminated on a semiconductor wafer on which a protruding electrode containing solder is formed, and the film-shaped semiconductor encapsulant is heat-pressed against the substrate to connect the protruding electrode and the substrate electrode . Then, in the mounting method of the semiconductor device in which the film-shaped semiconductor encapsulant is heat-cured and the semiconductor chip is mounted on the substrate.
A step of reducing the thickness of a semiconductor wafer on which the film-shaped semiconductor encapsulant is laminated by polishing.
The process of individualizing a semiconductor wafer laminated with the film-shaped semiconductor encapsulant.
A process of aligning an individualized semiconductor chip with the substrate electrode,
The process of pressure-welding the aligned semiconductor chip and the substrate while heating, and
It has a step of heating and curing the film-like semiconductor encapsulant under a pressure atmosphere after pressure welding.
The thickness of the film-shaped semiconductor encapsulant is 0.8 times or more and 1.3 times or less the height of the protruding electrode.
The difference between the maximum height and the minimum height of the semiconductor encapsulant surface laminated on the semiconductor wafer and then separated into pieces is 2.2 μm or less.
The lamination pressure is 0.1 MPa or more and 0.8 MPa or less.
A method for mounting a semiconductor device, wherein the heat curing is carried out in a pressurized atmosphere of 0.4 MPa or more.
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| PCT/JP2019/001139 WO2019150957A1 (en) | 2018-02-01 | 2019-01-16 | Semiconductor device mounting method |
| TW108102238A TWI773872B (en) | 2018-02-01 | 2019-01-21 | Mounting method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2014060241A (en) | 2012-09-18 | 2014-04-03 | Toray Ind Inc | Manufacturing method of semiconductor device |
| JP2014192238A (en) | 2013-03-26 | 2014-10-06 | Nitto Denko Corp | Underfill material, sealing sheet and method for manufacturing semiconductor device |
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| JP2014060241A (en) | 2012-09-18 | 2014-04-03 | Toray Ind Inc | Manufacturing method of semiconductor device |
| JP2014192238A (en) | 2013-03-26 | 2014-10-06 | Nitto Denko Corp | Underfill material, sealing sheet and method for manufacturing semiconductor device |
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| WO2019150957A1 (en) | 2019-08-08 |
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