JP7076498B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine such as a pachislot machine.

Conventionally, a so-called pachislot gaming machine is known. In such a gaming machine, a plurality of reels having a plurality of symbols arranged on their respective surfaces, game medals, coins, etc. (hereinafter referred to as "medals, etc.") are inserted, and the start lever is operated by the player. It is detected that the start switch that requests the start of rotation of a plurality of reels and the stop button provided corresponding to each of the plurality of reels are pressed by the player, and the rotation of the corresponding reel is detected. It is equipped with a stop switch that outputs a signal requesting the stop of.

Further, such a game machine is provided corresponding to each of a plurality of reels, and is based on a stepping motor that transmits each driving force to each reel and signals output by a start switch and a stop switch. It is provided with a reel control unit that controls the operation of the motor and rotates and stops each reel.

With this configuration, when the gaming machine detects that the start lever has been operated, it draws a lottery based on a random number value, and the result of this lottery (hereinafter referred to as "internal winning combination") and the stop button are operated. The rotation of the reel is stopped based on the detected timing.

In recent years, as a gaming machine of this type, after the end of a big bonus (hereinafter referred to as "BB") in which a game that gives a relatively large profit to a player can be played a predetermined number of times, a replay related to a replay is decided as an internal winning role. It is known that a gaming state (hereinafter referred to as "high RT") having a high probability of being activated is activated (see, for example, Patent Document 1).

Further, in this gaming machine, when the number of medals paid out during the operation of the BB is a predetermined number or more, in addition to the above-mentioned high RT, a specific internal winning combination related to the payout of medals (hereinafter, "small role"). ”) Is activated to notify the assist time (hereinafter referred to as“ AT ”). The state in which both the high RT and the AT are operated is called ART.

According to the gaming machine, during the operation of the ART, the probability that the winning combination will be lost is lower than that in the general gaming state, and in contrast, the probability that the small winning combination will be won is higher, so the number of medals to be paid out will be increased. be able to. Therefore, it is possible to attract the interest of the player and enhance the playability.

Further, in recent years, by internally winning a predetermined small role (for example, cherry) during a general game, a special gaming state (hereinafter referred to as a chance zone) advantageous to the player is generated with a predetermined probability and a predetermined number of games are generated. , A gaming machine that adds a predetermined number of chance zones with a predetermined probability by internally winning a predetermined small role in the chance zone (see, for example, Patent Document 2), or a predetermined small role (for example, replay). There is known a gaming machine that shifts to a high RT state by continuously winning the internal winnings over a plurality of games. According to the gaming machine, the player's interest can be maintained by appropriately extending the number of continuous games in the chance zone, which is advantageous for the player, and by expecting the ART state to operate by shifting to a high RT. Can be done.

On the other hand, important processing of the gaming machine such as control of the rotating reel of the gaming machine, internal winning combination processing, winning judgment processing, medal payout processing, etc. is performed by the CPU of the main control circuit, and the CPU performs these processing. It is executed according to the program stored in advance in the ROM.

The internal winning combination is determined based on a random number and an internal lottery table, and the rotation of each reel is stopped based on the determined internal winning combination and the timing at which the reel stop operation is detected. At this time, the extracted random value is stored in the random value storage area of the RAM, and the internal winning combination is determined at the time of the internal lottery processing based on the stored random value.

Further, the sub control circuit performs various processes such as determination and execution of staging data based on various commands output from the main control board such as a start command. Therefore, the sub-control circuit also has a RAM, and the RAM includes various information obtained by the processing of the CPU of the main control board, for example, the above-extracted random value, the game state, the internal winning combination, and the number of payouts. , Bonus carry-over status, information for specifying set values, various counters, flags, etc. are stored.

By the way, there is an illegal method of illegally inducing and continuing the above-mentioned ART that operates both the high RT and the AT. For example, the induction of ART by irradiating the information path connecting the main control circuit that manages the entire gaming machine and the sub-control circuit that manages the staging surface with electromagnetic waves to temporarily block the flow of information. -There is a technique called electromagnetic wave ART goto that continues.

For example, the sub-control circuit cannot recognize the end signal by irradiating electromagnetic waves at the final game of ART, whereas the game has the game property that ART is confirmed when a certain number of corresponding small wins are acquired during a specific game. To.

As a result, it is possible to continue until a specific small role is drawn, so that the ART can be surely entered and continued. In addition, the information that flows from the main control circuit to the sub-control circuit is transmitted by irradiating electromagnetic waves when a small role other than the replay is drawn, whereas the game has the game property that the ART is confirmed when the replay is continuously subtracted a predetermined number of times. Temporarily shut off to prevent the sub-control circuit from recognizing the game so that replays can be pulled continuously.

Japanese Unexamined Patent Publication No. 2009-5978 Japanese Unexamined Patent Publication No. 2004-236763 Japanese Unexamined Patent Publication No. 2001-58021 Japanese Unexamined Patent Publication No. 2011-11105

When the above-mentioned goto action is performed and the action is detected as, for example, a communication abnormality, a communication abnormality notification is generated. For example, a communication abnormality occurs on almost the entire surface of the liquid crystal screen of the gaming machine. Is displayed to the effect that you cannot continue. In the past, communication abnormalities were canceled by key reset after the staff confirmed the situation.

However, the communication abnormality can be canceled by the person other than the staff member canceling the abnormality to the sub-control circuit after the communication abnormality notification is generated due to the goto act. Further, in the conventional gaming machine, when a communication error, communication interruption, and cancellation of communication interruption occur between the main control circuit and the sub control circuit, the date and time and contents of the occurrence and cancellation of the error, etc. are subsequently confirmed. I couldn't.

The present invention has been made in view of the above circumstances, and when a communication error occurs between the main control circuit and the sub control circuit, the game can confirm the occurrence, date and time, and content of the error. The purpose is to provide an opportunity.

Therefore, the gaming machine according to the present invention is connected to a display unit (liquid crystal display device 5) that displays an image, a main control unit (main control circuit 60) that controls the progress of the game, and the main control unit. The setting key switch (setting key switch 20S), the sub-control unit (sub-control circuit 70) connected to the display unit and the main control unit to control the display unit, and the sub-control unit (sub-control circuit 70) recognize that an error has occurred. An error recognition means (communication error detection means 71a) is provided, and the sub-control unit includes an error information history storage area (error information history storage) for storing error information related to the error recognized by the error recognition means. Retaining storage means (DRAM73-1 and SRAM73-2) that include the area 73f-2) and can retain the stored information even when the power supply is cut off, and for measuring the time and outputting the timed information to the outside. The error information history storage area uses the error information related to the error generated and the time measurement information from the time measuring means as an error information history based on the time measuring means (built-in RTC70a) and at least the command received from the main control unit. Error information registration means (error information registration means 71d) sequentially stored in the error information history display means (error information history display means 71d) and error information history display means (error information history display means 71f) for displaying the error information history stored in the error information history storage area on the display unit. ), And when the setting key switch is operated in the ON state and the menu for displaying the error information history is selected, the error information history display means has the error on the display unit. The information history is displayed, and the error information registration means includes a command in which the received command has no physical layer error and an error detected by a command check process other than the physical layer error, and a command in which the received command has the physical layer error. Even if a certain command has the same command type, it may be stored in the error information history storage area as a different error information history.

According to this configuration, when a communication disconnection state occurs, a code indicating the communication disconnection and a date and time are stored in the storage area for abnormal occurrence, and the stored code indicating the communication disconnection and the date and time when the code is stored are displayed. Can be made to. As a result, when a communication error, communication interruption, and cancellation of communication interruption occur between the main control circuit and the sub control circuit, or when a power failure occurs in the sub control circuit, time information such as an error and communication occur. Since the cutoff release time is stored together with the error code, it becomes possible to later confirm the date and time and contents of the occurrence of an error or the like and the release.

According to the present invention, when a communication error occurs between a main control circuit and a sub control circuit, it is possible to provide a gaming machine capable of confirming the occurrence, date and time, and content of the error.

It is an external view of the gaming machine in this embodiment. It is a figure which shows the symbol display area and the winning line of the gaming machine in this embodiment. It is a figure which shows the symbol arrangement table of the gaming machine in this embodiment. It is a figure which shows the front upper part of the gaming machine in this embodiment. (A) is a figure which shows the left decorative panel and the left infrared sensor of the gaming machine in this embodiment. (B) is a figure which shows the left infrared sensor of the gaming machine in this embodiment. It is a figure which shows the structure of the main control circuit of the gaming machine in this embodiment. It is a figure which shows the structure of the auxiliary control circuit of the gaming machine in this embodiment. It is a figure which shows the area image in the sub ROM of the sub control circuit in this embodiment. It is a figure which shows the area image in the sub RAM of the sub control circuit in this embodiment. It is a figure which shows the area image in the backup RAM of the auxiliary control circuit in this embodiment. It is a figure which shows an example of the structure of the error information history storage area in the sub RAM of the sub control circuit in this embodiment. It is a figure which shows an example of the content of the data stored in the error information history storage area in the sub RAM of the sub control circuit in this embodiment. It is explanatory drawing which shows the ring buffer area for communication log collection in the sub RAM of the sub control circuit in this embodiment. It is explanatory drawing which shows the communication error storage area in the sub RAM of the sub control circuit in this embodiment. It is a figure which shows the transition example of the gaming state of the gaming machine in this embodiment. It is a figure which shows the example of the internal lottery table determination table of the gaming machine in this embodiment. It is a figure which shows the example of the internal lottery table of the gaming machine in this embodiment. It is a figure which shows the example of the internal lottery table for the RB1 gaming state of the gaming machine in this embodiment. It is a figure which shows the example of the internal lottery table for the RB2 gaming state of the gaming machine in this embodiment. It is a figure which shows the example of the RT transition table of the gaming machine in this embodiment. It is a figure which shows the example of the internal winning combination determination table for a bonus of a gaming machine in this embodiment. It is a figure which shows the example of the small winning combination / replay internal winning combination determination table of the gaming machine in this embodiment. It is a figure which shows the example of the symbol combination table of the gaming machine in this embodiment. It is a figure which shows the example of the bonus operation time table of the gaming machine in this embodiment. It is a figure which shows the example of the pull-in priority table A of the gaming machine in this embodiment. It is a figure which shows the example of the pull-in priority table B of the gaming machine in this embodiment. It is a figure which shows the example of the stop table of the gaming machine in this embodiment. It is a figure which shows the example of the internal winning combination storage area of the gaming machine in this embodiment. It is a figure which shows the example of the display combination storage area of the gaming machine in this embodiment. It is a figure which shows the example of the carry-over combination storage area of the gaming machine of this embodiment. It is a figure which shows the example of the game state flag storage area of the game machine of this embodiment. It is a figure which shows the storage example of the symbol storage area A of the gaming machine in this embodiment. It is a figure which shows the storage example of the symbol storage area B of the gaming machine in this embodiment. It is a figure which shows the flowchart of the reset interrupt process by the main CPU performed in the main control circuit in this embodiment. It is a figure which shows the flow chart of the bonus operation monitoring processing performed in the main control circuit in this embodiment. It is a figure which shows the flow chart of the internal lottery processing performed in the main control circuit in this embodiment. It is a figure which shows the flow chart of the internal lottery processing performed in the main control circuit in this embodiment. It is a figure which shows the flow chart of the reel stop control processing performed in the main control circuit in this embodiment. It is a figure which shows the flow chart of the display combination search process performed in the main control circuit in this embodiment. It is a figure which shows the flowchart of the RT control processing performed in the main control circuit in this embodiment. It is a figure which shows the flowchart of the bonus end check processing performed in the main control circuit in this embodiment. It is a figure which shows the flowchart of the bonus operation check process performed in the main control circuit in this embodiment. It is a figure which shows the flowchart of the communication data storage process performed by the main CPU of the main control circuit in embodiment of this invention. It is a figure which shows the flowchart of the interrupt process (1.1173ms) by the main CPU performed in the main control circuit in this embodiment. It is a figure which shows the flowchart of the communication data transmission processing performed by the main CPU of the main control circuit in embodiment of this invention. It is a figure which shows the flowchart of the non-operation command set processing in the communication data transmission processing performed by the main CPU of the main control circuit in embodiment of this invention. It is a schematic diagram which shows the whole management system of the gaming machine in this embodiment. It is a schematic diagram which shows the menu screen of the gaming machine in this embodiment. It is a schematic diagram which shows the error information history screen of the gaming machine in this embodiment. It is explanatory drawing which shows the content of the information of the 2D code used for the management system of the gaming machine in this embodiment. It is explanatory drawing which shows the code number, the type, and the parameter of the received command used for the gaming machine in this embodiment. It is explanatory drawing which shows the recording image of the information of the secondary code when the COM error occurs in the gaming machine in this embodiment, (a) is the case where it happens accidentally during a normal game, (b). Indicates the case where the setting is changed due to the goto action, and (c) indicates the case where the lever continuous transmission is performed. It is a figure which shows an example which notifies the liquid crystal display area of a RAM destruction when there is a RAM destruction in the gaming machine of this embodiment. It is a figure which shows an example of notifying the liquid crystal display area when there is an abnormality in the communication from the main control circuit to the sub control circuit in the gaming machine in this embodiment. It is a figure which shows the flowchart for demonstrating the process at the time of power-on of the sub CPU of the sub control circuit in this embodiment. It is a figure which shows the flow chart of the power interruption interrupt processing of the sub CPU of the sub control circuit in this embodiment. It is a figure which shows the flowchart of the mother task which performs various task activation requests performed by the sub CPU of the sub control circuit in this embodiment. It is a figure which shows the flowchart of the error monitoring task performed by the sub CPU of the sub control circuit in this embodiment. It is a figure which shows the flowchart of the main board communication reception interrupt processing by the sub CPU performed in the sub control circuit in this embodiment. It is a figure which shows the flow chart of the effect registration process performed in the sub-control circuit in this embodiment. It is a figure which shows the flow chart of the effect content determination process performed in the sub-control circuit in this embodiment. It is a figure which shows the flow chart of the effect content determination process performed in the sub-control circuit in this embodiment. It is a figure which shows the flowchart of the fraud determination processing at the time of receiving a reel stop command performed by the sub-control circuit in this embodiment. It is a figure which shows the flowchart of the fraud determination processing at the time of receiving a display command performed by the sub-control circuit in this embodiment. It is a figure which shows the flowchart of the fraud determination processing at the time of receiving a payout command performed by the sub-control circuit in this embodiment. It is a figure which shows the flow chart of the fraud occurrence processing performed in the sub-control circuit in this embodiment. It is a figure which shows the example of the symbol arrangement table for sub CPU fraud determination performed in the sub control circuit in this embodiment. It is a figure which shows the example of the symbol combination table for sub CPU fraud determination performed in the sub control circuit in this embodiment. It is a figure which shows the detailed flowchart of the sub CPU main board communication task performed by the sub control circuit in this embodiment. It is a figure which shows the flowchart of the main board communication reception data log preservation processing performed in the sub-control circuit in this embodiment. It is a figure which shows the flowchart of the main board communication reception data log temporary area preservation processing performed in the sub-control circuit in this embodiment. It is a figure which shows the flowchart of the main board communication error history data storage process performed in the sub-control circuit in this embodiment. It is a figure which shows the flowchart of the main board reception command check processing performed in the sub-control circuit in this embodiment. It is a figure which shows the flowchart of COM error check processing performed in the sub-control circuit in this embodiment. It is a figure which shows the flowchart of the RTC control task performed by the sub CPU of the sub control circuit in this embodiment. It is a figure which shows the flowchart of the backup creation process performed by the sub CPU of the sub control circuit in this embodiment. It is a perspective view which shows the appearance of the gaming machine in another embodiment of this invention. It is a front view which shows the schematic structure of the game board of the game machine in another embodiment of this invention. It is a block diagram which shows the structure of the main control circuit and the sub-control circuit of the gaming machine in another embodiment of this invention.

[Composition of pachislot machine]
Hereinafter, the gaming machine of the present invention will be specifically described with reference to the drawings. In the following embodiment, the gaming machine of the present invention is a gaming machine provided with three rotary reels for variable display of symbols, which are given to a player in addition to coins, medals, tokens, and the like. A gaming machine capable of playing using the gaming value of a card or the like, a so-called pachislot gaming machine, will be described.

Further, in the following embodiments, the pachi-slot gaming machine will be described as an example, but the gaming machine of the present invention is not limited, and a pachinko machine or a slot machine may be used. An example of a pachinko gaming machine will be described later.

First, with reference to FIG. 1, an overview of the pachi-slot gaming machine according to the present embodiment will be described. Note that FIG. 1 is a perspective view of the gaming machine 1 according to the present embodiment.

As shown in FIG. 1, the gaming machine 1 includes a housing 1a that houses reels 3L, 3C, 3R, a main control circuit 60 (see FIG. 6) described later, and the like. The housing 1a includes a front door 1b that can be opened and closed. Further, the gaming machine 1 is provided with a lock mechanism for switching the front door 1b to a locked state or an unlocked state with the front door 1b closed. This lock mechanism is operated by inserting the door key 2 into the door key hole 1c and rotating the door key 2.

On the front surface of the central portion of the front door 1b, a symbol display area 4L, 4C, 4R as a substantially vertical surface and a liquid crystal display area 23 are formed. Inside the front of the central portion of the cabinet 1a, three reels 3L, 3C, and 3R are rotatably provided in a horizontal row. On each of the three reels 3L, 3C, and 3R, a symbol sequence composed of a plurality of types of symbols is drawn on the outer peripheral surface thereof.

The symbols of the reels 3L, 3C, and 3R can be visually recognized through the symbol display areas 4L, 4C, and 4R. Further, each reel 3L, 3C, 3R is controlled by a main control circuit 60 (see FIG. 6) described later so as to rotate at a constant speed (for example, 80 rotations / minute), and is within the symbol display areas 4L, 4C, and 4R. The symbols drawn on the displayed reels 3L, 3C, and 3R fluctuate as the reels rotate.

A pedestal portion 10 having a substantially horizontal plane is formed below the liquid crystal display region 23. On the left side of the pedestal portion 10, a C / P button 14 for switching between credit (Credit) and payout (Pay) of medals acquired by the player in the game, and a push button operation for betting the credited medal. The maximum BET button 13 is provided.

The payout mode or the credit mode is switched by the player's operation on the C / P button 14. In the credit mode, when a prize is established, the number of medals to be paid out corresponding to the prize is credited.

Further, in the payout mode, when a prize is established, the number of medals to be paid out corresponding to the prize is paid out from the medal payout outlet 15 at the lower front, and the medals paid out from the medal payout outlet 15 are sent to the medal receiving unit 16. It can be stored.

In addition, winning means that the combination of symbols related to the small winning combination stops on the effective line. A small role is a role in which a medal is paid out when it is established.

Further, by the player's operation on the maximum BET button 13, the maximum number of medals that can be inserted at that time is inserted among the credited medals. By operating the maximum BET button 13, the winning line described later is activated.

A medal slot 22 is provided on the right side of the pedestal portion 10. Depending on the medals inserted into the medal slot 22, the winning line described later is activated.

A selection button 24 and a decision button 25 are provided on the left side of the medal insertion slot 22. The player can input to the menu screen or the like displayed on the liquid crystal display area 23 by using the selection button 24 and the decision button 25.

Speakers 21L and 21R are provided on the left and right above the medal receiving portion 16. The speakers 21L and 21R output game sounds such as staging sounds and notification sounds according to the game situation.

A start lever 6 is provided on the left side of the front surface portion of the pedestal portion 10. The start lever 6 rotates the reels 3L, 3C, and 3R by the start operation of the player, and starts the fluctuation of the symbols displayed in the symbol display areas 4L, 4C, and 4R.

At the center of the front surface of the pedestal portion 10, on the right side of the start lever 6, three stop buttons 7L for stopping the rotation of the three reels 3L, 3C, and 3R by the player's pressing operation (stop operation), respectively. , 7C, 7R are provided.

Here, the stop of the rotation of the reel that is performed first when the rotation of the three reels 3L, 3C, and 3R is performed is called the first stop, and is performed after the first stop, and the rotation of the two reels is performed. The second stop of reel rotation is called the second stop, which is performed after the second stop, and is finally performed when the remaining one reel is rotated. The stop of reel rotation is called the third stop.

Further, the stop operation for the player to make the first stop is called the first stop operation. Similarly, the stop operation for the player to make the second stop is called the second stop operation, and the stop operation for making the third stop is called the third stop operation.

A light-transmitting upper panel 101 is provided on the upper part of the front door 1b, and an LED (Light Emitting Diode) for an upper panel (not shown) is provided inside the upper panel 101. It should be noted that another light emitter may be used instead of the LED. The upper panel 101 emits light according to the content of the effect described later.

The liquid crystal display area 23 is arranged on the front side of the reels 3L, 3C, and 3R when viewed from the front side, displays an image, and is drawn on the reels 3L, 3C, and 3R in the symbol display areas 4L, 4C, and 4R. It is a transparent display of the drawn design. The transmittance in the symbol display areas 4L, 4C, and 4R can be changed.

The liquid crystal display area 23 displays the number of medals stored (credit) and displays the number of medals to be paid out when a prize is established. Further, the liquid crystal display area 23 displays a frame image having a predetermined shape so as to surround the symbol display areas 4L, 4C, and 4R, and a predetermined image according to the effect content described later.

A lower panel 102 is provided below the liquid crystal display area 23 and above the pedestal portion 10, and an LED for the lower panel 102 (even if another light emitter is used instead of the LED) inside the lower panel 102. Good) is provided. The lower panel 102 emits light according to the content of the effect described later.

A light-transmitting waist panel 103 is provided below the pedestal portion 10, and an LED for the waist panel 103 (an LED may be used instead of the LED) is provided inside the waist panel 103. There is. The waist panel 103 emits light according to the content of the effect described later.

One symbol is displayed in each of the upper, middle, and lower areas in each of the vertically long rectangular symbol display areas 4L, 4C, and 4R, and each symbol display area 4L, 4C, and 4R is on the peripheral surface of the corresponding reel. Three of the arranged symbols are displayed. That is, the symbol display areas 4L, 4C, and 4R have a function as a so-called display window.

Next, the winning line will be described with reference to FIG. In the symbol display areas 4L, 4C, and 4R, five winning lines (center line 8c, bottom line 8d, cross) connecting any of the upper, middle, and lower rows in each of the above-mentioned symbol display areas 4L, 4C, and 4R are connected. Upline 8a, crossdown line 8e and RB middle special line 8f) are provided.

When the rotation of the reels 3L, 3C, and 3R is stopped, the gaming machine 1 determines whether or not the winning combination is established based on the combination of the symbols displayed on the activated winning line. Hereinafter, the activated winning line is referred to as a valid line, and the non-validated winning line is referred to as a non-valid line.

As shown in FIG. 2, the center line 8c is a line connecting the left / middle stage region D, the middle / middle stage region E, and the right / middle stage region F, respectively. The bottom line 8d is a line connecting the left / lower region G, the middle / lower region H, and the right / lower region I, respectively.

The cross-up line 8a is a line connecting the left / lower region G, the middle / middle region E, and the right / upper region C, respectively. The cross-down line 8e is a line connecting the left / upper region A, the middle / middle region E, and the right / lower region I, respectively. The RB middle special line 8f is a line connecting the left / middle region D, the middle / lower region H, and the right / upper region C, respectively.

In the present embodiment, in the BB game state (RB game state), only the special line 8f in the RB becomes an effective line by inserting two medals. On the other hand, in a game state other than the BB game state (RB game state), four winning lines of center line 8c, bottom line 8d, cross-up line 8a, and cross-down line 8e become effective lines by inserting three medals. Become.

The BB1 gaming state to the BB4 gaming state may be collectively referred to as the BB gaming state. Further, the RB1 gaming state to the RB2 gaming state may be collectively referred to as the RB gaming state.

Next, the symbol rows arranged on the reels 3L, 3C, and 3R will be described with reference to the symbol arrangement table shown in FIG. FIG. 3 is a diagram showing an arrangement of symbols drawn on the outer peripheral surfaces of the reels 3L, 3C, and 3R of the gaming machine 1 according to the present embodiment.

On the outer peripheral surfaces of the reels 3L, 3C, and 3R, a symbol row in which 21 symbols of a plurality of types are arranged is drawn. Specifically, a sequence of symbols composed of 7 red symbols, 1 don symbol, 2 don symbols, BAR symbol, wave symbol, 1 bell symbol, 2 bell symbols, 1 cherry symbol, 2 cherry symbols, and a replay symbol is drawn. ing.

The symbol arrangement table is stored in the main ROM 32 of the main control circuit 60, which will be described later. As shown in FIG. 3, in order to associate the rotation positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel, the symbol arrangement table has every 1/21 rotation of the reels 3L, 3C, and 3R. The symbol positions from "0" to "20", which are sequentially assigned to the reels, are specified.

Next, the upper part of the gaming machine will be described with reference to FIG. Note that FIG. 4 is a diagram showing the upper part of the front surface of the gaming machine 1.

As shown in FIG. 4, a display panel unit 110 is provided in the upper center of the liquid crystal display area 23, and a left selection panel 151L and a right selection panel 151R are provided on the left and right sides of the display panel unit 110.

A left decorative panel 121L and a right decorative panel 121R are provided on the upper left and right of the display panel unit 110.

The display panel unit 110 has a plurality of display panels having high light transparency and excellent light guide property, and a plurality of LEDs.

As shown in FIG. 5A, a left infrared sensor 120L is provided behind the left decorative panel 121L. Although not shown, a right infrared sensor 120R is also provided behind the right decorative panel 121R.

The infrared sensors 120L and 120R are so-called reflective infrared sensors, and can detect whether an object (for example, a player's hand) is present or is approaching in the direction in which the infrared beam is output.

As shown in FIG. 5B, the left infrared sensor 120L outputs an infrared beam in the direction of the arrow AR and receives the reflected infrared beam so that the player's hand or the like approaches the vicinity of the left selection panel 151L. Detect that. Similarly, the right infrared sensor 120R also detects whether the player's hand or the like is approaching the vicinity of the right selection panel 151R.

The infrared sensors 120L and 120R are not always operating, but are designed to operate when a specific effect is executed.

Further, in the present embodiment, the reflective infrared sensor is adopted, but other sensors that can detect that the player's hand or the like approaches near the left selection panel 151L and the right selection panel 151R are adopted. May be. Further, the left selection panel 151L and the right selection panel 151R themselves may be used as so-called touch sensors.

[Circuit configuration of gaming machines]
Next, with reference to FIG. 6, the circuit configuration of the gaming machine 1 including the main control circuit 60, the sub control circuit 70, the main control circuit 60, the peripheral device electrically connected to the sub control circuit 70, and the like will be described. Note that FIG. 6 is a diagram showing a circuit configuration of the gaming machine 1.

The main control circuit 60 controls the progress of a series of games such as determination of an internal winning combination and reel rotation control. The main control circuit 60 has a microcomputer 30 arranged on a circuit board as a main component, and is configured by adding a circuit for random number sampling to the main component. The microcomputer 30 is composed of a main CPU 31, a main ROM 32, and a main RAM 33.

The main CPU 31 includes a command transmission means. The command transmission means is adapted to transmit a command to the sub-control circuit 70.

A clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37 are connected to the main CPU 31.

The main CPU 31 determines the internal winning combination based on the random number value and the internal lottery table, and stops the rotation of the reels 3L, 3C, and 3R based on the internal winning combination and the timing at which the stop operation is detected.

Further, the main CPU 31 determines whether or not the combination is established based on the combination of the symbols displayed in the symbol display areas 4L, 4C, and 4R when the rotation of the reels 3L, 3C, and 3R is stopped. If the winning combination is established, the player is given a benefit such as paying out a medal according to the winning combination.

The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse. The random number generator 36 generates a random number in the range of “0” to “65535”. The sampling circuit 37 extracts (samples) one random number value from the random numbers generated by the random number generator 36.

Further, in the gaming machine 1, the extracted random value is stored in the random value storage area of the main RAM 33, which will be described later. Then, based on the random number value stored in the random number value storage area of the main RAM 33 for each game, the internal winning combination is determined in the internal lottery process.

As a means for random number sampling, random number sampling may be executed in the microcomputer 30, that is, on the operation program of the main CPU 31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

The main ROM 32 of the microcomputer 30 stores programs, various tables, and the like related to the processing of the main CPU 31.

Various information obtained by the processing of the main CPU 31 is set in the main RAM 33. For example, information for specifying the extracted random number value, game state, internal winning combination, number of payouts, bonus carry-over status, set value, etc., various counters, and flags are set. A part of this information is transmitted to the sub-control circuit 70 by the above-mentioned command.

Major peripheral devices whose operation is controlled by a control signal from the microcomputer 30 include a hopper 40, stepping motors 49L, 49C, 49R and the like. Signals are exchanged between these actuators and the main CPU 31 via the I / O port 38.

Further, each circuit for controlling the operation of each of the above-mentioned peripheral devices and the like is connected to the output unit of the microcomputer 30 in response to the control signal output from the main CPU 31. Each circuit includes a motor drive circuit 39 and a hopper drive circuit 41.

The hopper drive circuit 41 drives and controls the hopper 40. As a result, the medals housed in the hopper 40 are paid out.

The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, and 49R. As a result, the reels 3L, 3C, and 3R are rotated and stopped.

Further, each switch and each circuit that generates an input signal that triggers the output of a control signal to each of the above-mentioned circuits and peripheral devices are connected to the input unit of the microcomputer 30. As each switch and each circuit, start switch 6S, stop switch 7LS, 7CS, 7RS, maximum BET switch 13S, C / P switch 14S, setting key switch 20S, medal sensor 22S, reset switch 23S, reel position detection circuit 50, There is a payout completion signal circuit 51. The stop switches 7LS, 7CS, and 7RS are collectively referred to as the stop switch 7S. The input of signals between each of these circuits and the main CPU 31 is performed via the I / O port 38.

The start switch 6S detects the player's start operation with respect to the start lever 6, and outputs a start signal instructing the start of the game to the microcomputer 30.

The stop switches 7LS, 7CS, and 7RS detect the player's stop operation for the stop buttons 7L, 7C, and 7R, respectively, and stop the rotation of the reels 3L, 3C, and 3R corresponding to the detected stop buttons 7L, 7C, and 7R, respectively. The commanding stop signal is output to the microcomputer 30.

The maximum BET switch 13S detects a player's insertion operation (pressing operation) for the maximum BET button 13 and outputs a signal instructing the insertion of medals from the credited medals to the microcomputer 30.

The C / P switch 14S detects the player's switching operation with respect to the C / P button 14, and outputs a signal for switching the credit mode or the payout mode to the microcomputer 30. Further, when the credit mode is switched to the payout mode, a signal instructing the payout of the medals credited to the gaming machine 1 is output to the microcomputer 30.

The setting key switch 20S detects that the setting key for operating the setting value of the gaming machine 1 has been operated, and outputs the detection signal to the microcomputer 30.

The medal sensor 22S detects the medal inserted into the medal insertion slot 22 by the player's insertion operation, and outputs a signal indicating that the medal has been inserted to the microcomputer 30.

The reset switch 23S functions as a state release command input means for inputting a state release command, and outputs a signal for canceling a selector error of a selector (not shown) installed inside the gaming machine or a hopper error of the hopper 40. do. The selector error is an error related to the inserted medal passing time, the inserted medal passage check, and the inserted medal retrograde, and the hopper error is an error related to the hopper jam, the hopper empty, and the auxiliary storage full.

The reel position detection circuit 50 detects a pulse signal from the reel rotation sensor and generates a signal for detecting the position of a symbol on each reel 3L, 3C, 3R.

The payout completion signal circuit 51 indicates that the payout of medals is completed when the number of medals detected by the medal detection unit 40S (that is, the number of medals paid out from the hopper 40) reaches the specified number. Generate a signal to indicate.

The sub-control circuit 70 performs various processes such as determination and execution of staging data based on various commands output from the main control circuit 60 such as a start command described later. The sub control circuit 70 does not input commands, information, or the like to the main control circuit 60, and communication is performed from the main control circuit 60 to the sub control circuit 70 in one direction.

The main peripheral devices whose operation is controlled by the control signal from the sub control circuit 70 include a liquid crystal display device 5 as a display unit for displaying an image in the liquid crystal display area 23, speakers 21L, 21R, and various operation panels 101 to. There are 103, a display panel unit 110, an infrared sensor 120L, and 120R.

The sub-control circuit 70 determines and displays an image displayed on the liquid crystal display device 5, determines and outputs a light emission pattern of various operation panels 101 to 103 and the display panel unit 110, and an infrared sensor based on the determined effect data. It determines the production sound and sound effect output from the speakers 21L and 21R, such as determining the operation timing of the 120L and 120R, and controls the output and the like.

The details of the configuration of the sub-control circuit 70 in this embodiment will be described later.

In the game machine 1, when a signal to start the game is output from the start switch 6S by the operation of the player with respect to the start lever 6 on condition that a medal is inserted, a control signal is output to the motor drive circuit 39 and the stepping motor is used. The rotation of the reels 3L, 3C, and 3R is started by the drive control of 49L, 49C, 49R (for example, excitation to each phase, etc.).

At this time, the number of pulses output to the stepping motors 49L, 49C, 49R is counted, and the counted value is set in a predetermined area of the main RAM 33 as a pulse counter.

In the gaming machine 1, when the pulse of "16" is output, the reels 3L, 3C, and 3R move by one symbol. The number of moved symbols is counted, and the counted value is set in a predetermined area of the main RAM 33 as a symbol counter. That is, every time the pulse counter counts "16" pulses, the symbol counter is updated by "1".

The symbol at the symbol position indicated by the value of the symbol counter (see FIG. 3) corresponds to the symbol located on the center line 8c. For example, when the symbol counter of the left reel 3L is "0", the red 7 at the symbol position "0" of the symbol arrangement table shown in FIG. 3 is located on the center line 8c.

Further, a reel index is obtained from the reels 3L, 3C, and 3R for each rotation, and is output to the main CPU 31 via the reel position detection circuit 50. The output of the reel index clears the pulse counter and the symbol counter set in the main RAM 33 to "0".

In this way, the symbol position within the range of one rotation is specified for each reel 3L, 3C, 3R. The distance that each symbol moves by one symbol due to the rotation of the reel is called one frame. That is, moving a symbol by one frame corresponds to updating the symbol counter by "1".

A symbol arrangement table (FIG. 3) is stored in the main ROM 32 in order to associate the rotation positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel. This symbol arrangement table has a code number from "0" to "20", which is sequentially assigned for each fixed rotation pitch of each reel 3L, 3C, 3R, based on the position where the above-mentioned reel index is output. , It is associated with a symbol code that identifies the type of symbol provided corresponding to each code number.

Further, when the start signal is output from the start switch 6S, the random number value is extracted by the random number generator 36 and the sampling circuit 37. When the random number value is extracted, the gaming machine 1 stores it in the random number value storage area of the main RAM 33. Then, the internal winning combination is determined based on the random number value stored in the random number value storage area.

When the stop signal is output from the stop switches 7LS, 7CS, 7RS by the stop operation after the reels 3L, 3C, and 3R reach the constant speed rotation, the output stop signal and the determined internal winning combination are used. A control signal for stopping and controlling the reels 3L, 3C, and 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R, and stops the rotation of the reels 3L, 3C, and 3R.

The gaming machine 1 pulls in the symbol related to the establishment of the internal winning combination by the maximum number of sliding frames, that is, four frames from the time when the stop operation is performed, and stops the rotation of the reel 3. Specifically, the gaming machine 1 determines whether or not there is a symbol related to the establishment of the internal winning combination within 4 frames after the stop operation is detected by the stop switches 7LS, 7CS, and 7RS. If there is a symbol related to the establishment of the internal winning combination within 4 frames, the number of sliding frames is determined so that the symbol is stopped and displayed on the effective line, and the corresponding reel is stopped.

Further, when the gaming machine 1 determines a plurality of roles as the internal winning combination, and if there are a plurality of symbols related to the establishment of the internal winning combination within 4 frames, the gaming machine 1 relates to the internal winning combination having a higher priority. Determine the number of sliding frames so that the symbol is stopped and displayed on the effective line.

Basically, the first priority (highest priority) is a combination of symbols related to replay, and the second priority is a combination of symbols related to small winning combination. Next, the third priority is the combination of symbols related to the bonus.

Further, when the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the symbol position corresponding to the symbol counter of the corresponding reel 3, that is, the symbol position where the rotation of the reel 3 is started to be stopped is set to the "stop start position". The symbol position obtained by adding the number of sliding frames (numerical range "0" to "4") determined to the stop start position, that is, the symbol position at which the rotation of the reel 3 is stopped is referred to as a "scheduled stop position". The number of sliding frames is the amount of rotation of the reel 3 from the time when the stop operation is detected by the stop switches 7LS, 7CS, and 7RS until the rotation of the corresponding reel 3 is stopped. In the gaming machine 1, the maximum number of sliding frames is set to ". 4 "is stipulated.

When the rotation of all the reels 3L, 3C, and 3R is stopped, a display combination search process, that is, a combination determination / failure determination process is performed based on the combination of symbols displayed on the effective line. The search for the display combination is performed based on the symbol combination table described later stored in the main ROM 32. In this symbol combination table, a combination of symbols related to a display combination and a corresponding dividend are set.

When it is determined by the search for the display combination that the combination of the symbols related to the winning is displayed, a control signal is output to the hopper drive circuit 41, and the medals are paid out by driving the hopper 40.

At this time, the medal detection unit 40S counts the number of medals to be paid out from the hopper 40, and when the counted value reaches a specified number, the payout completion signal circuit 51 outputs a signal indicating the completion of medal payout. .. As a result, a control signal is output to the hopper drive circuit 41, and the drive of the hopper 40 is stopped.

When it is determined that the combination of the symbols related to the winning is displayed when the mode is switched to the credit mode by the C / P switch 14S, the number of payouts according to the combination of the symbols related to the winning is calculated in the main RAM 33. Add to the credit counter.

Further, the number of medals paid out is transmitted to the sub-control circuit 70, and based on this, the number of medals paid out and the updated number of credits are displayed in the liquid crystal display area 23. Here, the payout or credit of medals, which is performed when a combination of symbols related to a prize is displayed, may be collectively referred to as “payout”.

Next, the circuit configuration of the sub-control circuit 70 will be described with reference to FIG. 7. Note that FIG. 7 is a diagram showing a circuit configuration of the sub-control circuit 70 of the gaming machine 1.

The sub-control circuit 70 controls for producing a game-related effect using video, sound, light, and the like. The sub control circuit 70 determines the effect data and performs various effect processes based on various commands transmitted from the main control circuit 60 and input information from the selection switch 24S and the determination switch 25S.

The selection switch 24S detects the player's operation on the selection button 24, and moves, for example, a display (for example, an icon) indicating which of the items to be selected displayed on the menu screen or the like is in the selected state. Is output to the sub CPU 71.

Further, the determination switch 25S detects the player's operation on the determination button 25, and outputs, for example, a signal indicating that the player has selected an item in the selected state to the sub CPU 71. That is, the player can select an item on the menu screen or the like by pressing the selection button 24 until the item to be selected is in the selected state and then pressing the enter button 25.

The sub control circuit 70 includes a sub CPU 71 as a processing means, a sub ROM 72 functioning as a processing information storage means, a DRAM 73-1 (also referred to as a “sub RAM73-1”) functioning as a control information storage means, a SRAM 73-2, and a GPU 74. It has a VRAM 75 and a digital amplifier 78.

The sub CPU 71 performs display control of the liquid crystal display device 5, output control of the speakers 21L and 21R, light emission control of various operation panels 101 to 103, display panel unit 110, and the like based on the program stored in the sub ROM 72. Specifically, the sub CPU 71 receives various commands and the like from the main control circuit 60, and stores various information included in the commands in the sub RAM 73-1.

As will be described in detail later, the sub CPU 71 includes a communication error detecting means 71a, a procedure detecting means 71b, a data destruction detecting means 71c, an error information registering means 71d, a received data log saving means 71e, and an error information history displaying means. It includes a 71f, a two-dimensional code conversion means 71g, and a communication disconnection detecting means 71h.

Further, a SRAM 73-2 (also referred to as a “backup RAM 73-2”) described later is connected to the sub CPU 71. The data copied to the sub RAM 73-1 is backed up in the backup RAM 73-2 when the power is turned on.

Further, a door open / close switch 29S is connected to the sub CPU 71. The door open / close switch 29S is a sensor for monitoring the opening / closing of the front door 1b of the gaming machine 1, detects the state in which the front door 1b is opened, and informs the sub CPU 71 from the speakers 21L and 21R, for example, "Door Outputs a signal to issue the warning "Open." The door open / close switch 29S functions as a door open state detecting means.

All information in the main control circuit 60 is transmitted by a command, and the sub control circuit 70 can determine the state of the main control circuit 60 one by one. The sub CPU 71 displays the liquid crystal display device 5, the speakers 21L, 21R, and various operation panels 101 to 103 by executing the program while referring to the game state information, the internal winning combination information, etc. stored in the DRAM 73-1. The content of the effect to be performed by the effect device such as the panel unit 110 is determined.

Further, the sub CPU 71 controls the liquid crystal display device 5 via the GPU 74 based on the determined effect data, and the sounds output from the speakers 21L and 21R, and the various operation panels 101 to 103 and the display panel unit 110. Control the light emission.

The upper panel 101, the waist panel 102, and the lower panel 103 are actually provided with a plurality of LEDs, and these are controlled by input / output processing of ports (not shown) individually provided. Therefore, it is possible to control the light emission individually by each port.

Further, the sub CPU 71 acquires a random number value used when determining the effect data or the like by executing the random number acquisition program stored in the sub ROM 72. However, when the random number generator and the sampling circuit are provided in the sub control circuit 70 as in the main control circuit 60, the process is not necessary.

As shown in FIG. 8, the sub ROM 72 includes an OS area 72a for storing an operating system, a sub control program storage area 72b for storing a program executed by the sub CPU 71, a game data initialization setting data area 72c, and a staff operation. The initial setting data area 72d, various program table areas 72e for storing various tables, the program management data area 72f, the image data (still image / moving image) area 72g, the sound data area 72h, and the accessory movable data area. It has 72i.

The sub-control program storage area 72b is various based on the device driver, the inter-board communication process for controlling the communication with the main control circuit 60, the effect registration process for determining the content of the effect, and the registered LED data. The LED control task for controlling the light output by the operation panels 101 to 103 and the display panel unit 110, and the voice control task for controlling the sound output by the speakers 21L and 21R based on the registered sound data are registered. A drawing control task or the like for controlling the display of an image by the liquid crystal display device 5 based on the animation data is stored.

The various program table areas 72e store the staging lottery table, the error code table of the sub-control circuit shown in FIG. 12, and the like. In addition, the various program table areas 72e are the symbol arrangement table for sub CPU fraud determination shown in FIG. 67 and the subs shown in FIG. 68 for the purpose of determining sub CPU fraud, which will be described later, regarding whether or not the winning combination is correct. Stores the symbol combination table for CPU fraud determination. The symbol arrangement table for determining the sub CPU fraud and the symbol combination table for determining the sub CPU fraud are stored in the main ROM 32 of the main control circuit 60, respectively, and are shown in the symbol arrangement table shown in FIG. 3 and FIG. 23. It is a table created based on the symbol combination table.

The program management data area 72f stores a magic code, a program version, and the like. The image data (still image / moving image) area 72g stores animation data such as character object data. The sound data area 72h stores sound data such as BGM and sound effects. Further, the accessory movable data area 72i stores, for example, LED control data for performing a light lighting pattern or the like.

As shown in FIG. 9, the sub RAM 73-1 includes a game data area 73a-1 as a game data storage area, a game data sum value area 73b-1, a work area 73c-1, and a staff operation setting data area 73g. -1, a staff operation setting data sum value area 73h-1, an error information history storage area 73d-1, a communication log collection ring buffer area 73e-1, and a communication error storage buffer area 73f-1. There is. The clerk operation setting data registered in the clerk operation setting data area 73g-1 is data in which setting items on the menu screen are stored.

The game data area 73a-1 is adapted to store the data stored in the sub RAM 73-1 among the information including the game data related to the progress of the game. The game data sum value area 73b-1 stores the sum value for the checksum of the game data stored in the game data area 73a-1. The work area 73c-1 is designed to store data in various processes.

The game data area 73a-1 and the work area 73c-1 are used as work temporary storage means when the sub CPU 71 executes each program. Further, the game data area 73a-1 is, for example, a command transmitted from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counters, and any of 4 to 8 bytes. Information such as magic code and various flags is stored.

The error information history storage area 73d-1 stores error codes (see FIG. 12) indicating all error information detected by the communication error detecting means 71a, the procedure detecting means 71b, the data corruption detecting means 71c, and the like. ing. In the error information history storage area 73d-1, the error information history is created by sequentially storing the error codes.

In the error information history storage area 73d-1, the error detected by the communication error detecting means 71a is stored as a COM error, and the error detected by the procedure detecting means 71b is stored as a procedure abnormality error. Further, the error detected by the data corruption detecting means 71c is stored as a data corruption error.

Further, in the error information history storage area 73d-1, when the communication interruption detection means 71h of the sub CPU 71 detects the interruption of communication from the main control circuit 60 to the sub control circuit 70, "communication interruption notification" is provided. The error code (COM DCN ALM) is stored together with the occurrence date and time information as the occurrence of, and when the "communication cutoff notification" is canceled, the release time is stored in the error code (COM DCN ALM) stored at the time of occurrence. ..

As shown in FIG. 10, the backup RAM 73-2 is a backup data 2 area 73c-that is a mirroring of the backup data 1 area 73a-2, the backup data 1 sum value area 73b-2, and the backup data 1 area 73a-2. 2. The backup data 2 sum value area 73d-2, the clerk backup data area 73e-2, the error information history storage area 73f-2, and the clerk backup data sum value area 73g-2 are provided.

In the present embodiment, the backup data 1 area 73a-2 and the backup data 2 area 73c-2 are configured as a single backup RAM 73-2. As used herein, "mirroring" is used to mean replicating data, and is not limited to replicating data to another storage.

Further, the backup data 1 area 73a-2 and the backup data 2 area 73c-2 each include an arbitrary magic code of 4 to 8 bytes.

As shown in FIG. 11, the error information history storage area 73d-1 of the sub RAM 73-1 includes an error code (ERROR CODE in the figure), an error occurrence time (“occurrence” in the figure), and an error release time (“occurrence”). In the figure, 128 sets can be stored with "release") as one set.

The error code is 1-byte data, and the content of the error code relating to the communication from the main body, the main control circuit 60 to the sub control circuit 70, and the sub control circuit 70 is the first lever after the power is turned on, as shown in FIG. Power failure error before operation (error code "WDR PRE" in the figure), power failure error after the first lever operation after power-on (error code "WDR POST" in the figure), communication error (in the figure) , "COM error"), procedure error error ("procedure error" in the figure), data destruction error ("sum error" in the figure), communication disconnection error between the main control circuit 60 and the sub control circuit 70. (In the figure, "communication cutoff notification") and other errors are included.

In the error information history storage area 73d-1, the error occurrence time and the error release time are both the year of 2-byte data, the month of 1-byte data, the day of 1-byte data, the time of 1-byte data, and the minute of 1-byte data. It is composed of seconds of 1-byte data.

As shown in FIG. 13, in the communication log collection ring buffer area 73e-1, a number of data groups consisting of 256 command and parameter data sets and one corresponding buffer index are stored as appropriate, and these are ringed. It is designed to function as a buffer.

As shown in FIG. 14, the communication error storage buffer area 73f-1 stores 1024 data groups including 256 command and parameter data sets and one corresponding buffer index. Further, the communication error storage buffer area 73f-1 is provided with one buffer selection index indicating which of the 1024 buffer indexes is selected.

Further, in the communication log collection ring buffer area 73e-1 shown in FIG. 13 and the communication error storage buffer area 73f-1 shown in FIG. 14, the command is composed of one-character data and the parameter is composed of two-character data. ..

Further, as shown in FIG. 7, the sub CPU 71 includes a communication error detecting means 71a, a procedure detecting means 71b, a data destruction detecting means 71c, an error information registering means 71d, a received data log saving means 71e, and error information. It includes a history display means 71f, a two-dimensional code conversion means 71g, and a communication disconnection detecting means 71h.

The communication error detecting means 71a detects that a communication error has occurred between the main control circuit 60 and the sub control circuit 70 by executing the COM error checking process shown in FIG. 74, which will be described later. ..

By executing the main board reception command check process shown in FIG. 73, which will be described later, the procedure detection means 71b detects that the game has progressed in a procedure different from the normal game procedure, that is, in an abnormal procedure. ing.

The data corruption detecting means 71c executes a thumb check process of the sub control game data storage area in the sub CPU main board communication task shown in FIG. 69, which will be described later, so that the game data area 73a-1 of the sub RAM 73-1 (FIG. 9). (See) data corruption, in particular, data corruption related to information such as commands received from the main control circuit 60, effect data information, game status information, internal winning combination information, display combination information, various counters, and various flags can be detected. It has become.

When the error information registration means 71d detects the occurrence of an error by each of the error detection means, the error information registration means 71d stores the error code of the detected error in the error information history storage area 73d-1 of the sub RAM 73-1. ing.

Specifically, when the communication error detection means 71a detects the occurrence of a communication error, the error information registration means 71d stores a COM error error code (COM ERR ALM) in the error information history storage area 73d-1. It is designed to do.

When the error information registration means 71d detects the occurrence of a procedure error error by the procedure detection means 71b, the error information registration means 71d stores the error code (for example, BLS123PE) of the procedure error in the error information history storage area 73d-1. There is.

When the data corruption detection means 71c detects the occurrence of a thumb error, the error information registration means 71d stores the thumb error error code (MEM ERR ALM) in the error information history storage area 73d-1. ing.

Further, when the error information registration means 71d detects the interruption of communication from the main control circuit 60 to the sub control circuit 70 by the communication interruption detection means 71h, the error information registration means 71d cuts off the communication in the error information history storage area 73d-1. The notification error code (COM DCN ALM) is stored.

Further, in the error information history storage area 73d-1, the error information history is created by sequentially storing the error codes.

The received data log saving means 71e collects information about the received log (hereinafter, also referred to as a communication log) by executing the main board communication received data log saving process shown in FIG. 70, which will be described later, and is shown in FIG. 71, which will be described later. By executing the main board communication reception data log temporary area storage process, only one communication log is temporarily stored in the communication log collection ring buffer area 73e-1.

Further, the received data log saving means 71e saves the communication error when the communication error detecting means 71a detects the occurrence of the communication error by executing the main board communication error history data saving process shown in FIG. 72, which will be described later. Up to 1024 communication logs (hereinafter referred to as communication error logs) related to communication errors are stored in the buffer area 73f-1.

When the error information history display means 71f performs a predetermined operation on the door key 2 and receives a predetermined signal from the door key switch 2S, the error information history display means 71f displays the error information history stored in the error information history storage area 73d-1 on the liquid crystal display device 5. It is designed to be displayed.

The two-dimensional code conversion means 71g manages a communication error log related to a communication error stored in the communication error storage buffer area 73f-1 and data management as a transmission destination when the occurrence of a communication error is detected by the communication error detecting means 71a. The domain of the server 500 is converted into the two-dimensional code 300 as transmission information and transmitted to the error information history display means 71f.

Then, as shown in FIG. 49, the error information history display means 71f has a "COM error alarm" item when the "COM error alarm" item 23b is selected in the liquid crystal display area 23 on which the error information history is displayed. The two-dimensional code 300 corresponding to the communication error is displayed on the right side of 23b.

Here, as shown in FIG. 50, the transmission information included in the two-dimensional code 300 created by the two-dimensional code conversion means 71g consists of 192 bytes. The transmission information has a general-purpose configuration so that not only the gaming machine 1 of the model described in the present embodiment but also the error information recorded by the gaming machines of other models can be transmitted. Alternatively, the transmission information may include the player's game record. The items included in the transmission information will be described below.

In the 0th to 28th bytes of the transmission information, the domain of the data management server 500 and the data indicating the request to the data management server 500 are set. A housing-specific code for identifying the gaming machine 1 is set in the 29th to 39th bytes of the transmission information.

The 40th to 61st bytes of the transmitted information are spare areas. The time when the transmission information is generated is set in the 62nd to 67th bytes of the transmission information. A model code indicating the type of the gaming machine 1 is set in the 68th to 71st bytes of the transmission information.

The type number is set in the 72nd to 73rd bytes of the transmission information. Here, both the 72nd byte and the 73rd byte are set to 3FH.

The error type is set in the 74th to 75th bytes of the transmission information. Error information is set in the 76th to 188th bytes of the transmission information. A checksum is set in the 189th to 191st bytes of the transmission information.

The error information set in the 76th to 188th bytes of the transmission information has a command type consisting of one character (6 bits). When the command type is accompanied by a parameter, the command type of one character is followed by a parameter consisting of two characters (12 bits). FIG. 51 shows an example of command types and parameters.

The communication disconnection detecting means 71h detects that the communication from the main control circuit 60 to the sub control circuit 70 is interrupted. It is assumed that communication interruption is detected when the intervals between commands transmitted from the main control circuit 60 to the sub control circuit 70 are separated by a certain period of time, for example, 30 ms or more.

When the communication error detecting means 71a detects the occurrence of a communication error, the error information registering means 71d stores the error code of the communication error in the error information history storage area 73d-1 of the sub RAM 73-1. Then, the received data log saving means 71e saves the communication log in the communication log collecting ring buffer area 73e-1 and saves the communication error log in the communication error saving buffer area 73f-1.

If an error other than the communication error is detected by the procedure detection means 71b other than the communication error detection means 71a, the data destruction detection means 71c, or other error detection means, the error information registration means 71d will perform an error error. The code is stored in the error information history storage area 73d-1 of the sub RAM 73-1. Then, the received data log storage means 71e stores the communication log in the communication log collection ring buffer area 73e-1, but does not store the communication log in the communication error storage buffer area 73f-1.

Then, when the clerk performs a predetermined operation on the door key 2, the error information history display means 71f displays the error information history stored in the error information history storage area 73d-1 on the liquid crystal display device 5. In this case, as shown in FIG. 49, when the "COM ERR ALM" item 23b is selected in the liquid crystal display area 23, the error information history display means 71f communicates with the right side of the "COM ERR ALM" item 23b. The two-dimensional code 300 corresponding to the error is displayed.

In this embodiment, in order to display the error information history shown in FIG. 49 on the liquid crystal display device 5, two types of operation methods, a normal operation and a simple operation by a staff member, are adopted.

In normal operation, a staff member rotates the door key 2 clockwise to release the lock mechanism of the front door 1b, and turns on the setting key to turn on the setting key switch 20S, so that the liquid crystal display area 23 is shown in FIG. 48. The menu screen is displayed. Then, the person in charge operates the operation key to select the "error information history" item 23a, so that the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23.

On the other hand, in the simple operation, the person in charge rotates the door key 2 counterclockwise and holds the state for a certain period of time, for example, 5 seconds or more, so that the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23. ing.

Further, the sub CPU 71 has a built-in RTC70a of a dedicated timekeeping circuit. An external RTC70c is connected to the sub CPU 71 for backup of the built-in RTC70a. A battery 70b is connected to the external RTC 70c and SRAM 73-2. The built-in RTC70a and the external RTC70c are processed by the RTC control task shown in FIG. 75, which will be described later.

The GPU 74 performs a process for displaying an image on the liquid crystal display device 5 based on an image display command or the like received from the sub CPU 71. The data required for the processing performed by the GPU 74 is expanded in the VRAM 75 at startup. The GPU 74 superimposes the image data developed in the VRAM 75 in order from the background image located at the rear to the image located at the front to generate image data, and supplies the image data to the liquid crystal display device 5.

As a result, the image corresponding to the effect data determined by the sub CPU 71 is displayed on the liquid crystal display area 23 by the liquid crystal display device 5.

The VRAM 75 has two frame buffers, a written image data area and a display image data area. The written image data area stores image data for which the GPU 74 has generated a display image, and the display image data area is a display image data area. The image data to be displayed on the liquid crystal display device 5 is stored.

The GPU 74 alternately switches these frame buffers (that is, switches banks) to sequentially display image data on the liquid crystal display device 5.

The digital amplifier 78 amplifies the sound data in the digital format selected by the sub CPU 71 based on the effect data based on the volume adjusted by the volume adjusting knob (not shown) provided in the game machine 1, and is in the analog format. It is converted into the sound data of the above and transmitted to the speakers 21L and 21R. As a result, the sound corresponding to the effect data determined by the sub CPU 71 is output from the speakers 21L and 21R.

[Game state]
Next, the transition of the gaming state will be described with reference to FIG. The main gaming states managed by the main control circuit 60 include a general gaming state, an RT1 gaming state, an RT2 gaming state, an RT3 gaming state, an RT4 gaming state, and a BB gaming state (general term for the BB1 gaming state to the BB4 gaming state). Further, although not shown, there are an SB game state in which only one game coexists with another game state, an RB1 game state that operates in the BB1 game state to the BB3 game state, and an RB2 game state that operates in the BB4 game state.

First, in the general gaming state, the SB spills (SB spills 1 to SB spills 12) are displayed on the effective line, so that the RT1 gaming state is entered. Next, in the RT1 gaming state, the raising 1-step lip 1 is displayed on the effective line, so that the RT2 gaming state is entered. Next, in the RT2 game state, the two-step up rip (up two-step rip 1, the two-step up rip 2) and the second up (up two-step 1 to up two-step 3) are displayed on the effective line, so that RT3 Transition to the game state.

Further, in the RT2 gaming state or the RT3 gaming state, the SB spills (SB spills 1 to SB spills 12) are displayed on the effective line, so that the RT1 gaming state is entered. In the RT1 gaming state to the RT3 gaming state, the push order bell failure (push order bell failure 1 to push order bell failure 4) is displayed on the valid line, so that the general gaming state is entered.

In the general gaming state, the RT1 gaming state to the RT3 gaming state, the BB (BB1 to BB4) is determined as the internal winning combination, so that the transition to the RT4 gaming state occurs. In the RT4 gaming state, when BB (BB1 to BB4) is displayed, the transition to the BB gaming state occurs. When a predetermined number (270 or 60) of medals are paid out in the BB gaming state, the transition to the general gaming state occurs.

Next, with reference to FIG. 16, the internal lottery table determination table stored in the main ROM 32 of the main control circuit 60 will be described. Note that FIG. 16 is a diagram showing an example of an internal lottery table determination table of the gaming machine 1 according to the present embodiment.

The internal lottery table determination table includes an internal lottery table used to determine the internal winning combination in the internal lottery process described later according to the game state (on / off of each game state flag described later), and the number of lottery. Is stipulated. As a result, for example, when only the SB game state flag and the RT1 game state flag are "1 (on)", the "internal lottery table for RT1 game state in SB" is selected as the internal lottery table, and the number of lottery is set. "49" is selected.

Next, the internal lottery table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. 17 to 19. FIG. 17 is a diagram summarizing an example of the internal lottery table for the general gaming state of the gaming machine 1 and the internal lottery table for the RT1 gaming state to the internal lottery table for the RT4 gaming state in the present embodiment.

FIG. 18 is a diagram showing an example of an internal lottery table for the RB1 gaming state of the gaming machine 1 according to the present embodiment.

FIG. 19 is a diagram showing an example of an internal lottery table for the RB2 gaming state of the gaming machine 1 according to the present embodiment. In the SB medium general game state internal lottery table, the SB medium RT1 game state internal lottery table to the SB medium RT4 game state internal lottery table, the lottery values corresponding to the winning numbers "1" in FIG. 17 are "1000", respectively. The only difference is that it is "1001" instead of "", so the illustration is omitted.

The internal lottery table is a table used when performing an internal lottery, that is, when determining an internal winning combination in the internal lottery process described later. In the internal lottery table, a lottery value and a data pointer are defined for each winning number. The lottery value is a numerical value used to determine the data pointer. There are two types of data pointers, a small winning combination / replay data pointer and a bonus data pointer, which correspond to one or more internal winning combinations.

In the right column of the winning number in the internal lottery table shown in FIGS. 17 to 19, the abbreviation of the internal winning combination corresponding to the data pointer is shown. Further, on the right side of each of the internal lottery tables shown in FIGS. 18 and 19, a symbol corresponding to the data pointer, which can be stopped and displayed on the line connecting the upper row, the middle row, or the lower row of each reel, is displayed. Shows a stop type.

For example, in the RB1 game state, when "25" is determined as the data pointer for small winning combination / replay, the stop operation is performed at the timing when the don symbol can be stopped and displayed on the lower stage of the left reel 3L and the lower stage of the middle reel 3C. If this is done, the don symbol is stopped and displayed on the lower row of the left reel 3L and the lower row of the middle reel 3C, but the stop operation is performed at the timing when the don symbol can be stopped and displayed on the lower row of the right reel 3R. Even in this case, the don symbol is not stopped and displayed at the bottom of the right reel 3R.

On the other hand, when "28" is determined as the data pointer for small role / replay, the stop operation is performed at the timing when the don symbol can be stopped and displayed on the lower stage of the left reel 3L, the lower stage of the middle reel 3C, and the lower stage of the right reel 3R. Is performed, and the don symbol is stopped and displayed on the line connecting the lower stages of each reel.

In addition, in the stop type of the symbols aligned on the winning line in FIG. 18, "tempai off" means that even if the stop operation is performed at the timing when the don symbol can be stopped and displayed on the corresponding line. "Don symbol-Don symbol-Don symbol" means a stop type that is not displayed as a stop on the line connecting the upper stage, the middle stage, and the lower stage of each reel.

On the other hand, "per tempai" is a line connecting the upper stages of each reel with "don symbol-don symbol-don symbol" by performing a stop operation at the timing when the don symbol can be stopped and displayed on the corresponding line. , Means a stop type that is displayed as a stop on the line connecting the middle row or the line connecting the lower row.

Next, a method of determining the data pointer using the lottery value, that is, an internal lottery method will be described. In the internal lottery, first, a random number value is extracted from a predetermined numerical value range "0 to 65535", and the lottery value corresponding to each winning number is sequentially subtracted from the extracted random number value and digit is performed. It is done by determining whether or not it is. The digit is performed when the numerical value to be subtracted is smaller, in other words, when the result of the subtraction is negative.

For example, when the internal lottery table for the general game state is determined as the internal lottery table and the extracted random number value is "1500", the main CPU 31 first corresponds to the winning number "1" from "1500". The lottery value "1000" is subtracted. The subtraction result is "1500-1000 = 500", which is positive.

Next, the main CPU 31 subtracts the lottery value "2100" corresponding to the winning number "2" from the subtracted value "500". The subtraction result is "500-2100 = -1600", which is negative. Therefore, the main CPU 31 determines the winning number "2" as the internal winning combination, that is, "13" as the small winning combination / replay data pointer and "0" as the bonus data pointer.

According to this internal lottery method, the larger the number defined as the lottery value, the more likely it is that the data pointer of the corresponding winning number will be determined. The winning probability of each winning number is "the lottery value corresponding to each winning number / the number of all random value values that may be extracted (" 65536 ")".

The various lottery performed using the lottery value described later is the same as the case of determining the data pointer. That is, in the tables for various lottery, the lottery value is defined corresponding to the item (for example, the winning number) that may be selected by the lottery. Hereinafter, the various lottery methods based on the lottery value are the same as the internal lottery method, and thus the description thereof will be omitted.

Next, the RT transition table will be described with reference to FIG. The RT transition table is a table used when updating the game state flag in the RT control process described later. As shown in FIG. 20, the RT transition table defines a display combination and correspondingly controlled contents for the game state flag.

Specifically, when the combination of the symbols pertaining to any of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the valid line, all the game status flags are turned off. That is, the general gaming state is activated. Further, when the combination of the symbols pertaining to any one of the SB spills 1 to the SB spills 12 is stopped and displayed on the effective line, the RT1 game state flag is turned on. Further, when the combination of symbols related to the 1-step raising 1-step lip 1 is stopped and displayed on the effective line, the RT2 game state flag is turned on. In addition, when the combination of symbols related to any of the two-step up rip 1, the two-step up rip 2, the up two-step 1 to the up two-step 3 is stopped and displayed on the valid line, the RT3 game status flag is turned on. do.

In addition, push order bell failure 1 to push order bell failure 4, SB spills 1 to SB spill 12, raise 1 step rip 1, raise 2 step rip 1, raise 2 step rip 2, raise 2nd 1 to raise 2 3 is a case where a predetermined combination is determined as an internal winning combination, and when a stop operation is performed according to a predetermined stop operation order, the stop operation order is different from the predetermined stop operation order. It is a display combination that may be stopped and displayed on the valid line when the operation is performed or when the stop operation is not performed at an appropriate timing, and the details will be described later.

Next, with reference to FIGS. 21 and 22, the bonus internal winning combination determination table and the small winning combination / replay internal winning combination determination table stored in the main ROM 32 of the main control circuit 60 will be described. Note that FIG. 21 is a diagram showing an example of an internal winning combination determination table for bonuses of the gaming machine 1 in the present embodiment. Further, FIG. 22 is a diagram showing an example of an internal winning combination determination table for small winning combination / replay of the gaming machine 1 in the present embodiment. Hereinafter, the internal winning combination determination table for bonuses and the internal winning combination determination table for small roles / replays are collectively referred to as the internal winning combination determination table.

The internal winning combination determination table is a table used when determining the internal winning combination based on the data pointer in the internal lottery process described later. The internal winning combination determination table defines each combination determined as the internal winning combination corresponding to the data pointer. Each combination corresponds to each bit stored in the internal winning combination storage area described later. Therefore, which combination is the internal winning combination can be identified by whether or not which bit in the internal winning combination storage area is "1".

In the bonus internal winning combination determination table shown in FIG. 21, the internal winning combination corresponding to the bonus data pointers "1" to "5" is defined. When "5" is determined as the bonus data pointer, the combination of symbols related to SB is stopped and displayed on the valid line depending on whether or not the stop operation is performed in the predetermined stop order. , The combination of the symbols pertaining to any of SB spills 1 to SB spills 12 is stopped and displayed on the effective line.

In the small winning combination / replay internal winning combination determination table shown in FIG. 22, the internal winning combination corresponding to the small winning combination / replay data pointers “1” to “31” is defined. For example, when "1" is determined as the small winning combination / replay data pointer, the normal rip 1 and the raised one-step rip 1 become the internal winning combination.

When "2" is determined as the small winning combination / replay data pointer, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the second stop operation is performed on the right reel 3R. 3 Only when the stop operation is performed, the combination of the symbols related to the raising 1-step lip 1 is stopped and displayed on the effective line. On the other hand, when the stop operation is performed in the stop operation order other than this, the combination of the symbols related to the normal lip 1 is normally displayed as a stop on the effective line.

For the small role / replay data pointers "3" to "6", the stop operation order in which the combination of symbols related to the raised 1-step lip 1 is stopped and displayed on the valid line is predetermined, and this stop operation order is defined. When the stop operation is performed in the stop operation order other than the normal stop operation, the combination of symbols related to the normal lip 1 is stopped and displayed on the valid line.

Further, when "7" is determined as the data pointer for the small winning combination / replay, only when the first stop operation is performed on the left reel 3L, the raising 2-step rip 1 and the raising 2-step rip 2 are performed. The combination of the symbols corresponding to any of the raising 2nd stitch 1, the raising 2nd stitch 2 and the raising 2nd stitch 3 is stopped and displayed on the effective line.

When the raising 2nd stitch 1, the raising 2nd stitch 2 and the raising 2nd stitch 3 are stopped and displayed on the effective line, the normal rip 1 or the raising 1-step rip 1 is stopped and displayed on the effective line at the same time. On the other hand, when the stop operation is performed in the stop operation order other than this, the combination of the symbols related to the normal lip 1 is normally displayed as a stop on the effective line.

For the data pointers "8" to "11" for small roles and replays, the combination of the symbols related to the two-step up rip 1, the two-step up rip 2, the two up two-step rip 2, the up two-eyed one, the up two-eyed two, and the up two-step rip 3 is effective. The stop operation order in which the stop is displayed on the line is predetermined, and when the stop operation is performed in a stop operation order other than this stop operation order, the combination of symbols related to the normal lip 1 is normally on the effective line. Stop is displayed.

When "12" is determined as the small winning combination / replay data pointer, the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C regardless of the stop operation order.

When "13" is determined as the small win / replay data pointer, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the third stop operation is performed on the right reel 3R. Only when the operation is performed, the symbol related to the bell is stopped and displayed in the middle stage of the middle reel 3C.

On the other hand, when the stop operation is performed in the stop operation order other than this, the combination of the symbols pertaining to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the valid line. When the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C, "Bell 1 symbol (bell 2 symbol) -bell 1 symbol-" is displayed on any of the center line 8c, the cross-up line 8a, and the cross-down line 8e. "Bell 1 symbol" is stopped and displayed.

Further, when the combination of the symbols pertaining to any of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the effective line, the lower row of the left reel 3L, the lower row of the middle reel 3C, and the lower row of the right reel 3R are displayed. , "Bell 1 symbol (bell 2 symbol) -bell 1 symbol-bell 1 symbol" is stopped and displayed.

For the small combination / replay data pointers "14" to "17", the stop operation order in which the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C is predetermined, and the stop operation order other than this stop operation order is predetermined. When the stop operation is performed in order, the combination of the symbols pertaining to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the valid line.

If a small winning combination / replay pointer whose abbreviation suggests a stop operation order (pushing order) for the reels is determined in the internal lottery table, the suggested pushing order is the so-called correct pushing order. By performing the stop operation in the order of pushing, each reel 3 is stopped so as to be advantageous to the player.

For example, when the small winning combination / replay pointer "2" (abbreviated as "left middle right bell") is determined, the first stop operation is performed on the left reel 3L, and the second stop operation is performed on the middle reel 3C. Only when the third stop operation is performed on the right reel 3R, the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C (number of payouts: 4 sheets x 3 lines = 12 sheets), and the other push orders. If this is the case, the symbol related to the bell is stopped and displayed at the bottom of the middle reel 3C (number of payouts: 4 sheets x 1 line = 4 sheets). The small winning combination / replay pointers whose abbreviations indicate the stop operation order (pushing order) for the reels are "2" to "11" and "13" to "17".

Next, with reference to FIG. 23, the symbol combination table stored in the main ROM 32 of the main control circuit 60 will be described. Note that FIG. 23 is a diagram showing an example of the symbol combination table of the gaming machine 1 in the present embodiment.

In the symbol combination table, the combination of symbols related to the privilege grant displayed on the valid line, the combination of symbols related to the transition of the gaming state, and the data indicating the display combination corresponding to the combination of the symbols and the storage area type. , And the number of payouts is specified. The data indicating the display combination is any one of the display combination storage area 1 to the display combination storage area 7 (the display combination storage area 1 to the display combination storage area 7 are collectively referred to as the display combination storage area), each of which is composed of 1 byte, which will be described later. It is the data stored in. In addition, which display combination storage area the data is stored in is defined by the storage area type.

In the symbol combination table, as display roles, BB1 to BB4, SB, normal rip 1, raised 1-step rip 1, raised 2-step rip 1, raised 2-step rip 2, control rip 1 to control rip 3, bell, ice 1 , Cherry 1 to Cherry 12, Control 1 to Control 3, BB Medium 1 to BB Medium 5, Raise 2 1 to Raise 2 3, Push Order Bell Failure 1 to Push Order Bell Failure 4, SB Spills 1 to SB spills 12 are specified.

For example, the normal lip 1 is established when "replay symbol-replay symbol-replay symbol" is displayed on the effective line. If any of the various replays (normal rip 1, up 1 step rip 1, up 2 step rip 1, up 2 step rip 2, control rip 1 to control rip 3) is established, the replay will be performed in the next game. Will be. That is, in the next game, the same number of medals as the number of medals inserted in the game in which any of the various replays is established is automatically inserted without being based on the insertion operation by the player.

As a result, the player can play the next game without consuming medals. Here, the above-mentioned payout of medals and re-games are examples of imparting game value. The bell is established when "ANY symbol-Bell 1 symbol-ANY symbol" is displayed on the valid line. In addition, "ANY" means that any symbol may be used.

Next, with reference to FIG. 24, the bonus operation time table stored in the main ROM 32 of the main control circuit 60 will be described. Note that FIG. 24 is a diagram showing an example of a bonus operating table of the gaming machine 1 according to the present embodiment.

The bonus operating table is a table used when setting the BB gaming state and the condition for ending the RB gaming state. The end conditions related to the BB1 gaming state to the BB4 gaming state, the RB1 gaming state, and the RB2 gaming state are defined in the bonus operating table. Specifically, in the bonus operating table, "270" is specified for the value of the bonus end number counter as the end condition of the BB1 game state to the BB3 game state.

Further, as an end condition of the BB4 game state, "60" is specified for the value of the bonus end number counter. The RB1 gaming state operates from the BB1 gaming state to the BB3 gaming state, and the RB2 gaming state operates in the BB4 gaming state. Further, in the bonus operating table, "12" and "8" are defined for the values of the number of possible games and the number of times the prize can be won, respectively, as the end conditions of the RB1 game state and the RB2 game state.

Next, the pull-in priority table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. 25 and 26. Note that FIG. 25 is a diagram showing an example of the attraction priority table A of the gaming machine 1 in the present embodiment, and FIG. 26 shows an example of the attraction priority table B of the gaming machine 1 in the present embodiment. It is a figure. Hereinafter, the pull-in priority table A and the pull-in priority table B are collectively referred to as a pull-in priority table.

In the pull-in priority table, when multiple wins are determined as internal winning wins, when the multiple wins can be pulled into the valid line, the symbol related to any of the wins is given priority on the valid line. It stipulates whether to stop. As mentioned above, basically, the order of priority is replay, small winning combination (the higher the number of payouts, the higher the priority. In the case of JAC1 (7 in BB), this is prioritized), and the bonus. It has become.

However, in the present embodiment, there are a plurality of types of replays, and the priority of each replay differs depending on the conditions. Therefore, a pull-in priority table A and a pull-in priority table B are provided for each of the conditions.

The pull-in priority table A is a table used at normal times (including during BB) and at the time of so-called push order correct answer, and the priority of each replay is raised 2 step rip 1, raised 2 step rip 2> raised 1 step rip 1 > Normal lip 1> Control lip 1-Control lip 3 in this order.

On the other hand, the pull-in priority table B is a table used when the so-called push order is incorrect, and the priority of each replay is usually rip 1> up 2-step rip 1, up 2-step rip 2, up 1-step rip 1> control. The order is Lip 1-Control Lip 3.

Although not shown, when two or more combinations related to the transition of the RT gaming state simultaneously serve as display combinations, which one is prioritized is predetermined. In the present embodiment, in order from the higher priority combination, raising 2 step rip 1, raising 2 step rip 2, raising 2nd 1-raising 2nd 3> raising 1 step rip 1> SB spill 1-SB spill Eye 12> Push order bell failure 1-Push order bell failure 4.

Next, the stop table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. 27. Note that FIG. 27 is a diagram showing an example of a stop table for when the small winning combination / replay data pointer “15” is won and when the middle reel is first stopped. The stop table defines line data and stop data corresponding to the symbol positions "0" to "20". The symbol position is a symbol position located in the middle of the symbol display area when a stop operation is detected, and is a symbol position at which the rotation of the reel is started to stop.

Although not shown, the main ROM 32 of the main control circuit 60 stores a small combination / replay data pointer and a plurality of stop tables according to the stop operation order of the player. For example, when "5" is determined as the bonus data pointer, the first stop operation is performed on the right reel 3R, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the middle reel 3C. Only when the above is performed, a stop table in which the number of slip frames is specified so that none of the SB spills 1 to SB spills 12 is stopped and displayed on the effective line is selected.

On the other hand, when the stop operation is performed in the stop operation order other than this stop operation order, the SB spill 1 is performed when the stop operation is performed for each reel at the timing when the combination of symbols related to SB is not stopped and displayed. A stop table in which the number of slip frames is specified is selected so that the combination of symbols pertaining to any of the SB spills 12 is stopped and displayed on the effective line.

Next, with reference to FIGS. 28 to 30, the internal winning combination storage area, the display combination storage area, and the carryover combination storage area allocated to the main RAM 33 of the main control circuit 60 will be described. Note that FIG. 28 is a diagram showing an example of the internal winning combination storage area of the gaming machine 1 according to the present embodiment. Further, FIG. 29 is a diagram showing an example of a display combination storage area of the gaming machine 1 according to the present embodiment. Further, FIG. 30 is a diagram showing an example of a carry-over combination storage area of the gaming machine 1 according to the present embodiment.

As shown in FIG. 28, the internal winning combination storage area is composed of the internal winning combination storage area 1 to the internal winning combination storage area 5. The internal winning combination storage area 1 to the internal winning combination storage area 5 are 8-bit data areas allocated on the main RAM 33, respectively, and store internal winning combination information. Each internal winning combination storage area indicates which combination is the internal winning combination by storing the data of "0" or "1" in the area of the bits "0" to "7".

As shown in FIG. 29, the display combination storage area is composed of the display combination storage area 1 to the display combination storage area 7. The display combination storage area 1 to the display combination storage area 7 are 8-bit data areas allocated on the main RAM 33, respectively, and store display combination information. Each display combination storage area indicates which combination is the display combination by storing the data of "0" or "1" in the area of the bits "0" to "7".

As shown in FIG. 30, the carry-over combination storage area is an 8-bit data area allocated on the main RAM 33, and stores carry-over combination information. The carry-over combination storage area indicates which combination is the carry-over combination by storing the data of "0" or "1" in the area of bits "0" to "3".

Next, with reference to FIG. 31, the game state flag storage area allocated to the main RAM 33 of the main control circuit 60 will be described. Note that FIG. 31 is a diagram showing an example of the game state flag storage area of the game machine 1 in the present embodiment.

As shown in FIG. 31, the game state flag storage area is composed of the game state flag storage area 1 and the game state flag storage area 2. The game state flag storage area is an 8-bit data area allocated on the main RAM 33, and indicates whether each game state flag is on or off. Further, when all the data in each area of the game state flag storage area is "0", it indicates that the game state is in the general game state.

Next, the symbol storage area in the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. 32 and 33. Note that FIG. 32 is a diagram showing a storage example (when the symbol position data of each reel is “0”) of the symbol storage area A (in the non-RB) of the gaming machine 1 in the present embodiment. FIG. 33 shows a storage example of the symbol storage area B (in RB) of the gaming machine 1 in the present embodiment (when the symbol position data of each reel is “9”, “8”, “9” from the left reel. ).

The symbol storage area is an area for storing the corresponding symbol code in the symbol display areas 4L, 4C, and 4R constituting each effective line, and is provided for each effective line. For example, when the gaming state is a gaming state other than the RB gaming state, it corresponds to each of the middle row of the left symbol display area 4L, the middle row of the middle symbol display area 4C, and the middle row of the right symbol display area 4R constituting the center line 8c. Store the symbol code.

Such a symbol storage area is also provided for other effective lines (cross-down line 8e, bottom line 8d, cross-up line 8a). When the gaming state is the RB gaming state, the effective line is only one line (RB medium special line 8f), and the RB medium special line 8f is configured in the symbol storage area corresponding to the RB medium special line 8f. The symbol code corresponding to each of the middle row of the left symbol display area 4L, the lower row of the middle symbol display area 4C, and the upper row of the right symbol display area 4R is stored.

The symbol storage area shown in FIG. 32 shows a symbol storage area when the symbol code is stored when the symbol position data of each reel is “0”. When the symbol position data is "0", the symbol of the symbol position "0" of each reel 3L, 3C, 3R (red 7 symbol on the left reel 3L, red 7 symbol on the middle reel 3C, red on the right reel 3R). 7 symbols) are displayed in the middle of the left symbol display area 4L, the middle of the middle symbol display area 4C, and the middle of the right symbol display area 4R, respectively.

Therefore, in this case, the symbol (wave symbol) of the symbol position "1" is in the symbol storage area corresponding to the upper part of the left symbol display area 4L, and the symbol position "" is in the symbol storage area corresponding to the lower part of the left symbol display area 4L. A symbol code indicating the symbol (replay symbol) of "20" will be stored. Further, the symbol (replay symbol) of the symbol position "1" is in the symbol storage area corresponding to the upper part of the middle symbol display area 4C, and the symbol position "20" is in the symbol storage area corresponding to the lower part of the middle symbol display area 4C. A symbol code indicating a symbol (cherry 1 symbol) will be stored.

Further, the symbol with the symbol position "1" (cherry 1 symbol) is in the symbol storage area corresponding to the upper part of the right symbol display area 4R, and the symbol position "20" is in the symbol storage area corresponding to the lower part of the right symbol display area 4R. The symbol code indicating the symbol (bell 1 symbol) is stored.

[Control operation of main control circuit]
Next, the control operation of the main CPU 31 of the main control circuit 60 will be described with reference to the flowcharts shown in FIGS. 34 to 46.

First, the reset interrupt process by the main CPU 31 of the main control circuit 60 will be described with reference to FIG. 34. Note that FIG. 34 is a diagram showing a flowchart of the reset interrupt process performed by the main CPU 31 in the main control circuit 60 of the present embodiment. Further, the main CPU 31 generates a reset interrupt by turning on the power and applying a voltage to the reset terminal, and based on the occurrence of the interrupt, the reset interrupt process stored in the main ROM 32 is sequentially performed. It is configured to do.

First, the main CPU 31 clears the designated storage area (step S1). Specifically, the main CPU 31 clears the designated storage area of the main RAM 33 at the end of the previous game. More specifically, the main CPU 31 erases the data in the writable area in the main RAM 33 used in the previous game, writes the parameters necessary for this game to the writable area in the main RAM 33, and in this game. Specify the start address for the sequence program.

Next, the main CPU 31 performs a bonus operation monitoring process (step S2).

Next, the main CPU 31 performs medal acceptance / start check processing (step S3). In the medal reception / start check process, the input number counter is updated by checking the medal sensor 22S and the maximum BET switch 13S, and the input check of the start switch 6S is performed. The main CPU 31 activates the winning line by the medal reception / start check process.

Next, the main CPU 31 performs a process of extracting the random number value and storing it in the random number value storage area (step S4). Specifically, the main CPU 31 extracts a random number value from the range of "0" to "65535" by the random number generator 36 and the sampling circuit 37, and stores the extracted random number value in the random number value storage area of the main RAM 33.

Next, the main CPU 31 performs an internal lottery process (step S5). Specifically, the main CPU 31 refers to the above-mentioned internal lottery table determination table (see FIG. 16), internal lottery table (see FIGS. 17 to 19), and internal winning combination determination table (see FIGS. 21 and 22). To determine the internal winning role.

Next, the main CPU 31 transmits the start command data to the sub control circuit 70 (step S6). The start command includes information such as game status information, internal winning combination information (small winning combination / replay data pointer, bonus data pointer and internal winning combination storage area), and carry-over status information indicating whether or not the bonus is carried over. It is included.

As a specific process, the main CPU 31 sets parameters such as flags and counters, sets a start command, and performs a communication data storage process described later, thereby storing communication data in a communication data storage area. It is designed to be registered in. The following command data is also transmitted to the sub-control circuit 70 in the same manner.

Next, the main CPU 31 requests the start of rotation of all reels (step S7). When the rotation start of all reels is requested, the rotation start processing and the acceleration control processing of the reels 3L, 3C and 3R are performed.

Next, the main CPU 31 waits for the reel rotation at a constant speed (step S8).

Next, the main CPU 31 performs a reel stop control process (step S9). In this reel stop control process, the main CPU 31 stops the rotation of each reel 3L, 3C, 3R based on the stop signals transmitted from the stop switches 7LS, 7CS, 7RS, etc. by the player's stop operation.

Next, the main CPU 31 performs a display combination search process (step S10). In this display combination search process, the main CPU 31 determines the display combination and the number of payouts based on the combination of the symbols displayed on the effective line as a result of stopping the rotation of all reels 3L, 3C, and 3R.

Next, the main CPU 31 performs RT control processing (step S11).

Next, the main CPU 31 transmits display command data (step S12). The display command includes information such as display combination information indicating a display combination and payout number information indicating the number of payouts.

As a specific process, the main CPU 31 sets, for example, the RT operation combination display flag in P1 and the winning number counter in P2. Then, the main CPU 31 sets a display command and performs a communication data storage process described later, so that the communication data to be transmitted is registered in the communication data storage area.

Next, the main CPU 31 performs a medal payout process (step S13). Specifically, in the payout mode, the main CPU 31 drives and controls the hopper 40 by the hopper drive circuit 41 based on the number of payouts to pay out medals, and in the credit mode, the main CPU 31 is based on the number of payouts. The credit counter set in the RAM 33 is updated.

Next, it is determined whether or not the bonus operation is in progress (step S14). Specifically, it is determined whether or not the game is in the BB1 gaming state to the BB4 gaming state, or in the SB gaming state. At this time, when the main CPU 31 determines that the bonus operation is in progress, the bonus end check process is performed (step S15), and the process proceeds to the process of step S16. On the other hand, when the main CPU 31 determines that the bonus operation is not in progress, or after the process of step S15 is completed, the main CPU 31 then performs a bonus operation check process (step S16).

As described above, the main CPU 31 executes the processes from step S1 to step S16 as the processes in one game (one game), and when the process of step S16 is completed, the process of step S1 is executed so as to execute the process in the next game. Move to.

Next, the bonus operation monitoring process will be described with reference to FIG. 35. Note that FIG. 35 is a diagram showing a flowchart of the bonus operation monitoring process performed by the main control circuit 60 of the present embodiment.

First, the main CPU 31 determines whether or not it is in the BB gaming state (step S31). At this time, when the main CPU 31 determines that it is in the BB gaming state, it shifts to the process of step S32. On the other hand, when the main CPU 31 determines that the game is not in the BB game state, the main CPU 31 ends the bonus operation monitoring process.

When the main CPU 31 determines in the process of step S31 that it is in the BB gaming state, it then determines whether or not it is in the RB gaming state (step S32). At this time, when the main CPU 31 determines that the game is in the RB game state, the main CPU 31 ends the bonus operation monitoring process.

On the other hand, when the main CPU 31 determines that it is not in the RB gaming state, it performs RB operation time processing according to the type of BB based on the bonus operation time table (see FIG. 24) (step S33), and performs bonus operation monitoring processing. To finish. Specifically, in the case of the BB1 gaming state to the BB3 gaming state, the RB1 gaming state is activated, and in the case of the BB4 gaming state, the RB2 gaming state is activated.

Next, the internal lottery process will be described with reference to FIGS. 36 and 37. 36 and 37 are diagrams showing a flowchart of the internal lottery process performed by the main control circuit 60 of the present embodiment.

First, the main CPU 31 refers to the internal lottery table determination table (see FIG. 16) and determines the type of the internal lottery table and the number of lottery based on the game status flag (step S61). Next, the main CPU 31 acquires a random number value from the random number value storage area and sets it as a determination random number value (step S62). Next, the main CPU 31 sets "1" as the initial value of the winning number (step S63).

Next, the main CPU 31 refers to the internal lottery table and acquires the lottery value based on the winning number (step S64). Next, the main CPU 31 subtracts the lottery value from the determination random value and sets the subtraction result as the determination random value (step S65). Specifically, the main CPU 31 subtracts the lottery value acquired in the process of step S64 from the determination random value stored in the determination random value storage area, and updates the determination random value storage area according to the subtraction result. ..

Next, the main CPU 31 determines whether or not the digit has been performed in the subtraction process in step S65, that is, whether or not the subtraction result has become a negative value (step S66). At this time, when it is determined that the digit has been digitized, the main CPU 31 acquires the small winning combination / replay data pointer and the bonus data pointer based on the winning number (step S70), and proceeds to the process of step S71.

On the other hand, when the main CPU 31 determines that the digit has not been performed, it then subtracts "1" from the number of lottery and adds "1" to the winning number (step S67). Next, the main CPU 31 determines whether or not the number of lottery is "0" (step S68).

When the main CPU 31 determines that the number of lottery is "0" in the process of step S68, the main CPU 31 determines each of the small winning combination / replay data pointer and the bonus data pointer to "0" (step S69), and in step S71. Move to processing. On the other hand, when the main CPU 31 determines that the number of lottery is not "0", the main CPU 31 proceeds to the process of step S64. After that, the main CPU 31 repeats the processes from step S64 to step S68 until the number of lottery becomes "0" or the digit is counted.

After the processing of step S69 or step S70 is completed, the main CPU 31 then refers to the internal winning combination determination table for small winning combination / replay (see FIG. 22), and the internal winning combination is based on the small winning combination / replay data pointer. Acquire a combination (step S71). Next, the main CPU 31 updates the internal winning combination storage area according to the internal winning combination (step S72).

Next, the main CPU 31 determines whether or not the carry-over combination storage area is "0000000000" (step S73). At this time, when the main CPU 31 determines that the carry-over combination storage area is not "000000", the main CPU 31 shifts to the process of step S80. On the other hand, when the main CPU 31 determines that the carry-over combination storage area is "000000", the main CPU 31 refers to the bonus internal winning combination determination table (FIG. 21) and acquires the internal winning combination based on the bonus data pointer (FIG. 21). Step S74).

Next, the main CPU 31 determines whether or not the SB is an internal winning combination (step S75). At this time, when the main CPU 31 determines that the SB is the internal winning combination, the main CPU 31 updates the internal winning combination storage area according to the SB (step S76), and proceeds to the process of step S80. On the other hand, when the main CPU 31 determines that the SB is not an internal winning combination, the main CPU 31 determines whether or not the BB is an internal winning combination (step S77).

When the main CPU 31 determines in the process of step S77 that the BB is not an internal winning combination, the main CPU 31 shifts to the process of step S80. On the other hand, when the main CPU 31 determines that the BB is the internal winning combination, the main CPU 31 updates the carry-over combination storage area according to the BB (step S78), turns on the RT4 game state flag (step S79), and processes in step S80. Move to.

When the main CPU 31 determines that the carry-over combination storage area is not "0000000000" in the process of step S73, and determines that the BB is not an internal winning combination in the process of step S77, the processes of steps S76 and S79. Next, the carry-over combination storage area and the internal winning combination storage area 1 are ORed, and the result is stored in the internal winning combination storage area 1 (step S80).

The main CPU 31 repeatedly executes the processes of steps S64 to S68 in the internal lottery process to draw the internal winning combination. Specifically, the main CPU 31 sequentially subtracts the lottery value from the extracted random number value to obtain a small winning combination / replay data pointer and a bonus data pointer corresponding to the winning number when the digit is performed. The internal winning combination is determined based on each of the determined data pointers and the internal winning combination determination table.

Next, the reel stop control process will be described with reference to FIG. 38. Note that FIG. 38 is a diagram showing a flowchart of the reel stop control process performed by the main control circuit 60 of the present embodiment.

First, the main CPU 31 sets "3" in the stop button non-operation counter (step S101), and then acquires a stop table according to the internal winning combination (step S102).

Next, the main CPU 31 determines whether or not a valid stop button has been pressed (step S103). A valid stop button is a stop button that has not been stopped. At this time, when the main CPU 31 determines that the valid stop button has been pressed, the process proceeds to the process of step S104.

On the other hand, when the main CPU 31 determines that the valid stop button has not been pressed, the main CPU 31 executes the process of step S103 again. That is, the main CPU 31 repeats the process of step S103 until a stop operation corresponding to a valid stop button is detected.

When the main CPU 31 determines that a valid stop button has been pressed in the process of step S103, the main CPU 31 invalidates the operation of the corresponding stop button (step S104). Then, the stop table is reselected according to the operation stop button (stop order) (step S105).

Next, the main CPU 31 sets "5" as the number of checks (step S106). Next, the main CPU 31 refers to the pull-in priority table (see FIGS. 25 and 26), and based on the internal winning combination, the symbol having the highest priority within the range of the number of checks from the symbol position corresponding to the symbol counter. Search for a position (step S107).

Next, the main CPU 31 determines the number of slip frames based on the stop table, the symbol position corresponding to the symbol counter, and the search result, and sets the scheduled stop position (step S108). Next, the main CPU 31 transmits a reel stop command (step S109). The reel stop command includes information such as stop reel type information indicating which reel has stopped, stop start position information indicating a stop start position, and slip frame number information indicating the number of slip frames.

Next, the main CPU 31 refers to the symbol arrangement table (see FIG. 3), acquires a symbol code based on the stop reel, the scheduled stop position, and the game state, and stores the symbol code in the symbol storage area (step S110).

Finally, the main CPU 31 determines whether or not there is a stop button for which the operation is valid (step S111). At this time, when the main CPU 31 determines that there is no stop button for which the operation is valid, the main CPU 31 ends the reel stop control process. On the other hand, when the main CPU 31 determines that there is a stop button for which the operation is valid, the process proceeds to the process of step S103. After that, the main CPU 31 repeats the processes from step S103 to step S111 until it is determined that there is no stop button for which the operation is valid.

Next, the display combination search process will be described with reference to FIG. 39. Note that FIG. 39 is a diagram showing a flowchart of the display combination search process performed by the main control circuit 60 of the present embodiment.

First, the main CPU 31 clears the display combination storage area (step S121).

Next, the main CPU 31 designates the start address of the symbol storage area (step S122). Specifically, the main CPU 31 designates an address corresponding to the center line 8c as a start address when the gaming state is a gaming state other than the RB gaming state, and RB when the gaming state is the RB gaming state. The address corresponding to the center special line 8f is specified as the start address.

Next, the main CPU 31 specifies the start address of the symbol combination table (see FIG. 23) (step S123). Specifically, the main CPU 31 designates the address corresponding to BB1 as the start address.

Next, the main CPU 31 compares the combination of symbols specified in the symbol combination table with the combination of symbols stored in the symbol storage area (step S124).

Next, as a result of comparison in the process of step S124, the main CPU 31 determines whether or not the combination of the symbols specified in the symbol combination table and the combination of the symbols stored in the symbol storage area match. Step S125). At this time, when the main CPU 31 determines that the combination of symbols specified in the symbol combination table and the combination of symbols stored in the symbol storage area do not match, the process proceeds to the process of step S129, while the main CPU 31 proceeds to the process of step S129. When it is determined that they match, data indicating the storage area type and the display combination is acquired from the symbol combination table (step S126).

Next, the main CPU 31 stores the acquired display combination storage area corresponding to the acquired storage area type and the logical sum of the data indicating the acquired display combination in the display combination storage area (step S127).

Next, the main CPU 31 acquires the number of payouts from the symbol combination table and adds them to the payout number counter (step S128).

When the main CPU 31 determines in the process of step S125 that the combination of symbols specified in the symbol combination table and the combination of symbols stored in the symbol storage area do not match, or the process of step S128 is terminated. Then, the address corresponding to the next combination of the symbol combination table is specified (step S129).

Next, the main CPU 31 determines whether or not the end code is stored in the address specified in the process of step S129 (step S130). At this time, when the main CPU 31 determines that the end code is not stored, the main CPU 31 proceeds to the process of step S124. On the other hand, when the main CPU 31 determines that the end code is stored, it then determines whether or not all valid lines have been searched, that is, whether or not the processes of steps S124 to S130 have been performed on all valid lines. Determination (step S131).

When the main CPU determines that all valid lines have been searched in the process of step S131, the display combination search process is terminated. On the other hand, when the main CPU determines that all valid lines have not been searched, the main CPU then designates an address corresponding to the next valid line in the symbol storage area (step S132), and proceeds to the process of step S123.

Next, the RT control process will be described with reference to FIG. 40. Note that FIG. 40 is a diagram showing a flowchart of RT control processing performed by the main control circuit 60 of the present embodiment.

First, the main CPU 31 determines whether or not the BB is being carried over (RT4 gaming state) (step S161). At this time, when the main CPU 31 determines that the BB is being carried over, the main CPU 31 ends the RT control process. On the other hand, when the main CPU 31 determines that the BB is not being carried over, the main CPU 31 determines whether or not the BB is being carried (step S162). Specifically, it is determined whether or not any of the BB game status flags is on.

When the main CPU 31 determines in the process of step S162 that it is in the BB, the main CPU 31 ends the RT control process. On the other hand, when it is determined that the main CPU 31 is not in the BB, the RT transition table (see FIG. 20) is referred to, and when it is necessary to update the game state flag based on the display combination, the main CPU 31 updates the game status flag (step S163). ), End the RT control process.

Next, the bonus end check process will be described with reference to FIG. 41. Note that FIG. 41 is a diagram showing a flowchart of the bonus end check process performed by the main control circuit 60 of the present embodiment.

First, the main CPU 31 determines whether or not it is in BB (step S141). At this time, when the main CPU 31 determines that it is not in the BB, it turns off the SB game state flag (step S142) and ends the bonus end check process. On the other hand, when the main CPU 31 determines that the BB is in progress, the main CPU 31 determines whether or not the value of the bonus end number counter is “0” (step S143).

When the main CPU 31 determines that the value of the bonus end number counter is "0", the main CPU 31 performs a bonus end process (step S144). Specifically, the BB game state flag and the RB game state flag that are on are turned off. Next, the main CPU 31 sends a bonus end command (step S145) to end the bonus end check process.

On the other hand, when the main CPU 31 determines that the value of the bonus end number counter is not "0", it subtracts "1" from the value of the playable number counter (step S146), and whether or not the display combination is a small combination. (Step S147). At this time, when the main CPU 31 determines that the display combination is not a small combination, the main CPU 31 shifts to the process of step S149. On the other hand, when the main CPU 31 determines that the display combination is a small combination, the main CPU 31 subtracts "1" from the value of the winning count counter (step S148), and proceeds to the process of step S149.

Next, the main CPU 31 determines whether or not the value of the winning count counter or the gameable counter is “0” (step S149). At this time, when the main CPU 31 determines that neither the value of the winning count counter nor the value of the gameable counter is "0", the main CPU 31 ends the bonus end check process. On the other hand, when the main CPU 31 determines that the value of the winning count counter or the gameable counter is "0", the main CPU 31 then performs RB end time processing (step S150) and ends the bonus end check processing. .. In the RB end processing, processing such as turning off the RB game state flag that is turned on is performed.

Next, the bonus operation check process will be described with reference to FIG. 42. Note that FIG. 42 is a diagram showing a flowchart of the bonus operation check process performed in the main control circuit 60 of the present embodiment.

First, the main CPU 31 determines whether or not the display combination is BB (any of BB1 to BB4) (step S171). At this time, when the main CPU 31 determines that the display combination is not BB, the main CPU 31 shifts to the process of step S174. On the other hand, when the main CPU 31 determines that the display combination is BB, the main CPU 31 performs a bonus operation time process (step S172).

In this bonus operation time processing, the game state flag is turned on and a value is set in the bonus end number counter according to the game state to be activated with reference to the bonus operation time table (FIG. 24). Next, the main CPU 31 turns off the RT4 game state flag, clears the carry-over combination storage area (step S173), transmits a bonus start command (step S176), and ends the bonus operation check process. The bonus start command includes information indicating the type of bonus to be started and the like.

When the main CPU 31 determines in the process of step S171 that the display combination is not BB, the main CPU 31 then determines whether or not the display combination is SB (step S174). At this time, when the main CPU 31 determines that the display combination is not SB, the main CPU 31 shifts to the process of step S177. On the other hand, when the main CPU 31 determines that the display combination is SB, the main CPU 31 performs a bonus operation time process (step S175). In this bonus operation time processing, the SB game state flag is turned on with reference to the bonus operation time table (FIG. 24). Next, the main CPU 31 sends a bonus start command (step S176) to end the bonus operation check process.

When the main CPU 31 determines in the process of step S174 that the display combination is not SB, the main CPU 31 then determines whether or not the display combination is a replay (step S177). At this time, when the main CPU 31 determines that the display combination is not a replay, the main CPU 31 ends the bonus operation check process. On the other hand, when the main CPU 31 determines that the display combination is a replay, the main CPU 31 copies the value of the input number counter to the automatic input number counter (step S178), and ends the bonus operation check process. When a value is set in the automatic insertion number counter, the number of medals corresponding to the value is automatically inserted in the process of step S3 in the next game (the player's medal is not reduced).

Next, the communication data storage process will be described with reference to FIG. 43. Note that FIG. 43 is a diagram showing a flowchart of communication data storage processing performed by the main control circuit 60 of the present embodiment. The P1 to P5 data shown in the figure indicate the parameters of each command.

The main CPU 31 stores the transmission command in the 0th byte of the communication temporary storage area (step S1291). The main CPU 31 stores P1 data in the first byte of the communication temporary storage area allocated to the main RAM 33 (step S1292). The main CPU 31 stores P2 data in the second byte of the communication temporary storage area (step S1293). The main CPU 31 stores P3 data in the third byte of the communication temporary storage area (step S1294). The main CPU 31 stores P4 data in the fourth byte of the communication temporary storage area (step S1295). The main CPU 31 stores P5 data in the fifth byte of the communication temporary storage area (step S1296). The main CPU 31 stores the game status flag in the sixth byte of the communication temporary storage area (step S1297).

Then, the main sum value calculating means 31b of the main CPU 31 calculates the data of the 0th byte to the 6th byte of the communication temporary storage area by exclusive OR to create BCC data which is the main sum value (step S1299). ).

The main CPU 31 stores the BCC data in the seventh byte of the communication temporary storage area (step S1300).

Next, the main CPU 31 obtains the storage destination address of the communication data storage area from the communication data storage setting information (step S1301). Here, the main CPU 31 determines whether or not there is a vacancy in the communication data storage area (step S1302). When the main CPU 31 determines that there is no space in the communication data storage area, the communication data storage process is terminated.

When the main CPU 31 determines that there is a vacancy in the communication data storage area, the data stored in the communication temporary storage area is stored in the communication data storage area (step S1303). Further, the main CPU 31 updates the communication data storage setting information (step S1304), and ends the communication data storage process.

Next, the interrupt process controlled by the main CPU 31 will be described with reference to FIG. 44. Note that FIG. 44 is a diagram showing a flowchart of an interrupt process controlled by the main CPU 31 performed by the main control circuit 60 of the present embodiment. Further, the interrupt process controlled by the main CPU 31 is an interrupt process that occurs every predetermined cycle (1.1173 milliseconds in the present embodiment).

First, the main CPU 31 interrupts the program being executed before calling the interrupt process controlled by the main CPU 31, and saves the address indicating the interrupted position and the values of various registers to a predetermined area of the main RAM 33. (Step S181). This is because when the interrupt process controlled by the main CPU 31 is completed, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the time of interruption. Is.

Next, the main CPU 31 performs an input port check process (step S182). Specifically, the main CPU 31 checks signals from each switch such as the maximum BET switch 13S.

Next, the main CPU 31 performs a reel control process (step S183). Specifically, the main CPU 31 starts the rotation of the reels 3L, 3C, and 3R when there is a request to start the rotation of the reel in the reset interrupt process (see FIG. 34), and rotates at a constant speed. Take control. Further, when the scheduled stop position is determined by the number of sliding frames determined in the reel stop control process (see FIG. 38), the main CPU 31 indicates the scheduled stop position by the value of the symbol counter of the corresponding reel. Control is performed to stop the reel when the value becomes the same as the value. For example, when the value indicating the scheduled stop position is "4", the main CPU 31 controls to stop the corresponding reel when the value of the symbol counter becomes "4".

Next, the main CPU 31 performs a communication data transmission process described later (step S184). Further, the main CPU 31 performs a lamp drive control process (step S185). Next, the main CPU 31 restores the register by referring to the value saved in the main RAM 33 in the process of step S181 (step S186). When this process is completed, the interrupt process controlled by the main CPU is terminated, and the program interrupted due to the occurrence of the interrupt process controlled by the main CPU is continuously executed.

Next, the communication data transmission process will be described with reference to FIG. 45. Note that FIG. 45 is a diagram showing a flowchart of communication data transmission processing performed by the main control circuit 60 of the present embodiment. This communication data transmission process is mainly executed as a command transmission means of the main CPU 31.

First, the main CPU 31 sets the address of the communication data storage area this time based on the communication data storage setting information (step S1341). Then, the main CPU 31 determines whether or not the communication data (transmission data) to be transmitted to the sub-control circuit 70 is stored in the set address of the communication data storage area (step S1342).

When the main CPU 31 determines that the transmission data is not stored at the address set in the communication data storage area, it sets a non-operation command (step S1343) and performs the above-mentioned communication data storage process (step S1344). ..

After the communication data storage process here is completed, or when the main CPU 31 determines that the transmission data is stored at the address set in the communication data storage area, the main CPU 31 transmits the main control circuit 60. It is determined whether or not there is a free port (step S1345). When the main CPU 31 determines that there is no vacancy in the transmission port of the main control circuit 60, the main CPU 31 ends the communication data transmission process.

When the main CPU 31 determines that there is a vacancy in the transmission port of the main control circuit 60, the number of data for one packet (8 in this embodiment) is set (step S1346). Then, the main CPU 31 sets the start number of the output port for packet transmission data setting (step S1347). Further, the main CPU 31 sets the data in the communication data storage area in the output port (step S1348).

The main CPU 31 adds 1 to the address of the communication data storage area and updates it (step S1349). Next, the main CPU 31 adds 1 to the output port number and updates it (step S1350). Further, the main CPU 31 subtracts 1 from the data number counter (step S1351).

Next, the main CPU 31 determines whether or not the data number counter is 0 (step S1352). If the main CPU 31 determines that the data count counter is not 0, it determines that data that has not yet been set in the output port remains in the communication data storage area, and again outputs the data in the communication data storage area to the output port. (Step 1348).

When the main CPU 31 determines that the data number counter is 0, it determines that the data for one packet is stored in the output port, and sets the transmission start request in the communication register port (step S1353). As a result, one packet of data will be transmitted.

Then, the main CPU 31 sets the transmitted data in the communication data storage area (step S1354). Further, the main CPU 31 updates the communication data storage setting information, sets the address of the next communication data storage area (step S1355), and ends the communication data transmission process.

Next, the no-operation command set process (step S1343) in the communication data transmission process of FIG. 45 will be described with reference to FIG. 46. FIG. 46 is a diagram showing a flowchart of non-operation command set processing performed by the main control circuit 60 of the present embodiment.

The non-operation command set processing targets the input from the one connected to the I / O port 38 of the main control circuit 60. First, the main CPU 31 sets the no-operation command in the communication parameter (step S401), and then sets the input port data regarding the port input information input via the I / O port 38 in the communication parameter (step S402). ). The input port data to be set is input to the I / O port 38 from the stop switch 7S, the start switch 6S, the medal sensor 22S, the reset switch 23S, the maximum BET switch 13S, the C / P switch 14S, the setting key switch 20S, and the like. It is data. After step S402, the main CPU 31 ends the no-operation command set process.

[Game machine management system]
Next, an error information history transmission system using the gaming machine 1 of the present embodiment will be described with reference to FIG. 47. The error information history transmission system is a system that stores various errors generated in the game machine 1 as error information, transmits the error information history to a remote server by using a mobile terminal, and analyzes the cause of the error. ..

As shown in FIG. 47, the error information history transmission system includes a game machine 1, a mobile communication terminal with a camera (hereinafter referred to as "mobile terminal") 400 as a mobile terminal possessed by a staff member, and a data management server as a server. It includes 500 and a PC 600 for analysis as an analysis means. In the example of FIG. 47, one mobile terminal 400 is shown for convenience of explanation, but in reality, the data management server 500 can be accessed from a large number of mobile terminals 400.

The data management server 500 manages not only error information but also game record information, for example. The mobile terminal 400 and the data management server 500 can transmit and receive data to and from each other via the network NW, for example, using TCP / IP or the like as a communication protocol. The network NW is constructed by, for example, the Internet, a dedicated communication line (for example, a CATV (Community Antenna Television) line), a mobile communication network (including a base station, etc.), a gateway, and the like. The gaming machine 1 is not connected to the network NW.

Although not shown in particular, the mobile terminal 400, the data management server 500, and the analysis PC 600 each include a control unit, a storage unit, a display unit, a communication unit, and the like. Further, the data management server 500 and the analysis PC 600 are preferably installed in an area 700 separated from the installation location of the gaming machine 1, such as a manufacturer of the gaming machine 1 or a system management company.

When the sub CPU 71 of the game machine 1 provides a service by the error information history transmission system, the sub CPU 71 causes the liquid crystal display area 23 to display the two-dimensional code 300 so that the staff (mobile terminal 400) accesses the data management server 500. Specifically, as shown in FIG. 49, a staff member displays an error information history in the liquid crystal display area 23, and selects a predetermined item such as a communication error alarm COM error alarm (COM ERR ALM) 23b. As a result, the two-dimensional code 300 is displayed.

The control unit of the mobile terminal 400 reads the displayed two-dimensional code 300 with the camera 401 of the mobile terminal 400, analyzes the two-dimensional code 300 with the dedicated software of the mobile terminal 400, for example, the domain in the code, the communication error log, and the like. The information is acquired, the data management server 500 is accessed according to the domain and the like included in the two-dimensional code 300, and the information included in the two-dimensional code 300 is transmitted as transmission data at the time of output.

On the other hand, the control unit of the data management server 500 stores the communication error information included in the received transmission data in the storage unit.

Further, the control unit of the data management server 500 stores the communication error information included in the output transmission data in an error information database DB (database) (not shown), and transmits the communication error information to the analysis PC 600. Further, the control unit of the data management server 500 generates display data (for example, a Web page) so that the mobile terminal 400 can display the error content indicated by the received communication error information or the like, and the mobile terminal 400 that has accessed the data management server 500. Reply (in the figure, one-dot chain line arrow). Then, the control unit of the mobile terminal 400 causes the display unit to display a screen 402 indicating the error content or the like based on the received display data. The person in charge can confirm the error content and the like from the screen 402.

Further, the analysis PC 600 that has received the communication error information analyzes the cause of the communication error based on the communication error information and various information stored in the error information database DB. The cause of the communication error analyzed by the analysis PC 600 is the improvement of the program, structure, etc. of the game machine 1 or the installation of the game machine 1 at the manufacturer or system management company of the game machine 1 in which the analysis PC 600 is installed. It will be used as appropriate, such as improving management in the halls that have been opened.

Next, the gaming machine 1 when the staff member uses the error information history transmission service will be described. The sub CPU 71 of the gaming machine 1 employs two types of operation methods, a normal operation and a simple operation by a staff member, in order to display the error information history shown in FIG. 49 on the liquid crystal display device 5. When performing a normal operation, a staff member rotates the door key 2 clockwise to release the lock mechanism of the front door 1b, turns on the setting key, and turns on the setting key switch 20S to display the liquid crystal display area 23. The menu screen shown in FIG. 48 is displayed.

Then, the staff operates the operation keys to select the "error information history" item 23a, so that the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23. On the other hand, when executing a simple operation, the staff member rotates the door key 2 counterclockwise when an error occurs or when the game is not played, and holds the state for a certain period of time, for example, 5 seconds or more. As a result, the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23.

When the staff member detects an operation of selecting the "error information history" item 23a by using the selection button 24 and the decision button 25, the sub CPU 71 displays the error information history in the liquid crystal display area 23 as shown in FIG. 49. .. Further, when the sub CPU 71 detects an operation of selecting the "COM error alarm" item 23b by the staff using the selection button 24 and the decision button 25, the sub CPU 71 generates transmission information based on the error information history, and FIG. 49 shows. As shown, the two-dimensional code 300 based on the transmission information is displayed on the right side of the "COM error alarm" item 23b.

Further, the sub CPU 71 does not display the COM error alarm when the communication error occurs once, and the COM error alarm occurs only when the communication error occurs again within 30 minutes after the first communication error occurs. Is to be displayed. Therefore, the sub CPU 71 includes a COM error timer for measuring the interval at which a communication error occurs. The COM error timer measures based on the time of the built-in RTC70a or the time of the function provided by the OS.

Further, in the present embodiment, the sub CPU 71 creates the two-dimensional code 300 only when a communication error occurs. Therefore, when a communication error occurs accidentally, for example, during a normal game, the data posted as error information in the two-dimensional code 300 communicates in the middle of normal processing as shown in FIG. 52 (a). An error occurs, and immediately after that, normal processing is executed again. Here, the numerical value in FIG. 52 is the number of characters of the data, the one-character data indicates the command type, and the two-character data indicates the parameter for the immediately preceding command.

Further, if the communication error is caused by a goto action and the setting is changed in the gaming machine 1, the data posted as the error information in the two-dimensional code 300 is the communication error as shown in FIG. 52 (b). The settings have been changed immediately after the occurrence. Further, when a communication error occurs and continuous transmission is performed by lever operation, the data to be loaded as error information in the two-dimensional code 300 is classified by the command type immediately after the communication error occurs, as shown in FIG. 52 (c). A certain lever operation and a winning combination, which is a parameter, are continuous.

In FIG. 53, when the data destruction detecting means 71c detects that the data in the sub RAM 73-1 of the sub control circuit 70 has been destroyed, the sub control circuit 70 covers almost the entire surface of the liquid crystal display area 23 of the gaming machine 1. , An example of notifying that the game cannot be continued because a thumb abnormality has occurred in the RAM data is shown.

For example, when a part or all of the data related to the information such as the command received from the main control circuit 60, the effect data information, the game state information, the internal winning combination information, the display combination information, various counters, and various flags is deleted. The part excluding the symbol display areas 4L, 4C, and 4R of the liquid crystal display area 23 of the game machine 1 is notified that "RAM data abnormality cannot continue the game. Please change the setting." By performing such notification, it can be expected to suppress the act of goto.

Further, in FIG. 54, when a communication error occurs between the main control circuit 60 and the sub control circuit 70, the sub control circuit 70 causes a communication abnormality on almost the entire surface of the liquid crystal display area 23 of the gaming machine 1. Here is an example of notifying that the game cannot be continued.

For example, when the communication error detecting means 71a of the sub control circuit 70 detects a COM error, when the procedure detecting means 71b detects a procedure abnormality error, or when the communication disconnection detecting means 71h detects a communication disconnection detecting means 71h from the main control circuit 60 to the sub control circuit 70. When it is detected that the communication to is cut off, the occurrence of a communication error is notified. As a result, it can be expected to suppress the goto action as in the case where the data of the sub RAM 73-1 of the sub control circuit 70 is destroyed.

[Sub CPU]
Next, the power-on processing (power-off determination processing unit) of the sub CPU 71 will be described with reference to FIG. 55. FIG. 55 is a flowchart of the power-on process of the sub CPU 71.

The power-on process of the sub CPU 71 is an initialization process in the OS, and when the power of the sub CPU 71 is turned on, the sub-CPU initialization process is performed to initialize the CPU and internal devices and the peripheral ICs. It is executed (step S910).

Next, the sub CPU 71 executes the mother task activation request processing described later based on FIG. 57 for various task activation requests (step S911). Then, the sub CPU 71 executes the sub RAM management process (step S912) to confirm that the backup data of the backup RAM 73-2 is normal.

Next, the sub CPU 71 reads the power failure determination flag written in the predetermined areas of the backup data 1 area 73a-2 and the backup data 2 area 73c-2 of the backup RAM 73-2, and the power failure determination flag is set to 1. Whether or not it is determined (step S913).

When the sub CPU 71 determines in step S913 that the power failure determination flag is 1, it determines that an abnormal power failure has occurred before the first operation of the start lever 6 after the power is turned on, and the error information registration means. By 71d, an error code (WDR PRE) indicating a power failure abnormality is registered in the error information history storage area 73d-1 of the sub RAM 73-1 (step S914).

On the other hand, when the sub CPU 71 determines in step S913 that the power cut determination flag is not 1, it determines whether or not the power cut determination flag is 2. (Step S915).

When the sub CPU 71 determines in step S915 that the power failure determination flag is 2, it is determined that an abnormal power failure has occurred after the operation of the start lever 6, and the error information registration means 71d causes the power failure error. The indicated error code (WDR POST) is registered in the error information history storage area 73d-1 of the sub RAM 73-1 (step S916).

The sub CPU 71 registers an error code (WDR PRE) indicating a power failure error (WDR PRE) (step S914), and then determines in step S915 that the power failure determination flag is not 2, or an error code indicating a power failure error. After registering (WDR POST) (step S916), the power cutoff determination flag is set to 1 (step S917), and the power-on process of the sub CPU is terminated.

Further, a power failure detection circuit is provided in the sub control circuit 70 (not shown). When the power failure detection circuit detects a voltage drop, for example, a voltage drop to 4.5 V, a power failure detection signal is output. The sub CPU 71 executes the power interruption interrupt processing (power interruption determination processing unit) of the sub CPU shown in FIG. 56 by interrupt input from the external interrupt port (NMI).

In the power interruption interrupt processing of the sub CPU, the sub CPU 71 sets the power cut determination flag written in the predetermined areas of the backup data 1 area 73a-2 and the backup data 2 area 73c-2 of the backup RAM 73-2 to 0. Set (step S950). Therefore, if the power failure determination flag is 0 when the power is turned on, error registration is not performed as a normal power failure.

Therefore, in comparison with the power interruption interrupt processing of the sub CPU 71 shown in FIG. 56, the power-on processing of the sub CPU 71 shown in FIG. 55 causes the power to be turned off without passing through the power interruption processing. Can be detected as. As a goto act, for example, there is an act of disconnecting the output line of the power failure detection circuit or supplying power to the power failure detection circuit even when the power is turned off so that the detection signal is not output. ..

Further, in the power interruption interrupt processing of the sub CPU shown in FIG. 56, the power interruption determination flag is set to 0 (step S950), and then the backup creation processing shown in FIG. 76 is executed (step S951).

Note that unlike the main control, the sub CPU 71 does not calculate the sum value in the power interruption interrupt processing of the sub CPU. The calculation of the sum value by the sub CPU 71 is performed every time a valid command is received, when the effect mode is changed, and the like.

The mother task request process shown in FIG. 57 is a process of requesting the OS to start a task necessary for the function of the gaming machine 1. First, the sub CPU 71 makes a request to start the effect registration process (step S1001). Next, as the subtask activation request, the accessory control task activation request (step S1002), the lamp control task activation request (step S1003), the sound control task activation request (step S1004), the main board communication task activation request (step S1005), An animation task activation request (step S1006), an RTC control task activation request (step S1007), and then an error monitoring task activation request are made.

The error monitoring task of the sub CPU 71 will be described with reference to FIG. 58. FIG. 58 is a flowchart of the error monitoring task of the sub CPU 71. The error monitoring task is executed by the error monitoring means (not shown) of the sub CPU 71.

The sub CPU 71 sets a cycle of 2 ms as the processing cycle of the error monitoring task (step S1101), and first determines whether or not COM ERR ALM is occurring (step S1102).

When the sub CPU 71 determines in step S1102 that COM ERR ALM is not occurring, the sub CPU 71 subsequently determines whether or not a sequence error has occurred (step S1103). The sequence error is an error due to a procedure abnormality related to communication other than the COM error.

When the sub CPU 71 determines that a sequence error has occurred in step S1103, or determines that COM ERR ALM is occurring in step S1102, the sub CPU 71 determines whether or not the door is in the open state. Step S1104). The door here is the front door 1b of the gaming machine 1, and it is determined that the door is in the open state by the input state of the door open / close switch 29S input to the port of the sub-control circuit 70.

When the sub CPU 71 determines in step S1104 that the door is in the open state, the sub CPU 71 determines whether or not the reset switch 23S is on (step S1105).

The signal of the reset switch 23S is the port input data of the main control circuit 60, and is input to the sub control circuit 70 via the I / O 38 as a parameter of the non-operation command. Whether or not the reception command of the sub control circuit 70 is a non-operation command is determined in the sub CPU main board communication task of FIG. 69, which will be described later (step S818). If it is determined that the command is a non-operation command in that step, the parameter of that command is registered in the work area 73c-1 (step S819).

Next, when the sub CPU 71 determines in step S1105 that the reset switch 23S is on, the sub CPU 71 performs release registration of the error being generated (step S1106). The error cleared here is a communication error between the main control circuit 60 and the sub control circuit 70. This release is registered in the error information history storage area 73d-1 of the sub RAM 73-1. As described above, the error cancellation during the occurrence is the input of the door open / close switch 29S input to the port of the sub control circuit 70 and the input of the non-operation command input via the I / O 38 of the main control circuit 60. Since both are required, it is not done only by the command from the main control circuit 60.

By the process from step S1102 to step S1106 described above, when the door is opened and the reset switch is further turned on, the communication abnormality notification can be canceled.

Next, the sub CPU 71 determines whether or not there is data in the received data registration queue (step S1107). Even if there is data in the received data registration queue, the data is not retrieved from the registration queue.

When the sub CPU 71 determines in step S1107 that there is no data in the received data registration queue, the sub CPU 71 updates the communication interruption counter by 1 (step S1108), and subsequently, when the communication interruption counter is 15 (30 ms) or more, the communication interruption notification is given. Is not generated or not (step S1109). Communication interruption is detected by the communication interruption detecting means 71h.

When the sub CPU 71 determines in step S1109 that the communication interruption notification does not occur when the communication interruption counter is 15 (30 ms) or more, the sub CPU 71 registers the occurrence of the communication interruption notification as error information (step S1110). Specifically, the error information registration means 71d registers an error code (COM DCN ALM) in the error information history storage area 73d-1 of the sub RAM 73-1.

When the sub CPU 71 registers error information in step S1110, or when it is determined in step S1109 that "the communication interruption counter is 15 (30 ms) or more and the communication cutoff notification has not occurred", the sub CPU 71 waits for a cycle of 2 ms. (Step S1114), the process is returned to step S1102.

On the other hand, when the sub CPU 71 determines in step S1107 that there is data in the received data registration queue, the sub CPU 71 subsequently determines whether or not a communication cutoff notification is occurring (step S1111).

When the sub CPU 71 determines in step S1111 that the communication cutoff notification is being generated, the sub CPU 71 registers the communication cutoff notification release in the error information (step S1112). Specifically, the error information registration means 71d registers the communication cutoff notification cancellation as error information in the error information history storage area 73d-1 of the sub RAM 73-1.

After the processing of step S1112 or when it is determined in step S1111 that the communication cutoff notification is not occurring, the sub CPU 71 clears the communication interruption counter (step S1113) and waits for a cycle of 2 ms (step S1114). ) Later, the process is returned to step S1102.

Next, the operation of the above-mentioned error information history transmission system will be described with reference to the flowcharts shown in FIGS. 59 to 74. First, the main board communication reception interrupt processing in the sub-control circuit 70 will be described with reference to FIG. 59. Note that FIG. 59 is a diagram showing a flowchart of the main board communication reception interrupt processing in the sub-control circuit 70 of the present embodiment. The program for the main board communication reception interrupt process in the sub control circuit 70 is executed by the sub CPU 71 as an interrupt process when transmission data is transmitted from the main control circuit 60 to the sub control circuit 70.

The sub CPU 71 acquires received data from the received data register (step S800). Further, the sub CPU 71 acquires the reception status data from the reception status register (step S801). Further, the sub CPU 71 registers the received data and the reception status data related to the received data in each queue buffer (step S802), and ends the main board communication reception interrupt process.

The sub CPU 71 processes 1 byte of received data by executing the main board communication reception interrupt processing of steps S800 to S802 described above once. In this embodiment, one command is composed of 8 bytes of data. Therefore, the sub CPU 71 completes the processing of one command by executing the serial data communication by continuously processing steps S800 to S802 eight times.

[Production registration process]
Next, the operation of the sub-control circuit 70 related to the game will be described with reference to the flowchart shown in FIG.

The effect registration process performed by the sub CPU will be described with reference to FIG. 60. Note that FIG. 60 is a diagram showing a flowchart of the effect registration process of the present embodiment.

First, the sub CPU 71 sets a cycle of 4 ms in the effect registration process (step S310). Next, the sub CPU 71 retrieves a message from the message queue (step S311). Next, the sub CPU 71 determines whether or not there is a message in the message queue (step S312). At this time, when the sub CPU 71 determines that there is no message in the message queue, the sub CPU 71 proceeds to the process of step S317.

On the other hand, when the sub CPU 71 determines in step S312 that there is a message in the message queue, the sub CPU 71 determines whether or not a communication cutoff notification is occurring (step S313). The communication interruption notification is performed when the communication interruption detection means 71h of the sub CPU 71 detects that the communication from the main control circuit 60 to the sub control circuit 70 is interrupted, and in the notification state, as shown in FIG. 54. , A communication abnormality is displayed on almost the entire surface of the liquid crystal display area 23, and no effect is performed.

When the sub CPU 71 determines in step S313 that the communication cutoff notification is not being generated, the sub CPU 71 copies the game information from the message (step S314), and then performs the effect content determination process (step S315). In the effect content determination process, as described in detail with reference to FIG. 61, the effect content is determined according to various commands transmitted from the main CPU 31, and is specified by the received command, for example, according to the game state or operation state. The staging data is registered in the sub RAM73-1.

Subsequently, the sub CPU 71 performs a backup creation process for creating backup data from the sub RAM 73-1 to the SRAM 73-2 (step S316).

Next, when the sub CPU 71 determines that there is no message in the message queue in step S312, determines that the communication cutoff notification is occurring in step S313, or after performing the backup creation process in step S316, the sub CPU 71 determines. , Register the animation data (step S317). Specifically, the sub CPU 71 registers the animation data based on the effect data registered in the effect content determination process. As a result, the image is displayed on the liquid crystal display device 5. That is, the sub CPU 71 transmits an image display command to the GPU 74 based on the effect data determined in the effect content determination process.

Based on the received image display command, the GPU 74 selects appropriate image data from the image data developed in the VRAM 75, determines the display position and size of the image data, and prepares the image data in the VRAM 75. Store in one of the frame buffers.

The GPU 74 performs a bank switching process in which the display image data area and the written image data area of the frame buffer area are exchanged at predetermined intervals (1/30 seconds). In the bank switching process, the GPU 74 outputs the image data written in the written image data area to the liquid crystal display device 5, replaces the display image data area with the written image data area, and displays the image data to be displayed next. Write.

Next, the sub CPU 71 registers the sound data (step S318). Specifically, the sub CPU 71 registers the sound data based on the effect data registered in the effect content determination process. As a result, sound is output from the speakers 21L and 21R.

Next, the sub CPU 71 registers the LED data (step S319). Specifically, the sub CPU 71 registers the LED data based on the effect data registered in the effect content determination process. As a result, the various operation panels 101 to 103 and the display panel unit 110 are turned on and off. When this process is completed, the sub CPU 71 waits for a cycle of 4 ms (step S320) and returns to the process of step S311.

Next, with reference to FIG. 61, the effect content determination process in the flowchart of the effect registration process performed by the sub CPU shown in FIG. 60 will be described. Note that FIG. 61 is a diagram showing a flowchart of the effect content determination process.

First, the sub CPU 71 determines whether or not a start command has been received (step S350). When the sub CPU 71 determines that the start command has been received, the sub CPU 71 acquires the internal winning combination for determination from the storage area in which the received data of the sub CPU 71 is stored and the symbol combination table for fraud determination, and the work of the sub RAM 73-1. It is stored in the area 73c-1 (step S351).

Next, the sub CPU 71 performs a process at the time of receiving a start command (step S352), and performs various processes such as determination and execution of effect data. Subsequently, the sub CPU 71 registers the effect data for the start (step S353), and then, in order to determine the power failure abnormality after the start of the game, the backup data 1 area 73a-2 of the backup RAM 73-2 and the backup. 2 is set as the power failure determination flag in the predetermined area of the data 2 area 73c-2 (step S354), and the effect content determination process is terminated.

When the sub CPU 71 determines that the start command has not been received in the process of step S350, the sub CPU 71 then determines whether or not the reel stop command has been received (step S355).

In the process of step S355, when the sub CPU 71 determines that the reel stop command has been received, the sub CPU 71 performs the reel stop command reception process (step S356), and outputs the effect data at the time of stop according to the type of the operation stop button and the like. Registration (step S357) is subsequently executed (step S358), and then the reel stop command reception fraud determination process shown in FIG. 63 is executed (step S358) to end the effect content determination process.

When the sub CPU 71 determines that the reel stop command has not been received in the process of step S355, the sub CPU 71 then determines whether or not the display command has been received (step S359). When the sub CPU 71 determines that the display command has been received, the sub CPU 71 performs a display command reception process (step S360), and subsequently, the sub CPU 71 executes a display command reception invalidity determination process (step S361) to produce an effect. The content determination process ends.

When the sub CPU 71 determines that the display command has not been received in the process of step S359, the sub CPU 71 then determines whether or not the BET command has been received (step S362). At this time, when the sub CPU 71 determines that the BET command has been received, the sub CPU 71 registers the effect data at the time of BET according to the number of input sheets and the like (step S363), and ends the effect content determination process.

When the sub CPU 71 determines that the BET command has not been received in the process of step S362, the sub CPU 71 determines whether or not the payout command has been received (step S364). At this time, when the sub CPU 71 determines that the payout command has been received, the sub CPU 71 executes the payout command reception time fraud determination process (step S365), and ends the effect content determination process.

When the sub CPU 71 determines that the payout command has not been received in the process of step S364, the sub CPU 71 then determines whether or not the bonus start command has been received (step S366). When the sub CPU 71 determines that the bonus start command has been received, the sub CPU 71 registers the effect data for starting the bonus (step S367), and ends the effect content determination process.

When the sub CPU 71 determines that the bonus start command has not been received in the process of step S366, the sub CPU 71 then determines whether or not the bonus end command has been received (step S368). At this time, when the sub CPU 71 determines that the bonus end command has not been received, the sub CPU 71 ends the effect content determination process. On the other hand, when the sub CPU 71 determines that the bonus end command has been received, the sub CPU 71 performs a bonus end command reception process (step S369), registers the bonus end effect data (step S370), and performs the effect content determination process. finish.

Next, the error determination process at the time of receiving the reel stop command of the sub CPU 71 will be described with reference to FIG. 63. FIG. 63 is a flowchart of an invalidity determination process when a reel stop command is received by the sub CPU 71.

First, the sub CPU 71 acquires the stop reel number from the stop reel type included in the received data of the reel stop command from the main CPU 31, and also acquires the reel stop position from the stop start position and the number of slip frames. Further, the symbol data is acquired from the symbol arrangement table for sub CPU fraud determination shown in FIG. 67, which is stored in the various program table areas 72e of the sub ROM 72 (step S411).

Next, the sub CPU 71 determines whether or not it is at the time of the third stop, that is, at the time of stopping all reels (step S412), and if it is not at the time of the third stop, the process is returned to the effect content determination process. On the other hand, when the sub CPU 71 is determined to be in the third stop state in step S412, the sub CPU 71 is stored in the various program table areas 72e of the sub ROM 72, and the determination prize is won from the symbol combination table for sub CPU fraud determination shown in FIG. Acquire a combination (winning number) (step S413).

Subsequently, the sub CPU 71 determines whether or not there is a winning combination for determination (step S414), and if there is no winning combination for determination, that is, in the case of loss or omission, no fraud occurs, so the reel is stopped. Terminates the invalidation judgment processing when a command is received.

When the sub CPU 71 determines in step S414 that there is a determination winning combination, it subsequently determines whether or not the determination internal winning combination and the determination winning combination match (step S415), and determines whether or not the determination internal winning combination matches. When it is determined that the winning combination does not match, the fraud occurrence processing shown in FIG. 66, which will be described later, is executed (step S416).

When the sub CPU 71 determines in step S415 that the determination internal winning combination and the determination winning combination match, since no error has occurred, the sub CPU 71 ends the error determination process when receiving the reel stop command.

Next, the fraud determination process at the time of receiving the display command of the sub CPU 71 will be described with reference to FIG. 64. FIG. 64 is a flowchart of the fraud determination process at the time of receiving the display command by the sub CPU 71.

First, the sub CPU 71 combines the display combination information (display combination storage area of the main RAM 33) included in the received data from the main CPU 31 and the symbol combination of the symbol combination table for sub CPU fraud determination stored in the sub ROM 72. The determination display combination (winning number) is acquired from (step S421).

Next, the sub CPU 71 collates the symbol data (symbol data of only the center) saved up to the third stop (when all stops) of the reel with the symbol combination in the symbol combination table for sub CPU fraud determination. Acquire the winning combination (winning number) for determination (step S422).

Next, the sub CPU 71 determines whether or not there is a determination display combination (step S423), and when it is determined that there is no determination display combination, the sub CPU 71 is missing or missed, and no fraud has occurred. Terminates invalidation judgment processing when a command is received.

When the sub CPU 71 determines in step S423 that there is a determination display combination, it determines whether or not the determination internal winning combination acquired and saved in step S352 and the determination display combination acquired in step S421 match. (Step S424).

When the sub CPU 71 determines in step S424 that the internal winning combination for determination and the display combination for determination match, subsequently, the winning combination for determination acquired in step S422 and the display combination for determination acquired in step S421 match. It is determined whether or not to do so (step S425).

When the sub CPU 71 determines in step S425 that the determination winning combination and the determination display combination match, no error has occurred, so that the error determination process at the time of receiving the display command ends.

On the other hand, when the sub CPU 71 determines in step S424 that the internal winning combination for determination and the display combination for determination do not match, or when it is determined in step S425 that the winning combination for determination and the display combination for determination do not match. , The fraud occurrence processing shown in FIG. 66, which will be described later, is executed (step S426), and the fraud determination processing at the time of receiving the display command is terminated.

Next, the fraud determination process at the time of receiving the payout command of the sub CPU 71 will be described with reference to FIG. 65. FIG. 65 is a flowchart of the fraud determination process at the time of receiving the payout command by the sub CPU 71.

First, the sub CPU 71 acquires the number of payouts from the data received from the main CPU 31 (step S431), and determines whether or not there is a payout number (step S432).

Next, in step S432, when the number of payouts is 0, the sub CPU 71 determines that no fraud has been performed, and ends the fraud determination process when the payout command is received.

When the sub CPU 71 determines in step S432 that there is a number of payouts, the sub CPU 71 is used for determination from the determination display combination (winning number) acquired in step S421 and the fraud determination symbol combination table stored in the sub ROM 72. Acquire the number of payouts (step S433). In the sub CPU fraud determination symbol combination table shown in FIG. 68, "2 sheets inserted" and "3 sheets inserted" in the payout number column are the number of sheets inserted at the time of BET, and 2 sheets are inserted during BB, and others. In the case of, 3 cards will be inserted.

Subsequently, the sub CPU 71 determines whether or not the number of sheets to be paid out for determination matches the number of sheets of data received from the main CPU 31 (step S434).

When the sub CPU 71 determines in step S434 that the number of sheets to be paid out for determination matches the number of sheets to be paid out of the received data, it is determined that no fraud has occurred, and the fraud determination process at the time of receiving the payout command is terminated. On the other hand, when the sub CPU 71 determines in step S434 that the number of sheets to be paid out for determination does not match the number of sheets to be paid out for the received data, the sub CPU 71 executes the fraud occurrence processing shown in FIG. 66, which will be described later (step S435), and receives the payout command. When the error judgment process is terminated.

Next, processing when an error occurs in the sub CPU 71 will be described with reference to FIG. 66. FIG. 66 is a flowchart of fraud occurrence processing by the sub CPU 71.

The sub CPU 71 first clears the counters for the number of navigation games and the number of navigation sets (step S441). This clears the ART winning information. Next, the error information registration means 71d of the sub CPU 71 regards the occurrence of a sequence error as error information of "procedure error (other)", and sets an error code (BLS) in the error information history storage area 73d-1 of the work area of the sub RAM 73-1. 123PE) is registered (step S442). As a result, as a serious error, as shown in FIG. 54, a notification that the game cannot be continued due to a communication abnormality has occurred on almost the entire surface of the liquid crystal display area 23, and the reset switch 23S is pressed with the front door 1b open. It is targeted for error cancellation that it cannot be reset unless it is operated.

FIG. 67 shows a symbol arrangement table for sub CPU fraud determination, and FIG. 68 shows a symbol combination table for sub CPU fraud determination. Each of these tables is a table created for the sub CPU 71 based on the symbol arrangement table shown in FIG. 3 and the symbol combination table shown in FIG. 23 stored in the main ROM 32 of the main control circuit 60, and is a sub table. It is stored in various program table areas 72e of the ROM 72.

[Main board communication processing]
Next, the main board communication process of the sub CPU 71 will be described with reference to FIG. 69. Note that FIG. 69 is a diagram showing a flowchart of the main board communication process of the sub CPU 71 according to the present embodiment.

The sub CPU 71 sets the cycle so as to execute the program of the main board communication processing of the sub CPU 71 in a cycle of 2 ms in response to the scheduling function of the OS (step S808). As a result, this task is repeated in a cycle of 2 ms including the processing time. Therefore, the sub CPU 71 waits for a cycle of 2 ms (step S809), and waits for the remaining time of 2 ms when the flowchart is repeated.

The cycle of this task processing is not limited to 2 ms, and may be executed between 2 ms and 4 ms. Further, the program for the main board communication processing of the sub CPU 71 is not limited to the one executed at predetermined time intervals, and the predetermined conditions are satisfied regardless of the time interval, for example, without setting the cycle and waiting for the cycle. It may be executed.

Next, the sub CPU 71 acquires the received data from the queue in which the received data is registered in step S802 (step S810). The sub CPU 71 determines whether or not there is received data in the queue (step S811). When the sub CPU 71 determines that there is no received data in the queue, the sub CPU 71 acquires the received data from the queue again (step S810).

When the sub CPU 71 determines that the received data is in the queue, it determines whether or not a physical layer error has occurred in the received data (step S812). When the sub CPU 71 determines that no physical layer error has occurred in the received data, the sub CPU 71 checks and acquires the numerical range of the received command (step S813). In the present embodiment, the numerical range of the received command is 01H to 10H as shown in FIG. 51. Then, the sub CPU 71 determines whether or not the numerical value of the received command is within the appropriate range (step S814).

When the sub CPU 71 determines that the numerical value of the command is within the appropriate range, BCC check processing is performed on the received data (step S815). Here, since one command is composed of 8 bytes of data, the sub CPU 71 XORs the data of the 1st byte to the 7th byte of each command in order, and sets the correct result in advance. The check process is performed by comparing with the data of the 8th byte.

Then, the sub CPU 71 determines whether or not the result of the BCC check process is normal (step S816). When the sub CPU 71 determines that the result of the BCC check process is normal, the command type is extracted (step S817).

Next, the sub CPU 71 determines whether or not the extracted command is a non-operation command (step S818). When the sub CPU 71 determines that the extracted command is a non-operation command, the sub CPU 71 saves the main board input port data in the work area 73c-1.

The main board input port data is data included in the parameter data of the non-operation command, and is data sent to the sub control circuit 70 via the I / O port 38 of the main control circuit 60.

When the sub CPU 71 saves the main board input port data (step S819), the sub CPU 71 returns to the 2 ms cycle wait (step S809) and acquires the data from the received data registration queue again (step S810).

On the other hand, if the sub CPU 71 determines in step S818 that the extracted command is not a non-operation command, the sub CPU 71 executes a received data log saving process described later (step S820). Further, the sub CPU 71 executes a main board reception command check process described later (step S821).

Then, the sub CPU 71 determines whether or not the command received this time is different from the command received last time (previous time) (step S822). If the sub CPU 71 determines that the command received this time is not different from the command received immediately before, that is, it is the same, the sub CPU 71 waits for a cycle of 2 ms (step S809) and acquires received data from the queue again (step). S810).

If the sub CPU 71 determines in step S822 that the command received this time is different from the command received immediately before, the sub CPU 71 registers the command received this time in the message queue (step S823). Then, the sub CPU 71 performs a sum check on the sub control game data sum value area 73b-1 (step S824).

Further, the sub CPU 71 determines whether or not the game data is normal as a result of the thumb check (step S825). When the sub CPU 71 determines that the game data is normal, the sub CPU 71 waits for a cycle of 2 ms (step S809) and acquires the received data from the queue again (step S810).

When the sub CPU 71 determines in step S825 that the game data is abnormal, the error information registration means 71d registers the occurrence of a data corruption error in the error information history storage area 73d-1 (step S826). Then, the sub CPU 71 waits for a cycle of 2 ms (step S809) and acquires received data from the queue again (step S810).

Further, when the sub CPU 71 determines that a physical layer error has occurred in the received data in step S812, or when it determines that the command is not within the appropriate range in step S814, or when the sub CPU 71 determines that the command is not within the appropriate range, the result of the BCC check process is normal in step S816. If it is determined that this is not the case, it is determined that a communication error has occurred, and the COM error check process described later is executed (step S827). Then, the sub CPU 71 waits for a cycle of 2 ms (step S809) and acquires received data from the queue again (step S810).

Next, the main board communication reception data log storage process will be described with reference to FIG. 70. Note that FIG. 70 is a diagram showing a flowchart of the main board communication reception data log storage process performed by the sub-control circuit 70 of the present embodiment. This main board communication received data log saving process is mainly executed by the received data log saving means 71e of the sub CPU 71.

When the main board communication reception data log storage process is executed, the sub CPU 71 executes the main board communication reception data log temporary area storage process described later (step S830). The main board communication received data log temporary area storage process uses the communication log collection ring buffer area 73e-1 shown in FIG. 13 and is a process for storing all communication logs regardless of the presence or absence of an error. ing.

Subsequently, the sub CPU 71 executes a main board communication error history data storage process described later (step S831). The main board communication error history data storage process uses the communication error storage buffer area shown in FIG. 14, and is a process for storing a related communication log when a communication error occurs. After that, the sub CPU 71 ends the main board communication reception data log storage process.

Next, the main board communication reception data log temporary area storage process in step S830 will be described with reference to FIG. 71. Note that FIG. 71 is a diagram showing a flowchart of the main board communication reception data log temporary area storage process performed by the sub-control circuit 70 of the present embodiment.

When the main board communication reception data log temporary area storage process is executed, the sub CPU 71 acquires the communication log data buffer index of the communication log collection ring buffer area 73e-1 (step S840). The number of buffers here is appropriately set.

Then, the sub CPU 71 calculates the communication log data buffer storage position of the communication log collection ring buffer area 73e-1 (step S841). Here, the sub CPU 71 calculates the storage position in the communication log collection ring buffer area 73e-1 from the value of the buffer index.

Further, the sub CPU 71 stores the received data in the communication log collection ring buffer area 73e-1 (step S842). In the present embodiment, as shown in FIG. 13, a set of consecutive numerical values of a command and a parameter corresponding to each command is stored at a maximum of 256 sets. Then, the sub CPU 71 updates the communication log data buffer index (step S843). Here, the sub CPU 71 adds one buffer index in which received data is stored.

Then, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S844). When the sub CPU 71 determines that the value of the buffer index is the upper limit value, the sub CPU 71 returns the communication log data buffer index to the beginning (step S845), and causes this buffer to function as a ring buffer. After that, the sub CPU 71 ends the main board communication reception data log temporary area storage process. If the sub CPU 71 determines that the buffer index value is not the upper limit value, the sub CPU 71 ends the main board communication reception data log temporary area storage process as it is.

Next, the main board communication error history data storage process in step S831 will be described with reference to FIG. 72. Note that FIG. 72 is a diagram showing a flowchart of the main board communication error history data storage process performed by the sub-control circuit 70 of the present embodiment.

When the main board communication error history data storage process is executed, the sub CPU 71 acquires the storage buffer selection index of the communication error storage buffer area 73f-1 (step S850). Then, the sub CPU 71 selects the communication error storage buffer based on the storage buffer selection index (step S851).

Here, the sub CPU 71 determines whether or not a communication error (COM error) has occurred (step S852). When the sub CPU 71 determines that a COM error has occurred, the received data log storage means 71e saves the communication log related to the communication error in the communication error storage buffer area 73f-1 selected in step S851 (step). S853). Then, the sub CPU 71 updates the selected buffer index (step S854). After that, the sub CPU 71 ends the main board communication error history data storage process.

Further, when the sub CPU 71 determines that the COM error has not occurred in step S852, the selected buffer index is acquired (step S855). Then, the sub CPU 71 determines whether or not the received data is being collected (step S856). If the sub CPU 71 determines that the received data is not being collected, the sub CPU 71 ends the main board communication error history data storage process.

When the sub CPU 71 determines that the received data is being collected in step S856, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S857). In the present embodiment, the value of the buffer index is 0 to 255, and the upper limit is 255. When the sub CPU 71 determines that the value of the buffer index is not the upper limit value, the sub CPU 71 saves the received data in the communication error storage buffer selected in step S851 (step S858). Then, the sub CPU 71 updates the selected buffer index (step S859). After that, the sub CPU 71 ends the main board communication error history data storage process.

When the sub CPU 71 determines in step S857 that the value of the buffer index is the upper limit value, the sub CPU 71 acquires the storage buffer selection index (step S860). Then, the sub CPU 71 determines whether or not the value of the storage buffer selection index is the upper limit value (step S861). In this embodiment, the upper limit of the storage buffer selection index is 1024.

When the sub CPU 71 determines in step S861 that the value of the storage buffer selection index is not the upper limit value, the sub CPU 71 updates the storage buffer selection index (step S862). Here, the sub CPU 71 adds one storage buffer selection index. After that, the sub CPU 71 ends the main board communication error history data storage process. When the sub CPU 71 determines that the value of the buffer selection index is the upper limit value, the sub CPU 71 ends the main board communication error history data storage process.

Next, the main board reception command check process in step S821 will be described with reference to FIG. 73. Note that FIG. 73 is a diagram showing a flowchart of the main board reception command check process performed by the sub-control circuit 70 of the present embodiment.

When the main board reception command check process is executed, the sub CPU 71 acquires the received data (step S870). Then, the sub CPU 71 sets the reception command check table (step S871). Further, the sub CPU 71 acquires the received data of the previous time (immediately before) (step S872).

Then, the sub CPU 71 sets the command check counter (step S873). Further, the sub CPU 71 acquires confirmation data from the reception protocol confirmation data table (step S874). That is, here, the table of the received command and the previous received command shown in FIG. 51 is acquired.

Next, the sub CPU 71 checks the table of the received command and the previous received command acquired in step S874, and determines whether or not the received commands are in the normal order (step S875). For example, when the reception command shown in 03H of Data is "BET", if the previous reception command is demo display, BET, payout end, bonus start or error, it is determined that the procedure is in the normal order.

If the sub CPU 71 determines in step S875 that the received commands are in the normal order, the sub CPU 71 ends the received command check process.

When the sub CPU 71 determines in step S875 that the received commands are not in the normal order, for example, in the table shown in FIG. 51, when the received command shown in 07H of Data is "display", the previous received command is In the case of the second stop instead of the full-time body stop state, it is determined that the procedure is not performed in a normal game, and the received command check table is updated (step S876). Then, the sub CPU 71 subtracts the command check counter (step S877).

Following step S877, the sub CPU 71 determines whether or not the command check has been completed (step S878). Here, the sub CPU 71 determines that the command check is completed because, for example, the command check counter becomes equal to or less than a threshold value such as 0.

If the sub CPU 71 determines in step S878 that the command check has not been completed, the sub CPU 71 again acquires confirmation data from the reception protocol confirmation data table (step S874).

When the sub CPU 71 determines in step S878 that the command check has been completed, the error information registration means 71d registers the occurrence of an abnormal procedure error (sequence error) in the error information history storage area 73d (step S879). After that, the sub CPU 71 ends the received command check process.

Next, the COM error check process in step S827 will be described with reference to FIG. 74. Note that FIG. 74 is a diagram showing a flowchart of COM error check processing performed by the sub-control circuit 70 of the present embodiment.

When the COM error check process is executed, the sub CPU 71 executes the received data log storage process (step S880). The procedure of this received data log saving process is as shown in the flowchart of the main board communication received data log saving process shown in FIG. 70. In this case, in step S852 of the main board communication error history data storage process shown in FIG. 72, it is determined that a COM error has occurred, and the received data log storage means 71e causes a communication error in the communication error storage buffer area 73f-1. Save the related communication log (step S853).

Then, the sub CPU 71 determines whether or not the COM error timer is counting (step S881). When the sub CPU 71 determines that the COM error timer is counting, it determines whether or not the COM error timer is within 30 minutes (step S882).

When the sub CPU 71 determines in step S882 that the COM error timer is within 30 minutes, the error information registration means 71d registers the occurrence of a communication error (COM error) in the error information history storage area 73d-1 (step). S883). Then, the sub CPU 71 sets the count stop of the COM error timer (step S884), and ends the COM error check process.

Further, when the sub CPU 71 determines in step S881 that the COM error timer is not counting, or when it is determined in step S882 that the COM error timer is not within 30 minutes, the sub CPU 71 sets the count start of the COM error timer ( Step S885), the COM error check process is terminated.

As described above, the game machine management system of the present embodiment is for analysis that acquires error information from the two-dimensional code 300 received by the data management server 500 and analyzes the cause of the error based on the error information. It is equipped with a PC600.

Therefore, not only the content of the communication error can be specified in the gaming machine 1 as in the conventional case, but also the cause of the error can be analyzed and specified from the error information by using the separately installed analysis PC 600. The cause of the obtained error can be used for subsequent improvement of the gaming machine 1.

Further, in the gaming machine 1 of the present embodiment, the communication error information regarding the communication error is converted into the two-dimensional code 300 only when the occurrence of the communication error is detected by the sub CPU 71, so that the two-dimensional code is used more than necessary. Control can be simplified compared to the case of creating.

Further, in the gaming machine 1 of the present embodiment, the error information history can be displayed on the liquid crystal display device 5 by operating the door key 2, so that the staff member can display the error information history without operating the setting key of the gaming machine 1. You will be able to confirm. Therefore, since the staff member can display the error information history of the gaming machine 1 even during business hours, it becomes possible to more effectively promote the identification of the cause of the error.

Moreover, in the gaming machine 1 of the present embodiment, the staff member rotates the door key 2 in the counterclockwise direction and holds the state for a certain period of time to display the error information history. Therefore, the staff holding the door key 2 can easily display the error information history, and usually, the staff holding the door key 2 is larger than the staff holding the setting key, which improves convenience. be able to.

Further, in the gaming machine 1 of the present embodiment, when the occurrence of a communication error is detected, the sub CPU 71 uses the occurrence time of the communication error, the occurrence time, and the release time as error information in the sub RAM 73. It is designed to be sequentially stored in -1.

Further, the sub CPU 71 creates an error information history from the stored error information, and when an information disclosure request is made by operating the door key 2, the error information history is displayed on the liquid crystal display device 5.

Therefore, it is possible to confirm the illegal cancellation of the communication error notification in the gaming machine 1, and to confirm the occurrence time and the cancellation time of the communication error notification later.

Further, in the gaming machine 1 of the present embodiment, when the procedure detecting means 71b detects that the game has progressed in a procedure that cannot occur in a normal game, that is, an abnormal procedure, the sub CPU 71 will do so. The occurrence of an abnormal procedure and the procedure missed in the normal procedure are sequentially stored in the sub RAM 73-1 as error information.

Further, the sub CPU 71 creates an error information history from the stored error information, and when an information disclosure request is made by operating the door key 2, the error information history is displayed on the liquid crystal display device 5.

For example, FIG. 49 shows an example of the error information history in the liquid crystal display area 23. For example, No. In the error content "BLS123PE" shown in 6, usually, after the procedure of "B" indicating the insertion of a medal or the like, the procedures of "L" and "S" indicating the start of rotation of the reel by operating the lever, the reel 1 The game ends, followed by the procedure of "1" indicating the stop of the reel 2, the procedure of "2" indicating the stop of the reel 2, the procedure of "3" indicating the stop of the reel 3, and the procedure of "P" for payment.

However, there, the number "1" is circled to indicate that the procedure for stopping reel 1 was missed. For this reason, compared to the case of simply returning to the demo screen when an abnormal procedure occurs as in the past, the procedure that could not occur in normal games occurred, the procedure that was missed, the number of occurrences, the presence or absence of continuous occurrence, etc. Since it will be possible to confirm, the occurrence of goto can be used as one of the judgment factors. In addition to enclosing the missing procedure, it can be clearly expressed by distinguishing it by the color of the character itself, making the typeface different, or making the line of the character thicker.

Further, in the gaming machine 1 of the present embodiment, when the data destruction of the sub RAM 73-1 is detected by the data destruction detecting means 71c, the sub CPU 71 uses the fact that the data destruction has occurred as error information and the sub RAM 73-1. Is sequentially stored in (step S826). Further, when an information disclosure request is made by operating the door key 2, the sub CPU 71 reads the error information history from the error information history storage area 73d-1 and displays it on the liquid crystal display device 5.

Therefore, according to the gaming machine 1, it becomes possible to detect the data destruction of the sub RAM 73-1 during the game, and it is possible to suppress the occurrence of goto by immediately notifying the error of the data destruction.

As an error notification, for example, when the data of the sub RAM 73-1 of the sub control circuit 70 is destroyed, as a fatal error, as shown in FIG. 53, almost the entire surface of the liquid crystal display area 23 of the gaming machine 1 is covered. , Indicates that the game cannot be continued because an error has occurred in the RAM data. As a result, it is possible to suppress the RAM destruction action due to the goto action. Such cancellation of the notification is performed, for example, by changing the setting such as turning off the power.

Further, as another example of the error information history shown in FIG. 49, for example, No. In 2 and 4, "WDR POST" and "WDR PRE" are shown, respectively. "WDR PRE" indicates a power failure error before the first lever operation after the power is turned on, and "WDR POST" indicates a power failure error after the first lever operation after the power is turned on. As a result, it can be seen that there was a power failure different from the normal power failure process, and it becomes possible to confirm the goto action.

Further, in the gaming machine of the present embodiment described above, the case where the gaming machine 1 is used as a pachislot machine has been described. However, the gaming machine according to the present invention is not limited to this, and can be applied to, for example, a pachinko machine having a symbol variation display device, as will be described later.

Further, in the gaming machine of the present embodiment described above, the two-dimensional code 300 has been described as including only the communication error history data. However, the gaming machine according to the present invention is not limited to this, and may include, for example, an error information history or a player's gaming record.

As described above, in the gaming machine of the present embodiment, when a communication error occurs between the main control circuit 60 and the sub control circuit 70, the communication is cut off, and the communication cutoff is canceled, or the sub control circuit 70 is disconnected. When the error occurs, the time information of the occurrence of the error and the release time of the communication interruption are stored together with the error code, so that the date and time and the contents of the occurrence and cancellation of the error can be confirmed later. It is useful for managing machines and gaming machines.

In the flowchart of the mother task shown in FIG. 57, when the main board communication task start request is issued from the OS in response to the main board communication task start request (step S1005), the main board communication task is shown in FIG. 69 as described above. It is executed according to the flowchart.

Further, the RTC control task is executed according to the flow chat shown in FIG. 75. First, the sub CPU 71 sets a cycle of 100 ms for OS time management (step S1011). Next, the sub CPU 71 reads the date and time from the external RTC70c (step S1012), and sets the date and time of the read external RTC70c as the initial value of the built-in RTC70a (step S1013).

Next, the sub CPU 71 reads the status information from the external RTC70c (step S1014), determines whether or not the status information can be read normally (step S1015), and if it can be read normally, the power supply is turned on. It is determined whether or not there is an abnormality (step S1016), and if there is no power supply abnormality, it is determined whether or not there is an oscillation abnormality (step S1017), and if there is no oscillation abnormality, a reset signal is detected. Whether or not it is determined (step S1018), and if the reset signal is not detected, the date and time are read from the external RTC70c (step S1019).

When this date and time is read, the sub CPU 71 determines whether or not there is an abnormality in the date and time range (step S1020). For example, if the value of year, month, day or time exceeds two digits, it is determined that there is an abnormality in the date and time range. When the sub CPU 71 determines that there is an abnormality in the date and time range, as shown in the table of FIG. 12, the sub CPU 71 sets the error code (RTC TIM) as the RTC time abnormality and sets the error code (RTC TIM) in the error information history storage area 73d-1 of the sub RAM 73-1. (Step S1021).

On the other hand, when the sub CPU 71 determines in step S1015 that the status information cannot be normally read from the external RTC 70c, an error code (RTC) is set in the error information history storage area 73d-1 as an RTC communication line error. DSC) is registered (step S1021).

When the sub CPU 71 determines in step S1016 that there is an abnormality in the power supply with respect to the external RTC 70c, the sub CPU 71 registers an error code (RTC POWER) as an RTC voltage drop in the error information history storage area 73d-1 (step). S1021).

When the sub CPU 71 determines in step S1017 that there is an oscillation abnormality with respect to the external RTC 70c, the sub CPU 71 registers an error code (RTC CLK) in the error information history storage area 73d-1 as oscillation stop detection (step S1021). ).

If the sub CPU 71 determines in step S1018 that a reset signal has been detected, the sub CPU 71 registers an error code (RTC RESET) in the error information history storage area 73d-1 as reset detection (step S1021).

As described above, when the sub CPU 71 registers the error code corresponding to the error type of the external RTC70c as error information in step S1021, the sub CPU 71 initializes the external RTC70c and sets the current date and time of the built-in RTC70a in the external RTC70c. (Step S1022).

In this way, when the external RTC70c is initialized and the current date and time of the built-in RTC70a is set in the external RTC70c, or when it is determined in step S1020 that there is no abnormality in the range of the date and time read from the external RTC70c by step S1019. The sub CPU 71 determines whether or not the date and time setting of the external RTC70c has been changed from the staff operation screen (step S1023), and if it has been changed, the date and time data of the built-in RTC70a is externally attached. Set to RTC70c (step S1024).

If the date and time data of the built-in RTC70a is set to the external RTC70c in step S1024, or if it is determined in step S1023 that there is no change in the date and time setting of the external RTC70c, the sub CPU 71 waits for a cycle of 100 ms. Then (step S1025), the status information is read again from the external RTC70c (step S1014).

Next, the backup creation process will be described with reference to FIG. 76. FIG. 76 is a flowchart of the backup creation process. This process allows the correct value to be saved as a backup even if the data is corrupted. As described above, this backup creation process is also executed in the power interruption interrupt process of the sub CPU shown in FIG. 56.

First, the sub CPU 71 creates a sum value of the game data area 73a-1, and stores the created sum value in the game data sum value area 73b-1 (step S1051). Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 1 area 73a-2, and saves the sum value saved in step S1051 in the backup data 1 sum value area 73b-2 (step S1052).

Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 2 area 73c-2 as mirroring of the backup data 1 area 73a-2, and the sum value saved in step S1051 is the backup data 2 sum value area. Save in 73d-2 (step S1053).

Next, the sub CPU 71 creates a sum value of the clerk operation setting data area 73g-1, and saves the created sum value in the clerk operation setting data sum value area 73h-1 (step S1054).

Next, the sub CPU 71 copies the clerk operation setting data area 73g-1 to the clerk backup data area 73e-2, and saves the sum value saved in step S1054 in the clerk backup data sum value area 73g-2 (step S1055). ). This ends the backup creation process.

[Structure of pachinko gaming machine]
The present invention is not limited to pachislot machines, but can also be applied to pachinko gaming machines. Hereinafter, the pachinko gaming machine will be described.

As shown in FIGS. 77, 78 and 79, the pachinko machine 1010 includes a glass door 1011, a wooden frame 1012, a base door 1013, a game board 1014, a dish unit 1020, a liquid crystal display device 1032 for displaying an image, and a game ball. It is composed of a launching device 1130 for firing, a payout unit (not shown), a board unit, and the like.

The glass door 1011 is attached to the base door 1013 so as to be openable and closable by a rotating shaft. An opening 1011a is formed in the center of the glass door 1011, and a protective glass 1019 having transparency is arranged in the opening 1011a.

The plate unit 1020 is a unit body in which the upper plate 1021 and the lower plate 1022 are integrated, and is arranged below the glass door 1011 in the base door 1013. The upper plate 1021 and the lower plate 1022 are formed with payout outlets 1021a and 1022a for lending and paying out the game balls (prize balls), and if the predetermined payout conditions are satisfied, the game is played. The balls are discharged, and in particular, the upper plate 1021 stores game balls for firing in the game area 1015, which will be described later.

The launcher 1130 is disposed at the lower right of the base door 1013 and includes a launch handle 1026 that can be operated by the player and a panel body 1027 that fits into the lower right of the dish unit 1020. The firing handle 1026 is provided on the front side of the panel body 1027. A drive device for launching a game ball is provided on the back side of the panel body 1027. The player can launch the game ball and advance the game by operating the launch handle 1026.

The game board 1014 is arranged in front of the base door 1013 so as to be located behind the protective glass 1019. A liquid crystal display device 1032 or the like is arranged behind the game board 1014. A payout unit and a board unit are arranged behind the base door 1013. At the bottom of the lower plate 1022, a speaker for staging (not shown) is arranged.

The game board 1014 is made of various resins (transparent members) such as a plate-shaped acrylic resin, a polycarbonate resin, and a methacrylic resin, all of which have transparency. Further, the game board 1014 has a game area 1015 on the front side thereof, on which the launched game ball can roll and flow down. A plurality of game nails 1017 are driven into the game area 1015. Further, an LED unit 1053 is provided at the lower left of the game board 1014.

The liquid crystal display device 1032 is arranged behind (rear side) the game board 1014. The liquid crystal display device 1032 has a display area 1032a that enables display of an image related to the game. In the display area 1032a, various images such as an identification symbol for effect, an effect image, and a decorative image for decoration are displayed.

The firing handle 1026 is rotatable, and a firing solenoid (not shown), which is a driving device, is provided on the back side thereof. Further, a touch sensor (not shown) is provided on the peripheral edge of the launch handle 1026. Inside the firing handle 1026, a firing volume is provided that changes the resistance value according to the amount of rotation of the firing handle 1026 and changes the electric power supplied to the firing solenoid (not shown).

When the player comes into contact with the touch sensor (not shown), it is detected that the launch handle 1026 has been grasped by the player. When the firing handle 1026 is grasped by the player and rotated in the clockwise direction, the resistance value of the firing volume (not shown) changes according to the rotation angle, and corresponds to the resistance value at this time. Power is supplied to the firing solenoid (not shown). As a result, the game balls stored in the upper plate 1021 are sequentially launched into the game area 1015, and the game is advanced. When the launch stop button (not shown) is pressed, the launch of the game ball is stopped even when the launch handle 1026 is held and rotated.

A member forming the general winning openings 1056a, 1056b, and 1056c is arranged in the lower left of the game board 1014, and the portion of this member facing the LED unit 1053 is transparent. Therefore, the LED unit 1053 can be visually recognized from the lower left of the game board 1014. The LED unit 1053 includes a special symbol display device shown in FIG. 79, a normal symbol display device 1033, a first special symbol hold display LED 1034a, 1034b, a second special symbol hold display LED 1034c, 1034d, a normal symbol hold display LED 1050a, 1050b, and the like. Is provided.

The special symbol display device is composed of 16 LEDs. These 16 LEDs are divided into two groups consisting of eight LEDs, one group performs variable display triggered by a start winning prize to the first starting port 1023, and the other group performs variable display. , The variable display is performed with the start winning prize to the second starting port 1044 as an opportunity. For convenience of the following description, one LED group is referred to as a first special symbol display device 1035a (see FIG. 79), and the other LED group is referred to as a second special symbol display device 1035b (see FIG. 79).

The LEDs of the first and second special symbol display devices 1035a and 1035b display the variation of the special symbol by repeatedly turning on and off in group units when the predetermined variation display start condition of the special symbol is satisfied. Then, when the special symbol has a specific stop display mode, the gaming state shifts from the normal gaming state to the hit gaming state (special gaming state) which is a state advantageous to the player. In this hit game state, as will be described later, the shutter 1040 is controlled to the open state, and the game ball is in a state where the game ball can be accepted by the big winning opening 1039.

The normal symbol display device 1033 is variablely displayed as a normal symbol by repeatedly turning on and off the two display lamps alternately, and the normal electric accessory 1048 is opened according to the stop mode.

The normal symbol hold display LEDs 1050a and 1050b display the number of executions of the variation display of the normal symbol held by turning on, off, or blinking (so-called "holding number", "holding number related to the normal symbol").

The first special symbol hold display LED 1034a, 1034b and the second special symbol hold display LED 1034c, 1034d are the number of executions of the variable display of the special symbol held by turning on, off, or blinking (so-called "number of hold", "special symbol". Hold quantity for ") is displayed.

Further, in the display area of the liquid crystal display device 1032, an effect image related to the special symbol displayed on the first special symbol display device 1035a and the second special symbol display device 1035b is displayed.

As shown in FIG. 78, on the game board 1014, two guide rails 1030 (1030a and 1030b), a stage 1055, a first starting port 1023, a second starting port 1044, a passing gate 1054, a shutter 1040, and a large winning opening. 1039, general winning openings 1056a, 1056b, 1056c, 1056d, ordinary electric accessory 1048 and the like are provided.

The stage 1055 is provided on the upper part of the game board 1014, and the guide rail 1030 is provided so as to surround the game area 1015.

The guide rail 1030 is composed of an outer rail 1030a and an inner rail 1030b. The launched game ball is guided by the guide rail 1030, moves to the upper part of the game board 1014, and changes its traveling direction by colliding with the above-mentioned multiple game nails (not shown), the stage 1055, and the like. It flows down toward the bottom of the game board 1014. Specifically, the system that flows down the left side of the stage 1055 (so-called left-handed) and the launch handle 1026 are rotated to the right to the maximum, a game ball is driven into the right side of the stage 1055, and the right side of the stage 1055 is flowed down. There is a system (so-called right-handed).

The first starting port 1023 is provided below the center of the game board 1014. The passage gate 1054 is provided on the upper right side of the stage 1055, and a second starting port 1044 is provided below the passage gate 1054. The ordinary electric accessory 1048 is provided at the second starting port 1044.

Further, the ordinary electric accessory 1048 includes a tongue-shaped member 1048a that projects and retracts in the front-rear direction with respect to the game board surface. The ordinary electric accessory 1048 makes it possible to win a game ball in the second starting port 1044 when the tongue-shaped member 1048a protrudes, and makes it impossible to win a game ball in the second starting port 1044 when the tongue-shaped member 1048a is retracted. The ordinary electric accessory 1048 may be a pair of blade members that open and close (so-called electric tulip).

Further, when hitting to the right, the game ball is configured so that the game ball cannot win a prize from the right side of the stage 1055 to the first starting port 1023 by the game nail 1017.

Further, when the game ball passes through the passing gate 1054 during the variable display of the normal symbol, the display mode by the normal symbol hold display LEDs 1050a and 1050b is switched, and the normal symbol being displayed in the variable display is stopped and displayed. Execution (start) of the variation display of the normal symbol based on the passage of the game ball to the passage gate 1054 is suspended. After that, when the normal symbol that has been variablely displayed is stopped and displayed, the variable display of the reserved normal symbol is started.

When a specific symbol is stopped and displayed as a normal symbol on the normal symbol display device 1033, an effect image for the player to understand that the normal symbol lottery is won is displayed in the display area of the liquid crystal display device 1032. You may do so.

Further, the shutter 1040 is arranged directly below the first starting port 1023 so as to open and close the large winning opening 1039. An out port 1057 is formed at the lowermost portion of the game area 1015 directly below the shutter 1040. The general winning openings 1056a, 1056b, and 1056c are provided in the lower left side of the game area 1015. Further, a general winning opening 1056d is provided at the lower right side of the game area 1015.

Further, a winning area is provided in the first starting opening 1023 described above, and the winning area is provided with a first starting winning opening switch 1116 (see FIG. 79). A winning area is provided in the second starting opening 1044, and the winning area is provided with a second starting winning opening switch 1117 (see FIG. 79). When the game ball is detected by the first start winning opening switch 1116, the variation display of the special symbol by the first special symbol display device 1035a is started.

In addition, when a game ball enters the first start port 1023 during the variation display of the special symbol, the game ball enters the first start port 1023 until the special symbol being displayed in the variation is stopped and displayed. Execution (start) of the variable display of the special symbol based on is suspended. After that, when the special symbol that has been variablely displayed is stopped and displayed, the variable display of the reserved special symbol is started. In the following description, the special symbol that is variablely displayed on the first special symbol display device 1035a based on the entry of the game ball into the first starting port 1023 is referred to as a first special symbol.

Further, when the game ball is detected by the second start winning opening switch 1117, the variation display of the special symbol by the second special symbol display device 1035b is started. In addition, when a game ball enters the second starting port 1044 during the variation display of the special symbol, the game ball enters the second starting port 1044 until the special symbol being displayed in the variation is stopped and displayed. Execution (start) of the variable display of the special symbol based on is suspended. After that, when the special symbol that has been variablely displayed is stopped and displayed, the variable display of the reserved special symbol is started. In the following description, the special symbol that is variablely displayed on the second special symbol display device 1035b based on the entry of the game ball into the second starting port 1044 is referred to as a second special symbol.

Here, the special symbol does not change at the same time in the first special symbol display device 1035a and the second special symbol display device 1035b. In addition, the variable display of the special symbol is performed with priority given to the starting prize for the second starting port 1044.

The number of pending changes in the special symbol due to ball entry into the first starting port 1023 and the second starting port 1044 is limited to four times, respectively. Therefore, it is possible to hold up to 8 times.

In addition, another condition (start of variable display of a predetermined special symbol) is that the special symbol is stopped and displayed. That is, the variable display of the special symbol is started every time the condition for starting the variable display of the predetermined special symbol is satisfied.

In the first special symbol display device 1035a and the second special symbol display device 1035b, when the special symbol becomes a specific stop display mode and the gaming state shifts to the big hit gaming state, the shutter 1040 is opened. Driven. As a result, the large winning opening 1039 is in an open state (first state) in which it is easy to accept the game ball.

On the other hand, the large winning opening 1039 provided on the back side (rear side) of the shutter 1040 has a region (not shown) having a count switch 1104 (see FIG. 79), and a predetermined number of game balls (for example, not shown) in that region. The shutter 1040 is driven to the open state until it passes (7 pieces) or a predetermined time (for example, about 0.1 second or about 30 seconds) has elapsed. Then, when either the condition of winning a predetermined number of game balls to the large winning opening 1039 or the lapse of a predetermined time is satisfied in the open state, the shutter 1040 is driven to be in the closed state. As a result, the big winning opening 1039 is in a closed state where it is difficult to accept the game ball (second state).

A game in which the big winning opening 1039 is in a state where it is easy to accept a game ball for a certain period of time is called a round game. Therefore, the shutter 1040 is opened during the round game and closed between the round games. Further, the round game is counted as the number of rounds such as "1" round and "2" round. For example, the first round of a round game may be referred to as a first round, and the second round may be referred to as a second round. In this example, the shutter 1040 may be opened and closed a plurality of times in one round, and the open state may be set to a fixed time.

Subsequently, the shutter 1040 driven from the open state to the closed state (second state) is driven to the open state again. That is, when the round game is over, the next round game can be continued. The game from the first round round game to the end of the (final) round game in which the next round game cannot be continued is called a special game or a big hit game. In this example, all jackpots are 15 rounds.

Further, when a game ball wins in the first starting port 1023, the second starting port 1044, the general winning openings 1056a to 1056d, and the large winning opening 1039, the number is set in advance according to the type of each winning opening. The game ball is paid out to the upper plate 1021 or the lower plate 1022.

Further, in this example, after the big hit game is completed, the winning probability of the normal symbol lottery becomes a high probability state, and the support by the ordinary electric accessory 1048 may shift to a time saving state in which the reserved balls of the special symbol game are easily accumulated. .. Here, in the time-saving state, passing the game ball through the passing gate 1054 is a condition for executing the normal symbol lottery, so that the game proceeds while hitting right.

Further, when a big hit occurs in the right-handed state, it is possible to win a prize in the big winning opening 1039 by continuing the right-handed hit as it is. In addition, if the support from the ordinary electric accessory 1048 cannot be received, the game will proceed while hitting left.

Further, as shown in FIG. 77, effect buttons 1080a, 1080b, 1080c are provided on the front surface of the upper plate 1021, and they are produced during a mini-game such as a push game, card turning, sugoroku, or the like. By pressing the button, the effect display content on the liquid crystal display device 1032 can be changed.

In the pachinko machine 1010, a liquid crystal display device is described as an example of the directing means, but the present invention is not limited to this, and a plasma display, a rear projection display, a CRT display, a lamp, a speaker, a movable accessory, or the like is used as the directing means. May be good.

Next, the electrical configuration of the pachinko machine 1010 will be described with reference to FIG. 79.

As shown in FIG. 79, the pachinko machine 1010 is mainly composed of a main control circuit 1060 that controls a game and a sub control circuit 1200 that controls an effect according to the progress of the game.

The main control circuit 1060 includes a main CPU 1066, a main ROM 1068 (read-only memory), and a main RAM 1070 (read / write memory).

A main ROM 1068, a main RAM 1070, and the like are connected to the main CPU 1066, and have a function of executing various processes according to a program stored in the main ROM 1068.

The main ROM 1068 stores a program for controlling the operation of the pachinko machine 1010 by the main CPU 1066, a program for causing the main CPU 1066 to execute main processing, and various tables.

The main RAM 1070 has a function of storing the values of various flags and variables as a temporary storage area of the main CPU 1066. The temporary storage area of the main CPU 1066 is not limited to the main RAM 1070, and other readable and writable storage media may be used.

Further, the main control circuit 1060 includes an initial reset circuit 1064, an I / O port 1071, and a command output port 1072 that generate a reset signal when the power is turned on. Further, the initial reset circuit 1064 is connected to the main CPU 1066. The I / O port 1071 transmits input signals from various devices to the main CPU 1066 and output signals from the main CPU 1066 to various devices.

The command output port 1072 transmits a command from the main CPU 1066 to the sub control circuit 1200. Further, the main control circuit 1060 includes a backup capacitor 1074. The backup capacitor 1074 is used to hold various data stored in the main RAM 1070 by promptly supplying power to the main RAM 1070, for example, when the power is cut off.

Further, various devices are connected to the main control circuit 1060. For example, the main control circuit 1060 includes a first special symbol display device 1035a, a second special symbol display device 1035b, a first special symbol hold display LED 1034a, 1034b, a second special symbol hold display LED 1034c, 1034d, and a normal symbol display device 1033. , Ordinary symbol hold display LED 1050a, 1050b, starting port solenoid 1118 that makes the tongue-shaped member 1048a of the ordinary electric accessory 1048 in a protruding state or a retracted state, and shutter 1040 are driven to open or close the large winning opening 1039. The big winning opening solenoid 1120 and the like are connected.

Further, the main control circuit 1060 has a calling device (not shown) having a function of calling a hall clerk and a function of displaying the number of hits, and an external terminal used for transmitting data to a hall computer 1400 that manages a pachinko machine for the entire hall. The plate 1310 is connected.

Further, the main control circuit 1060 includes, for example, a count switch 1104 that supplies a predetermined detection signal to the main control circuit 1060 when the game ball passes through the area of the large winning opening 1039, and each general winning opening 1056. When the game ball passes through the general winning opening switches 1106, 1108, 1110, 1112, and the passing gate 1054, which supply a predetermined detection signal to the main control circuit 60 when the game ball passes through the main control circuit 60. When the game ball wins the passage gate switch 1114 and the first start port 1023 supplied to the 1060, the first start winning port switch 1116 and the second start port 1044 that supply a predetermined detection signal to the main control circuit 1060 are played. The second start winning opening switch 1117 that supplies a predetermined detection signal to the main control circuit 1060 when the ball wins, and the backup clear switch that clears the backup data at the time of power failure etc. according to the operation of the game hall administrator. 1124 etc. are connected.

Further, a payout / launch control circuit 1126 is connected to the main control circuit 1060. A payout device 1128 for paying out game balls, a launcher 1130 for firing game balls, and a card unit 1300 are connected to the payout / launch control circuit 1126. The card unit 1300 can be transmitted / received to / from the ball lending operation panel 1155 that outputs a signal requesting the card unit 1300 to lend the game ball by the operation of the player.

The payout / launch control circuit 1126 receives the prize ball control command supplied from the main control circuit 1060 and the rental ball control signal supplied from the card unit 1300, and transmits a predetermined signal to the payout device 1128. Have the payout device 1128 pay out the game ball. Further, the payout / launch control circuit 1126 supplies electric power to the launch solenoid according to the rotation angle when the launch handle 1026 is gripped by the player and is rotated in the clockwise direction, and the game is played. Controls the firing of the ball.

A sub-control circuit 1200 is connected to the command output port 1072. The sub control circuit 1200 performs display control in the liquid crystal display device 1032, control related to sound generated from the speaker 1046, control of lamps including decorative lamps, and the like in response to various commands supplied from the main control circuit 1060. Further, the sub-control circuit 1200 has the same configuration as the sub-control circuit 70 described in the pachi-slot gaming machine of the present embodiment, and can execute various processes.

As described above, according to the pachinko gaming machine according to the present embodiment, the same effect as that of the pachislot gaming machine according to the above-described embodiment can be obtained.

1 Pachinko machine 1a Housing 1b Front door 2 Door key 3L, 3C, 3R reel 4L, 4C, 4R Symbol display area (symbol display means)
5 Liquid crystal display device (display unit, display device)
6S start switch (start operation detection means)
7LS, 7CS, 7RS stop switch (stop operation detection means)
20S setting key switch (operation unit , setting switch )
23 Liquid crystal display area 23S Reset switch (state release command input means, operation unit)
29S Door open / close switch (door open state detection means)
31 Main CPU (internal winning combination determination means, command transmission means, command data transmission means)
32 Main ROM (storage means)
39 Motor drive circuit (design change means, stop control means)
49L, 49C, 49R Stepping motors (design change means, stop control means)
50 Reel position detection circuit (design change means, stop control means)
60, 1060 Main control circuit (main control unit)
70, 1200 Sub-control circuit (sub-control unit)
70a Built-in RTC (timekeeping means , timekeeping means )
71 Sub CPU (effect content determination means, effect control means, command receiving means, processing means, data receiving means, error monitoring means, error canceling means, command data receiving means)
71a Communication error detecting means (error detecting means, first error detecting means, second error detecting means, third error detecting means , error recognizing means )
71b Procedure detection means 71c Data corruption detection means 71d Error information registration means (communication disconnection information registration means)
71e Received data log storage means 71f Error information history display means (display processing means)
71g Two-dimensional code conversion means 71h Communication disconnection detecting means (communication disconnection counter, counter updating means)
72 sub ROM
72a OS area 72b Sub control program area 72c Game data initialization setting data area 72d Staff operation initial setting data area 72e Various program table areas 72f Program management data area 72g Image data (still image / moving image)
72h Sound data 72i Character movable data 73-1 DRAM (storage unit, holding storage means)
73a-1 Sub-control game data area (game data storage area)
73b-1 Sub-control game data sum value area 73c-1 Work area 73d-1 Error information history storage area (error information registration area)
73e-1 Communication log collection ring buffer area 73f-1 Communication error storage buffer area 73-2 SRAM (holding and storing means)
73a-2 Backup data 1 area 73b-2 Backup data 1 Sam value 73c-2 Backup data 2 area 73d-2 Backup data 2 Sam value 73e-2 Personnel backup data area 73f-2 Error information history storage area 73g-2 Personnel backup Data sum value 74 GPU
75 VRAM
300 Two-dimensional code 330 QR code (registered trademark)
400 Mobile communication terminal with camera (mobile terminal)
500 Data management server (server)
600 Analysis PC (analysis means)

Claims (1)

A display unit that displays images and
The main control unit that controls the progress of the game,
The setting key switch connected to the main control unit,
A sub-control unit that is connected to the display unit and the main control unit to control the display unit, and
Equipped with an error recognition means to recognize that an error has occurred,
The sub-control unit
A holding storage means that includes an error information history storage area for storing error information related to the error recognized by the error recognition means and can hold the stored information even when the power supply is cut off.
Timekeeping means for timing and outputting timekeeping information to the outside,
At least, an error information registration means for sequentially storing the error information related to the error that occurred and the timekeeping information from the timekeeping means as an error information history in the error information history storage area based on a command received from the main control unit. When,
It has an error information history display means for displaying the error information history stored in the error information history storage area on the display unit.
The error information history display means displays the error information history on the display unit when the setting key switch is operated in the ON state and a menu for displaying the error information history is selected.
The error information registration means is the same as a command in which the received command has no physical layer error and an error detected by a command check process other than the physical layer error, and a command in which the received command has the physical layer error. A gaming machine characterized in that even if it is a command type, it may be stored in the error information history storage area as a different error information history.

Images