JP7096992B2 - Through Silicon Via Board and Mounting Board - Google Patents

Description

An embodiment of the present disclosure relates to a through silicon via substrate including a substrate, a first wiring structure portion, and a second wiring structure portion. Moreover, the embodiment of the present disclosure relates to a mounting substrate including a through electrode substrate and an element.

In recent years, as integrated circuits represented by semiconductor memories have become faster and more highly integrated, there is also a demand for miniaturization of through silicon via boards on which integrated circuits are mounted and passive components used around integrated circuits. ing. For example, Patent Document 1 proposes forming an LC parallel resonant circuit integrally with a multilayer board by forming an inductor by combining a conductive layer and vias of the multilayer board.

Japanese Unexamined Patent Publication No. 2005-347781

In a filter such as an LC parallel resonant circuit, a plurality of types of inductors having different inductances and a plurality of types of capacitors having different capacitances are used. As a means for adjusting the inductance of the inductor formed on the multilayer board, it is conceivable to adjust the length of the conductive layer constituting the inductor. Further, as a means for adjusting the inductance of the capacitor formed on the multilayer board, it is conceivable to adjust the area of the conductive layer that functions as the electrode of the capacitor. However, there is a limit to the range of inductance and capacitance that can be adjusted depending on the length and area of the conductive layer.

It is an object of the present disclosure to provide a through silicon via substrate that can effectively solve such a problem.

One embodiment of the present disclosure includes a first surface and a second surface located on the opposite side of the first surface, provided with a substrate through hole from the first surface to the second surface, and glass. The substrate, the first wiring structure portion including the first surface conductive layer and the first surface insulating layer located on the first surface side, and the second surface conductive layer and the second surface insulating located on the second surface side. A second wiring structure including a layer, a through electrode extending along a wall surface of the substrate through hole, the first surface conductive layer of the first wiring structure, and the second wiring structure of the second wiring structure. The second surface conductive layer and the through electrode electrically connected to the first surface conductive layer of the first wiring structure portion and the second surface conductive layer of the second wiring structure portion have a first inductance. The first surface conductive layer extending along the wall surface of the first through hole penetrating the first surface insulating layer of the first wiring structure portion and the surface of the first surface insulating layer. However, it is a through electrode substrate that constitutes a second inductor having a second inductance different from the first inductance.

In the through silicon via substrate according to the embodiment of the present disclosure, the first inductance of at least a part of the first inductor may be at least five times the second inductance of the second inductor of the present disclosure.

The through electrode substrate according to the embodiment of the present disclosure further includes an in-hole insulating layer located between the surfaces of the through silicon vias facing each other inside the through silicon via, and the in-hole insulating layer and the first surface insulation. The layer may have, at least partially, a resin containing an organic material and a plurality of particles located within the resin and containing an inorganic material.

In the through silicon via substrate according to the embodiment of the present disclosure, the second surface insulating layer has at least a resin containing an organic material and a plurality of particles located in the resin and containing an inorganic material, at least partially. May be.

In the through silicon via substrate according to the embodiment of the present disclosure, the first inductor and the second inductor are arranged so as not to overlap each other when viewed along the normal direction of the first surface of the substrate. May be good.

In the through silicon via substrate according to the embodiment of the present disclosure, the first inductor and the second inductor are the first inductor and the second inductor when viewed along the normal direction of the first surface of the substrate. It may be arranged so as not to overlap with the first surface conductive layer other than the first surface conductive layer constituting the inductor.

In the through silicon via substrate according to the embodiment of the present disclosure, the first inductor and the second inductor constitute the first inductor when viewed along the normal direction of the first surface of the substrate. It may be arranged so as not to overlap with the second surface conductive layer other than the second surface conductive layer.

In the through silicon via substrate according to the embodiment of the present disclosure, the first inductor and the second inductor may be electrically connected in series or in parallel.

In the through electrode substrate according to the embodiment of the present disclosure, the first surface conductive layer of the first wiring structure portion is arranged in order from the first surface side along the normal direction of the first surface of the substrate. The first surface insulating layer of the first wiring structure portion includes the first surface first conductive layer, the first surface second conductive layer, and the first surface third conductive layer on the first surface first conductive layer. The first surface first insulating layer including the first surface first insulating layer and the first surface second insulating layer located on the first surface first insulating layer or the first surface second conductive layer. The conductive layer, the first surface first insulating layer located on the first surface first conductive layer, the first surface second insulating layer located on the first surface first insulating layer, and the first surface. The first surface third conductive layer located on the first surface second insulating layer constitutes a first capacitor having a first capacitance, and the first surface first conductive layer and the first surface first conductive layer. The first surface first insulating layer located on the layer and the first surface second conductive layer located on the first surface first insulating layer have a second capacitance different from the first capacitance. The second capacitor may be configured.

In the through silicon via substrate according to the embodiment of the present disclosure, the second capacitance of at least a part of the second capacitor may be at least five times or more the second capacitance of the first capacitor of the part.

In the through silicon via substrate according to the embodiment of the present disclosure, the first capacitor and the second capacitor overlap with the second surface conductive layer when viewed along the normal direction of the first surface of the substrate. It may be arranged so as not to become.

In the through electrode substrate according to the embodiment of the present disclosure, the first capacitor and the second capacitor may be electrically connected in series or in parallel.

In the through electrode substrate according to the embodiment of the present disclosure, the first surface insulating layer of the first wiring structure portion is located between the first surface first conductive layer and the first surface second conductive layer. Further having a first surface first inorganic layer containing an inorganic material, the first surface first conductive layer, the first surface first inorganic layer located on the first surface conductive layer, and the first surface. The first surface second conductive layer located on the surface first inorganic layer may form a third capacitor having a third capacitance different from the first capacitance and the second capacitance.

One embodiment of the present disclosure includes a first surface and a second surface located on the opposite side of the first surface, provided with a substrate through hole from the first surface to the second surface, and the glass. The substrate, the first wiring structure portion including the first surface conductive layer and the first surface insulating layer located on the first surface side, and the second surface conductive layer and the second surface insulating located on the second surface side. A second wiring structure including a layer, and a through electrode extending along the wall surface of the substrate through hole and electrically connected to at least one of the first surface conductive layer or the second surface conductive layer. The first surface conductive layer of the first wiring structure portion is the first surface first conductive layer, which is arranged in order from the first surface side along the normal direction of the first surface of the substrate. The first surface insulating layer of the first wiring structure portion includes the second surface conductive layer and the first surface third conductive layer, and the first surface insulating layer is located on the first surface first conductive layer. And the first surface first insulating layer or the first surface second insulating layer located on the first surface second conductive layer, the first surface first conductive layer and the first surface first. 1 The first surface first insulating layer located on the conductive layer, the first surface second insulating layer located on the first surface first insulating layer, and the position on the first surface second insulating layer. The first surface third conductive layer constitutes a first capacitor having a first capacitance, and the first surface first conductive layer and the first surface located on the first surface first conductive layer. A through electrode in which the first insulating layer and the first surface second conductive layer located on the first surface first insulating layer form a second capacitor having a second capacitance different from the first capacitance. It is a board.

In the through silicon via substrate according to the embodiment of the present disclosure, the second capacitance of at least a part of the second capacitor may be at least five times or more the second capacitance of the first capacitor of the part.

In the through silicon via substrate according to the embodiment of the present disclosure, the first capacitor and the second capacitor overlap with the second surface conductive layer when viewed along the normal direction of the first surface of the substrate. It may be arranged so as not to become.

In the through electrode substrate according to the embodiment of the present disclosure, the first capacitor and the second capacitor may be electrically connected in series or in parallel.

In the through electrode substrate according to the embodiment of the present disclosure, the first wiring structure portion is located between the first surface first conductive layer and the first surface second conductive layer, and is a first surface containing an inorganic material. Further having a surface first inorganic layer, the first surface first conductive layer, the first surface first inorganic layer located on the first surface conductive layer, and the first surface first inorganic layer. The second surface second conductive layer to be located may form a third capacitor having a third capacitance different from the first capacitance and the second capacitance.

The through electrode substrate according to the embodiment of the present disclosure is a resin substrate provided with an accommodating portion for accommodating the substrate, the first wiring structure portion, and the laminate of the second wiring structure portion, and the resin substrate is used. A resin substrate provided with a penetrating electrode may be further provided.

The through electrode substrate according to the embodiment of the present disclosure is located on the first surface side of the substrate, and when viewed along the normal direction of the first surface of the substrate, the first wiring structure portion and the said A first surface layer that extends so as to overlap both of the resin substrates is further provided, and the first surface layer penetrates the first surface layer, and the first surface conductive layer of the first wiring structure portion and the resin substrate. It may have an electrode electrically connected to the electrode.

The through electrode substrate according to the embodiment of the present disclosure is located on the second surface side of the substrate, and when viewed along the normal direction of the second surface of the substrate, the second wiring structure portion and the said A second surface layer that extends so as to overlap both of the resin substrates is further provided, and the second surface layer penetrates the second surface layer, and the second surface conductive layer of the second wiring structure portion and the resin substrate. It may have an electrode electrically connected to the electrode.

One embodiment of the present disclosure is a mounting substrate including the through silicon via substrate described above and an element mounted on the through silicon via substrate.

In the mounting substrate according to one embodiment of the present disclosure, the element may include at least one of a power amplifier, a surface acoustic wave filter, or a switch.

According to the embodiment of the present disclosure, it is possible to provide a through silicon via substrate capable of easily adjusting the inductance of the inductor or the capacitance of the capacitor.

It is sectional drawing which shows the through silicon via substrate which concerns on one Embodiment. It is sectional drawing which shows the through hole and the through electrode of a through electrode substrate in an enlarged manner. It is sectional drawing which shows one modification of the through electrode of a through electrode substrate. It is a top view which shows the 1st inductor of the through silicon via substrate enlarged. It is sectional drawing which shows the 2nd inductor of the through electrode substrate enlarged. It is a top view which shows the 2nd inductor of the through electrode substrate enlarged. It is sectional drawing which shows the 1st capacitor, the 2nd capacitor and the 3rd capacitor of a through silicon via substrate in an enlarged manner. It is a figure which shows an example of the filter circuit which is constructed by combining an inductor and a capacitor. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is a figure which shows the manufacturing process of the through electrode substrate. It is sectional drawing which shows one modification of the through silicon via substrate. It is sectional drawing which shows one modification of the through silicon via substrate. It is sectional drawing which shows one modification of the through silicon via substrate. It is sectional drawing which shows an example of a mounting board. It is sectional drawing which shows an example of a mounting board. It is sectional drawing which shows one modification of the through silicon via substrate. It is a figure which shows the manufacturing process of the through silicon via substrate shown in FIG. It is a figure which shows the manufacturing process of the through silicon via substrate shown in FIG. It is sectional drawing which shows the mounting substrate including the through silicon via substrate shown in FIG. 23. It is sectional drawing which shows an example of an electronic device. It is sectional drawing which shows an example of an electronic device. It is a figure which shows the example of the product which mounts a through electrode substrate.

Hereinafter, the configuration of the through silicon via substrate and the manufacturing method thereof according to the embodiment of the present disclosure will be described in detail with reference to the drawings. It should be noted that the embodiments shown below are examples of the embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Further, in the present specification, terms such as "board", "base material", "sheet" and "film" are not distinguished from each other based only on the difference in names. For example, "base material" and "base material" are concepts including members that can be called sheets or films. Furthermore, the terms such as "parallel" and "orthogonal" and the values of length and angle used in the present specification to specify the shape and geometric conditions and their degrees are bound by a strict meaning. Instead, the interpretation shall be made to include the range in which similar functions can be expected. Further, in the drawings referred to in the present embodiment, the same parts or parts having similar functions may be designated by the same reference numerals or similar reference numerals, and the repeated description thereof may be omitted. Further, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

Through Silicon Via Substrate Hereinafter, embodiments of the present disclosure will be described. First, the configuration of the through silicon via substrate 10 according to the present embodiment will be described. FIG. 1 is a cross-sectional view showing a through silicon via substrate 10.

The through electrode substrate 10 includes a substrate 12, a through electrode 22, a first wiring structure portion 30, and a second wiring structure portion 40. Hereinafter, each component of the through silicon via substrate 10 will be described.

(substrate)
The substrate 12 includes a first surface 13 and a second surface 14 located on the opposite side of the first surface 13. Further, the substrate 12 is provided with a plurality of substrate through holes 20 from the first surface 13 to the second surface 14.

The substrate 12 contains an inorganic material having a certain insulating property. For example, the substrate 12 includes a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO ₂ ) substrate, and a niobium. A lithium oxide substrate, a tantalum niobate substrate, etc., or a laminate of these substrates. The substrate 12 may partially include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate.

Examples of the glass used in the substrate 12 include non-alkali glass. Non-alkali glass is glass that does not contain alkaline components such as sodium and potassium. The non-alkali glass contains, for example, boric acid instead of the alkaline component. The non-alkali glass also contains, for example, alkaline earth metal oxides such as calcium oxide and barium oxide. Examples of non-alkali glass include EN-A1 manufactured by Asahi Glass and Eagle XG manufactured by Corning. When the substrate 12 contains glass, the thickness of the substrate 12 is, for example, 0.1 mm or more and 0.5 mm or less. Since the substrate 12 contains glass, the insulating property of the substrate 12 can be improved as compared with the case where the substrate 12 is made of silicon, and thereby the withstand voltage characteristics of the capacitor located on the substrate 12 can be improved. can.

FIG. 2 is an enlarged cross-sectional view showing the substrate through hole 20 and the through electrode 22 of the through electrode substrate 10. In FIG. 2, reference numeral S1 represents the dimension of the substrate through hole 20 at a position where the substrate through hole 20 is connected to the first surface 13, and reference numeral S2 is a position where the substrate through hole 20 is connected to the second surface 14. Represents the dimensions of the substrate through hole 20 in. As shown in FIG. 2, the dimension S1 of the substrate through hole 20 on the first surface 13 side may be smaller than the dimension S2 of the substrate through hole 20 on the second surface 14 side. In the example shown in FIG. 2, the size of the substrate through hole 20 becomes smaller from the second surface 14 to the first surface 13. The dimension S1 is, for example, 30 μm or more and 100 μm or less. Further, the dimension S2 is, for example, 50 μm or more and 150 μm or less. Further, the ratio of the length of the substrate through hole 20 to the dimension S1 of the substrate through hole 20, that is, the aspect ratio of the substrate through hole 20 is, for example, 2 or more and 10 or less.

As shown in FIG. 3, the substrate through hole 20 may have a dimension S1 and a dimension S3 smaller than the dimension S2 at a position between the first surface 13 and the second surface 14 of the substrate 12. For example, the substrate through hole 20 may have a shape in which the dimension decreases toward the central portion in the thickness direction of the substrate 12 from the first surface 13 and the second surface 14 of the substrate 12.

Although not shown, the size S1 of the substrate through hole 20 on the first surface 13 side may be larger than the size S2 of the substrate through hole 20 on the second surface 14 side.

(Through Silicon Via)
FIG. 2 is an enlarged cross-sectional view showing the through electrode 22 provided in the substrate through hole 20. The through electrode 22 is a member that is located inside the substrate through hole 20, extends along the wall surface 21 of the substrate through hole 20, and has conductivity. In the present embodiment, the thickness of the through electrode 22 on the wall surface 21 is smaller than the width of the substrate through hole 20, so that there is a hollow portion inside the substrate through hole 20 in which the through electrode 22 does not exist. .. That is, the through electrode 22 is a so-called conformal via. The hollow portion is defined as a region between the surfaces of the through silicon vias 22 facing each other inside the substrate through hole 20 in the region inside the substrate through hole 20. The thickness of the through electrode 22 is, for example, 2 μm or more and 25 μm or less.

As long as the through electrode 22 has conductivity, the method for forming the through electrode 22 is not particularly limited. For example, the through electrode 22 may be formed by a physical film forming method such as a vapor deposition method or a sputtering method, or may be formed by a chemical film forming method or a plating method. Further, the through electrode 22 may be composed of a single layer having conductivity, or may include a plurality of layers having conductivity. Here, as shown in FIG. 2, an example in which the through silicon via 22 includes the first layer 221 and the second layer 222 will be described.

The first layer 221 is a layer that is at least partially located on the wall surface 21 of the substrate through hole 20 and has conductivity. The first layer 221 is formed on the wall surface 21 by a physical film forming method such as a sputtering method or a vapor deposition method, or a sol-gel method. Preferably, the first layer 221 is formed on the wall surface 21 by a sputtering method. As a result, the first layer 221 can be firmly adhered to the wall surface 21. The thickness of the first layer 221 is, for example, 0.05 μm or more and 5.0 μm or less. In addition, another layer may be provided between the first layer 221 and the wall surface 21 of the substrate through hole 20.

When the first layer 221 is formed by the physical film forming method, the material constituting the first layer 221 is a metal such as titanium, chromium, nickel, or copper, an alloy using these, or a laminated material thereof. Can be used. When the first layer 221 is formed by the sol-gel method, zinc oxide or the like can be used as the material constituting the first layer 221. In addition to the sol-gel layer formed by the sol-gel method, the first layer 221 may further have an electroless plating layer containing a metal such as copper formed on the sol-gel layer by the electroless plating method. ..

The first layer 221 may be a single layer or may include a plurality of layers. For example, the first layer 221 may include a titanium layer located on the wall surface 21 and a copper layer located on the titanium layer.

The second layer 222 is a layer that is located on the first layer 221 and has conductivity. The second layer 222 contains, for example, copper as a main component, and more specifically, contains 80% by mass or more of copper. Further, the second layer 222 may contain a metal such as gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium, or an alloy using these. The second layer 222 is formed on the first layer 221 by the electrolytic plating method. As a method for analyzing the composition of the second layer 222, for example, TEM (transmission electron microscope) or EDS (energy dispersion type X-ray spectroscope) can be adopted. The thickness of the second layer 222 is, for example, 2 μm or more and 20 μm or less. In addition, another conductive layer may be provided between the first layer 221 and the second layer 222.

(1st wiring structure part)
Next, the first wiring structure portion 30 will be described. The first wiring structure portion 30 has a layer such as a conductive layer or an insulating layer provided on the first surface 13 side so as to form an electric circuit on the first surface 13 side of the substrate 12. For example, the first wiring structure portion 30 has a plurality of conductive layers and a plurality of insulating layers provided at different positions in the normal direction of the first surface 13 of the substrate 12. In the following description, a plurality of conductive layers located on the first surface 13 side of the substrate 12 may be collectively referred to as a first surface conductive layer. Further, a plurality of insulating layers located on the first surface 13 side of the substrate 12 may be collectively referred to as a first surface insulating layer. As will be described later, passive components such as capacitors and inductors are configured by combining the first surface conductive layer, the first surface insulating layer, and the like.

In the present embodiment, the first wiring structure portion 30 includes a first surface first conductive layer 31, a first surface first inorganic layer 32, a first surface first insulating layer 33, and a first surface second conductive layer 34. It has a first surface second insulating layer 35, a first surface third conductive layer 36, and a first surface third insulating layer 37. Hereinafter, each layer will be described.

[First surface, first conductive layer]
The first surface first conductive layer 31 is a layer having conductivity located on the first surface 13 of the substrate 12. The first surface first conductive layer 31 may be electrically connected to the through electrode 22. Further, the first surface first conductive layer 31 may be composed of a single layer having conductivity, or may include a plurality of layers having conductivity. For example, the first surface first conductive layer 31 may include a first layer 221 and a second layer 222 sequentially laminated on the first surface 13 of the substrate 12, similarly to the through silicon via 22. Further, the first surface first conductive layer 31 may include only a part of the conductive layers of the first layer 221 and the second layer 222. The material constituting the first surface first conductive layer 31 is the same as the material constituting the through electrode 22. The thickness of the first surface first conductive layer 31 is, for example, 100 nm or more and 20 μm or less, and may be 2 μm or more and 20 μm or less.

[First surface, first inorganic layer]
The first surface first inorganic layer 32 is a layer that is at least partially located on the first surface first conductive layer 31 and contains an inorganic material and has an insulating property. The first surface first inorganic layer 32 may be partially located on the first surface 13 of the substrate 12.

The inorganic material of the first surface first inorganic layer 32 has an insulation breakdown electric field of preferably 6 MV / cm or more, more preferably 8 MV / cm or more. As the inorganic material of the first surface first inorganic layer 32, a silicon nitride such as SiN can be used. In addition, examples of the inorganic material of the first surface first inorganic layer 32 include silicon oxide, aluminum oxide, and tantalum pentoxide. The relative permittivity of the inorganic material of the first surface first inorganic layer 32 is, for example, 3 or more and 50 or less. The thickness of the first surface first inorganic layer 32 is, for example, 50 nm or more and 400 nm or less. The first surface first inorganic layer 32 may be composed of a single layer or may include a plurality of layers.

Preferably, the leakage current of the first surface first inorganic layer 32 in the inorganic material is 1 × 10 ^-8 A or less, more preferably 1 × 10 ^-9 A or less, and further preferably 1 × 10 ^-10 A. It is A or less, and particularly preferably 1 × ^10-11 A or less. As a result, the electrical characteristics of the third capacitor 19, which will be described later, including the first surface first inorganic layer 32 can be further improved.

[First surface, first insulating layer]
The first surface first insulating layer 33 is located at least partially on the first surface 13 of the substrate 12, on the first surface first conductive layer 31, or on the first surface first inorganic layer 32, and contains an organic material. It is a layer containing and having an insulating property. The organic material of the first surface first insulating layer 33 preferably has a dielectric loss tangent of less than 0.03, as will be described later. By constructing the first surface first insulating layer 33 using an organic material having a small dielectric loss tangent, it is possible to prevent an electric signal to pass through a capacitor or an inductor described later from passing through the first surface first insulating layer 33. be able to. As a result, the band of the through electrode substrate 10 including the capacitor and the inductor can be expanded to the high frequency side. The thickness of the first surface first insulating layer 33 is, for example, 5 μm or more and 40 μm or less.

[First surface, second conductive layer]
The first surface second conductive layer 34 is a layer having conductivity located on the first surface first inorganic layer 32 or the first surface first insulating layer 33. Like the through silicon via 22 and the first surface first conductive layer 31, the first surface second conductive layer 34 is laminated on the first surface first inorganic layer 32 or on the first surface first insulating layer 33 in order. It may contain a plurality of conductive layers. The material constituting the first surface second conductive layer 34 is the same as the material constituting the through electrode 22 and the first surface first conductive layer 31. The thickness of the first surface second conductive layer 34 is, for example, 100 nm or more and 20 μm or less.

[First surface, second insulating layer]
The first surface second insulating layer 35 is a layer located on the first surface first insulating layer 33 or on the first surface second conductive layer 34, containing an organic material, and having an insulating property. The first surface second insulating layer 35, like the first surface first insulating layer 33, preferably contains an organic material having a dielectric loss tangent of less than 0.03. The thickness of the first surface second insulating layer 35 is, for example, 5 μm or more and 40 μm or less.

[First surface, third conductive layer]
The first surface third conductive layer 36 is a layer having conductivity located on the first surface first conductive layer 31, the first surface second conductive layer 34, or the first surface second insulating layer 35. be. The first surface third conductive layer 36 may include a plurality of conductive layers laminated in order, similar to the through electrode 22 and the first surface first conductive layer 31. The material constituting the first surface third conductive layer 36 is the same as the material constituting the through electrode 22 and the first surface first conductive layer 31.

[First surface, third insulating layer]
The first surface third insulating layer 37 is a layer located on the first surface second insulating layer 35 or on the first surface third conductive layer 36, containing an organic material, and having an insulating property. The first surface third insulating layer 37, like the first surface first insulating layer 33, preferably contains an organic material having a dielectric loss tangent of less than 0.03. The thickness of the first surface third insulating layer 37 is, for example, 5 μm or more and 40 μm or less.

(2nd wiring structure part)
Next, the second wiring structure unit 40 will be described. The second wiring structure portion 40 has a layer such as a conductive layer or an insulating layer provided on the second surface 14 side so as to form an electric circuit on the second surface 14 side of the substrate 12. Like the first wiring structure portion 30, the second wiring structure portion 40 has a plurality of conductive layers and a plurality of insulating layers provided at different positions in the normal direction of the second surface 14 of the substrate 12. May be good. In the following description, one or more conductive layers located on the second surface 14 side of the substrate 12 may be collectively referred to as a second surface conductive layer. Further, one or more insulating layers located on the second surface 14 side of the substrate 12 may be collectively referred to as a second surface insulating layer.

In the present embodiment, the second wiring structure portion 40 has a second surface first conductive layer 41 and a second surface first insulating layer 43.

[Second surface, first conductive layer]
The second surface first conductive layer 41 is a layer having conductivity located on the second surface 14 of the substrate 12. The second surface first conductive layer 41 may be electrically connected to the through electrode 22.

The second surface first conductive layer 41 includes a first layer 221 and a second layer 222 sequentially laminated on the second surface 14 of the substrate 12, similarly to the through electrode 22 and the first surface first conductive layer 31. You may be. Further, the first conductive layer 41 on the second surface may include only a part of the conductive layers of the first layer 221 and the second layer 222. The material constituting the second surface first conductive layer 41 is the same as the material constituting the through electrode 22. The thickness of the second surface first conductive layer 41 is, for example, 100 nm or more and 20 μm or less, and may be 2 μm or more and 20 μm or less.

[Second surface, first insulating layer]
The second surface first insulating layer 43 is a layer located on the second surface first conductive layer 41 and on the second surface 14 of the substrate 12, contains an organic material, and has an insulating property. The second surface first insulating layer 43, like the first surface first insulating layer 33 and the first surface second insulating layer 35, preferably contains an organic material having a dielectric loss tangent of 0.03 or less. The thickness of the second surface first insulating layer 43 is, for example, 5 μm or more and 40 μm or less.

(Insulation layer in the hole)
As shown in FIGS. 1 to 3, the through electrode substrate 10 may be further provided with an in-hole insulating layer 26 which is located in the hollow portion of the through silicon via 20 and contains an organic material and has an insulating property. The in-hole insulating layer 26 is located between the surfaces of the through silicon vias 22 facing each other inside the substrate through hole 20. By providing the in-hole insulating layer 26 in the substrate through hole 20, it is possible to prevent a treatment liquid such as a developing solution or a cleaning liquid from infiltrating into the substrate through hole 20 in the manufacturing process of the through electrode substrate 10.

The in-hole insulating layer 26, like the first surface first insulating layer 33, contains, for example, an organic material having a dielectric loss tangent of less than 0.03. By forming the in-hole insulating layer 26 using an organic material having a small dielectric loss tangent, it is possible to prevent an electric signal that should pass through the first inductor 15, which will be described later, from passing through the in-hole insulating layer 26.

The in-hole insulating layer 26 may be at least partially integrated with the first surface first insulating layer 33 of the first wiring structure portion 30 or the second surface first insulating layer 43 of the second wiring structure portion 40. "Integral" means that there is no interface between the in-hole insulating layer 26 and the first surface first insulating layer 33 or the second surface first insulating layer 43. For example, the film containing the organic material is pressed from the second surface 14 side toward the substrate 12, thereby partially pushing the organic material into the inside of the substrate through hole 20, thereby forming the in-hole insulating layer 26 and the second surface. The first insulating layer 43 can be integrally formed. The same applies to the in-hole insulating layer 26 on the first surface 13 side and the first surface first insulating layer 33. The in-hole insulating layer 26 may be integrated with both the first surface first insulating layer 33 and the second surface first insulating layer 43.

The in-hole insulating layer 26 may be filled in the hollow portion of the substrate through hole 20 without a gap. Alternatively, the in-hole insulating layer 26 may not be completely filled in the hollow portion of the substrate through hole 20. For example, when the substrate through hole 20 is viewed along the normal direction of the first surface 13 of the substrate 12, a hole may be present in a part of the in-hole insulating layer 26, and the in-hole insulating layer may be present. There may be a gap between the 26 and the through electrode 22.

(Passive parts)
In the through electrode substrate 10, a passive component is formed by a part of the through electrode 22, the first wiring structure portion 30, and the second wiring structure portion 40. In the present embodiment, an example in which the first inductor 15, the second inductor 16, the first capacitor 17, the second capacitor 18, and the third capacitor 19 are formed on the through electrode substrate 10 will be described.

[First inductor]
First, the first inductor 15 will be described. As shown in FIG. 1, the first inductor 15 has a first surface first conductive layer 31 of the first wiring structure portion 30, a second surface first conductive layer 41 of the second wiring structure portion 40, and a first surface. It has a through electrode 22 electrically connected to the first conductive layer 31 and the second surface first conductive layer 41. The first inductor 15 has a first inductance.

FIG. 4 is a plan view showing a case where the first surface first conductive layer 31 constituting the first inductor 15 is viewed from the first surface 13 side. In FIG. 4, the second surface first conductive layer 41 located on the second surface 14 side of the substrate 12 is represented by a dotted line. The first inductor 15 in FIG. 1 corresponds to a cross-sectional view when the first inductor 15 shown in FIG. 4 is cut along the lines AA. The first surface first conductive layer 31, the through electrode 22, and the second surface first conductive layer 41 form a wiring that spirally orbits a part of the substrate 12 around an axis along the plane direction of the substrate 12. It is connected.

[Second inductor]
Next, the second inductor 16 will be described. FIG. 5 is an enlarged sectional view showing the second inductor 16. As shown in FIG. 5, the second inductor 16 includes a first surface first conductive layer 31 and a first surface third conductive layer 36. The first surface first conductive layer 31 constituting the second inductor 16 extends along the surface of the first surface first insulating layer 33 on the substrate 12 side. Further, the first surface third conductive layer 36 constituting the second inductor 16 is connected to the first surface first conductive layer 31 and penetrates the first surface first insulating layer 33 and the first surface second insulating layer 35. A first portion 361 extending along the wall surface of the first through hole 38 and a surface extending along the surface of the surface of the first surface second insulating layer 35 opposite to the substrate 12 connected to the first portion 361. The second part 362 and the like are included. The second inductor 16 has a second inductance different from the first inductance.

FIG. 6 is a plan view showing a case where the first surface third conductive layer 36 constituting the second inductor 16 is viewed from the upper side of FIG. In FIG. 6, the first through hole 38 and the first surface first conductive layer 31 are represented by dotted lines. The second inductor 16 in FIG. 5 corresponds to a cross-sectional view when the second inductor 16 shown in FIG. 6 is cut along the line BB. The first portion 361 and the second portion 362 of the first surface first conductive layer 31, the first surface third conductive layer 36 are in the plane direction of the first surface first insulating layer 33 and the first surface second insulating layer 35. It is connected so as to form a wiring that spirally orbits a part of the laminated body of the first surface first insulating layer 33 and the first surface second insulating layer 35 about the axis along the axis.

The inductance of the inductor is proportional to the cross-sectional area of the inductor in a plane orthogonal to the axis of the inductor. The cross section of the first inductor 15 is composed of the substrate 12. The cross section of the second inductor 16 is composed of the first surface first insulating layer 33 and the first surface second insulating layer 35. The thickness of the substrate 12 is larger than the sum of the thickness of the first surface first insulating layer 33 and the thickness of the first surface second insulating layer 35. Therefore, when other conditions such as the number of turns and the length of the inductor are the same, the first inductance of the first inductor 15 becomes larger than the second inductance of the second inductor 16. For example, when the occupied area of each inductor is the same when viewed along the normal direction of the first surface 13 of the substrate 12, the first inductance becomes larger than the second inductance. The first inductance of at least a part of the first inductor 15 may be 5 times or more or 10 times or more the second inductance of at least a part of the second inductor 16.

[Capacitor]
Next, the first capacitor 17, the second capacitor 18, and the third capacitor 19 will be described. FIG. 7 is an enlarged sectional view showing the first capacitor 17, the second capacitor 18, and the third capacitor 19. The first surface conductive layer of the first wiring structure portion 30 constituting each capacitor is the above-mentioned first surface first conductive layer arranged in order from the first surface 13 side along the normal direction of the first surface 13 of the substrate 12. 31, including the second portion 362 of the first surface second conductive layer 34 and the first surface third conductive layer 36.

First, the first capacitor 17 will be described. As shown in FIG. 7, the first capacitor 17 has a first surface first conductive layer 31, a first surface first insulating layer 33 located on the first surface first conductive layer 31, and a first surface first surface. It has a first surface second insulating layer 35 located on the insulating layer 33 and a second portion 362 of the first surface third conductive layer 36 located on the first surface second insulating layer 35. The second portion 362 of the first surface first conductive layer 31 and the first surface third conductive layer 36 functions as the facing first electrode and the second electrode. Further, the first surface first insulating layer 33 and the first surface second insulating layer 35 function as a dielectric located between the first electrode and the second electrode. The first capacitor 17 has a first capacitance.

Next, the second capacitor 18 will be described. As shown in FIG. 7, the second capacitor 18 includes a first surface first conductive layer 31, a first surface first insulating layer 33 located on the first surface first conductive layer 31, and a first surface first surface. It has a first surface and a second conductive layer 34 located on the insulating layer 33. The first surface first conductive layer 31 and the first surface second conductive layer 34 function as facing first electrodes and second electrodes. Further, the first surface first insulating layer 33 functions as a dielectric located between the first electrode and the second electrode. The second capacitor 18 has a second capacitance different from the first capacitance.

Next, the third capacitor 19 will be described. As shown in FIG. 7, the third capacitor 19 has a first surface first conductive layer 31, a first surface first inorganic layer 32 located on the first surface first conductive layer 31, and a first surface first surface. It has a first surface second conductive layer 34 located on the inorganic layer 32. The first surface first conductive layer 31 and the first surface second conductive layer 34 function as facing first electrodes and second electrodes. Further, the first surface first inorganic layer 32 functions as a dielectric located between the first electrode and the second electrode. The third capacitor 19 has a third capacitance different from the first capacitance and the second capacitance.

The capacitance of the capacitor is inversely proportional to the distance between the first and second electrodes. In the first capacitor 17, the first surface first insulating layer 33 and the first surface second insulating layer 35 are present between the first electrode and the second electrode. On the other hand, in the second capacitor 18, the first surface first insulating layer 33 exists between the first electrode and the second electrode. Therefore, when the other conditions are the same, the second capacitance of the second capacitor 18 becomes larger than the first capacitance of the first capacitor 17. For example, when the area of the electrodes is the same, the second capacitance becomes larger than the first capacitance. The second capacitance of at least a part of the second capacitor 18 may be 5 times or more or 10 times or more the first capacitance of at least a part of the first capacitors 17.

Also, the capacitance of the capacitor is proportional to the permittivity of the dielectric. In the second capacitor 18, the first surface first insulating layer 33 containing an organic material functions as a dielectric. On the other hand, in the third capacitor 19, the first surface first inorganic layer 32 containing the inorganic material functions as a dielectric. The relative permittivity of an inorganic material such as silicon nitride is generally higher than the relative permittivity of an organic material such as polyimide or epoxy. Therefore, when the other conditions are the same, the third capacitance of the third capacitor 19 becomes larger than the second capacitance of the second capacitor 18. For example, when the area of the electrodes is the same, the third capacitance becomes larger than the second capacitance. The third capacitance of at least a part of the third capacitor 19 may be 5 times or more, or 20 times or more, the second capacitance of at least a part of the second capacitor 18.

The third capacitance of at least a part of the third capacitor 19 may be 5 times or more or 10 times or more the first capacitance of at least a part of the first capacitors 17.

FIG. 8 is a diagram showing an example of a filter circuit 100 configured by combining the above-mentioned inductors 15 and 16 and capacitors 17, 18 and 19. The filter circuit 100 shown in FIG. 8 is configured by electrically connecting the inductors 15, 16 and the capacitors 17, 18, and 19 in series or in parallel, respectively. For example, the first inductor 15 and the second inductor 16 are electrically connected in series or in parallel. Further, the first capacitor 17 and the second capacitor 18 are electrically connected in series or in parallel.

The filter circuit 100 shown in FIG. 8 is, for example, a bandpass filter in which the center frequency of the pass band is 24 GHz or more and 32 GHz or less, and the width of the pass band is 6 GHz or more and 10 GHz or less. An example of the configuration of the bandpass filter is shown below.
・ Center frequency of passband: 27.925GHz
・ Passband width: 0.85GHz
・ Inductor: L1 = 14.04pH, L2 = 15.15nH, L3 = 4.34pH, L4 = 15.15nH, L5 = 14.04pH
-Capacitors: C1 = 2.31pF, C2 = 2.14fF, C3 = 7.49pF, C4 = 2.14fF, C5 = 2.31pF

In order to form a filter circuit having desired characteristics, it is required to combine a plurality of types of inductors having different inductances and a plurality of types of capacitors having different capacitances. For example, in the filter circuit 100 shown in FIG. 8, the ratio of the maximum inductance to the minimum inductance is 3000 times or more. Moreover, the ratio of the maximum capacitance to the minimum capacitance is 3000 times or more.

Here, in the present embodiment, as described above, the through silicon via substrate 10 has a first inductor 15 that spirally orbits a part of the substrate 12, a first surface first insulating layer 33, and a first surface second surface. It has a second inductor 16 that spirally orbits the insulating layer 35. Therefore, it is easy to increase the ratio of the first inductance of the first inductor 15 to the second inductance of the second inductor 16.
Further, as described above, the through electrode substrate 10 has a first capacitor 17 using the first surface first conductive layer 31 and the second portion 362 of the first surface third conductive layer 36 as electrodes, and the first surface first. It has a second capacitor 18 that uses one conductive layer 31 and a first surface second conductive layer 34 as electrodes. Therefore, it is easy to increase the ratio of the second capacitance of the second capacitor 18 to the first capacitance of the first capacitor 17.
Further, as described above, the through electrode substrate 10 includes a second capacitor 18 using the first surface first insulating layer 33 as a dielectric and a third capacitor 19 using the first surface first inorganic layer 32 as a dielectric. , Have. Therefore, it is easy to increase the ratio of the third capacitance of the third capacitor 19 to the second capacitance of the second capacitor 18. Further, it is easy to increase the ratio of the third capacitance of the third capacitor 19 to the first capacitance of the first capacitor 17.

Therefore, according to the present embodiment, a plurality of types of inductors having significantly different inductances and a plurality of types of capacitors having significantly different capacitances can be formed on the through silicon via substrate 10. As a result, a filter circuit having desired characteristics can be formed on the through electrode substrate 10.

(Arrangement of passive parts)
Next, a preferred example of arranging passive components such as inductors and capacitors will be described.

Preferably, as shown in FIG. 1, the first inductor 15 and the second inductor 16 are arranged so as not to overlap each other when viewed along the normal direction of the first surface 13 of the substrate 12. As a result, it is possible to suppress the occurrence of interference between the first inductor 15 and the second inductor 16. For example, it is possible to suppress the noise generated in the first inductor 15 from being transmitted to the second inductor 16. Similarly, it is possible to suppress the noise generated in the second inductor 16 from being transmitted to the first inductor 15.

Further, preferably, as shown in FIG. 1, the first inductor 15 and the second inductor 16 are the first inductor 15 and the second inductor when viewed along the normal direction of the first surface 13 of the substrate 12. It is arranged so as not to overlap with the first surface conductive layer other than the first surface conductive layer constituting 16. For example, the first inductor 15 and the second inductor 16 are arranged so as not to overlap with the first surface conductive layer constituting the wiring and the first surface conductive layer constituting the capacitor. As a result, it is possible to suppress the occurrence of interference between the first inductor 15 and the second inductor 16 and the first surface conductive layer.

Further, preferably, as shown in FIG. 1, the first inductor 15 and the second inductor 16 form the first inductor 15 when viewed along the normal direction of the first surface 13 of the substrate 12. It is arranged so as not to overlap with the second surface conductive layer other than the second surface first conductive layer 41. As a result, it is possible to suppress the occurrence of interference between the first inductor 15 and the second inductor 16 and the second surface conductive layer.

Preferably, as shown in FIG. 1, the first capacitor 17, the second capacitor 18, and the third capacitor 19 are the second surface first when viewed along the normal direction of the first surface 13 of the substrate 12. It is arranged so as not to overlap with the second surface conductive layer such as the conductive layer 41. As a result, it is possible to suppress the occurrence of interference between the first capacitor 17, the second capacitor 18, the third capacitor 19, and the second surface conductive layer.

(Preferable example of organic material for insulating layer)
In order to widen the band of passive components such as inductors 15 and 16 and capacitors 17, 18 and 19 to the high frequency side, for example, 10 GHz or more, a material having excellent high frequency characteristics is used and the first surface of the first wiring structure portion 30 is used. It is preferable to form an insulating layer, a second surface insulating layer of the second wiring structure portion 40, and an in-hole insulating layer 26. For example, it is preferable that the dielectric loss tangent of each insulating layer is small. Hereinafter, an example of the configuration of each insulating layer will be described.

Each insulating layer has, for example, a resin containing an organic material and a plurality of particles located within the resin and containing an inorganic material. The dielectric loss tangent of the resin of each insulating layer at 10 GHz may be less than 0.03, less than 0.02, less than 0.01, less than 0.006. It may be less than 0.004. Examples of the resin having such a dielectric loss tangent include a polyimide resin, an epoxy resin, a polyphenylene ether resin, a fluorine resin such as a polytetrafluoroethylene resin, and the like. Specific examples of the epoxy resin include GY11, GL102, GL103 manufactured by Ajinomoto Fine-Techno Co., Ltd., Zaristo517X manufactured by Taiyo Ink Mfg. Co., Ltd., and the like. Specific examples of the polyphenylene ether-based resin include NC0209 manufactured by Namics Co., Ltd. Specific examples of the fluororesin include Cytop and EPRIMA AL manufactured by Asahi Glass Co., Ltd.

The resin of each insulating layer does not have to have photosensitivity to ultraviolet rays and the like. For example, the resin does not contain a photopolymerization initiator. This makes it easier to lower the dielectric loss tangent of the resin. If the resin does not have photosensitivity, the photolithography method cannot be used as a method of processing each insulating layer to form through holes in each insulating layer. In this case, as a method of forming the through hole, a laser processing method of irradiating each insulating layer with a laser beam such as an ultraviolet laser can be adopted.

The particles contained in each insulating layer are, for example, granular members containing an inorganic material, which is also called a filler. By dispersing the particles in the resin, it is possible to prevent each insulating layer from expanding or contracting due to a temperature change. Examples of the material constituting the particles include silicon oxides such as silicon dioxide. The average particle size of the particles is preferably 1 μm or less, more preferably 0.6 μm or less. As a result, the smoothness of each insulating layer is improved, so that the high frequency characteristics of the conductive layer in contact with each insulating layer can be improved. For example, the transmission loss in the conductive layer can be reduced. The average particle size of the particles can be calculated, for example, based on the average value of the dimensions of the cross section of the particles appearing in the image of the cross section of each insulating layer. The number of particles to be measured when calculating the average particle size is arbitrary, but is, for example, 1000.

It is not necessary that the first surface insulating layer of the first wiring structure portion 30, the second surface insulating layer of the second wiring structure portion 40, and the in-hole insulating layer 26 all have a uniformly low dielectric loss tangent. For example, the first surface first insulating layer 33 and the first surface second insulating layer 35 of the first wiring structure portion 30 contain a resin having a dielectric loss tangent of less than 0.01, but the first surface third insulating layer 37. May contain a resin having a dielectric loss tangent of 0.01 or more.

(Manufacturing method of through silicon via board)
Hereinafter, an example of a method for manufacturing the through silicon via substrate 10 will be described with reference to FIGS. 9 to 18.

(Through hole forming process)
First, the substrate 12 is prepared. Next, a resist layer is provided on at least one of the first surface 13 and the second surface 14. After that, an opening is provided in the resist layer at a position corresponding to the substrate through hole 20. Next, by processing the substrate 12 at the opening of the resist layer, the substrate through hole 20 can be formed in the substrate 12 as shown in FIG. As a method for processing the substrate 12, a dry etching method such as a reactive ion etching method or a deep digging reactive ion etching method, a wet etching method, or the like can be used.

The substrate through hole 20 may be formed in the substrate 12 by irradiating the substrate 12 with a laser. In this case, the resist layer may not be provided. As the laser for laser processing, an excimer laser, an Nd: YAG laser, a femtosecond laser, or the like can be used. When the Nd: YAG laser is adopted, a fundamental wave having a wavelength of 1064 nm, a second harmonic having a wavelength of 532 nm, a third harmonic having a wavelength of 355 nm, and the like can be used.

Further, laser irradiation and wet etching can be appropriately combined. Specifically, first, the altered layer is formed in the region of the substrate 12 where the substrate through hole 20 should be formed by laser irradiation. Subsequently, the substrate 12 is immersed in hydrogen fluoride or the like to etch the altered layer. As a result, the substrate through hole 20 can be formed in the substrate 12. In addition, the substrate through hole 20 may be formed in the substrate 12 by a blast treatment of spraying an abrasive on the substrate 12.

(Through Silicon Via Forming Process)
Next, the through electrode 22 is formed on the wall surface 21 of the substrate through hole 20. In the present embodiment, at the same time as the through silicon via 22, the first surface first conductive layer 31 is formed on a part of the first surface 13 of the substrate 12, and the second surface is formed on a part of the second surface 14 of the substrate 12. An example of forming the first conductive layer 41 will be described.

First, as shown in FIG. 10, the first layer 221 is formed on the first surface 13, the second surface 14, and the wall surface 21 of the substrate 12 by a physical film forming method, a sol-gel method, an electroless plating method, or the like. Subsequently, as shown in FIG. 11, a resist layer 81 is partially formed on the first layer 221. As the material of the resist layer 81, a photosensitive material such as a dry film resist containing an acrylic resin can be used. Subsequently, as shown in FIG. 11, the second layer 222 is formed on the first layer 221 not covered by the resist layer 81 by the electrolytic plating method. For example, the substrate 12 is immersed in an electrolytic plating solution containing copper. Further, a current is passed through the first layer 221. As a result, the second layer 222 can be deposited on the first layer 221.

(Resist and conductive layer removal process)
Then, as shown in FIG. 12, the resist layer 81 is removed. Subsequently, as shown in FIG. 12, the portion of the first layer 221 that was covered by the resist layer 81, in other words, the portion of the first layer 221 that was exposed from the second layer 222, was wet-etched, for example. Removed by. In this way, the through silicon via 22 including the first layer 221 and the second layer 222, the first surface first conductive layer 31 and the second surface first conductive layer 41 can be formed. As a result, the second surface first conductive layer 41, the through electrode 22 electrically connected to the second surface first conductive layer 41, and the first surface first conductive layer electrically connected to the through electrode 22 The first inductor 15 including 31 can be configured. The step of annealing the conductive layer such as the second layer 222 may be carried out.

(Step of forming the first inorganic layer on the first surface)
Next, as shown in FIG. 13, the first surface first inorganic layer 32 is formed on a part of the first surface first conductive layer 31. As a method for forming the first surface first inorganic layer 32, for example, plasma CVD, sputtering, atomic layer deposition method and the like can be adopted.

(Step of forming the first insulating layer on the first surface)
Further, as shown in FIG. 14, the first surface first insulating layer 33 is formed on the first surface 13 of the substrate 12 and on the first surface first conductive layer 31. For example, first, a resin film (not shown) having a resin layer containing an organic material and a base material is attached to the first surface 13 side of the substrate 12. Subsequently, the resin film is irradiated with a laser beam such as an ultraviolet laser. As a result, the through hole 331 can be formed in the first surface first insulating layer 33.

Similar to the first surface first insulating layer 33, as shown in FIG. 14, the second surface first insulating layer 43 is formed on the second surface 14 of the substrate 12 and on the second surface first conductive layer 41. You may. Further, as shown in FIG. 14, the in-hole insulating layer 26 is formed by pushing a part of the first surface first insulating layer 33 or a part of the second surface first insulating layer 43 into the inside of the substrate through hole 20. It may be formed.

As the organic material constituting the first surface first insulating layer 33, the second surface first insulating layer 43, and the in-hole insulating layer 26, a material having photosensitivity to ultraviolet rays or the like may be used. In this case, a photolithography method can be used as a method for forming the through hole 331 in the first surface first insulating layer 33.

Further, the order of the step of forming the first surface first inorganic layer 32 and the step of forming the first surface first insulating layer 33 is arbitrary. For example, the first surface first insulating layer 33 may be formed after the first surface first inorganic layer 32 is formed, or the first surface first inorganic layer 33 may be formed after the first surface first insulating layer 33 is formed. 32 may be formed.

(Step of forming the first surface and the second conductive layer)
Subsequently, as shown in FIG. 15, the first surface second conductive layer 34 is formed on the first surface first inorganic layer 32 and on a part of the first surface first insulating layer 33. As a result, the third capacitor 19 including the first surface first conductive layer 31, the first surface first inorganic layer 32, and the first surface second conductive layer 34 can be configured. Further, the second capacitor 18 including the first surface first conductive layer 31, the first surface first insulating layer 33, and the first surface second conductive layer 34 can be configured. Since the step of forming the first surface second conductive layer 34 is the same as the step of forming the first surface first conductive layer 31, the description thereof will be omitted.

(Step of forming the first surface and the second insulating layer)
Subsequently, as shown in FIG. 16, the first surface second insulating layer 35 is formed on the first surface first insulating layer 33 and on a part of the first surface second conductive layer 34. For example, as in the case of the first surface first insulating layer 33, first, a resin film (not shown) having a resin layer containing an organic material and a base material is attached to the first surface first insulating layer 33. Subsequently, the resin film is irradiated with a laser beam such as an ultraviolet laser to form a through hole 351 communicating with the through hole 331 of the first surface first insulating layer 33 in the first surface second insulating layer 35. As a result, as shown in FIG. 16, the first through hole 38 that penetrates the first surface first insulating layer 33 and the first surface second insulating layer 35 can be formed.

Although not shown, the first surface first insulating layer 33 and the first surface second insulating layer 35 are simultaneously processed to penetrate the first surface first insulating layer 33 and the first surface second insulating layer 35. The first through hole 38 may be formed.

(Step of forming the first surface third conductive layer)
Subsequently, as shown in FIG. 17, the first surface third conductive layer 36 is formed inside the first through hole 38 and on a part of the first surface second insulating layer 35. Thereby, the second inductor 16 including the first surface first conductive layer 31, the first surface third conductive layer 36, the first portion 361, and the second portion 362 can be configured. Further, the first capacitor 17 including the first surface first conductive layer 31, the first surface first insulating layer 33, the first surface second insulating layer 35, and the first surface third conductive layer 36 can be configured. Since the step of forming the first surface third conductive layer 36 is the same as the step of forming the first surface first conductive layer 31, the description thereof will be omitted.

(Step of forming the first surface and the third insulating layer)
Subsequently, the first surface third insulating layer 37 is formed on the first surface second insulating layer 35 and the first surface third conductive layer 36. In this way, the through silicon via substrate 10 shown in FIG. 1 can be obtained. Since the step of forming the first surface third insulating layer 37 is the same as the step of forming the first surface first insulating layer 33, the description thereof will be omitted.

In the present embodiment, as described above, the second surface conductive layer extending along the surface of the first surface insulating layer of the first wiring structure portion 30 and the wall surface of the first through hole 38 is used. The inductor 16 is configured. Therefore, the second inductor 16 having an inductance different from that of the first inductor 15 using the through electrode 22 can be easily formed on the through electrode substrate 10.

Further, in the present embodiment, the first surface first conductive layer 31, the first surface first inorganic layer 32, the first surface first insulating layer 33, the first surface second conductive layer 34, and the first surface second surface. Capacitors 17, 18 and 19 are configured by variously combining the insulating layer 35 and the first surface third conductive layer 36. Therefore, the capacitors 17, 18, and 19 having different capacitances can be easily formed on the through electrode substrate 10.

It is possible to make various changes to the above-described embodiment. Hereinafter, modification examples will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, the same reference numerals as those used for the corresponding portions in the above-described embodiment will be used for the portions that can be configured in the same manner as in the above-described embodiment. Duplicate explanations will be omitted. Further, when it is clear that the action and effect obtained in the above-described embodiment can be obtained in the modified example, the description thereof may be omitted.

In the above-described embodiment, an example is shown in which the through silicon via substrate 10 includes a first inductor 15, a second inductor 16, a first capacitor 17, a second capacitor 18, and a third capacitor 19. However, the combination of the inductor and the capacitor configured in the through electrode substrate 10 is not particularly limited.

For example, as shown in FIG. 18, the through silicon via substrate 10 includes a first inductor 15 and a second inductor 16, but may not include capacitors 17, 18, and 19. Although not shown, the through silicon via substrate 10 may include some of the capacitors 17, 18, and 19 in addition to the first inductor 15 and the second inductor 16.

Further, as shown in FIG. 19, the through silicon via substrate 10 includes a first inductor 15 and capacitors 17, 18 and 19, but does not have to include a second inductor 16. Although not shown, the through silicon via substrate 10 includes the second inductor 16 and the capacitors 17, 18, and 19, but may not include the first inductor 15. Although not shown, the through electrode substrate 10 may include capacitors 17, 18, and 19, but may not include inductors 15, 16.

Further, the through electrode substrate 10 may include only any two types of capacitors among the three types of capacitors 17, 18, and 19. For example, as shown in FIG. 20, the through electrode substrate 10 includes a first capacitor 17 and a second capacitor 18, but does not have to include a third capacitor 19. Alternatively, although not shown, the through silicon via substrate 10 may include a first capacitor 17 and a third capacitor 19, but may not include a second capacitor 18. Alternatively, although not shown, the through silicon via substrate 10 may include a second capacitor 18 and a third capacitor 19, but may not include a first capacitor 17.

(Other variants)
In the above-described embodiment, an example is shown in which the number of conductive layers included in the first wiring structure portion 30 is larger than the number of conductive layers included in the second wiring structure portion 40. However, the number is not limited to this, and although not shown, even if the number of conductive layers included in the first wiring structure portion 30 and the number of conductive layers included in the second wiring structure portion 40 are the same. good. Further, the number of conductive layers included in the first wiring structure portion 30 may be smaller than the number of conductive layers included in the second wiring structure portion 40. The same applies to the number of insulating layers.

Further, in the above-described embodiment, an example is shown in which the second inductor 16 is configured by wiring that spirally orbits a part of the first surface first insulating layer 33 and the first surface second insulating layer 35. rice field. However, the insulating layer provided with the wiring constituting the second inductor 16 is not limited to the first surface first insulating layer 33 and the first surface second insulating layer 35. The second inductor 16 can be configured by providing a conductive layer constituting a spirally circulating wiring in any insulating layer among the first surface insulating layers included in the first wiring structure portion 30.

Further, in the above-described embodiment, the first surface first insulating layer 33 and the first surface second insulating layer 35 form the dielectric of the first capacitor 17, and the first surface first insulating layer 33 is the second. An example of forming the dielectric of the capacitor 18 is shown. However, as long as the first capacitance of the first capacitor 17 and the second capacitance of the second capacitor 18 are different, the combination of the first surface insulating layers constituting the dielectric is not particularly limited. For example, the dielectric of the first capacitor 17 may be formed by using the first surface first insulating layer 33, the first surface second insulating layer 35, and the first surface third insulating layer 37.

Mounting board FIG. 21 is a cross-sectional view showing an example of a mounting board 60 including a through electrode board 10 and an element 50 mounted on the through electrode board 10. The element 50 is an LSI chip such as a logic IC or a memory IC. Further, the element 50 may be a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip is an electronic device in which machine element parts, sensors, actuators, electronic circuits, and the like are integrated on one substrate. Further, the element 50 may include at least one of a power amplifier, a surface acoustic wave filter or a switch.

As shown in FIG. 21, the element 50 has a terminal 51 electrically connected to the first surface conductive layer of the first wiring structure portion 30 of the through electrode substrate 10 via a first bump 39 or the like. As shown in FIG. 21, the second bump 49 may be connected to the second surface conductive layer of the second wiring structure portion 40. The second bump 49 is used to electrically connect the mounting board 60 to a motherboard or the like. The second bump 49 is provided inside, for example, a through hole formed in the second surface second insulating layer 45 located on the second surface first insulating layer 43. Further, the second bump 49 is electrically connected to the through electrode 22 via, for example, the second surface second conductive layer 44 located inside the through hole of the second surface first insulating layer 43.

The electrical connection between the first surface conductive layer of the first wiring structure portion 30 and the terminal 51 of the element 50 is not limited to the connection via the first bump 39. Although not shown, the element 50 may be mounted on the through silicon via substrate 10 in a state of being sealed in the first surface insulating layer of the first wiring structure portion 30. In this case, the electrical connection between the first surface conductive layer of the first wiring structure portion 30 and the terminal 51 of the element 50 is, for example, the first that penetrates the first surface insulating layer of the first wiring structure portion 30. This is realized by connecting the surface conductive layer to the terminal 51 of the element 50. In this case, the element 50 may be mounted on the through silicon via substrate 10 so that the terminal 51 faces the side opposite to the substrate 12.

(Modification example of mounting board)
FIG. 22 is a cross-sectional view showing a modified example of the mounting board 60. As shown in FIG. 22, the mounting substrate 60 may include an element 50 that overlaps with the first inductor 15 of the through electrode substrate 10 when viewed along the normal direction of the first surface 13 of the substrate 12. In this case, the through electrode substrate 10 may have a second surface conductive layer such as the first surface third conductive layer 36 electrically connected to the element 50. Further, when the second surface conductive layer such as the first surface third conductive layer 36 electrically connected to the element 50 is viewed along the normal direction of the first surface 13 of the substrate 12, the first inductor is used. It may overlap with 15. Although not shown, the mounting board 60 shown in FIG. 22 also has a second bump 49 connected to the second surface conductive layer of the second wiring structure portion 40, similarly to the mounting board 60 shown in FIG. 21. May be good.

Further, as shown in FIG. 22, even if the mounting board 60 includes an element 50 that overlaps with the second inductor 16 of the through electrode board 10 when viewed along the normal direction of the first surface 13 of the board 12. good. The element 50 may overlap with a capacitor such as the third capacitor 19. In this case, the through electrode substrate 10 may have a second surface conductive layer such as the first surface third conductive layer 36 electrically connected to the element 50. Further, when the second surface conductive layer such as the first surface third conductive layer 36 electrically connected to the element 50 is viewed along the normal direction of the first surface 13 of the substrate 12, the second inductor It may overlap with 16 or a capacitor.

(Modification example of through silicon via board)
FIG. 23 is a cross-sectional view showing a modified example of the through silicon via substrate 10. In this modification, the through silicon via substrate 10 further includes a resin substrate 27 provided with the accommodating portion 271. In this modification, the member including the substrate 12, the through electrode 22, the first wiring structure portion 30, and the second wiring structure portion 40, as shown in FIG. 1, is housed in the housing portion 271 of the resin substrate 27.

The resin substrate 27 is a substrate containing a resin material such as a glass epoxy resin. The glass epoxy resin is a material obtained by impregnating a glass fiber cloth with an epoxy resin and then subjecting it to a heat curing treatment. The accommodating portion 271 is, for example, an opening that penetrates the resin substrate 27. Although not shown, the accommodating portion 271 may be a recess that does not penetrate the resin substrate 27. Further, the resin substrate 27 may include an electrode 272 that penetrates the resin substrate 27. The thickness of the resin substrate 27 is equivalent to the thickness of the substrate 12, and is, for example, 0.2 mm or more and 0.5 mm or less.

As shown in FIG. 23, the through silicon via substrate 10 is located on the first surface 13 side of the substrate 12, and when viewed along the normal direction of the first surface 13 of the substrate 12, the first wiring structure portion 30 and A first surface layer 28 may be provided so as to overlap both of the resin substrates 27. The first surface layer 28 contains an insulating material such as an epoxy resin or a prepreg. Further, the first surface layer 28 has an electrode 281 penetrating the first surface layer 28. The electrode 281 is electrically connected to the first surface conductive layer of the first wiring structure portion 30 and the electrode 272 of the resin substrate 27. The thickness of the first surface layer 28 is, for example, 20 μm or more and 100 μm or less.

Further, the through silicon via substrate 10 is located on the second surface 14 side of the substrate 12, and both the second wiring structure portion 40 and the resin substrate 27 are viewed along the normal direction of the second surface 14 of the substrate 12. A second surface layer 29 may be provided so as to overlap with the surface layer 29. The second surface layer 29, like the first surface layer 28, contains an insulating material such as an epoxy resin and a prepreg. Further, the second surface layer 29 has an electrode 291 penetrating the second surface layer 29. The electrode 291 is electrically connected to the first surface conductive layer of the second wiring structure portion 40 and the electrode 272 of the resin substrate 27. The thickness of the second surface layer 29 is, for example, 20 μm or more and 100 μm or less.

Hereinafter, a method for manufacturing the through silicon via substrate 10 shown in FIG. 23 will be described with reference to FIGS. 24 and 25. First, as shown in FIG. 24, the resin substrate 27 provided with the accommodating portion 271 and the electrode 272 is prepared. Further, a laminated body in which the substrate 12, the first wiring structure portion 30 and the second wiring structure portion 40 are laminated is prepared. Subsequently, this laminated body is positioned in the accommodating portion 271 of the resin substrate 27.

Subsequently, as shown in FIG. 25, the first surface layer 28 provided with the electrode 281 is prepared. In addition, a second surface layer 29 provided with the electrode 291 is prepared. Subsequently, the first surface layer 28 is attached to the first wiring structure portion 30 and the resin substrate 27. For example, the electrode 281 of the first surface layer 28 is connected to the first surface conductive layer of the first wiring structure portion 30 and the electrode 272 of the resin substrate 27 by hot pressing. Further, the second surface layer 29 is attached to the second wiring structure portion 40 and the resin substrate 27. For example, the electrode 291 of the second surface layer 29 is connected to the second surface conductive layer of the second wiring structure portion 40 and the electrode 272 of the resin substrate 27 by hot pressing. In this way, the through silicon via substrate 10 shown in FIG. 23 can be obtained.

According to this modification, by accommodating the member including the substrate 12, the through electrode 22, the first wiring structure portion 30, and the second wiring structure portion 40 in the accommodating portion 271 of the resin substrate 27, the through electrode substrate 10 as a whole is accommodated. The area and the number of wires can be increased. This makes it easier to mount various functions and elements on the through silicon via substrate 10.

FIG. 26 is a cross-sectional view showing a mounting substrate 60 including the through silicon via substrate 10 shown in FIG. 23 and the element 50 mounted on the through silicon via substrate 10. In the example shown in FIG. 26, the element 50 is electrically connected to the first surface conductive layer of the first wiring structure portion 30 via the electrode 281 of the first surface layer 28. Further, the mounting substrate 60 includes a bump 61 connected to the electrode 291 of the second surface layer 29. Although not shown, the through electrode substrate 10 includes an element 50 electrically connected to the second surface conductive layer of the second wiring structure portion 40 via the electrode 291 of the second surface layer 29, and the electrode 281 or the electrode 291. An element 50 or the like electrically connected to the electrode 272 of the resin substrate 27 may be provided.

Note that FIG. 24 shows an example in which the electrode 272 is already formed on the resin substrate 27 before the substrate 12 or the like is accommodated in the accommodating portion 271 of the resin substrate 27, but the present invention is not limited to this. Although not shown, the electrode 272 may be formed on the resin substrate 27 after the substrate 12 or the like is accommodated in the accommodating portion 271 of the resin substrate 27.

Further, FIG. 25 shows an example in which the electrode 281 is already formed on the first surface layer 28 before the first surface layer 28 is attached to the first wiring structure portion 30 and the resin substrate 27, but this is limited to this. It will not be done. Although not shown, the electrode 281 may be formed on the first surface layer 28 after the first surface layer 28 is attached to the first wiring structure portion 30 and the resin substrate 27. The same applies to the second surface layer 29.

Electronic Device FIG. 27 is a cross-sectional view showing an example of an electronic device 70 including a motherboard 68 and a mounting board 60 mounted on the motherboard 68. The electronic device 70 may further include an element 65 mounted on the motherboard 68. The element 65 includes, for example, at least one of a power amplifier, a surface acoustic wave filter or a switch.

FIG. 28 is a cross-sectional view showing another example of the electronic device 70. As described above, the through electrode substrate 10 incorporates a filter circuit composed of an inductor and a capacitor. Therefore, an element preferably electrically connected to the filter circuit, such as a power amplifier, a surface acoustic wave filter, or a switch, can be mounted on the through electrode substrate 10 as the element 50. The element 50 may be mounted on the through silicon via substrate 10 via bumps, or may be sealed in the first surface insulating layer of the first wiring structure portion 30 of the through silicon via substrate 10. good.

An example of a product on which a through silicon via substrate is mounted FIG. 29 is a diagram showing an example of a product on which the through silicon via substrate 10 according to the embodiment of the present disclosure can be mounted. The through silicon via substrate 10 according to the embodiment of the present disclosure can be used in various products. For example, it is mounted on a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

10 Through electrode board 12 Board 13 First surface 14 Second surface 15 First inductor 16 Second inductor 17 First capacitor 18 Second capacitor 19 Third capacitor 20 Board through hole 21 Wall surface 22 Through electrode 221 First layer 222 Second Layer 26 Insulation layer in holes 27 Resin substrate 271 Capacitor 272 Electrode 28 First surface layer 281 Electrode 29 Second surface layer 291 Electrode 30 First wiring structure 31 First surface First conductive layer 32 First surface first inorganic layer 33 1st surface 1st insulating layer 34 1st surface 2nd conductive layer 35 1st surface 2nd insulating layer 36 1st surface 3rd conductive layer 37 1st surface 3rd insulating layer 38 1st through hole 39 1st bump 40 2nd wiring structure 41 2nd surface 1st conductive layer 43 2nd surface 1st insulating layer 44 2nd surface 2nd conductive layer 45 2nd surface 2nd insulating layer 49 2nd bump 50 Element 51 Terminal 60 Mounting board 61 Bump 65 element 68 motherboard 70 electronic device 100 filter circuit

Claims (21)

A substrate including a first surface and a second surface located on a side opposite to the first surface, provided with a substrate through hole from the first surface to the second surface, and having glass.
The first wiring structure portion including the first surface conductive layer and the first surface insulating layer located on the first surface side,
A second wiring structure including a second surface conductive layer and a second surface insulating layer located on the second surface side, and
A through electrode extending along the wall surface of the substrate through hole,
The first surface conductive layer of the first wiring structure portion, the second surface conductive layer of the second wiring structure portion, the first surface conductive layer of the first wiring structure portion, and the second wiring structure portion. The through electrode electrically connected to the second surface conductive layer constitutes a first inductor having a first inductance.
The wall surface of the first through hole penetrating the first surface insulating layer of the first wiring structure portion and the first surface conductive layer extending along the surface of the first surface insulating layer are different from the first inductance. A second inductor with a second inductance is configured to
The first surface conductive layer of the first wiring structure portion is a first surface first conductive layer and a first surface second arranged in order from the first surface side along the normal direction of the first surface of the substrate. Includes a conductive layer and a first surface third conductive layer
The first surface insulating layer of the first wiring structure portion is located on the first surface first conductive layer, and has a dielectric loss tangent of less than 0.03, the first surface first insulating layer, and the first surface. A first surface second insulating layer located on the first insulating layer or the first surface second conductive layer and having a dielectric loss tangent of less than 0.03 .
The first surface first conductive layer, the first surface first insulating layer located on the first surface first conductive layer, and the first surface second located on the first surface first insulating layer. The insulating layer and the first surface third conductive layer located on the first surface second insulating layer form a first capacitor having a first capacitance.
The first surface first conductive layer, the first surface first insulating layer located on the first surface first conductive layer, and the first surface second located on the first surface first insulating layer. The conductive layer constitutes a second capacitor having a second capacitance different from the first capacitance.
The second capacitor further includes the first surface third conductive layer that penetrates the first surface second insulating layer and is connected to the first surface second conductive layer.
The first wiring structure portion is located between the first surface first conductive layer and the first surface second conductive layer, and further has a first surface first inorganic layer containing an inorganic material.
The first surface first conductive layer, the first surface first inorganic layer located on the first surface conductive layer, and the first surface second conductive layer located on the first surface first inorganic layer. Consists of a third capacitor having a third capacitance different from the first capacitance and the second capacitance.
The third capacitor further includes the first surface third conductive layer that penetrates the first surface second insulating layer and is connected to the first surface second conductive layer.
Through silicon via board. The through electrode substrate according to claim 1, wherein the first inductance of at least a part of the first inductor is at least five times the second inductance of the second inductor of a part. The through silicon via substrate further comprises an in-hole insulating layer located between the surfaces of the through silicon vias facing each other inside the through silicon via.
Claim 1 or 2, wherein the in-hole insulating layer and the first surface insulating layer have at least a resin containing an organic material and a plurality of particles located in the resin and containing an inorganic material. Described through electrode substrate. The through silicon via according to claim 3, wherein the second surface insulating layer has at least a resin containing an organic material and a plurality of particles located in the resin and containing an inorganic material. According to any one of claims 1 to 4, the first inductor and the second inductor are arranged so as not to overlap each other when viewed along the normal direction of the first surface of the substrate. The described through electrode substrate. The first inductor and the second inductor are other than the first surface conductive layer constituting the first inductor and the second inductor when viewed along the normal direction of the first surface of the substrate. The through silicon via according to any one of claims 1 to 5, which is arranged so as not to overlap the first surface conductive layer. The first inductor and the second inductor are the second surface conductive other than the second surface conductive layer constituting the first inductor when viewed along the normal direction of the first surface of the substrate. The through electrode substrate according to any one of claims 1 to 6, which is arranged so as not to overlap with the layer. The through electrode substrate according to any one of claims 1 to 7, wherein the first inductor and the second inductor are electrically connected in series or in parallel. The through silicon via according to any one of claims 1 to 8, wherein the second capacitance of at least a part of the second capacitor is at least five times the second capacitance of the first capacitor of at least a part. The first capacitor and the second capacitor are arranged so as not to overlap with the second surface conductive layer when viewed along the normal direction of the first surface of the substrate. 9. The through electrode substrate according to any one of 9. The through electrode substrate according to any one of claims 1 to 10, wherein the first capacitor and the second capacitor are electrically connected in series or in parallel. A substrate including a first surface and a second surface located on a side opposite to the first surface, provided with a substrate through hole from the first surface to the second surface, and having glass.
The first wiring structure portion including the first surface conductive layer and the first surface insulating layer located on the first surface side,
A second wiring structure including a second surface conductive layer and a second surface insulating layer located on the second surface side, and
A through electrode extending along the wall surface of the substrate through hole and electrically connected to at least one of the first surface conductive layer or the second surface conductive layer is provided.
The first surface conductive layer of the first wiring structure portion is a first surface first conductive layer and a first surface second arranged in order from the first surface side along the normal direction of the first surface of the substrate. Includes a conductive layer and a first surface third conductive layer
The first surface insulating layer of the first wiring structure portion is located on the first surface first conductive layer, and has a dielectric loss tangent of less than 0.03, the first surface first insulating layer, and the first surface. Includes a first surface second insulating layer located on the first surface second conductive layer or the first surface second conductive layer and having a dielectric loss tangent of less than 0.03 .
The first surface first conductive layer, the first surface first insulating layer located on the first surface first conductive layer, and the first surface second located on the first surface first insulating layer. The insulating layer and the first surface third conductive layer located on the first surface second insulating layer form a first capacitor having a first capacitance.
The first surface first conductive layer, the first surface first insulating layer located on the first surface first conductive layer, and the first surface second located on the first surface first insulating layer. The conductive layer constitutes a second capacitor having a second capacitance different from the first capacitance.
The second capacitor further includes the first surface third conductive layer that penetrates the first surface second insulating layer and is connected to the first surface second conductive layer.
The first wiring structure portion is located between the first surface first conductive layer and the first surface second conductive layer, and further has a first surface first inorganic layer containing an inorganic material.
The first surface first conductive layer, the first surface first inorganic layer located on the first surface conductive layer, and the first surface second conductive layer located on the first surface first inorganic layer. Consists of a third capacitor having a third capacitance different from the first capacitance and the second capacitance.
The third capacitor is a through electrode substrate further including the first surface third conductive layer that penetrates the first surface second insulating layer and is connected to the first surface second conductive layer. The through electrode substrate according to claim 12, wherein the second capacitance of at least a part of the second capacitor is at least five times the second capacitance of the first capacitor. 12. The first capacitor and the second capacitor are arranged so as not to overlap with the second surface conductive layer when viewed along the normal direction of the first surface of the substrate, claim 12 or 13. The through electrode substrate according to 13. The through electrode substrate according to any one of claims 12 to 14, wherein the first capacitor and the second capacitor are electrically connected in series or in parallel. The first wiring structure portion is located between the first surface first conductive layer and the first surface second conductive layer, and further has a first surface first inorganic layer containing an inorganic material.
The first surface first conductive layer, the first surface first inorganic layer located on the first surface conductive layer, and the first surface second conductive layer located on the first surface first inorganic layer. The through silicon via substrate according to any one of claims 12 to 15, wherein the third capacitor having the first capacitance and the third capacitance different from the second capacitance is configured. A resin substrate provided with an accommodating portion for accommodating the substrate, the first wiring structure portion, and the laminate of the second wiring structure portion, further comprising a resin substrate provided with an electrode penetrating the resin substrate. , The through electrode substrate according to any one of claims 1 to 16. A first surface layer that is located on the first surface side of the substrate and extends so as to overlap both the first wiring structure portion and the resin substrate when viewed along the normal direction of the first surface of the substrate. Further prepared,
17. The first surface layer has an electrode that penetrates the first surface layer and is electrically connected to the first surface conductive layer of the first wiring structure portion and the electrode of the resin substrate. The through electrode substrate according to. A second surface layer that is located on the second surface side of the substrate and extends so as to overlap both the second wiring structure portion and the resin substrate when viewed along the normal direction of the second surface of the substrate. Further prepared,
17. The second surface layer has an electrode that penetrates the second surface layer and is electrically connected to the second surface conductive layer of the second wiring structure portion and the electrode of the resin substrate. Or the through electrode substrate according to 18. The through silicon via substrate according to any one of claims 1 to 19.
A mounting substrate comprising an element mounted on the through silicon via substrate. The mounting substrate according to claim 20, wherein the element includes at least one of a power amplifier, a surface acoustic wave filter, and a switch.

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